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-rw-r--r--src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout1
-rw-r--r--src/mainboard/intel/dg43gt/cmos.layout1
-rw-r--r--src/northbridge/intel/x4x/early_init.c6
-rw-r--r--src/northbridge/intel/x4x/raminit_ddr2.c13
4 files changed, 16 insertions, 5 deletions
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout
index 15cd29b106..4da0e96cbf 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout
@@ -92,7 +92,6 @@ enumerations
7 0 Disable
7 1 Enable
7 2 Keep
-11 0 1M
11 1 4M
11 2 8M
11 3 16M
diff --git a/src/mainboard/intel/dg43gt/cmos.layout b/src/mainboard/intel/dg43gt/cmos.layout
index 1175cafdc2..abeff71f8b 100644
--- a/src/mainboard/intel/dg43gt/cmos.layout
+++ b/src/mainboard/intel/dg43gt/cmos.layout
@@ -92,7 +92,6 @@ enumerations
7 2 Keep
10 0 AHCI
10 1 Compatible
-11 0 1M
11 1 4M
11 2 8M
11 3 16M
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index ab4864b880..d410259d82 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -74,7 +74,11 @@ void x4x_early_init(void)
get_option(&gfxsize, "gfx_uma_size");
if (gfxsize > 12)
gfxsize = 6;
- pci_write_config16(d0f0, D0F0_GGC, 0x0100 | (gfxsize + 1) << 4);
+ /* Need at least 4M for cbmem_top alignment */
+ else if (gfxsize < 1)
+ gfxsize = 1;
+ /* Set GTT size to 2+2M */
+ pci_write_config16(d0f0, D0F0_GGC, 0x0b00 | (gfxsize + 1) << 4);
} else { /* Does not feature internal graphics */
pci_write_config32(d0f0, D0F0_DEVEN, D0EN | D1EN | PEG1EN);
pci_write_config16(d0f0, D0F0_GGC, (1 << 1));
diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c
index 04dad085de..ddbcd5b700 100644
--- a/src/northbridge/intel/x4x/raminit_ddr2.c
+++ b/src/northbridge/intel/x4x/raminit_ddr2.c
@@ -1293,18 +1293,22 @@ static void mmap_ddr2(struct sysinfo *s)
bool reclaim;
u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud;
u32 gfxbase, gttbase, tsegbase, reclaimbase, reclaimlimit;
+ u32 mmiostart, umasizem;
u16 ggc;
u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96,
160, 224, 352 };
u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4};
+ u8 reg8;
ggc = pci_read_config16(PCI_DEV(0, 0, 0), 0x52);
gfxsize = ggc2uma[(ggc & 0xf0) >> 4];
gttsize = ggc2gtt[(ggc & 0xf00) >> 8];
- tsegsize = 1; // 1MB TSEG
+ tsegsize = 8; // 8MB TSEG
mmiosize = 0x800; // 2GB MMIO
+ umasizem = gfxsize + gttsize + tsegsize;
+ mmiostart = 0x1000 - mmiosize + umasizem;
tom = s->channel_capacity[0] + s->channel_capacity[1] - ME_UMA_SIZEMB;
- tolud = MIN(0x1000 - mmiosize, tom);
+ tolud = MIN(mmiostart, tom);
reclaim = false;
if ((tom - tolud) > 0x40)
@@ -1336,6 +1340,11 @@ static void mmap_ddr2(struct sysinfo *s)
pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, touud);
pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, gfxbase << 20);
pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, gttbase << 20);
+ /* Enable and set tseg size to 8M */
+ reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
+ reg8 &= ~0x7;
+ reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */
+ pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8);
pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegbase << 20);
}