diff options
| -rw-r--r-- | src/mainboard/supermicro/h8qgi/buildOpts.c | 8 | ||||
| -rw-r--r-- | src/mainboard/supermicro/h8scm/buildOpts.c | 8 | ||||
| -rw-r--r-- | src/mainboard/tyan/s8226/buildOpts.c | 8 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family10/Kconfig | 8 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family10/northbridge.c | 8 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family12/Kconfig | 4 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family15/Kconfig | 4 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family15/northbridge.c | 8 |
8 files changed, 23 insertions, 33 deletions
diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c index b30016311a..7e38ccd8ee 100644 --- a/src/mainboard/supermicro/h8qgi/buildOpts.c +++ b/src/mainboard/supermicro/h8qgi/buildOpts.c @@ -204,7 +204,9 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA h8qgi_manual_swaplist[2] = } }; -#if CONFIG_HT3_SUPPORT +#define HYPERTRANSPORT_V31_SUPPORT 1 + +#if HYPERTRANSPORT_V31_SUPPORT /** * The socket and link match values are platform specific * @@ -240,7 +242,7 @@ CONST IO_PCB_LIMITS ROMDATA h8qgi_io_limit_list[2] = HT_LIST_TERMINAL, } }; -#else //CONFIG_HT3_SUPPORT == 0 +#else /* HYPERTRANSPORT_V31_SUPPORT == 0 */ CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8qgi_cpu2cpu_limit_list[2] = { { @@ -272,7 +274,7 @@ CONST IO_PCB_LIMITS ROMDATA h8qgi_io_limit_list[2] = HT_LIST_TERMINAL } }; -#endif //CONFIG_HT3_SUPPORT == 0 +#endif /* HYPERTRANSPORT_V31_SUPPORT == 0 */ /** * HyperTransport links will typically require an equalization at high frequencies. diff --git a/src/mainboard/supermicro/h8scm/buildOpts.c b/src/mainboard/supermicro/h8scm/buildOpts.c index 95dffaa440..d107cd895d 100644 --- a/src/mainboard/supermicro/h8scm/buildOpts.c +++ b/src/mainboard/supermicro/h8scm/buildOpts.c @@ -204,7 +204,9 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA h8scm_manual_swaplist[2] = } }; -#if CONFIG_HT3_SUPPORT +#define HYPERTRANSPORT_V31_SUPPORT 1 + +#if HYPERTRANSPORT_V31_SUPPORT /** * The socket and link match values are platform specific * @@ -240,7 +242,7 @@ CONST IO_PCB_LIMITS ROMDATA h8scm_io_limit_list[2] = HT_LIST_TERMINAL, } }; -#else //CONFIG_HT3_SUPPORT == 0 +#else /* HYPERTRANSPORT_V31_SUPPORT == 0 */ CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8scm_cpu2cpu_limit_list[2] = { { @@ -272,7 +274,7 @@ CONST IO_PCB_LIMITS ROMDATA h8scm_io_limit_list[2] = HT_LIST_TERMINAL } }; -#endif //CONFIG_HT3_SUPPORT == 0 +#endif /* HYPERTRANSPORT_V31_SUPPORT == 0 */ /** * HyperTransport links will typically require an equalization at high frequencies. diff --git a/src/mainboard/tyan/s8226/buildOpts.c b/src/mainboard/tyan/s8226/buildOpts.c index ff04fb7d4b..5f2e29432c 100644 --- a/src/mainboard/tyan/s8226/buildOpts.c +++ b/src/mainboard/tyan/s8226/buildOpts.c @@ -204,7 +204,9 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA s8226_manual_swaplist[2] = } }; -#if CONFIG_HT3_SUPPORT +#define HYPERTRANSPORT_V31_SUPPORT 1 + +#if HYPERTRANSPORT_V31_SUPPORT /** * The socket and link match values are platform specific * @@ -240,7 +242,7 @@ CONST IO_PCB_LIMITS ROMDATA s8226_io_limit_list[2] = HT_LIST_TERMINAL, } }; -#else //CONFIG_HT3_SUPPORT == 0 +#else /* HYPERTRANSPORT_V31_SUPPORT == 0 */ CONST CPU_TO_CPU_PCB_LIMITS ROMDATA s8226_cpu2cpu_limit_list[2] = { { @@ -272,7 +274,7 @@ CONST IO_PCB_LIMITS ROMDATA s8226_io_limit_list[2] = HT_LIST_TERMINAL } }; -#endif //CONFIG_HT3_SUPPORT == 0 +#endif /* HYPERTRANSPORT_V31_SUPPORT == 0 */ /** * HyperTransport links will typically require an equalization at high frequencies. diff --git a/src/northbridge/amd/agesa/family10/Kconfig b/src/northbridge/amd/agesa/family10/Kconfig index 244c133ec0..a4dc09bd68 100644 --- a/src/northbridge/amd/agesa/family10/Kconfig +++ b/src/northbridge/amd/agesa/family10/Kconfig @@ -25,19 +25,21 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY10 select MMCONF_SUPPORT if NORTHBRIDGE_AMD_AGESA_FAMILY10 -config HT3_SUPPORT - bool - default y + config HW_MEM_HOLE_SIZEK hex default 0x100000 + config HW_MEM_HOLE_SIZE_AUTO_INC bool default n + config MMCONF_BASE_ADDRESS hex default 0xE0000000 + config MMCONF_BUS_NUMBER int default 256 + endif #NORTHBRIDGE_AMD_AGESA_FAMILY10 diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 2b2dad5530..8e47c1a5a3 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -1133,13 +1133,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Ok, We need to set the links for that device. * otherwise the device under it will not be scanned */ - int linknum; -#if CONFIG_HT3_SUPPORT - linknum = 8; -#else - linknum = 4; -#endif - add_more_links(cdb_dev, linknum); + add_more_links(cdb_dev, 8); } cores_found = 0; // one core diff --git a/src/northbridge/amd/agesa/family12/Kconfig b/src/northbridge/amd/agesa/family12/Kconfig index 16be288905..671bd4d93c 100644 --- a/src/northbridge/amd/agesa/family12/Kconfig +++ b/src/northbridge/amd/agesa/family12/Kconfig @@ -26,10 +26,6 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY12 if NORTHBRIDGE_AMD_AGESA_FAMILY12 -config HT3_SUPPORT - bool - default y - config HW_MEM_HOLE_SIZEK hex default 0x100000 diff --git a/src/northbridge/amd/agesa/family15/Kconfig b/src/northbridge/amd/agesa/family15/Kconfig index cb6b0d33c3..9d15be06fd 100644 --- a/src/northbridge/amd/agesa/family15/Kconfig +++ b/src/northbridge/amd/agesa/family15/Kconfig @@ -26,9 +26,7 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY15 select PER_DEVICE_ACPI_TABLES if NORTHBRIDGE_AMD_AGESA_FAMILY15 -config HT3_SUPPORT - bool - default y + config HW_MEM_HOLE_SIZEK hex default 0x100000 diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index c030d577d9..89e1644732 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -1131,13 +1131,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Ok, We need to set the links for that device. * otherwise the device under it will not be scanned */ - int linknum; -#if CONFIG_HT3_SUPPORT - linknum = 8; -#else - linknum = 4; -#endif - add_more_links(cdb_dev, linknum); + add_more_links(cdb_dev, 8); } family = cpuid_eax(1); |