diff options
| -rw-r--r-- | src/mainboard/google/dedede/Kconfig | 10 | ||||
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 29 | ||||
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/gpio.c | 22 |
3 files changed, 57 insertions, 4 deletions
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 5254d16b7c..9b5bd4af5e 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -1,11 +1,14 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE def_bool n + select DRIVERS_SPI_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_SPI_TPM_CR50 + select MAINBOARD_HAS_TPM2 select SOC_INTEL_JASPERLAKE if BOARD_GOOGLE_BASEBOARD_DEDEDE @@ -25,6 +28,9 @@ config DEVICETREE string default "variants/baseboard/devicetree.cb" +config DRIVER_TPM_SPI_BUS + default 0x1 + config MAINBOARD_DIR string default "google/dedede" @@ -41,6 +47,10 @@ config MAX_CPUS int default 4 +config TPM_TIS_ACPI_INTERRUPT + int + default 4 # GPE0_DW0_4 (GPP_B4) + config UART_FOR_CONSOLE int default 2 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 2a0b760728..e98b686608 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -29,13 +29,13 @@ chip soc/intel/tigerlake }" register "SerialIoGSpiMode" = "{ - [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI0] = PchSerialIoPci, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, }" register "SerialIoGSpiCsMode" = "{ - [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI0] = 1, [PchSerialIoIndexGSPI1] = 0, [PchSerialIoIndexGSPI2] = 0, }" @@ -52,6 +52,22 @@ chip soc/intel/tigerlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" + device domain 0 on device pci 00.0 off end # Host Bridge device pci 02.0 off end # Integrated Graphics Device @@ -87,7 +103,14 @@ chip soc/intel/tigerlake device pci 1c.7 off end # PCI Express Root Port 8 device pci 1e.0 off end # UART 0 device pci 1e.1 off end # UART 1 - device pci 1e.2 off end # GSPI 0 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B4_IRQ)" + device spi 0 on end + end + end # GSPI 0 device pci 1e.3 off end # GSPI 1 device pci 1f.0 on chip ec/google/chromeec diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 090841260f..b9d77bf585 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -21,11 +21,31 @@ static const struct pad_config gpio_table[] = { /* A4 : ESPI_CS# */ /* A5 : ESPI_CLK */ /* A6 : ESPI_RESET_L */ + + /* B4 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - /* ToDo: Fill early gpio configuration */ + /* B4 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), }; const struct pad_config *__weak variant_gpio_table(size_t *num) |