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-rw-r--r--src/soc/intel/baytrail/chip.h1
-rw-r--r--src/soc/intel/baytrail/ehci.c3
2 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h
index f19055c1bb..97b92efb99 100644
--- a/src/soc/intel/baytrail/chip.h
+++ b/src/soc/intel/baytrail/chip.h
@@ -55,6 +55,7 @@ struct soc_intel_baytrail_config {
uint32_t usb2_per_port_rcomp_hs_pullup2;
uint32_t usb2_per_port_lane3;
uint32_t usb2_per_port_rcomp_hs_pullup3;
+ uint32_t usb2_comp_bg;
/* LPE Audio Clock configuration. */
int lpe_codec_clk_freq; /* 19 or 25 are valid. */
diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c
index 5d1a4d83c5..bfdb61aa1a 100644
--- a/src/soc/intel/baytrail/ehci.c
+++ b/src/soc/intel/baytrail/ehci.c
@@ -96,7 +96,8 @@ static void usb2_phy_init(device_t dev)
struct soc_intel_baytrail_config *config = dev->chip_info;
struct reg_script usb2_phy_script[] = {
/* USB3PHYInit() */
- REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG, 0x4700),
+ REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG,
+ config->usb2_comp_bg),
/* Per port phy settings, set in devicetree.cb */
REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE0,
config->usb2_per_port_lane0),