summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/soc/intel/cannonlake/bootblock/bootblock.c2
-rw-r--r--src/soc/intel/cannonlake/bootblock/pch.c13
-rw-r--r--src/soc/intel/cannonlake/include/soc/bootblock.h2
-rw-r--r--src/soc/intel/cannonlake/include/soc/romstage.h1
-rw-r--r--src/soc/intel/cannonlake/romstage/Makefile.inc1
-rw-r--r--src/soc/intel/cannonlake/romstage/pch.c27
-rw-r--r--src/soc/intel/cannonlake/romstage/romstage.c2
7 files changed, 35 insertions, 13 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c
index 6a6dd8be25..4cc15fca46 100644
--- a/src/soc/intel/cannonlake/bootblock/bootblock.c
+++ b/src/soc/intel/cannonlake/bootblock/bootblock.c
@@ -74,5 +74,5 @@ void bootblock_soc_init(void)
*/
gpi_clear_int_cfg();
report_platform_info();
- pch_early_init();
+ bootblock_pch_init();
}
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index 9ad7e86178..a6e9f9db52 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2017-2018 Intel Corporation.
+ * Copyright (C) 2017-2019 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -25,8 +25,6 @@
#include <intelblocks/pcr.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/rtc.h>
-#include <intelblocks/smbus.h>
-#include <intelblocks/tco.h>
#include <soc/bootblock.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
@@ -36,7 +34,6 @@
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
#include <soc/pm.h>
-#include <soc/smbus.h>
#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP 0x1400
#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H 0x0980
@@ -181,7 +178,7 @@ void pch_early_iorange_init(void)
pch_enable_lpc();
}
-void pch_early_init(void)
+void bootblock_pch_init(void)
{
/*
* Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
@@ -189,12 +186,6 @@ void pch_early_init(void)
*/
soc_config_acpibase();
- /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
- tco_configure();
-
- /* Program SMBUS_BASE_ADDRESS and Enable it */
- smbus_common_init();
-
/* Set up GPE configuration */
pmc_gpe_init();
diff --git a/src/soc/intel/cannonlake/include/soc/bootblock.h b/src/soc/intel/cannonlake/include/soc/bootblock.h
index a5c3c323ae..efc837eb80 100644
--- a/src/soc/intel/cannonlake/include/soc/bootblock.h
+++ b/src/soc/intel/cannonlake/include/soc/bootblock.h
@@ -23,7 +23,7 @@ void bootblock_cpu_init(void);
void bootblock_pch_early_init(void);
/* Bootblock post console init programming */
-void pch_early_init(void);
+void bootblock_pch_init(void);
void pch_early_iorange_init(void);
void report_platform_info(void);
diff --git a/src/soc/intel/cannonlake/include/soc/romstage.h b/src/soc/intel/cannonlake/include/soc/romstage.h
index 643105a0a2..ab20ee7e3f 100644
--- a/src/soc/intel/cannonlake/include/soc/romstage.h
+++ b/src/soc/intel/cannonlake/include/soc/romstage.h
@@ -24,6 +24,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd);
/* Provide a callback to allow mainboard to override the DRAM part number. */
void mainboard_get_dram_part_num(const char **part_num, size_t *len);
void systemagent_early_init(void);
+void romstage_pch_init(void);
/* Board type */
enum board_type {
diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc
index 33d9629e1d..ff3d73dee0 100644
--- a/src/soc/intel/cannonlake/romstage/Makefile.inc
+++ b/src/soc/intel/cannonlake/romstage/Makefile.inc
@@ -17,3 +17,4 @@ romstage-y += ../../../../cpu/intel/car/romstage.c
romstage-y += romstage.c
romstage-y += fsp_params.c
romstage-y += systemagent.c
+romstage-y += pch.c
diff --git a/src/soc/intel/cannonlake/romstage/pch.c b/src/soc/intel/cannonlake/romstage/pch.c
new file mode 100644
index 0000000000..8e783da6f9
--- /dev/null
+++ b/src/soc/intel/cannonlake/romstage/pch.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/smbus.h>
+#include <intelblocks/tco.h>
+#include <soc/romstage.h>
+
+void romstage_pch_init(void)
+{
+ /* Program TCO_BASE_ADDRESS and TCO Timer Halt */
+ tco_configure();
+
+ /* Program SMBUS_BASE_ADDRESS and enable it */
+ smbus_common_init();
+}
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index f782f63622..2505683479 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -132,6 +132,8 @@ void mainboard_romstage_entry(void)
/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
systemagent_early_init();
+ /* Program PCH init */
+ romstage_pch_init();
/* initialize Heci interface */
heci_init(HECI1_BASE_ADDRESS);