summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/northbridge/intel/e7505/memmap.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c
index 48527fdd96..1b86012907 100644
--- a/src/northbridge/intel/e7505/memmap.c
+++ b/src/northbridge/intel/e7505/memmap.c
@@ -48,9 +48,12 @@ void platform_enter_postcar(void)
if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
die("Unable to initialize postcar frame.\n");
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
- MTRR_TYPE_WRPROT);
+ /*
+ * Choose to NOT set ROM as WP cacheable here.
+ * Timestamps indicate the CPU this northbridge code is
+ * connected to, performs better for memcpy() and un-lzma
+ * operations when source is left as UC.
+ */
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);