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-rw-r--r--src/mainboard/google/urara/bootblock.c2
-rw-r--r--src/soc/imgtec/pistachio/clocks.c36
-rw-r--r--src/soc/imgtec/pistachio/include/soc/clocks.h2
3 files changed, 20 insertions, 20 deletions
diff --git a/src/mainboard/google/urara/bootblock.c b/src/mainboard/google/urara/bootblock.c
index 814eb53631..c8e15c8899 100644
--- a/src/mainboard/google/urara/bootblock.c
+++ b/src/mainboard/google/urara/bootblock.c
@@ -193,7 +193,7 @@ static int init_clocks(void)
uart1_clk_setup(6, 61);
/* System PLL divided by 4 divided by 3 -> 33.33 MHz */
- i2c0_clk_setup(3, 2);
+ i2c_clk_setup(3, 2, 0);
/* Ethernet clocks setup: ENET as clock source */
eth_clk_setup(0, 7);
diff --git a/src/soc/imgtec/pistachio/clocks.c b/src/soc/imgtec/pistachio/clocks.c
index f3a9ceee21..0b9774a241 100644
--- a/src/soc/imgtec/pistachio/clocks.c
+++ b/src/soc/imgtec/pistachio/clocks.c
@@ -98,11 +98,11 @@
#define UART1CLKOUT_CTRL_ADDR 0xB8144240
#define UART1CLKOUT_MASK 0x000003FF
-/* Definitions for I2C0 setup */
-#define I2C0CLKDIV1_CTRL_ADDR 0xB814413C
-#define I2C0CLKDIV1_MASK 0x0000007F
-#define I2C0CLKOUT_CTRL_ADDR 0xB8144140
-#define I2C0CLKOUT_MASK 0x0000007F
+/* Definitions for I2C setup */
+#define I2CCLKDIV1_CTRL_ADDR(i) (0xB8144000 + 0x013C + (2*(i)*4))
+#define I2CCLKDIV1_MASK 0x0000007F
+#define I2CCLKOUT_CTRL_ADDR(i) (0xB8144000 + 0x0140 + (2*(i)*4))
+#define I2CCLKOUT_MASK 0x0000007F
/* Definitions for ROM clock setup */
#define ROMCLKOUT_CTRL_ADDR 0xB814490C
@@ -307,29 +307,29 @@ void uart1_clk_setup(u8 divider1, u16 divider2)
}
/*
- * i2c_clk_setup: sets up clocks for I2C0
+ * i2c_clk_setup: sets up clocks for I2C
* divider1: 7-bit divider value
* divider2: 7-bit divider value
*/
-void i2c0_clk_setup(u8 divider1, u16 divider2)
+void i2c_clk_setup(u8 divider1, u16 divider2, u8 interface)
{
u32 reg;
/* Check input parameters */
- assert(!(divider1 & ~(I2C0CLKDIV1_MASK)));
- assert(!(divider2 & ~(I2C0CLKOUT_MASK)));
-
+ assert(!(divider1 & ~(I2CCLKDIV1_MASK)));
+ assert(!(divider2 & ~(I2CCLKOUT_MASK)));
+ assert(interface < 4);
/* Set divider 1 */
- reg = read32(I2C0CLKDIV1_CTRL_ADDR);
- reg &= ~I2C0CLKDIV1_MASK;
- reg |= divider1 & I2C0CLKDIV1_MASK;
- write32(I2C0CLKDIV1_CTRL_ADDR, reg);
+ reg = read32(I2CCLKDIV1_CTRL_ADDR(interface));
+ reg &= ~I2CCLKDIV1_MASK;
+ reg |= divider1 & I2CCLKDIV1_MASK;
+ write32(I2CCLKDIV1_CTRL_ADDR(interface), reg);
/* Set divider 2 */
- reg = read32(I2C0CLKOUT_CTRL_ADDR);
- reg &= ~I2C0CLKOUT_MASK;
- reg |= divider2 & I2C0CLKOUT_MASK;
- write32(I2C0CLKOUT_CTRL_ADDR, reg);
+ reg = read32(I2CCLKOUT_CTRL_ADDR(interface));
+ reg &= ~I2CCLKOUT_MASK;
+ reg |= divider2 & I2CCLKOUT_MASK;
+ write32(I2CCLKOUT_CTRL_ADDR(interface), reg);
}
/* system_clk_setup: sets up the system (peripheral) clock */
diff --git a/src/soc/imgtec/pistachio/include/soc/clocks.h b/src/soc/imgtec/pistachio/include/soc/clocks.h
index 81b640ebbd..f351a6f9c3 100644
--- a/src/soc/imgtec/pistachio/include/soc/clocks.h
+++ b/src/soc/imgtec/pistachio/include/soc/clocks.h
@@ -28,7 +28,7 @@ int mips_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback);
void system_clk_setup(u8 divider);
void mips_clk_setup(u8 divider1, u8 divider2);
void uart1_clk_setup(u8 divider1, u16 divider2);
-void i2c0_clk_setup(u8 divider1, u16 divider2);
+void i2c_clk_setup(u8 divider1, u16 divider2, u8 interface);
int usb_clk_setup(u8 divider, u8 refclksel, u8 fsel);
void rom_clk_setup(u8 divider);
void eth_clk_setup(u8 mux, u8 divider);