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-rw-r--r--src/southbridge/intel/lynxpoint/pch.c10
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h1
2 files changed, 6 insertions, 5 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c
index 05462c5e74..f13efb0f7f 100644
--- a/src/southbridge/intel/lynxpoint/pch.c
+++ b/src/southbridge/intel/lynxpoint/pch.c
@@ -92,7 +92,7 @@ static void pch_enable_d3hot(device_t dev)
}
/* Set bit in Function Disble register to hide this device */
-static void pch_hide_devfn(device_t dev)
+void pch_disable_devfn(device_t dev)
{
switch (dev->path.pci.devfn) {
case PCI_DEVFN(19, 0): /* Audio DSP */
@@ -432,8 +432,8 @@ static void pch_pcie_enable(device_t dev)
/* Do not claim downstream transactions for PCIe ports */
new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn));
- /* Hide this device if possible */
- pch_hide_devfn(dev);
+ /* Disable this device if possible */
+ pch_disable_devfn(dev);
} else {
int fn;
@@ -491,8 +491,8 @@ void pch_enable(device_t dev)
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config32(dev, PCI_COMMAND, reg32);
- /* Hide this device if possible */
- pch_hide_devfn(dev);
+ /* Disable this device if possible */
+ pch_disable_devfn(dev);
} else {
/* Enable SERR */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index c46153ca44..7c187054cc 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -162,6 +162,7 @@ void disable_gpe(u32 mask);
#include <arch/acpi.h>
#include "chip.h"
void pch_enable(device_t dev);
+void pch_disable_devfn(device_t dev);
u32 pch_iobp_read(u32 address);
void pch_iobp_write(u32 address, u32 data);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);