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-rw-r--r--src/mainboard/amd/bettong/PlatformGnbPcie.c27
-rw-r--r--src/mainboard/amd/bettong/devicetree.cb2
2 files changed, 21 insertions, 8 deletions
diff --git a/src/mainboard/amd/bettong/PlatformGnbPcie.c b/src/mainboard/amd/bettong/PlatformGnbPcie.c
index af272dd97a..16ac427e07 100644
--- a/src/mainboard/amd/bettong/PlatformGnbPcie.c
+++ b/src/mainboard/amd/bettong/PlatformGnbPcie.c
@@ -22,7 +22,7 @@
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
static const PCIe_PORT_DESCRIPTOR PortList [] = {
- /* Initialize Port descriptor (PCIe port, Lanes 8-15, PCI Device Number 2, ...) */
+ /* Initialize Port descriptor (PCIe port, Lanes 8-15, PCI Device Number 3, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
@@ -46,33 +46,44 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 6, 6),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 4,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmDisabled, 0x04, 0)
},
- /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
+ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 2, ...) */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
+ PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmDisabled, 0x05, 0)
},
- /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
+ /* Initialize Port descriptor (PCIe port, Lanes 4-5, PCI Device Number 2, ...) */
{
- DESCRIPTOR_TERMINATE_LIST, // Descriptor flags !!!IMPORTANT!!! Terminate last element of array
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmDisabled, 0x06, 0)
},
+ /* Initialize Port descriptor (PCIe port, Lanes 0-3, PCI Device Number 2, ...) */
+ {
+ DESCRIPTOR_TERMINATE_LIST, // Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x07, 0)
+ },
+
};
static const PCIe_DDI_DESCRIPTOR DdiList [] = {
diff --git a/src/mainboard/amd/bettong/devicetree.cb b/src/mainboard/amd/bettong/devicetree.cb
index 44ae75a09f..90b03247cd 100644
--- a/src/mainboard/amd/bettong/devicetree.cb
+++ b/src/mainboard/amd/bettong/devicetree.cb
@@ -37,6 +37,8 @@ chip northbridge/amd/pi/00660F01/root_complex
device pci 2.3 on end # Realtek NIC
device pci 2.4 on end # Edge Connector
device pci 2.5 on end # Edge Connector
+ device pci 3.0 on end # Edge Connector
+ device pci 3.1 on end # Edge Connector
end #chip northbridge/amd/pi/00660F01
chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus