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-rw-r--r--src/mainboard/google/chell/devicetree.cb1
-rw-r--r--src/mainboard/google/glados/devicetree.cb1
-rw-r--r--src/mainboard/google/lars/devicetree.cb1
-rw-r--r--src/mainboard/intel/kunimitsu/devicetree.cb1
4 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index ffc805c652..ac3a5c1da2 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -50,6 +50,7 @@ chip soc/intel/skylake
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
+ register "PmTimerDisabled" = "1"
# VR Settings Configuration for 5 Domains
#+----------------+-------+-------+-------------+-------------+-------+
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index c3aae8cf97..894f0e1858 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -50,6 +50,7 @@ chip soc/intel/skylake
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
+ register "PmTimerDisabled" = "1"
# VR Settings Configuration for 5 Domains
#+----------------+-------+-------+-------------+-------------+-------+
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index c601507b1f..bc39f3e345 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -32,6 +32,7 @@ chip soc/intel/skylake
register "HeciEnabled" = "0"
register "SaGv" = "3"
register "FspSkipMpInit" = "1"
+ register "PmTimerDisabled" = "1"
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 73eced13b8..d2a70c8711 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -31,6 +31,7 @@ chip soc/intel/skylake
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
+ register "PmTimerDisabled" = "1"
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s