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-rw-r--r--Makefile.inc7
-rw-r--r--src/Kconfig8
-rw-r--r--src/arch/x86/Makefile.inc2
-rw-r--r--src/mainboard/Kconfig8
-rw-r--r--src/southbridge/intel/bd82x6x/Makefile.inc16
5 files changed, 31 insertions, 10 deletions
diff --git a/Makefile.inc b/Makefile.inc
index 2a5e821bbf..4e31e83849 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -164,7 +164,7 @@ CFLAGS += -Werror
endif
CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
-additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/options
+additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/ifdtool $(objutil)/options
#######################################################################
# generate build support files
@@ -222,6 +222,11 @@ $(ROMCC): $(top)/util/romcc/romcc.c
@# http://www.coreboot.org/pipermail/coreboot/2010-February/055825.html
$(HOSTCC) -g $(STACK) -Wall -o $@ $<
+IFDTOOL:=$(objutil)/ifdtool/ifdtool
+$(IFDTOOL): $(top)/util/ifdtool/ifdtool.c
+ @printf " HOSTCC $(subst $(obj)/,,$(@))\n"
+ $(HOSTCC) $(HOSTCFLAGS) -o $@ $<
+
#######################################################################
# needed objects that every mainboard uses
# Creation of these is architecture and mainboard independent
diff --git a/src/Kconfig b/src/Kconfig
index 9630e0c816..b5fcdafa3a 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -325,6 +325,14 @@ config TPM
bool
default n
+config CBFS_SIZE
+ hex
+ default ROM_SIZE
+
+config CACHE_ROM_SIZE
+ hex
+ default CBFS_SIZE
+
# TODO: Can probably be removed once all chipsets have kconfig options for it.
config VIDEO_MB
int
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 6e35dee753..abc71de0c7 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -76,7 +76,7 @@ $(obj)/coreboot.pre1: $(CBFSTOOL)
mv $(obj)/coreboot.rom $@
endif
-$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES))
+$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE)
@printf " CBFS $(subst $(obj)/,,$(@))\n"
cp $(obj)/coreboot.pre $@.tmp
if [ -f $(objcbfs)/coreboot_ap.elf ]; \
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index 77bfa0f007..da76327a35 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -304,14 +304,6 @@ config ROM_SIZE
default 0x800000 if COREBOOT_ROMSIZE_KB_8192
default 0x1000000 if COREBOOT_ROMSIZE_KB_16384
-config CBFS_SIZE
- hex
- default ROM_SIZE
-
-config CACHE_ROM_SIZE
- hex
- default CBFS_SIZE
-
config ENABLE_POWER_BUTTON
bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL
default y if POWER_BUTTON_DEFAULT_ENABLE
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index 9ffed9babb..eca3d9e2af 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -17,6 +17,11 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+# Run an intermediate step when producing coreboot.rom
+# that adds additional components to the final firmware
+# image outside of CBFS
+INTERMEDIATE+=bd82x6x_add_me
+
driver-y += pch.c
driver-y += azalia.c
driver-y += lpc.c
@@ -46,3 +51,14 @@ smm-$(CONFIG_USBDEBUG) += usb_debug.c
romstage-y += reset.c
romstage-y += early_spi.c
+bd82x6x_add_me: $(obj)/coreboot.pre $(IFDTOOL)
+ printf " DD Adding Intel Firmware Descriptor\n"
+ dd if=3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin \
+ of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
+ printf " IFDTOOL me.bin -> coreboot.pre\n"
+ $(objutil)/ifdtool/ifdtool \
+ -i ME:3rdparty/mainboard/$(MAINBOARDDIR)/me.bin \
+ $(obj)/coreboot.pre
+ mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
+
+PHONY += bd82x6x_add_me