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-rw-r--r--src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb5
-rw-r--r--src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb5
-rw-r--r--src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb5
3 files changed, 3 insertions, 12 deletions
diff --git a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb
index e2340b9f03..f697bff010 100644
--- a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb
+++ b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb
@@ -37,10 +37,7 @@ chip northbridge/intel/x4x # Northbridge
chip southbridge/intel/i82801jx # Southbridge
register "gpe0_en" = "0x40"
- # Set AHCI mode.
- register "sata_port_map" = "0x3f"
- register "sata_clock_request" = "0"
- register "sata_traffic_monitor" = "0"
+ register "sata_port_map" = "0x3f"
# Enable PCIe ports 0,2,3 as slots.
register "pcie_slot_implemented" = "0x31"
diff --git a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb
index ebaaecaad2..94ef717e60 100644
--- a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb
+++ b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb
@@ -37,10 +37,7 @@ chip northbridge/intel/x4x # Northbridge
chip southbridge/intel/i82801jx # Southbridge
register "gpe0_en" = "0x40"
- # Set AHCI mode.
- register "sata_port_map" = "0x3f"
- register "sata_clock_request" = "0"
- register "sata_traffic_monitor" = "0"
+ register "sata_port_map" = "0x3f"
# Enable PCIe ports 0,2,3 as slots.
register "pcie_slot_implemented" = "0x31"
diff --git a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb
index 4e27b467d9..91e45b4f29 100644
--- a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb
+++ b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb
@@ -37,10 +37,7 @@ chip northbridge/intel/x4x # Northbridge
chip southbridge/intel/i82801jx # Southbridge
register "gpe0_en" = "0x40"
- # Set AHCI mode.
- register "sata_port_map" = "0x3f"
- register "sata_clock_request" = "0"
- register "sata_traffic_monitor" = "0"
+ register "sata_port_map" = "0x3f"
# Enable PCIe ports 0,2,3 as slots.
register "pcie_slot_implemented" = "0x31"