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-rw-r--r--src/soc/intel/quark/include/soc/fsp/FspmUpd.h14
-rw-r--r--src/soc/intel/quark/romstage/fsp1_1.c17
-rw-r--r--src/soc/intel/quark/romstage/fsp2_0.c5
-rw-r--r--src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h21
4 files changed, 41 insertions, 16 deletions
diff --git a/src/soc/intel/quark/include/soc/fsp/FspmUpd.h b/src/soc/intel/quark/include/soc/fsp/FspmUpd.h
index bb0fc51b3d..a7a54a842d 100644
--- a/src/soc/intel/quark/include/soc/fsp/FspmUpd.h
+++ b/src/soc/intel/quark/include/soc/fsp/FspmUpd.h
@@ -53,7 +53,7 @@ struct FSP_M_CONFIG {
/** Offset 0x0048 - SerialPortBaseAddress
Debug serial port base address set by BIOS. Zero disables debug serial output.
**/
- uint32_t SerialPortBaseAddress;
+ uint32_t Reserved_48;
/** Offset 0x004C - tRAS
ACT to PRE command period in picoseconds.
@@ -200,6 +200,18 @@ struct FSP_M_CONFIG {
/** Offset 0x0080
**/
+ uint32_t SerialPortPollForChar;
+
+/** Offset 0x0084
+**/
+ uint32_t SerialPortReadChar;
+
+/** Offset 0x0088
+**/
+ uint32_t SerialPortWriteChar;
+
+/** Offset 0x008C
+**/
uint16_t UpdTerminator;
} __attribute__((packed));
diff --git a/src/soc/intel/quark/romstage/fsp1_1.c b/src/soc/intel/quark/romstage/fsp1_1.c
index 5ba2174628..d7f19a74f5 100644
--- a/src/soc/intel/quark/romstage/fsp1_1.c
+++ b/src/soc/intel/quark/romstage/fsp1_1.c
@@ -21,7 +21,6 @@
#include "../chip.h"
#include <fsp/memmap.h>
#include <fsp/util.h>
-#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/QuarkNcSocId.h>
#include <soc/romstage.h>
@@ -120,8 +119,8 @@ void soc_memory_init_params(struct romstage_params *params,
upd->RankMask = config->RankMask;
upd->RmuBaseAddress = (uintptr_t)rmu_file;
upd->RmuLength = rmu_file_len;
- upd->SerialPortBaseAddress = console_log_level(BIOS_SPEW)
- ? UART_BASE_ADDRESS : 0;
+ upd->SerialPortWriteChar = console_log_level(BIOS_SPEW)
+ ? (uintptr_t)fsp_write_line : 0;
upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
config->SmmTsegSize : 0;
upd->SocRdOdtVal = config->SocRdOdtVal;
@@ -176,9 +175,15 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
old->RmuBaseAddress, new->RmuBaseAddress);
fsp_display_upd_value("RmuLength", sizeof(old->RmuLength),
old->RmuLength, new->RmuLength);
- fsp_display_upd_value("SerialPortBaseAddress",
- sizeof(old->SerialPortBaseAddress),
- old->SerialPortBaseAddress, new->SerialPortBaseAddress);
+ fsp_display_upd_value("SerialPortPollForChar",
+ sizeof(old->SerialPortPollForChar),
+ old->SerialPortPollForChar, new->SerialPortPollForChar);
+ fsp_display_upd_value("SerialPortReadChar",
+ sizeof(old->SerialPortReadChar),
+ old->SerialPortReadChar, new->SerialPortReadChar);
+ fsp_display_upd_value("SerialPortWriteChar",
+ sizeof(old->SerialPortWriteChar),
+ old->SerialPortWriteChar, new->SerialPortWriteChar);
fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize),
old->SmmTsegSize, new->SmmTsegSize);
fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal),
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c
index 6ca6a4c011..51fcde71e5 100644
--- a/src/soc/intel/quark/romstage/fsp2_0.c
+++ b/src/soc/intel/quark/romstage/fsp2_0.c
@@ -20,7 +20,6 @@
#include "../chip.h"
#include <cpu/x86/cache.h>
#include <fsp/util.h>
-#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/romstage.h>
@@ -161,8 +160,8 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *fspm_upd)
upd->RankMask = config->RankMask;
upd->RmuBaseAddress = (uintptr_t)rmu_file;
upd->RmuLength = rmu_file_len;
- upd->SerialPortBaseAddress = console_log_level(BIOS_SPEW)
- ? UART_BASE_ADDRESS : 0;
+ upd->SerialPortWriteChar = console_log_level(BIOS_SPEW)
+ ? (uintptr_t)fsp_write_line : 0;
upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
config->SmmTsegSize : 0;
upd->SocRdOdtVal = config->SocRdOdtVal;
diff --git a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
index c27a156624..743e4ee861 100644
--- a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
+++ b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
@@ -88,7 +88,7 @@ typedef struct {
UINT32 RmuLength;
/** Offset 0x0030
**/
- UINT32 SerialPortBaseAddress;
+ UINT32 Reserved_30;
/** Offset 0x0034
**/
UINT32 tRAS;
@@ -175,17 +175,26 @@ typedef struct {
UINT32 MrcDataLength;
/** Offset 0x0068
**/
- UINT8 ReservedMemoryInitUpd[8];
+ UINT32 SerialPortPollForChar;
+/** Offset 0x006C
+**/
+ UINT32 SerialPortReadChar;
+/** Offset 0x0070
+**/
+ UINT32 SerialPortWriteChar;
+/** Offset 0x0074
+**/
+ UINT8 ReservedMemoryInitUpd[12];
} MEMORY_INIT_UPD;
typedef struct {
-/** Offset 0x0070
+/** Offset 0x0080
**/
UINT64 Signature;
-/** Offset 0x0078
+/** Offset 0x0088
**/
UINT64 Revision;
-/** Offset 0x0080
+/** Offset 0x0090
**/
UINT16 PcdRegionTerminator;
} SILICON_INIT_UPD;
@@ -210,7 +219,7 @@ typedef struct _UPD_DATA_REGION {
/** Offset 0x0018
**/
MEMORY_INIT_UPD MemoryInitUpd;
-/** Offset 0x0070
+/** Offset 0x0080
**/
SILICON_INIT_UPD SiliconInitUpd;
} UPD_DATA_REGION;