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-rw-r--r--src/soc/intel/quark/include/soc/reg_access.h23
-rw-r--r--src/soc/intel/quark/reg_access.c38
2 files changed, 61 insertions, 0 deletions
diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h
index 0e64917177..8be7f83e88 100644
--- a/src/soc/intel/quark/include/soc/reg_access.h
+++ b/src/soc/intel/quark/include/soc/reg_access.h
@@ -19,6 +19,7 @@
#define __SIMPLE_DEVICE__
#include <arch/io.h>
+#include <cpu/x86/cr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <delay.h>
@@ -39,6 +40,7 @@ enum {
PCIE_RESET,
GPE0_REGS,
HOST_BRIDGE,
+ CPU_CR,
};
enum {
@@ -50,6 +52,27 @@ enum {
_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, SOC_TYPE, \
size_, reg_, mask_, value_, timeout_, reg_set_)
+/* CPU CRx register access macros */
+#define REG_CPU_CR_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
+ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
+ CPU_CR)
+#define REG_CPU_CR_READ(reg_) \
+ REG_CPU_CR_ACCESS(READ, reg_, 0, 0, 0)
+#define REG_CPU_CR_WRITE(reg_, value_) \
+ REG_CPU_CR_ACCESS(WRITE, reg_, 0, value_, 0)
+#define REG_CPU_CR_AND(reg_, value_) \
+ REG_CPU_CR_RMW(reg_, value_, 0)
+#define REG_CPU_CR_RMW(reg_, mask_, value_) \
+ REG_CPU_CR_ACCESS(RMW, reg_, mask_, value_, 0)
+#define REG_CPU_CR_RXW(reg_, mask_, value_) \
+ REG_CPU_CR_ACCESS(RXW, reg_, mask_, value_, 0)
+#define REG_CPU_CR_OR(reg_, value_) \
+ REG_CPU_CR_RMW(reg_, 0xffffffff, value_)
+#define REG_CPU_CR_POLL(reg_, mask_, value_, timeout_) \
+ REG_CPU_CR_ACCESS(POLL, reg_, mask_, value_, timeout_)
+#define REG_CPU_CR_XOR(reg_, value_) \
+ REG_CPU_CR_RXW(reg_, 0xffffffff, value_)
+
/* GPE0 controller register access macros */
#define REG_GPE0_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c
index 368417b694..e5c0f0b6dc 100644
--- a/src/soc/intel/quark/reg_access.c
+++ b/src/soc/intel/quark/reg_access.c
@@ -141,6 +141,34 @@ void port_reg_write(uint8_t port, uint32_t offset, uint32_t value)
mcr_write(QUARK_OPCODE_WRITE, port, offset);
}
+static CRx_TYPE reg_cpu_cr_read(uint32_t reg_address)
+{
+ /* Read the CPU CRx register */
+ switch(reg_address) {
+ case 0:
+ return read_cr0();
+
+ case 4:
+ return read_cr4();
+ }
+ die("ERROR - Unsupported CPU register!\n");
+}
+
+static void reg_cpu_cr_write(uint32_t reg_address, CRx_TYPE value)
+{
+ /* Write the CPU CRx register */
+ switch(reg_address) {
+ default:
+ die("ERROR - Unsupported CPU register!\n");
+
+ case 0:
+ write_cr0(value);
+
+ case 4:
+ write_cr4(value);
+ }
+}
+
static uint32_t reg_gpe0_read(uint32_t reg_address)
{
/* Read the GPE0 register */
@@ -278,6 +306,11 @@ static uint64_t reg_read(struct reg_script_context *ctx)
ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING;
return 0;
+ case CPU_CR:
+ ctx->display_prefix = "CPU CR";
+ value = reg_cpu_cr_read(step->reg);
+ break;
+
case GPE0_REGS:
ctx->display_prefix = "GPE0";
value = reg_gpe0_read(step->reg);
@@ -333,6 +366,11 @@ static void reg_write(struct reg_script_context *ctx)
ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING;
return;
+ case CPU_CR:
+ ctx->display_prefix = "CPU CR";
+ reg_cpu_cr_write(step->reg, step->value);
+ break;
+
case GPE0_REGS:
ctx->display_prefix = "GPE0";
reg_gpe0_write(step->reg, (uint32_t)step->value);