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-rw-r--r--src/arch/riscv/Kconfig14
-rw-r--r--src/arch/riscv/Makefile.inc12
-rw-r--r--src/soc/lowrisc/lowrisc/Kconfig12
-rw-r--r--src/soc/sifive/fu540/Kconfig12
-rw-r--r--src/soc/ucb/riscv/Kconfig12
5 files changed, 50 insertions, 12 deletions
diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig
index 2513c50030..916e269b32 100644
--- a/src/arch/riscv/Kconfig
+++ b/src/arch/riscv/Kconfig
@@ -2,12 +2,14 @@ config ARCH_RISCV
bool
default n
-config ARCH_RISCV_COMPRESSED
- bool
- default n
- help
- Enable this option if your RISC-V processor supports compressed
- instructions (RVC). Currently, this enables RVC for all stages.
+config RISCV_ARCH
+ string
+
+config RISCV_ABI
+ string
+
+config RISCV_CODEMODEL
+ string
config ARCH_BOOTBLOCK_RISCV
bool
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 4b2ff035d7..90e4240468 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -23,15 +23,15 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)
check-ramstage-overlap-regions += stack
endif
-riscv_arch = rv64imafd
+riscv_flags = -I$(src)/arch/riscv/ -mcmodel=$(CONFIG_RISCV_CODEMODEL) -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI)
-ifeq ($(CONFIG_ARCH_RISCV_COMPRESSED),y)
- riscv_arch := $(riscv_arch)c
-endif
+riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI)
+
+COMPILER_RT_bootblock = $(shell $(GCC_bootblock) $(riscv_flags) -print-libgcc-file-name)
-riscv_flags = -I$(src)/arch/riscv/ -mcmodel=medany -march=$(riscv_arch)
+COMPILER_RT_romstage = $(shell $(GCC_romstage) $(riscv_flags) -print-libgcc-file-name)
-riscv_asm_flags = -march=$(riscv_arch)
+COMPILER_RT_ramstage = $(shell $(GCC_ramstage) $(riscv_flags) -print-libgcc-file-name)
################################################################################
## bootblock
diff --git a/src/soc/lowrisc/lowrisc/Kconfig b/src/soc/lowrisc/lowrisc/Kconfig
index 528e7444f7..71078b5c25 100644
--- a/src/soc/lowrisc/lowrisc/Kconfig
+++ b/src/soc/lowrisc/lowrisc/Kconfig
@@ -11,4 +11,16 @@ config SOC_LOWRISC_LOWRISC
if SOC_LOWRISC_LOWRISC
+config RISCV_ARCH
+ string
+ default "rv64imafd"
+
+config RISCV_ABI
+ string
+ default "lp64d"
+
+config RISCV_CODEMODEL
+ string
+ default "medany"
+
endif
diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig
index d247c280b5..c438a10162 100644
--- a/src/soc/sifive/fu540/Kconfig
+++ b/src/soc/sifive/fu540/Kconfig
@@ -23,4 +23,16 @@ config SOC_SIFIVE_FU540
if SOC_SIFIVE_FU540
+config RISCV_ARCH
+ string
+ default "rv64imac"
+
+config RISCV_ABI
+ string
+ default "lp64"
+
+config RISCV_CODEMODEL
+ string
+ default "medany"
+
endif
diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig
index ff50f6f835..2a73f5c284 100644
--- a/src/soc/ucb/riscv/Kconfig
+++ b/src/soc/ucb/riscv/Kconfig
@@ -10,4 +10,16 @@ config SOC_UCB_RISCV
if SOC_UCB_RISCV
+config RISCV_ARCH
+ string
+ default "rv64imafd"
+
+config RISCV_ABI
+ string
+ default "lp64d"
+
+config RISCV_CODEMODEL
+ string
+ default "medany"
+
endif