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-rw-r--r--src/include/reset.h3
-rw-r--r--src/soc/intel/common/reset.c11
2 files changed, 13 insertions, 1 deletions
diff --git a/src/include/reset.h b/src/include/reset.h
index 95ba608254..67f58db81f 100644
--- a/src/include/reset.h
+++ b/src/include/reset.h
@@ -10,5 +10,6 @@ void soft_reset(void);
void cpu_reset(void);
/* Some Intel SoCs use a special reset that is specific to SoC */
void global_reset(void);
-
+/* Some Intel SoCs may need to prepare/wait before reset */
+void reset_prepare(void);
#endif
diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c
index 79547c6edb..08f36b6560 100644
--- a/src/soc/intel/common/reset.c
+++ b/src/soc/intel/common/reset.c
@@ -25,8 +25,17 @@
#define RST_CPU (1 << 2)
#define SYS_RST (1 << 1)
+#ifdef __ROMCC__
+#define WEAK
+#else
+#define WEAK __attribute__((weak))
+#endif
+
+void WEAK reset_prepare(void) { /* do nothing */ }
+
void hard_reset(void)
{
+ reset_prepare();
/* S0->S5->S0 trip. */
outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
while (1)
@@ -35,6 +44,7 @@ void hard_reset(void)
void soft_reset(void)
{
+ reset_prepare();
/* PMC_PLTRST# asserted. */
outb(RST_CPU | SYS_RST, RST_CNT);
while (1)
@@ -43,6 +53,7 @@ void soft_reset(void)
void cpu_reset(void)
{
+ reset_prepare();
/* Sends INIT# to CPU */
outb(RST_CPU, RST_CNT);
while (1)