diff options
| -rw-r--r-- | src/mainboard/lenovo/x60/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/devicetree.cb | 18 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/mainboard.c | 13 |
3 files changed, 32 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 3b39ed8fe7..69f83a8b24 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_NSC_PC87392 select EC_LENOVO_PMH7 select EC_LENOVO_H8 + select DRIVERS_ICS_954309 select BOARD_HAS_FADT select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 55e0b2d499..000f9c7995 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -60,6 +60,8 @@ chip northbridge/intel/i945 register "gpe0_en" = "0x11000006" register "alt_gp_smi_en" = "0x1000" + + register "c4onc3_enable" = "1" device pci 1b.0 on # Audio Cnotroller subsystemid 0x17aa 0x2010 end @@ -174,6 +176,22 @@ chip northbridge/intel/i945 end device pci 1f.3 on # SMBUS subsystemid 0x17aa 0x200f + chip drivers/ics/954309 + register "reg0" = "0x2e" + register "reg1" = "0xf7" + register "reg2" = "0x3c" + register "reg3" = "0x20" + register "reg4" = "0x01" + register "reg5" = "0x00" + register "reg6" = "0x1b" + register "reg7" = "0x01" + register "reg8" = "0x54" + register "reg9" = "0xff" + register "reg10" = "0xff" + register "reg11" = "0x07" + device i2c 69 on end + end + end end chip southbridge/ricoh/rl5c476 diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index e59b2e492f..5bc1dcae81 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -36,6 +36,19 @@ #include <northbridge/intel/i945/i945.h> #include <pc80/mc146818rtc.h> #include "dock.h" +#include <arch/x86/include/arch/acpigen.h> + +static struct cst_entry cst_entries[] = { + { 0x7f, 1, 2, 0, 1, 1, 1, 1000 }, + { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 2, 1, 500 }, + { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 2, 17, 250 }, +}; + +int get_cst_entries(struct cst_entry **entries) +{ + *entries = cst_entries; + return ARRAY_SIZE(cst_entries); +} static void mainboard_enable(device_t dev) { |