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-rw-r--r--src/mainboard/google/drallion/romstage.c9
-rw-r--r--src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h4
-rw-r--r--src/mainboard/google/drallion/variants/drallion/memory.c46
3 files changed, 58 insertions, 1 deletions
diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c
index c9f009e599..03bc17f185 100644
--- a/src/mainboard/google/drallion/romstage.c
+++ b/src/mainboard/google/drallion/romstage.c
@@ -58,11 +58,18 @@ static const struct cnl_mb_cfg memcfg = {
.vref_ca_config = 2,
};
+const struct cnl_mb_cfg * __weak get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg)
+{
+ return &memcfg;
+}
+
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
+ struct cnl_mb_cfg board_memcfg;
+
variant_mainboard_post_init_params(memupd);
wilco_ec_romstage_init();
- cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+ cannonlake_memcfg_init(&memupd->FspmConfig, get_variant_memory_cfg(&board_memcfg));
}
diff --git a/src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h
index 1edd660bbe..eb1d9aec48 100644
--- a/src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h
@@ -17,7 +17,11 @@
#define BASEBOARD_VARIANTS_H
#include <fsp/api.h>
+#include <soc/cnl_memcfg_init.h>
void variant_mainboard_post_init_params(FSPM_UPD *mupd);
+/* Return board specific memory configuration */
+const struct cnl_mb_cfg *get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg);
+
#endif /* BASEBOARD_VARIANTS_H */
diff --git a/src/mainboard/google/drallion/variants/drallion/memory.c b/src/mainboard/google/drallion/variants/drallion/memory.c
index c837805016..10996a3e7b 100644
--- a/src/mainboard/google/drallion/variants/drallion/memory.c
+++ b/src/mainboard/google/drallion/variants/drallion/memory.c
@@ -16,6 +16,8 @@
#include <variant/variant.h>
#include <gpio.h>
#include <variant/gpio.h>
+#include <baseboard/variants.h>
+#include <string.h>
/* Use spd_index array to save mem_id */
static const int spd_index[32] = {
@@ -25,6 +27,50 @@ static const int spd_index[32] = {
5, 0, 7, 2, 0, 0, 0, 0
};
+const struct cnl_mb_cfg *get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg)
+{
+ int mem_sku;
+ struct cnl_mb_cfg baseboard_memcfg = {
+ /*
+ * The dqs_map arrays map the ddr4 pins to the SoC pins
+ * for both channels.
+ *
+ * the index = pin number on ddr4 part
+ * the value = pin number on SoC
+ */
+ .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 },
+ .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 },
+
+ /* Baseboard uses 120, 81 and 100 rcomp resistors */
+ .rcomp_resistor = { 120, 81, 100 },
+
+ /* Baseboard Rcomp target values */
+ .rcomp_targets = { 100, 40, 20, 20, 26 },
+
+ /* Set CaVref config to 2 */
+ .vref_ca_config = 2,
+
+ /* Enable Early Command Training */
+ .ect = 1,
+ };
+
+ mem_sku = variant_memory_sku();
+
+ memcpy(mem_cfg, &baseboard_memcfg, sizeof(baseboard_memcfg));
+
+ /* In Drallion dual channel is enabled by default.
+ * spd[0]-spd[3] map to CH0D0, CH0D1, CH1D0, Ch1D1 respectively.
+ * Dual-DIMM memory is not used in drallion family, so we only
+ * fill in spd info for CH0D0 and CH1D0 here.
+ */
+ for (int i = 0; i < 3; i = i+2) {
+ mem_cfg->spd[i].read_type = READ_SPD_CBFS;
+ mem_cfg->spd[i].spd_spec.spd_index = mem_sku;
+ }
+
+ return mem_cfg;
+}
+
int variant_memory_sku(void)
{
gpio_t spd_gpios[] = {