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-rw-r--r--src/cpu/intel/model_206ax/Makefile.inc1
-rw-r--r--src/cpu/intel/model_206ax/cache_as_ram.inc10
-rw-r--r--src/northbridge/intel/sandybridge/romstage.c5
3 files changed, 13 insertions, 3 deletions
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 6042991ef4..25f07425dd 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -10,3 +10,4 @@ cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
+romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index 56feab994e..0dc3cab1dd 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -172,7 +172,12 @@ clear_mtrrs:
before_romstage:
post_code(0x29)
/* Call romstage.c main function. */
- call main
+ call romstage_main
+
+ /* Save return value from romstage_main. It contains the stack to use
+ * after cache-as-ram is torn down.
+ */
+ movl %eax, %ebx
post_code(0x2f)
@@ -303,7 +308,8 @@ __main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
- movl $CONFIG_RAMTOP, %esp
+ /* Setup stack as indicated by return value from romstage_main(). */
+ movl %ebx, %esp
movl %esp, %ebp
call copy_and_run
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index df0c5bbba5..a2ca1c1835 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -43,7 +43,10 @@ static void early_pch_init(void)
pci_write_config8(PCH_LPC_DEV, 0xa4, reg8);
}
-void main(unsigned long bist)
+/* Platform has no romstage entry point under mainboard directory,
+ * so this one is named with prefix mainboard.
+ */
+void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0;