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-rw-r--r--src/soc/intel/cannonlake/bootblock/pch.c5
-rw-r--r--src/soc/intel/icelake/bootblock/pch.c5
-rw-r--r--src/soc/intel/skylake/bootblock/pch.c6
-rw-r--r--src/soc/intel/tigerlake/bootblock/pch.c5
4 files changed, 21 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index a6e9f9db52..e7b79a0a68 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -172,6 +172,11 @@ void pch_early_iorange_init(void)
* value program in LPC PCI offset 82h.
*/
pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
+ /*
+ * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same
+ * value programmed in LPC PCI offset 80h.
+ */
+ pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode());
}
/* Program generic IO Decode Range */
diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c
index fd2ffd2c88..b1309a45b0 100644
--- a/src/soc/intel/icelake/bootblock/pch.c
+++ b/src/soc/intel/icelake/bootblock/pch.c
@@ -144,6 +144,11 @@ void pch_early_iorange_init(void)
* value program in ESPI PCI offset 82h.
*/
pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
+ /*
+ * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same
+ * value programmed in LPC PCI offset 80h.
+ */
+ pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode());
}
/* Program generic IO Decode Range */
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index ddf1139aa0..7763cf0033 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -140,6 +140,12 @@ void pch_early_iorange_init(void)
* value program in LPC PCI offset 82h.
*/
pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
+ /*
+ * As per PCH BWG 2.5.1.5.
+ * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same
+ * value programmed in LPC PCI offset 80h.
+ */
+ pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode());
}
/* Program generic IO Decode Range */
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index cd264d682c..33637e9e01 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -169,6 +169,11 @@ void pch_early_iorange_init(void)
* value program in ESPI PCI offset 82h.
*/
pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
+ /*
+ * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same
+ * value programmed in LPC PCI offset 80h.
+ */
+ pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode());
}
/* Program generic IO Decode Range */