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-rw-r--r--src/soc/intel/skylake/include/soc/pm.h1
-rw-r--r--src/soc/intel/skylake/include/soc/smm.h2
-rw-r--r--src/soc/intel/skylake/pmutil.c3
-rw-r--r--src/soc/intel/skylake/smi.c3
-rw-r--r--src/soc/intel/skylake/smihandler.c7
5 files changed, 14 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index ede3efb982..0045fa04e8 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -46,6 +46,7 @@
#define SMI_EN 0x30
#define XHCI_SMI_EN (1 << 31)
#define ME_SMI_EN (1 << 30)
+#define ESPI_SMI_EN (1 << 28)
#define GPIO_UNLOCK_SMI_EN (1 << 27)
#define INTEL_USB2_EN (1 << 18)
#define LEGACY_USB2_EN (1 << 17)
diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h
index 1beaaa4986..71083b3cbf 100644
--- a/src/soc/intel/skylake/include/soc/smm.h
+++ b/src/soc/intel/skylake/include/soc/smm.h
@@ -50,6 +50,8 @@ struct smm_relocation_params {
/* Mainboard handler for GPI SMIs*/
void mainboard_smi_gpi_handler(const struct gpi_status *sts);
+/* Mainboard handler for eSPI SMIs */
+void mainboard_smi_espi_handler(void);
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 7d83e9f240..203a430ffa 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -177,7 +177,8 @@ static u32 print_smi_status(u32 smi_sts)
[20] = "PCI_EXP_SMI",
[21] = "MONITOR",
[26] = "SPI",
- [27] = "GPIO_UNLOCK"
+ [27] = "GPIO_UNLOCK",
+ [28] = "ESPI_SMI",
};
if (!smi_sts)
diff --git a/src/soc/intel/skylake/smi.c b/src/soc/intel/skylake/smi.c
index 77f395126a..442607f2e7 100644
--- a/src/soc/intel/skylake/smi.c
+++ b/src/soc/intel/skylake/smi.c
@@ -62,11 +62,12 @@ void southbridge_smm_enable_smi(void)
* - on APMC writes (io 0xb2)
* - on writes to SLP_EN (sleep states)
* - on writes to GBL_RLS (bios commands)
+ * - on eSPI events (does nothing on LPC systems)
* No SMIs:
* - on microcontroller writes (io 0x62/0x66)
* - on TCO events
*/
- enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
+ enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS);
}
void southbridge_trigger_smi(void)
diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c
index 1834815611..872cce1e15 100644
--- a/src/soc/intel/skylake/smihandler.c
+++ b/src/soc/intel/skylake/smihandler.c
@@ -361,6 +361,12 @@ static void southbridge_smi_gpi(void)
gpi_clear_get_smi_status(&smi_sts);
}
+void __attribute__((weak)) mainboard_smi_espi_handler(void) { }
+static void southbridge_smi_espi(void)
+{
+ mainboard_smi_espi_handler();
+}
+
static void southbridge_smi_mc(void)
{
u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN);
@@ -482,6 +488,7 @@ static smi_handler_t southbridge_smi[SMI_STS_BITS] = {
[PM1_STS_BIT] = southbridge_smi_pm1,
[GPE0_STS_BIT] = southbridge_smi_gpe0,
[GPIO_STS_BIT] = southbridge_smi_gpi,
+ [ESPI_SMI_STS_BIT] = southbridge_smi_espi,
[MCSMI_STS_BIT] = southbridge_smi_mc,
[TCO_STS_BIT] = southbridge_smi_tco,
[PERIODIC_STS_BIT] = southbridge_smi_periodic,