summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/southbridge/intel/lynxpoint/Makefile.inc3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index 0358267164..e504db09b7 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -20,8 +20,7 @@
# Run an intermediate step when producing coreboot.rom
# that adds additional components to the final firmware
# image outside of CBFS
-# FIXME, uncomment as soon as we have ME firmware in the blobs repo
-# INTERMEDIATE:=lynxpoint_add_me
+INTERMEDIATE:=lynxpoint_add_me
ramstage-y += pch.c
ramstage-y += azalia.c