diff options
| -rw-r--r-- | src/mainboard/google/chell/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/google/chell/gpio.h | 9 |
2 files changed, 7 insertions, 6 deletions
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index 1a9f423600..599f242c19 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -36,7 +36,7 @@ chip soc/intel/skylake register "Cio2Enable" = "0" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "2" + register "ScsSdCardEnabled" = "0" register "IshEnable" = "0" register "PttSwitch" = "0" register "InternalGfx" = "1" @@ -118,7 +118,7 @@ chip soc/intel/skylake device pci 1e.3 off end # GSPI #1 device pci 1e.4 on end # eMMC device pci 1e.5 off end # SDIO - device pci 1e.6 on end # SDCard + device pci 1e.6 off end # SDCard device pci 1f.0 on chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/google/chell/gpio.h b/src/mainboard/google/chell/gpio.h index c6e07a63f6..f9374d14fa 100644 --- a/src/mainboard/google/chell/gpio.h +++ b/src/mainboard/google/chell/gpio.h @@ -60,10 +60,10 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* PIRQA# */ /* GPP_A7 */ @@ -234,6 +234,7 @@ static const struct pad_config gpio_table[] = { static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ +/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ }; #endif |