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-rw-r--r--src/cpu/x86/mp_init.c27
-rw-r--r--src/include/cpu/x86/mp.h10
2 files changed, 35 insertions, 2 deletions
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index 57a5648ad4..61f153ea3d 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -138,14 +138,37 @@ struct cpu_map {
/* Keep track of APIC and device structure for each CPU. */
static struct cpu_map cpus[CONFIG_MAX_CPUS];
-static inline void barrier_wait(atomic_t *b)
+inline void barrier_wait(atomic_t *b)
{
while (atomic_read(b) == 0)
asm ("pause");
mfence();
}
-static inline void release_barrier(atomic_t *b)
+/* Returns 1 if timeout occurs before barier is released.
+ * returns 0 if barrier is released before timeout. */
+int barrier_wait_timeout(atomic_t *b, uint32_t timeout_ms)
+{
+ int timeout = 0;
+ struct mono_time current, end;
+
+ timer_monotonic_get(&current);
+ end = current;
+ mono_time_add_msecs(&end, timeout_ms);
+
+ while ((atomic_read(b) == 0) && (!mono_time_after(&current, &end))) {
+ timer_monotonic_get(&current);
+ asm ("pause");
+ }
+ mfence();
+
+ if (mono_time_after(&current, &end))
+ timeout = 1;
+
+ return timeout;
+}
+
+inline void release_barrier(atomic_t *b)
{
mfence();
atomic_set(b, 1);
diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h
index b9b4d5772c..0671b62551 100644
--- a/src/include/cpu/x86/mp.h
+++ b/src/include/cpu/x86/mp.h
@@ -150,5 +150,15 @@ int mp_park_aps(void);
void smm_initiate_relocation_parallel(void);
/* Send SMI to self with single execution. */
void smm_initiate_relocation(void);
+/* Make a CPU wait until the barrier is released */
+void barrier_wait(atomic_t *b);
+/*
+ * Make a CPU wait until the barrier is released, or timeout occurs
+ * returns 1 if timeout occurs before barier is released.
+ * returns 0 if barrier is released before timeout.
+ */
+int barrier_wait_timeout(atomic_t *b, uint32_t timeout_ms);
+/* Release a barrier so that other CPUs waiting for that barrier can continue */
+void release_barrier(atomic_t *b);
#endif /* _X86_MP_H_ */