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-rw-r--r--src/cpu/x86/32bit/entry32.inc11
1 files changed, 6 insertions, 5 deletions
diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc
index 4e0f3b953a..abb4a97236 100644
--- a/src/cpu/x86/32bit/entry32.inc
+++ b/src/cpu/x86/32bit/entry32.inc
@@ -2,15 +2,16 @@
#include <arch/rom_segs.h>
-/* .section ".rom.text" */
.code32
+
+ /* This is the GDT for the ROM stage part of coreboot. It
+ * is different from the RAM stage GDT which is defined in
+ * c_start.S
+ */
+
.align 4
.globl gdtptr
-
- /* This is the gdt for ROMCC/ASM part of coreboot.
- * It is different from the gdt in GCC part of coreboot
- * which is defined in c_start.S */
gdt:
gdtptr:
.word gdt_end - gdt -1 /* compute the table limit */