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-rw-r--r--src/drivers/pc80/mc146818rtc.c142
-rw-r--r--src/include/pc80/mc146818rtc.h4
-rw-r--r--src/northbridge/via/cx700/lpc.c2
-rw-r--r--src/northbridge/via/vx800/lpc.c2
-rw-r--r--src/soc/intel/baytrail/southcluster.c2
-rw-r--r--src/soc/intel/fsp_baytrail/romstage/romstage.c2
-rw-r--r--src/southbridge/amd/agesa/hudson/lpc.c8
-rw-r--r--src/southbridge/amd/amd8111/lpc.c2
-rw-r--r--src/southbridge/amd/cimx/sb700/late.c8
-rw-r--r--src/southbridge/amd/cimx/sb800/late.c8
-rw-r--r--src/southbridge/amd/cimx/sb900/late.c8
-rw-r--r--src/southbridge/amd/cs5536/cs5536.c2
-rw-r--r--src/southbridge/amd/sb600/lpc.c2
-rw-r--r--src/southbridge/amd/sb600/sm.c2
-rw-r--r--src/southbridge/amd/sb700/lpc.c2
-rw-r--r--src/southbridge/amd/sb700/sm.c2
-rw-r--r--src/southbridge/amd/sb800/lpc.c2
-rw-r--r--src/southbridge/amd/sb800/sm.c2
-rw-r--r--src/southbridge/broadcom/bcm5785/lpc.c2
-rw-r--r--src/southbridge/dmp/vortex86ex/southbridge.c2
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c2
-rw-r--r--src/southbridge/intel/esb6300/lpc.c2
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/lpc.c2
-rw-r--r--src/southbridge/intel/fsp_rangeley/early_init.c2
-rw-r--r--src/southbridge/intel/i3100/lpc.c2
-rw-r--r--src/southbridge/intel/i82371eb/isa.c2
-rw-r--r--src/southbridge/intel/i82801ax/lpc.c2
-rw-r--r--src/southbridge/intel/i82801bx/lpc.c2
-rw-r--r--src/southbridge/intel/i82801cx/lpc.c2
-rw-r--r--src/southbridge/intel/i82801dx/lpc.c2
-rw-r--r--src/southbridge/intel/i82801ex/lpc.c2
-rw-r--r--src/southbridge/intel/i82801gx/lpc.c2
-rw-r--r--src/southbridge/intel/i82801ix/lpc.c2
-rw-r--r--src/southbridge/intel/ibexpeak/lpc.c2
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c2
-rw-r--r--src/southbridge/nvidia/ck804/lpc.c2
-rw-r--r--src/southbridge/nvidia/mcp55/lpc.c2
-rw-r--r--src/southbridge/sis/sis966/lpc.c2
-rw-r--r--src/southbridge/via/vt8231/lpc.c2
-rw-r--r--src/southbridge/via/vt8235/lpc.c2
-rw-r--r--src/southbridge/via/vt8237r/lpc.c2
41 files changed, 125 insertions, 123 deletions
diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c
index c54f6cefa5..9670e9ce6b 100644
--- a/src/drivers/pc80/mc146818rtc.c
+++ b/src/drivers/pc80/mc146818rtc.c
@@ -10,7 +10,8 @@
#endif
#include <arch/acpi.h>
-static void rtc_update_cmos_date(u8 has_century)
+
+static void cmos_update_date(u8 has_century)
{
/* Now setup a default date equals to the build date */
cmos_write(0, RTC_CLK_SECOND);
@@ -24,28 +25,27 @@ static void rtc_update_cmos_date(u8 has_century)
}
#if CONFIG_USE_OPTION_TABLE
-static int rtc_checksum_valid(int range_start, int range_end, int cks_loc)
+static int cmos_checksum_valid(int range_start, int range_end, int cks_loc)
{
int i;
u16 sum, old_sum;
sum = 0;
- for(i = range_start; i <= range_end; i++) {
+ for (i = range_start; i <= range_end; i++)
sum += cmos_read(i);
- }
- old_sum = ((cmos_read(cks_loc)<<8) | cmos_read(cks_loc+1))&0x0ffff;
+ old_sum = ((cmos_read(cks_loc) << 8) | cmos_read(cks_loc + 1)) &
+ 0x0ffff;
return sum == old_sum;
}
-static void rtc_set_checksum(int range_start, int range_end, int cks_loc)
+static void cmos_set_checksum(int range_start, int range_end, int cks_loc)
{
int i;
u16 sum;
sum = 0;
- for(i = range_start; i <= range_end; i++) {
+ for (i = range_start; i <= range_end; i++)
sum += cmos_read(i);
- }
cmos_write(((sum >> 8) & 0x0ff), cks_loc);
- cmos_write(((sum >> 0) & 0x0ff), cks_loc+1);
+ cmos_write(((sum >> 0) & 0x0ff), cks_loc + 1);
}
#endif
@@ -60,7 +60,7 @@ static void rtc_set_checksum(int range_start, int range_end, int cks_loc)
#endif
#ifndef __SMM__
-void rtc_init(int invalid)
+void cmos_init(int invalid)
{
int cmos_invalid = 0;
int checksum_invalid = 0;
@@ -87,7 +87,7 @@ void rtc_init(int invalid)
cmos_invalid = !(x & RTC_VRT);
/* See if there is a CMOS checksum error */
- checksum_invalid = !rtc_checksum_valid(PC_CKS_RANGE_START,
+ checksum_invalid = !cmos_checksum_valid(PC_CKS_RANGE_START,
PC_CKS_RANGE_END,PC_CKS_LOC);
#define CLEAR_CMOS 0
@@ -102,13 +102,11 @@ void rtc_init(int invalid)
cmos_write(0, 0x01);
cmos_write(0, 0x03);
cmos_write(0, 0x05);
- for(i = 10; i < 128; i++) {
+ for (i = 10; i < 128; i++)
cmos_write(0, i);
- }
#endif
- if (cmos_invalid) {
- rtc_update_cmos_date(RTC_HAS_NO_ALTCENTURY);
- }
+ if (cmos_invalid)
+ cmos_update_date(RTC_HAS_NO_ALTCENTURY);
printk(BIOS_WARNING, "RTC:%s%s%s%s\n",
invalid?" Clear requested":"",
@@ -126,30 +124,29 @@ void rtc_init(int invalid)
#if CONFIG_USE_OPTION_TABLE
/* See if there is a LB CMOS checksum error */
- checksum_invalid = !rtc_checksum_valid(LB_CKS_RANGE_START,
+ checksum_invalid = !cmos_checksum_valid(LB_CKS_RANGE_START,
LB_CKS_RANGE_END,LB_CKS_LOC);
- if(checksum_invalid)
+ if (checksum_invalid)
printk(BIOS_DEBUG, "RTC: coreboot checksum invalid\n");
/* Make certain we have a valid checksum */
- rtc_set_checksum(PC_CKS_RANGE_START,
- PC_CKS_RANGE_END,PC_CKS_LOC);
+ cmos_set_checksum(PC_CKS_RANGE_START, PC_CKS_RANGE_END, PC_CKS_LOC);
#endif
/* Clear any pending interrupts */
- (void) cmos_read(RTC_INTR_FLAGS);
+ cmos_read(RTC_INTR_FLAGS);
}
#endif
#if CONFIG_USE_OPTION_TABLE
-/* This routine returns the value of the requested bits
- input bit = bit count from the beginning of the cmos image
- length = number of bits to include in the value
- ret = a character pointer to where the value is to be returned
- output the value placed in ret
- returns CB_SUCCESS = successful, cb_err code if an error occurred
-*/
+/*
+ * This routine returns the value of the requested bits.
+ * input bit = bit count from the beginning of the cmos image
+ * length = number of bits to include in the value
+ * ret = a character pointer to where the value is to be returned
+ * returns CB_SUCCESS = successful, cb_err code if an error occurred
+ */
static enum cb_err get_cmos_value(unsigned long bit, unsigned long length,
void *vret)
{
@@ -158,21 +155,22 @@ static enum cb_err get_cmos_value(unsigned long bit, unsigned long length,
unsigned long i;
unsigned char uchar;
- /* The table is checked when it is built to ensure all
- values are valid. */
+ /*
+ * The table is checked when it is built to ensure all
+ * values are valid.
+ */
ret = vret;
- byte=bit/8; /* find the byte where the data starts */
- byte_bit=bit%8; /* find the bit in the byte where the data starts */
- if(length<9) { /* one byte or less */
+ byte = bit / 8; /* find the byte where the data starts */
+ byte_bit = bit % 8; /* find the bit in the byte where the data starts */
+ if (length < 9) { /* one byte or less */
uchar = cmos_read(byte); /* load the byte */
uchar >>= byte_bit; /* shift the bits to byte align */
/* clear unspecified bits */
- ret[0] = uchar & ((1 << length) -1);
- }
- else { /* more that one byte so transfer the whole bytes */
- for(i=0;length;i++,length-=8,byte++) {
+ ret[0] = uchar & ((1 << length) - 1);
+ } else { /* more that one byte so transfer the whole bytes */
+ for (i = 0; length; i++, length -= 8, byte++) {
/* load the byte */
- ret[i]=cmos_read(byte);
+ ret[i] = cmos_read(byte);
}
}
return CB_SUCCESS;
@@ -183,7 +181,7 @@ enum cb_err get_option(void *dest, const char *name)
struct cmos_option_table *ct;
struct cmos_entries *ce;
size_t namelen;
- int found=0;
+ int found = 0;
/* Figure out how long name is */
namelen = strnlen(name, CMOS_MAX_NAME_LENGTH);
@@ -196,22 +194,22 @@ enum cb_err get_option(void *dest, const char *name)
"Options are disabled\n");
return CB_CMOS_LAYOUT_NOT_FOUND;
}
- ce=(struct cmos_entries*)((unsigned char *)ct + ct->header_length);
- for(;ce->tag==LB_TAG_OPTION;
- ce=(struct cmos_entries*)((unsigned char *)ce + ce->size)) {
+ ce = (struct cmos_entries*)((unsigned char *)ct + ct->header_length);
+ for(; ce->tag == LB_TAG_OPTION;
+ ce = (struct cmos_entries*)((unsigned char *)ce + ce->size)) {
if (memcmp(ce->name, name, namelen) == 0) {
- found=1;
+ found = 1;
break;
}
}
- if(!found) {
+ if (!found) {
printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name);
return CB_CMOS_OPTION_NOT_FOUND;
}
- if(get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS)
+ if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS)
return CB_CMOS_ACCESS_ERROR;
- if(!rtc_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END,LB_CKS_LOC))
+ if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC))
return CB_CMOS_CHECKSUM_INVALID;
return CB_SUCCESS;
}
@@ -226,9 +224,9 @@ static enum cb_err set_cmos_value(unsigned long bit, unsigned long length,
unsigned int chksum_update_needed = 0;
ret = vret;
- byte = bit / 8; /* find the byte where the data starts */
- byte_bit = bit % 8; /* find the bit in the byte where the data starts */
- if(length <= 8) { /* one byte or less */
+ byte = bit / 8; /* find the byte where the data starts */
+ byte_bit = bit % 8; /* find the bit where the data starts */
+ if (length <= 8) { /* one byte or less */
mask = (1 << length) - 1;
mask <<= byte_bit;
@@ -238,19 +236,20 @@ static enum cb_err set_cmos_value(unsigned long bit, unsigned long length,
cmos_write(uchar, byte);
if (byte >= LB_CKS_RANGE_START && byte <= LB_CKS_RANGE_END)
chksum_update_needed = 1;
- } else { /* more that one byte so transfer the whole bytes */
+ } else { /* more that one byte so transfer the whole bytes */
if (byte_bit || length % 8)
return CB_ERR_ARG;
- for(i=0; length; i++, length-=8, byte++)
+ for (i = 0; length; i++, length -= 8, byte++)
cmos_write(ret[i], byte);
- if (byte >= LB_CKS_RANGE_START && byte <= LB_CKS_RANGE_END)
+ if (byte >= LB_CKS_RANGE_START &&
+ byte <= LB_CKS_RANGE_END)
chksum_update_needed = 1;
}
if (chksum_update_needed) {
- rtc_set_checksum(LB_CKS_RANGE_START,
- LB_CKS_RANGE_END,LB_CKS_LOC);
+ cmos_set_checksum(LB_CKS_RANGE_START, LB_CKS_RANGE_END,
+ LB_CKS_LOC);
}
return CB_SUCCESS;
}
@@ -262,7 +261,7 @@ enum cb_err set_option(const char *name, void *value)
struct cmos_entries *ce;
unsigned long length;
size_t namelen;
- int found=0;
+ int found = 0;
/* Figure out how long name is */
namelen = strnlen(name, CMOS_MAX_NAME_LENGTH);
@@ -271,18 +270,19 @@ enum cb_err set_option(const char *name, void *value)
ct = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "cmos_layout.bin",
CBFS_COMPONENT_CMOS_LAYOUT, NULL);
if (!ct) {
- printk(BIOS_ERR, "cmos_layout.bin could not be found. Options are disabled\n");
+ printk(BIOS_ERR, "cmos_layout.bin could not be found. "
+ "Options are disabled\n");
return CB_CMOS_LAYOUT_NOT_FOUND;
}
- ce=(struct cmos_entries*)((unsigned char *)ct + ct->header_length);
- for(;ce->tag==LB_TAG_OPTION;
- ce=(struct cmos_entries*)((unsigned char *)ce + ce->size)) {
+ ce = (struct cmos_entries*)((unsigned char *)ct + ct->header_length);
+ for(; ce->tag == LB_TAG_OPTION;
+ ce = (struct cmos_entries*)((unsigned char *)ce + ce->size)) {
if (memcmp(ce->name, name, namelen) == 0) {
- found=1;
+ found = 1;
break;
}
}
- if(!found) {
+ if (!found) {
printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name);
return CB_CMOS_OPTION_NOT_FOUND;
}
@@ -308,17 +308,19 @@ enum cb_err set_option(const char *name, void *value)
* hurts some OSes. Even if we don't set USE_OPTION_TABLE, we need
* to make sure the date is valid.
*/
-void rtc_check_update_cmos_date(u8 has_century)
+void cmos_check_update_date(u8 has_century)
{
u8 year, century;
- /* Note: We need to check if the hardware supports RTC_CLK_ALTCENTURY. */
- century = has_century ? cmos_read(RTC_CLK_ALTCENTURY) : 0;
- year = cmos_read(RTC_CLK_YEAR);
+ /* Note: Need to check if the hardware supports RTC_CLK_ALTCENTURY. */
+ century = has_century ? cmos_read(RTC_CLK_ALTCENTURY) : 0;
+ year = cmos_read(RTC_CLK_YEAR);
- /* TODO: If century is 0xFF, 100% that the cmos is cleared.
- * Other than that, so far rtc_year is the only entry to check if the date is valid. */
- if (century > 0x99 || year > 0x99) { /* Invalid date */
- rtc_update_cmos_date(has_century);
- }
+ /*
+ * TODO: If century is 0xFF, 100% that the cmos is cleared.
+ * Other than that, so far rtc_year is the only entry to check
+ * if the date is valid.
+ */
+ if (century > 0x99 || year > 0x99) /* Invalid date */
+ cmos_update_date(has_century);
}
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index a4018219f8..3d65909faf 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -172,8 +172,8 @@ static inline void cmos_write32(u8 offset, u32 value)
#endif
#if !defined(__ROMCC__)
-void rtc_init(int invalid);
-void rtc_check_update_cmos_date(u8 has_century);
+void cmos_init(int invalid);
+void cmos_check_update_date(u8 has_century);
#if CONFIG_USE_OPTION_TABLE
enum cb_err set_option(const char *name, void *val);
enum cb_err get_option(void *dest, const char *name);
diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c
index c09fbb4968..da3e2cef1b 100644
--- a/src/northbridge/via/cx700/lpc.c
+++ b/src/northbridge/via/cx700/lpc.c
@@ -283,7 +283,7 @@ static void cx700_lpc_init(struct device *dev)
setup_i8259();
/* Start the Real Time Clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c
index 1908a8a4ae..c2a8a1dd39 100644
--- a/src/northbridge/via/vx800/lpc.c
+++ b/src/northbridge/via/vx800/lpc.c
@@ -295,7 +295,7 @@ static void vx800_sb_init(struct device *dev)
pci_write_config8(dev, 0x40, 0x54);
// Start the rtc
- rtc_init(0);
+ cmos_init(0);
}
/* total kludge to get lxb to call our childrens set/enable functions - these are
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index 261c95ae1d..500a13d1e2 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -143,7 +143,7 @@ static void sc_rtc_init(void)
printk(BIOS_DEBUG, "RTC failure.\n");
}
- rtc_init(rtc_fail);
+ cmos_init(rtc_fail);
}
/*
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index 0c72b98d50..cd3cd90d21 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -151,7 +151,7 @@ static void baytrail_rtc_init(void)
write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS);
}
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
/* Entry from cache-as-ram.inc. */
diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c
index 20212ef223..1f60bc4ed9 100644
--- a/src/southbridge/amd/agesa/hudson/lpc.c
+++ b/src/southbridge/amd/agesa/hudson/lpc.c
@@ -70,14 +70,14 @@ static void lpc_init(device_t dev)
byte |= 1 << 0 | 1 << 3;
pci_write_config8(dev, 0xBB, byte);
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
/* Initialize the real time clock.
- * The 0 argument tells rtc_init not to
+ * The 0 argument tells cmos_init not to
* update CMOS unless it is invalid.
- * 1 tells rtc_init to always initialize the CMOS.
+ * 1 tells cmos_init to always initialize the CMOS.
*/
- rtc_init(0);
+ cmos_init(0);
}
static void hudson_lpc_read_resources(device_t dev)
diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c
index 8cabcab842..718b40bf9d 100644
--- a/src/southbridge/amd/amd8111/lpc.c
+++ b/src/southbridge/amd/amd8111/lpc.c
@@ -77,7 +77,7 @@ static void lpc_init(struct device *dev)
}
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index 42330ca1e9..20da0733f0 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -80,14 +80,14 @@ static void lpc_init(device_t dev)
{
printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - Start.\n");
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
/* Initialize the real time clock.
- * The 0 argument tells rtc_init not to
+ * The 0 argument tells cmos_init not to
* update CMOS unless it is invalid.
- * 1 tells rtc_init to always initialize the CMOS.
+ * 1 tells cmos_init to always initialize the CMOS.
*/
- rtc_init(0);
+ cmos_init(0);
setup_i8259(); /* Initialize i8259 pic */
setup_i8254(); /* Initialize i8254 timers */
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index b132bf17d0..7d6e221a6f 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -132,14 +132,14 @@ static void lpc_init(device_t dev)
{
printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n");
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
/* Initialize the real time clock.
- * The 0 argument tells rtc_init not to
+ * The 0 argument tells cmos_init not to
* update CMOS unless it is invalid.
- * 1 tells rtc_init to always initialize the CMOS.
+ * 1 tells cmos_init to always initialize the CMOS.
*/
- rtc_init(0);
+ cmos_init(0);
setup_i8259(); /* Initialize i8259 pic */
setup_i8254(); /* Initialize i8254 timers */
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
index 7303bdceba..8d9b486831 100644
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
@@ -102,14 +102,14 @@ static void lpc_init(device_t dev)
printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n");
/* SB Configure HPET base and enable bit */
//- hpetInit(sb_config, &(sb_config->BuildParameters));
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
/* Initialize the real time clock.
- * The 0 argument tells rtc_init not to
+ * The 0 argument tells cmos_init not to
* update CMOS unless it is invalid.
- * 1 tells rtc_init to always initialize the CMOS.
+ * 1 tells cmos_init to always initialize the CMOS.
*/
- rtc_init(0);
+ cmos_init(0);
setup_i8259(); /* Initialize i8259 pic */
setup_i8254(); /* Initialize i8254 timers */
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index e305594b7f..1f7eab87ad 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -245,7 +245,7 @@ static void lpc_init(struct southbridge_amd_cs5536_config *sb)
msr.lo = RTC_MONA;
wrmsr(MDD_RTC_MONA_IND, msr);
- rtc_init(0);
+ cmos_init(0);
isa_dma_init();
}
diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c
index 7f1ca2597a..d8e63b557c 100644
--- a/src/southbridge/amd/sb600/lpc.c
+++ b/src/southbridge/amd/sb600/lpc.c
@@ -63,7 +63,7 @@ static void lpc_init(device_t dev)
byte &= ~(1 << 1);
pci_write_config8(dev, 0x78, byte);
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
}
static void sb600_lpc_read_resources(device_t dev)
diff --git a/src/southbridge/amd/sb600/sm.c b/src/southbridge/amd/sb600/sm.c
index 8de39a6429..a8e72c28f7 100644
--- a/src/southbridge/amd/sb600/sm.c
+++ b/src/southbridge/amd/sb600/sm.c
@@ -169,7 +169,7 @@ static void sm_init(device_t dev)
/* ab index */
pci_write_config32(dev, 0xF0, AB_INDX);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/*3.4 Enabling IDE/PCIB Prefetch for Performance Enhancement */
abcfg_reg(0x10060, 9 << 17, 9 << 17);
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index 6995861a8d..173de8369f 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -90,7 +90,7 @@ static void lpc_init(device_t dev)
}
#endif
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
}
void backup_top_of_ram(uint64_t ramtop)
diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
index 0fb6556f37..8bb5378ff7 100644
--- a/src/southbridge/amd/sb700/sm.c
+++ b/src/southbridge/amd/sb700/sm.c
@@ -197,7 +197,7 @@ static void sm_init(device_t dev)
/* ab index */
pci_write_config32(dev, 0xF0, AB_INDX);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* 4.3 Enabling Upstream DMA Access */
axcfg_reg(0x04, 1 << 2, 1 << 2);
diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c
index 12fd96fbfa..7a4dd831da 100644
--- a/src/southbridge/amd/sb800/lpc.c
+++ b/src/southbridge/amd/sb800/lpc.c
@@ -67,7 +67,7 @@ static void lpc_init(device_t dev)
byte |= 1 << 0 | 1 << 3;
pci_write_config8(dev, 0xBB, byte);
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
}
static void sb800_lpc_read_resources(device_t dev)
diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c
index 315bc20b72..acdfb090a6 100644
--- a/src/southbridge/amd/sb800/sm.c
+++ b/src/southbridge/amd/sb800/sm.c
@@ -111,7 +111,7 @@ static void sm_init(device_t dev)
pm_iowrite(0xE2, (AB_INDX >> 16) & 0xFF);
pm_iowrite(0xE3, (AB_INDX >> 24) & 0xFF);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
byte = pm_ioread(0x8);
byte |= 1 << 2 | 1 << 4;
diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c
index 834f0a1a4b..af79892a7b 100644
--- a/src/southbridge/broadcom/bcm5785/lpc.c
+++ b/src/southbridge/broadcom/bcm5785/lpc.c
@@ -33,7 +33,7 @@
static void lpc_init(device_t dev)
{
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c
index a2b1246c71..d4f263bab1 100644
--- a/src/southbridge/dmp/vortex86ex/southbridge.c
+++ b/src/southbridge/dmp/vortex86ex/southbridge.c
@@ -595,7 +595,7 @@ static void southbridge_init(struct device *dev)
pci_routing_fixup(dev);
fix_cmos_rtc_time();
- rtc_init(0);
+ cmos_init(0);
/* Check keyboard controller ready. If timeout, reload firmware code
* and try again.
*/
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 75b8a6c91e..0e3a4f6466 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -294,7 +294,7 @@ static void pch_rtc_init(struct device *dev)
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
/* CougarPoint PCH Power Management init */
diff --git a/src/southbridge/intel/esb6300/lpc.c b/src/southbridge/intel/esb6300/lpc.c
index 67bcadc961..b5b77efa14 100644
--- a/src/southbridge/intel/esb6300/lpc.c
+++ b/src/southbridge/intel/esb6300/lpc.c
@@ -297,7 +297,7 @@ static void lpc_init(struct device *dev)
esb6300_gpio_init(dev);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c
index 2fc3ea7e7b..e5d63b66db 100644
--- a/src/southbridge/intel/fsp_bd82x6x/lpc.c
+++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c
@@ -305,7 +305,7 @@ static void pch_rtc_init(struct device *dev)
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
/* CougarPoint PCH Power Management init */
diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c
index 0697785b21..bd3d12ccb5 100644
--- a/src/southbridge/intel/fsp_rangeley/early_init.c
+++ b/src/southbridge/intel/fsp_rangeley/early_init.c
@@ -69,7 +69,7 @@ static void reset_rtc(void)
write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS);
}
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
void rangeley_sb_early_initialization(void)
diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c
index 7c79e5879d..ba74f30748 100644
--- a/src/southbridge/intel/i3100/lpc.c
+++ b/src/southbridge/intel/i3100/lpc.c
@@ -375,7 +375,7 @@ static void lpc_init(struct device *dev)
i3100_gpio_init(dev);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index 5605106ddf..5261fbafa3 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -64,7 +64,7 @@ static void isa_init(struct device *dev)
u32 reg32;
/* Initialize the real time clock (RTC). */
- rtc_init(0);
+ cmos_init(0);
/*
* Enable special cycles, needed for soft poweroff.
diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c
index 212c95f270..11519c1fb3 100644
--- a/src/southbridge/intel/i82801ax/lpc.c
+++ b/src/southbridge/intel/i82801ax/lpc.c
@@ -190,7 +190,7 @@ static void i82801ax_rtc_init(struct device *dev)
}
reg32 = pci_read_config32(dev, GEN_STA);
rtc_failed |= reg32 & (1 << 2);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
/* Enable access to the upper 128 byte bank of CMOS RAM. */
pci_write_config8(dev, RTC_CONF, 0x04);
diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c
index 13b15996dc..278d65c3c1 100644
--- a/src/southbridge/intel/i82801bx/lpc.c
+++ b/src/southbridge/intel/i82801bx/lpc.c
@@ -205,7 +205,7 @@ static void i82801bx_rtc_init(struct device *dev)
}
reg32 = pci_read_config32(dev, GEN_STS);
rtc_failed |= reg32 & (1 << 2);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
/* Enable access to the upper 128 byte bank of CMOS RAM. */
pci_write_config8(dev, RTC_CONF, 0x04);
diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c
index f9c0ece4fe..f6c33b7feb 100644
--- a/src/southbridge/intel/i82801cx/lpc.c
+++ b/src/southbridge/intel/i82801cx/lpc.c
@@ -108,7 +108,7 @@ static void i82801cx_rtc_init(struct device *dev)
dword = pci_read_config32(dev, GEN_STS);
rtc_failed |= dword & (1 << 2);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c
index de09b165d6..1b23fad832 100644
--- a/src/southbridge/intel/i82801dx/lpc.c
+++ b/src/southbridge/intel/i82801dx/lpc.c
@@ -200,7 +200,7 @@ static void i82801dx_rtc_init(struct device *dev)
}
reg32 = pci_read_config32(dev, GEN_STS);
rtc_failed |= reg32 & (1 << 2);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
/* Enable access to the upper 128 byte bank of CMOS RAM. */
pci_write_config8(dev, RTC_CONF, 0x04);
diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c
index fb1586eb12..1823e65cf4 100644
--- a/src/southbridge/intel/i82801ex/lpc.c
+++ b/src/southbridge/intel/i82801ex/lpc.c
@@ -308,7 +308,7 @@ static void lpc_init(struct device *dev)
i82801ex_gpio_init(dev);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 80abb78861..10e40be608 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -294,7 +294,7 @@ static void i82801gx_rtc_init(struct device *dev)
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
static void enable_hpet(void)
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 8105a4dc16..664088cd22 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -326,7 +326,7 @@ static void i82801ix_rtc_init(struct device *dev)
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
static void enable_hpet(void)
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 31bb4e7921..a833a3d83a 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -294,7 +294,7 @@ static void pch_rtc_init(struct device *dev)
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
static void mobile5_pm_init(struct device *dev)
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 64b835f870..a2024242c2 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -301,7 +301,7 @@ static void pch_rtc_init(struct device *dev)
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
/* LynxPoint PCH Power Management init */
diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c
index b68785ab76..9b6049c993 100644
--- a/src/southbridge/nvidia/ck804/lpc.c
+++ b/src/southbridge/nvidia/ck804/lpc.c
@@ -162,7 +162,7 @@ static void lpc_init(device_t dev)
outb(byte, 0x70);
/* Initialize the real time clock (RTC). */
- rtc_init(0);
+ cmos_init(0);
/* Initialize ISA DMA. */
isa_dma_init();
diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c
index ef3c6f655e..11c2c4f612 100644
--- a/src/southbridge/nvidia/mcp55/lpc.c
+++ b/src/southbridge/nvidia/mcp55/lpc.c
@@ -152,7 +152,7 @@ static void lpc_init(device_t dev)
outb(byte, 0x70);
/* Initialize the real time clock. */
- rtc_init(0);
+ cmos_init(0);
/* Initialize ISA DMA. */
isa_dma_init();
diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c
index 824bb6a174..0e11c6f9b7 100644
--- a/src/southbridge/sis/sis966/lpc.c
+++ b/src/southbridge/sis/sis966/lpc.c
@@ -148,7 +148,7 @@ static void lpc_init(device_t dev)
}
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/southbridge/via/vt8231/lpc.c b/src/southbridge/via/vt8231/lpc.c
index 40854dbcf7..c6b74fdaa1 100644
--- a/src/southbridge/via/vt8231/lpc.c
+++ b/src/southbridge/via/vt8231/lpc.c
@@ -121,7 +121,7 @@ static void vt8231_init(struct device *dev)
//ethernet_fixup();
// Start the rtc
- rtc_init(0);
+ cmos_init(0);
}
static void vt8231_read_resources(device_t dev)
diff --git a/src/southbridge/via/vt8235/lpc.c b/src/southbridge/via/vt8235/lpc.c
index b355ad0d88..2c7848179a 100644
--- a/src/southbridge/via/vt8235/lpc.c
+++ b/src/southbridge/via/vt8235/lpc.c
@@ -209,7 +209,7 @@ static void vt8235_init(struct device *dev)
pci_write_config8(dev, 0x40, 0x54);
// Start the rtc
- rtc_init(0);
+ cmos_init(0);
}
/* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 5ddd816153..9e8f6f62e5 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -565,7 +565,7 @@ static void vt8237_common_init(struct device *dev)
setup_pm(dev);
/* Start the RTC. */
- rtc_init(0);
+ cmos_init(0);
}
static void vt8237r_read_resources(device_t dev)