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-rw-r--r--src/vendorcode/amd/agesa/f10/Legacy/PlatformMemoryConfiguration.inc383
-rw-r--r--src/vendorcode/amd/agesa/f10/Legacy/Proc/arch2008.asm2670
-rw-r--r--src/vendorcode/amd/agesa/f10/Legacy/agesa.inc2466
-rw-r--r--src/vendorcode/amd/agesa/f10/Legacy/amd.inc461
-rw-r--r--src/vendorcode/amd/agesa/f10/Legacy/bridge32.inc577
-rw-r--r--src/vendorcode/amd/agesa/f10/Lib/IA32/amdlib32.asm624
-rw-r--r--src/vendorcode/amd/agesa/f10/Lib/IA32/ms_shift.asm110
-rw-r--r--src/vendorcode/amd/agesa/f10/Lib/IA32/msmemcpy.asm84
-rw-r--r--src/vendorcode/amd/agesa/f10/Lib/x64/amdlib64.asm569
-rw-r--r--src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD32.asm113
-rw-r--r--src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD64.asm127
-rw-r--r--src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm319
-rw-r--r--src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib32.asm138
-rw-r--r--src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib64.asm143
-rw-r--r--src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mu.asm483
-rw-r--r--src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.asm187
-rw-r--r--src/vendorcode/amd/agesa/f10/cpcarmac.inc406
-rw-r--r--src/vendorcode/amd/agesa/f12/Legacy/PlatformMemoryConfiguration.inc420
-rw-r--r--src/vendorcode/amd/agesa/f12/Legacy/Proc/arch2008.asm2674
-rw-r--r--src/vendorcode/amd/agesa/f12/Legacy/agesa.inc2776
-rw-r--r--src/vendorcode/amd/agesa/f12/Legacy/amd.inc461
-rw-r--r--src/vendorcode/amd/agesa/f12/Legacy/bridge32.inc576
-rw-r--r--src/vendorcode/amd/agesa/f12/cpcarmac.inc452
-rw-r--r--src/vendorcode/amd/agesa/f14/Legacy/PlatformMemoryConfiguration.inc402
-rw-r--r--src/vendorcode/amd/agesa/f14/Legacy/Proc/arch2008.asm2674
-rw-r--r--src/vendorcode/amd/agesa/f14/Legacy/agesa.inc2570
-rw-r--r--src/vendorcode/amd/agesa/f14/Legacy/amd.inc461
-rw-r--r--src/vendorcode/amd/agesa/f14/Legacy/bridge32.inc577
-rw-r--r--src/vendorcode/amd/agesa/f14/Lib/IA32/amdlib32.asm151
-rw-r--r--src/vendorcode/amd/agesa/f14/Lib/IA32/ms_shift.asm110
-rw-r--r--src/vendorcode/amd/agesa/f14/Lib/IA32/msmemcpy.asm84
-rw-r--r--src/vendorcode/amd/agesa/f14/Lib/x64/amdlib64.asm591
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevD32.asm113
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevD64.asm127
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm345
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt64.asm157
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.asm497
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mru.asm187
-rw-r--r--src/vendorcode/amd/agesa/f14/cpcarmac.inc447
-rw-r--r--src/vendorcode/amd/agesa/f15/Legacy/PlatformMemoryConfiguration.inc670
-rw-r--r--src/vendorcode/amd/agesa/f15/Legacy/Proc/arch2008.asm2676
-rw-r--r--src/vendorcode/amd/agesa/f15/Legacy/agesa.inc2989
-rw-r--r--src/vendorcode/amd/agesa/f15/Legacy/amd.inc460
-rw-r--r--src/vendorcode/amd/agesa/f15/Legacy/bridge32.inc575
-rw-r--r--src/vendorcode/amd/agesa/f15/Lib/IA32/amdlib32.asm671
-rw-r--r--src/vendorcode/amd/agesa/f15/Lib/IA32/ms_shift.asm110
-rw-r--r--src/vendorcode/amd/agesa/f15/Lib/IA32/msmemcpy.asm84
-rw-r--r--src/vendorcode/amd/agesa/f15/Lib/x64/amdlib64.asm591
-rw-r--r--src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevD32.asm113
-rw-r--r--src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevD64.asm127
-rw-r--r--src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.asm362
-rw-r--r--src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt64.asm174
-rw-r--r--src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mu.asm497
-rw-r--r--src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mru.asm187
-rw-r--r--src/vendorcode/amd/agesa/f15/cpcarmac.inc457
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Legacy/PlatformMemoryConfiguration.inc688
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Legacy/Proc/arch2008.asm2675
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Legacy/agesa.inc3089
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Legacy/amd.inc461
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Legacy/bridge32.inc576
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Lib/x64/amdlib64.asm602
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt.asm361
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt64.asm173
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib32.asm335
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib64.asm342
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mu.asm496
-rw-r--r--src/vendorcode/amd/agesa/f15tn/cpcarmac.inc456
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Legacy/PlatformMemoryConfiguration.inc701
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Legacy/Proc/arch2008.asm2676
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Legacy/agesa.inc3300
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Legacy/amd.inc462
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Legacy/bridge32.inc576
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/IDS/Control/IdsLib32.asm335
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/IDS/Control/IdsLib64.asm342
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mu.asm496
75 files changed, 0 insertions, 56597 deletions
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/PlatformMemoryConfiguration.inc b/src/vendorcode/amd/agesa/f10/Legacy/PlatformMemoryConfiguration.inc
deleted file mode 100644
index 27e57c1b93..0000000000
--- a/src/vendorcode/amd/agesa/f10/Legacy/PlatformMemoryConfiguration.inc
+++ /dev/null
@@ -1,383 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * AMD Platform Specific Memory Configuration
-; *
-; * Contains AMD AGESA Memory Configuration Override Interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 22910 $ @e \$Date: 2009-11-27 04:50:20 -0600 (Fri, 27 Nov 2009) $
-;
-; ****************************************************************************
-; *
-; * Copyright (c) 2011, Advanced Micro Devices, Inc.
-; * All rights reserved.
-; *
-; * Redistribution and use in source and binary forms, with or without
-; * modification, are permitted provided that the following conditions are met:
-; * * Redistributions of source code must retain the above copyright
-; * notice, this list of conditions and the following disclaimer.
-; * * Redistributions in binary form must reproduce the above copyright
-; * notice, this list of conditions and the following disclaimer in the
-; * documentation and/or other materials provided with the distribution.
-; * * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; * its contributors may be used to endorse or promote products derived
-; * from this software without specific prior written permission.
-; *
-; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; *
-; *
-; **************************************************************************
-IFNDEF PSO_ENTRY
- PSO_ENTRY TEXTEQU <UINT8>; < Platform Configuration Table Entry
-ENDIF
-; *****************************************************************************************
-; *
-; * PLATFORM SPECIFIC MEMORY DEFINITIONS
-; *
-; *****************************************************************************************
-; */
-;
-; < Memory Speed and DIMM Population Masks
-;
-; < DDR Speed Masks
-;
-ANY_SPEED EQU 0FFFFFFFFh
-DDR400 EQU ( 1 SHL (DDR400_FREQUENCY / 66))
-DDR533 EQU ( 1 SHL (DDR533_FREQUENCY / 66))
-DDR667 EQU ( 1 SHL (DDR667_FREQUENCY / 66))
-DDR800 EQU ( 1 SHL (DDR800_FREQUENCY / 66))
-DDR1066 EQU ( 1 SHL (DDR1066_FREQUENCY / 66))
-DDR1333 EQU ( 1 SHL (DDR1333_FREQUENCY / 66))
-DDR1600 EQU ( 1 SHL (DDR1600_FREQUENCY / 66))
-DDR1866 EQU ( 1 SHL (DDR1866_FREQUENCY / 66))
-; <
-; < DIMM POPULATION MASKS
-;
-ANY_ EQU 0FFh
-SR_DIMM0 EQU 0001h
-SR_DIMM1 EQU 0010h
-SR_DIMM2 EQU 0100h
-SR_DIMM3 EQU 1000h
-DR_DIMM0 EQU 0002h
-DR_DIMM1 EQU 0020h
-DR_DIMM2 EQU 0200h
-DR_DIMM3 EQU 2000h
-QR_DIMM0 EQU 0004h
-QR_DIMM1 EQU 0040h
-QR_DIMM2 EQU 0400h
-QR_DIMM3 EQU 4000h
-ANY_DIMM0 EQU 000Fh
-ANY_DIMM1 EQU 00F0h
-ANY_DIMM2 EQU 0F00h
-ANY_DIMM3 EQU 0F000h
-;
-; Number of Dimms
-;
-ANY_NUM EQU 0FFh
-NO_DIMM EQU 00h
-ONE_DIMM EQU 01h
-TWO_DIMM EQU 02h
-THREE_DIMM EQU 04h
-FOUR_DIMM EQU 08h
-; *****************************************************************************************
-; *
-; * Platform Specific Override Definitions for Socket, Channel and Dimm
-; * This indicates where a platform override will be applied.
-; *
-; *****************************************************************************************
-;
-; SOCKET MASKS
-;
-ANY_SOCKET EQU 0FFh
-SOCKET0 EQU 01h
-SOCKET1 EQU 02h
-SOCKET2 EQU 04h
-SOCKET3 EQU 08h
-SOCKET4 EQU 10h
-SOCKET5 EQU 20h
-SOCKET6 EQU 40h
-SOCKET7 EQU 80h
-;
-; CHANNEL MASKS
-;
-ANY_CHANNEL EQU 0FFh
-CHANNEL_A EQU 01h
-CHANNEL_B EQU 02h
-CHANNEL_C EQU 04h
-CHANNEL_D EQU 08h
-;
-; DIMM MASKS
-;
-ALL_DIMMS EQU 0FFh
-DIMM0 EQU 01h
-DIMM1 EQU 02h
-DIMM2 EQU 04h
-DIMM3 EQU 08h
-;
-; REGISTER ACCESS MASKS
-;
-ACCESS_NB0 EQU 0h
-ACCESS_NB1 EQU 01h
-ACCESS_NB2 EQU 02h
-ACCESS_NB3 EQU 03h
-ACCESS_NB4 EQU 04h
-ACCESS_PHY EQU 05h
-ACCESS_DCT_XT EQU 06h
-; *****************************************************************************************
-; *
-; * Platform Specific Overriding Table Definitions
-; *
-; *****************************************************************************************
-PSO_END EQU 0 ; < Table End
-PSO_CKE_TRI EQU 1 ; < CKE Tristate Map
-PSO_ODT_TRI EQU 2 ; < ODT Tristate Map
-PSO_CS_TRI EQU 3 ; < CS Tristate Map
-PSO_MAX_DIMMS EQU 4 ; < Max Dimms per channel
-PSO_CLK_SPEED EQU 5 ; < Clock Speed
-PSO_DIMM_TYPE EQU 6 ; < Dimm Type
-PSO_MEMCLK_DIS EQU 7 ; < MEMCLK Disable Map
-PSO_MAX_CHNLS EQU 8 ; < Max Channels per Socket
-PSO_BUS_SPEED EQU 9 ; < Max Memory Bus Speed
-PSO_MAX_CHIPSELS EQU 10 ; < Max Chipsel per Channel
-PSO_MEM_TECH EQU 11 ; < Channel Memory Type
-PSO_WL_SEED EQU 12 ; < DDR3 Write Levelization Seed delay
-PSO_LVDIMM_VOLT1_5_SUPPORT EQU 16 ; < Force LvDimm voltage to 1.5V
-; **********************************
-; * CONDITIONAL PSO SPECIFIC ENTRIES
-; **********************************
-; Condition Types
-CONDITIONAL_PSO_MIN EQU 100 ; < Start of Conditional Entry Types
-PSO_CONDITION_AND EQU 100 ; < And Block - Start of Conditional block
-PSO_CONDITION_LOC EQU 101 ; < Location - Specify Socket, Channel, Dimms to be affected
-PSO_CONDITION_SPD EQU 102 ; < SPD - Specify a specific SPD value on a Dimm on the channel
-PSO_CONDITION_REG EQU 103 ; Reserved
-PSO_CONDITION_MAX EQU 103 ; < End Of Condition Entry Types
-; Action Types
-PSO_ACTION_MIN EQU 120 ; < Start of Action Entry Types
-PSO_ACTION_ODT EQU 120 ; < ODT values to override
-PSO_ACTION_ADDRTMG EQU 121 ; < Address/Timing values to override
-PSO_ACTION_ODCCONTROL EQU 122 ; < ODC Control values to override
-PSO_ACTION_SLEWRATE EQU 123 ; < Slew Rate value to override
-PSO_ACTION_REG EQU 124 ; Reserved
-PSO_ACTION_SPEEDLIMIT EQU 125 ; < Memory Bus speed Limit based on configuration
-PSO_ACTION_MAX EQU 125 ; < End of Action Entry Types
-CONDITIONAL_PSO_MAX EQU 139 ; < End of Conditional Entry Types
-; *****************************************************************************************
-; *
-; * CONDITIONAL OVERRIDE TABLE MACROS
-; *
-; *****************************************************************************************
-MEMCLK_DIS_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
- DB PSO_MEMCLK_DIS
- DB 10
- DB SocketID
- DB ChannelID
- DB Bit0Map
- DB Bit1Map
- DB Bit2Map
- DB Bit3Map
- DB Bit4Map
- DB Bit5Map
- DB Bit6Map
- DB Bit7Map
-ENDM
-
-CKE_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ
- DB PSO_CKE_TRI
- DB 4
- DB SocketID
- DB ChannelID
- DB Bit0Map
- DB Bit1Map
-ENDM
-
-ODT_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ
- DB PSO_ODT_TRI
- DB 6
- DB SocketID
- DB ChannelID
- DB Bit0Map
- DB Bit1Map
- DB Bit2Map
- DB Bit3Map
-ENDM
-
-CS_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
- DB PSO_CS_TRI
- DB 10
- DB SocketID
- DB ChannelID
- DB Bit0Map
- DB Bit1Map
- DB Bit2Map
- DB Bit3Map
- DB Bit4Map
- DB Bit5Map
- DB Bit6Map
- DB Bit7Map
-ENDM
-
-NUMBER_OF_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfDimmSlotsPerChannel:REQ
- DB PSO_MAX_DIMMS
- DB 3
- DB SocketID
- DB ChannelID
- DB NumberOfDimmSlotsPerChannel
-ENDM
-
-NUMBER_OF_CHIP_SELECTS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfChipSelectsPerChannel:REQ
- DB PSO_MAX_CHIPSELS
- DB 3
- DB SocketID
- DB ChannelID
- DB NumberOfChipSelectsPerChannel
-ENDM
-
-NUMBER_OF_CHANNELS_SUPPORTED MACRO SocketID:REQ, NumberOfChannelsPerSocket:REQ
- DB PSO_MAX_CHNLS
- DB 3
- DB SocketID
- DB ANY_CHANNEL
- DB NumberOfChannelsPerSocket
-ENDM
-
-OVERRIDE_DDR_BUS_SPEED MACRO SocketID:REQ, ChannelID:REQ, TimingMode:REQ, BusSpeed:REQ
- PSO_BUS_SPEED
- DB 10
- DB SocketID
- DB ChannelID
- DD TimingMode
- DD BusSpeed
-ENDM
-
-DRAM_TECHNOLOGY MACRO SocketID:REQ, MemTechType:REQ
- DB PSO_MEM_TECH
- DB 6
- DB SocketID
- DB ANY_CHANNEL
- DD MemTechType
-ENDM
-
-WRITE_LEVELING_SEED MACRO SocketID:REQ, ChannelID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
-Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
- DB PSO_WL_SEED
- DB 11
- DB SocketID
- DB ChannelID
- DB Byte0Seed
- DB Byte1Seed
- DB Byte2Seed
- DB Byte3Seed
- DB Byte4Seed
- DB Byte5Seed
- DB Byte6Seed
- DB Byte7Seed
- DB ByteEccSeed
-ENDM
-
-LVDIMM_FORCE_VOLT1_5_FOR_D0 MACRO
- DB PSO_LVDIMM_VOLT1_5_SUPPORT
- DB 3
- DB ANY_SOCKET
- DB ANY_CHANNEL
- DB 1
-ENDM
-
-; *****************************************************************************************
-; *
-; * CONDITIONAL OVERRIDE TABLE MACROS
-; *
-; *****************************************************************************************
-CONDITION_AND MACRO
- DB PSO_CONDITION_AND
- DB 0
-ENDM
-
-COND_LOC MACRO SocketMsk:REQ, ChannelMsk:REQ, DimmMsk:REQ
- DB PSO_CONDITION_LOC
- DB 3
- DB SocketMsk
- DB ChannelMsk
- DB DimmMsk
-ENDM
-
-COND_SPD MACRO Byte:REQ, Mask:REQ, Value:REQ
- DB PSO_CONDITION_SPD
- DB 3
- DB Byte
- DB Mask
- DB Value
-ENDM
-
-COND_REG MACRO Access:REQ, Offset:REQ, Mask:REQ, Value:REQ
- DB PSO_CONDITION_REG
- DB 11
- DB Access
- DW Offset
- DD Mask
- DD Value
-ENDM
-
-ACTION_ODT MACRO Frequency:REQ, Dimms:REQ, QrDimms:REQ, DramOdt:REQ, QrDramOdt:REQ, DramDynOdt:REQ
- DB PSO_ACTION_ODT
- DB 9
- DD Frequency
- DB Dimms
- DB QrDimms
- DB DramOdt
- DB QrDramOdt
- DB DramDynOdt
-ENDM
-
-ACTION_ADDRTMG MACRO Frequency:REQ, DimmConfig:REQ, AddrTmg:REQ
- DB PSO_ACTION_ADDRTMG
- DB 10
- DD Frequency
- DW DimmConfig
- DD AddrTmg
-ENDM
-
-ACTION_ODCCTRL MACRO Frequency:REQ, DimmConfig:REQ, OdcCtrl:REQ
- DB PSO_ACTION_ODCCONTROL
- DB 10
- DD Frequency
- DW DimmConfig
- DD OdcCtrl
-ENDM
-
-ACTION_SLEWRATE MACRO Frequency:REQ, DimmConfig:REQ, SlewRate:REQ
- DB PSO_ACTION_SLEWRATE
- DB 10
- DD Frequency
- DW DimmConfig
- DD SlewRate
-ENDM
-
-ACTION_SPEEDLIMIT MACRO DimmConfig:REQ, Dimms:REQ, SpeedLimit15:REQ, SpeedLimit135:REQ, SpeedLimit125:REQ
- DB PSO_ACTION_SPEEDLIMIT
- DB 9
- DW DimmConfig
- DB Dimms
- DW SpeedLimit15
- DW SpeedLimit135
- DW SpeedLimit125
-ENDM
-
-; *****************************************************************************************
-; *
-; * END OF CONDITIONAL OVERRIDE TABLE MACROS
-; *
-; *****************************************************************************************
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/Proc/arch2008.asm b/src/vendorcode/amd/agesa/f10/Legacy/Proc/arch2008.asm
deleted file mode 100644
index eb1f838ab5..0000000000
--- a/src/vendorcode/amd/agesa/f10/Legacy/Proc/arch2008.asm
+++ /dev/null
@@ -1,2670 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; Workfile: arch2008.asm $Revision: 44323 $ $Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
-;
-; Description: ARCH2008.ASM - AGESA Architecture 2008 Wrapper Template
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- .XLIST
- INCLUDE agesa.inc
- INCLUDE acwrapg.inc ; Necessary support file as part of wrapper, including but not limited to segment start/end macros.
- INCLUDE acwrap.inc ; IBVs may specify host BIOS-specific include files required when building.
- INCLUDE cpcarmac.inc
- INCLUDE bridge32.inc
- .LIST
- .586p
-
-
-;----------------------------------------------------------------------------
-; Local definitions
-;----------------------------------------------------------------------------
-
-sOemCallout STRUCT
- FuncName DD ? ; Call out function name
- FuncPtr DW ? ; Call out function pointer
-sOemCallout ENDS
-
-sOemEventHandler STRUCT
- ClassCode DD ? ; AGESA event log sub-class code
- FuncPtr DW ? ; Event handler function pointer
-sOemEventHandler ENDS
-
-;; A typical legacy BIOS implementation may require the E000 and F000 segments
-;; to be cached.
-EXE_CACHE_REGION_BASE_0 EQU 0E0000h
-EXE_CACHE_REGION_SIZE_0 EQU 20000h
-
-;; In this sample implementation, the B1 and B2 images are placed next to each
-;; other in the BIOS ROM to help with the maximization of cached code.
-EXE_CACHE_REGION_BASE_1 EQU AGESA_B1_ADDRESS
-EXE_CACHE_REGION_SIZE_1 EQU 40000h
-
-;; The third region is not needed in our example.
-EXE_CACHE_REGION_BASE_2 EQU 0
-EXE_CACHE_REGION_SIZE_2 EQU 0
-
-
-;----------------------------------------------------------------------------
-; PERSISTENT SEGMENT
-; This segment is required to be present throughout all BIOS execution.
-;----------------------------------------------------------------------------
-
-AMD_PERSISTENT_START
-
-
-;----------------------------------------------------------------------------
-; Instantiate the global descriptor table
-;----------------------------------------------------------------------------
-
-AMD_BRIDGE_32_GDT AMD_GDT ; Instantiate the global descriptor table
- ; required by the push-high mechanism.
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the persistent segment
-;----------------------------------------------------------------------------
-
-;+-------------------------------------------------------------------------
-;
-; AmdDfltRet
-;
-; Entry:
-; None
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Near stub procedure. Simply perform a retn instruction.
-;
-EXTERN AmdDfltRet:NEAR
-
-
-;+-------------------------------------------------------------------------
-;
-; AmdDfltRetFar
-;
-; Entry:
-; None
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Far stub procedure. Simply perform a retf instruction.
-;
-EXTERN AmdDfltRetFar:FAR
-
-
-;----------------------------------------------------------------------------
-; Declare the optional external routines in the persistent segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myModuleTypeMismatchHandler (Example)
-;
-; Entry:
-; ESI - Pointer to the EVENT_PARAMS structure of the failure.
-; [ESI].DataParam1 - Socket
-; [ESI].DataParam2 - DCT
-; [ESI].DataParam3 - Channel
-; [ESI].DataParam4 - 0x00000000
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure can be used to react to a memory module type
-; mismatch error discovered by the AGESA code. Actions taken
-; may include, but are not limited to:
-; Logging the event to NV for display later
-; Reset, excluding the mismatch on subsequent reboot
-; Do nothing
-;
-; Dependencies:
-; None
-;
-EXTERN myModuleTypeMismatchHandler(AmdDfltRet):NEAR
-
-;+---------------------------------------------------------------------------
-;
-; oemPlatformConfigInit (Optional)
-;
-; Entry:
-; EDI - 32-bit flat pointer to the PLATFORM_CONFIGURATION to be
-; passed in to the next AGESA entry point.
-;
-; typedef struct {
-; IN PERFORMANCE_PROFILE PlatformProfile;
-; IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList;
-; IN UINT8 CoreLevelingMode;
-; IN PLATFORM_C1E_MODES C1eMode;
-; IN UINT32 C1ePlatformData;
-; IN BOOLEAN UserOptionDmi;
-; IN BOOLEAN UserOptionPState;
-; IN BOOLEAN UserOptionSrat;
-; IN BOOLEAN UserOptionSlit;
-; IN BOOLEAN UserOptionWhea;
-; IN UINT32 PowerCeiling;
-; IN BOOLEAN PstateIndependent;
-; } PLATFORM_CONFIGURATION;
-;
-; typedef struct {
-; IN UINT8 Socket;
-; IN UINT8 Link;
-; IN UINT8 LoFreq;
-; IN UINT8 HighFreq;
-; IN PLATFORM_DEEMPHASIS_LEVEL ReceiverDeemphasis;
-; IN PLATFORM_DEEMPHASIS_LEVEL DcvDeemphasis;
-; } CPU_HT_DEEMPHASIS_LEVEL;
-;
-; typedef struct {
-; IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode;
-; IN BOOLEAN UseHtAssist;
-; IN BOOLEAN Use32ByteRefresh;
-; IN BOOLEAN UseVariableMctIsocPriority;
-; } PERFORMANCE_PROFILE;
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Provide a single hook routine to modify the parameters of a
-; PLATFORM_CONFIGURATION structure before any entry point that
-; has such a structure as an input.
-;
-; Dependencies:
-; None
-;
-; Example:
-; If your platform is running in UMA mode, the following code
-; may be added:
-; mov (PLATFORM_CONFIGURATION PTR [edi]).PlatformProfile.PlatformControlFlowMode, UmaDr
-;
-EXTERN oemPlatformConfigInit(AmdDfltRetFar):FAR
-
-;+---------------------------------------------------------------------------
-;
-; oemCallout (Optional)
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The default call out router function which resides in the same
-; segment as the push-high bridge code.
-;
-; Dependencies:
-; None
-;
-EXTERN oemCallout(AmdDfltRet):NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the persistent segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdBridge32
-;
-; Entry:
-; EDX - A Real Mode FAR pointer using seg16:Offset16 format that
-; points to a local host environment call-out router. If
-; this pointer is not equal to zero, then this pointer is
-; used as the call-out router instead of the standard
-; OemCallout. This may be useful when the call-out router
-; is not located in the same segment as the AmdBridge32 and
-; AmdCallout16 routines.
-; ESI - A Flat Mode pointer (32-bit address) that points to the
-; configuration block (AMD_CONFIG_PARAMS) for the AGESA
-; software function.
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; Execute an AGESA software function through the Push-High interface.
-;
-; Dependencies:
-; This procedure requires a stack. The host environment must use the
-; provided service function to establish the stack environment prior
-; to making the call to this procedure.
-;
-AmdBridge32 PROC FAR PUBLIC
- AMD_BRIDGE_32 AMD_GDT ; use the macro for the body
- ret
-AmdBridge32 ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdEnableStack
-;
-; Entry:
-; BX - Return address
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; SS:ESP - Points to the private stack location for this processor core.
-; ECX - Upon success, contains this processor core's stack size in bytes.
-;
-; Modified:
-; EAX, ECX, EDX, EDI, ESI, ESP, DS, ES
-;
-; Purpose:
-; This procedure is used to establish the stack within the host environment.
-;
-; Dependencies:
-; The host environment must use this procedure and not rely on any other
-; sources to create the stack region.
-;
-AmdEnableStack PROC NEAR PUBLIC
- AMD_ENABLE_STACK
- ;; EAX = AGESA_SUCCESS, The stack space has been allocated for this core.
- ;; EAX = AGESA_WARNING, The stack has already been set up. SS:ESP is set
- ;; to stack top, and ECX is the stack size in bytes.
- jmp bx
-AmdEnableStack ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdDisableStack
-;
-; Entry:
-; BX - Return address
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; EAX, ECX, EDX, ESI, ESP
-;
-; Purpose:
-; This procedure is used to remove the pre-memory stack from within the
-; host environment.
-; The exit state for the BSP is described as follows:
-; Memory region 00000-9FFFF MTRRS are set as WB memory.
-; Processor Cache is enabled (CD bit is cleared).
-; MTRRs used for execution cache are kept.
-; Cache content is flushed (invalidated without write-back).
-; Any family-specific clean-up done.
-; The exit state for the APs is described as follows:
-; Memory region 00000-9FFFF MTRRS are set as WB memory.
-; Memory region A0000-DFFFF MTRRS are set as UC IO.
-; Memory region E0000-FFFFF MTRRS are set as UC memory.
-; MTRRs used for execution cache are cleared.
-; Processor Cache is disabled (CD bit is set).
-; Top-of-Memory (TOM) set to the system top of memory as determined
-; by the memory initialization routines.
-; System lock command is enabled.
-; Any family-specific clean-up done.
-;
-; Dependencies:
-; The host environment must use this procedure and not rely on any other
-; sources to break down the stack region.
-; If executing in 16-bit code, the host environment must establish the
-; "Big Real" mode of 32-bit addressing of data.
-;
-AmdDisableStack PROC NEAR PUBLIC
- AMD_DISABLE_STACK
- ;; EAX = AGESA_SUCCESS, The stack space has been disabled for this core.
- jmp bx
-AmdDisableStack ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCallout16
-;
-; Entry:
-; [esp+8] - Func
-; [esp+12] - Data
-; [esp+16] - Configuration Block
-; [esp+4] - Return address to AGESA
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; Execute callback from the push-high interface.
-;
-; Dependencies:
-; None
-;
-AmdCallout16 PROC FAR PUBLIC ; declare the procedure
- AMD_CALLOUT_16 oemCallout ; use the macro for the body
- ret
-AmdCallout16 ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdProcessAgesaErrors (Optional)
-;
-; Entry:
-; AL - Heap status of the AGESA entry point that was just invoked.
-; EBX - AGESA image base address.
-; EDX - Segment / Offset of the appropriate callout router function.
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure is used to handle any errors that may have occurred
-; during an AGESA entry point.
-;
-; Dependencies:
-; None
-;
-AmdProcessAgesaErrors PROC FAR PUBLIC
- LOCAL localCpuInterfaceBlock:EVENT_PARAMS
-
- pushad
- xor edi, edi
- mov di, ss
- shl edi, 4
- lea esi, localCpuInterfaceBlock
- add esi, edi
-
- ; Fill default config block
- mov (EVENT_PARAMS PTR [esi]).StdHeader.Func, AMD_READ_EVENT_LOG
- mov (EVENT_PARAMS PTR [esi]).StdHeader.ImageBasePtr, ebx
- mov (EVENT_PARAMS PTR [esi]).StdHeader.AltImageBasePtr, 0
- mov (EVENT_PARAMS PTR [esi]).StdHeader.HeapStatus, al
- mov edi, SEG AmdCallout16
- shl edi, 4
- add edi, OFFSET AmdCallout16
- mov (EVENT_PARAMS PTR [esi]).StdHeader.CalloutPtr, edi
-
- ; Flush the event log searching for, and handling all monitored events
- xor eax, eax
- .while (eax == 0)
- push edx
- call AmdBridge32
- pop edx
- .if (eax == AGESA_SUCCESS)
- mov eax, (EVENT_PARAMS PTR [esi]).EventInfo
- .if (eax != 0)
- lea di, cs:AgesaEventTable
-
-loopThruTable:
- cmp di, OFFSET cs:AgesaEventTableEnd
- jae unhandledEvent
-
- cmp eax, cs:[di].sOemEventHandler.ClassCode
- je FoundMatch
- add di, SIZEOF sOemEventHandler
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemEventHandler.FuncPtr
- call bx
-
-unhandledEvent:
- xor eax, eax
- .else
- mov al, 1
- .endif
- .endif
- .endw
- popad
- ret
-
-AmdProcessAgesaErrors ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the error handler table
-;----------------------------------------------------------------------------
-
-AgesaEventTable LABEL BYTE
- ;; Add entries as desired
- ;;---------
- ;; EXAMPLE
- ;;---------
- sOemEventHandler <MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, OFFSET myModuleTypeMismatchHandler>
-AgesaEventTableEnd LABEL BYTE
-
-
-AMD_PERSISTENT_END
-
-
-
-
-;----------------------------------------------------------------------------
-; RECOVERY SEGMENT
-; This segment resides in the classic 'boot-block,' and is used
-; for recovery.
-;----------------------------------------------------------------------------
-
-AMD_RECOVERY_START
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the recovery segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myReadSPDRecovery (Required for proper recovery mode operation)
-;
-; Entry:
-; ESI - Pointer to an AGESA_READ_SPD_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT8 SocketId;
-; IN UINT8 MemChannelId;
-; IN UINT8 DimmId;
-; IN OUT UINT8 *Buffer;
-; IN OUT MEM_DATA_STRUCT *MemData;
-; } AGESA_READ_SPD_PARAMS;
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS Indicates the SPD block for the indicated
-; DIMM was read successfully.
-; AGESA_BOUNDS_CHK The specified DIMM is not present.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function and no memory initialized.
-; AGESA_ERROR The DIMM SPD read process has generated
-; communication errors.
-;
-; Modified:
-; None
-;
-; Purpose:
-; This call out reads a block of memory SPD data and places it
-; into the provided buffer.
-;
-; Dependencies:
-; None
-;
-EXTERN myReadSPDRecovery:NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the recovery segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitResetWrapper
-;
-; Entry:
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; A minimal initialization of the processor core is performed. This
-; procedure must be called by all processor cores. The code path
-; separates the BSP from the APs and performs a separate and appropriate
-; list of tasks for each class of core.
-; For the BSP, the following actions are performed:
-; Internal heap sub-system initialization
-; Primary non-coherent HyperTransportT link initialization
-; Return to the host environment to test for Recovery Mode.
-; The AP processor cores do not participate in the recovery process.
-; However, they execute this routine after being released to execute
-; by the BSP during the main boot process. Their actions include the
-; following:
-; Internal heap sub-system initialization
-; Proceed to a wait loop waiting for commands from the BSP
-;
-; For the cache regions, up to three regions of execution cache can be
-; allocated following the following rules:
-; 1. Once a region is allocated, it cannot be de-allocated. However, it
-; can be expanded.
-; 2. At most, two of the three regions can be located above 1 MByte. A
-; region failing this rule is ignored.
-; 3. All region addresses must be at or above the 0x000D0000 linear
-; address. A region failing this rule is ignored.
-; 4. The address is aligned on a 32-KByte boundary. Starting addresses
-; is rounded down to the nearest 32-Kbyte boundary.
-; 5. The execution cache size must be a multiple of 32 KByte. Size is
-; rounded up to the next multiple of 32 KByte.
-; 6. A region must not span either the 1-MByte boundary or the 4-GByte
-; boundary. Allocated size is truncated to not span the boundary.
-; 7. The granted cached execution regions, address, and size are calculated
-; based on the available cache resources of the processor core.
-; Allocations are made up to the limit of cache available on the
-; installed processor.
-; Warning: Enabling instruction cache outside of this interface can cause
-; data corruption.
-;
-; Dependencies:
-; This procedure is expected to be executed soon after a system reset
-; for the main boot path or resume path of execution.
-;
-; This procedure requires a stack.
-;
-; Because the heap system is not yet operational at the point of the
-; interface call, the host environment must allocate the storage for
-; the AMD_RESET_PARAMS structure before making the first call to
-; AmdCreateStruct. This is the ByHost method of allocation.
-;
-AmdInitResetWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
- local localResetParams:AMD_RESET_PARAMS
-
- pushad
-
- ; Prepare for the call to initialize the input parameters for AmdInitReset
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B1_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- ; Use the 'ByHost' allocation method because the heap has not been initialized as of yet.
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RESET
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, ByHost
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, sizeof AMD_RESET_PARAMS
- lea edx, localResetParams
- add edx, eax
- push edx
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr, edx
- mov dx, SEG AmdCalloutRouterRecovery
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterRecovery
- push edx
- call AmdBridge32
- pop edx
- pop esi
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- ; Allocate the execution cache to maximize the amount of code in ROM that is cached.
- ; Placing the B1 and B2 images near one another is a good way to ensure the AGESA code
- ; is cached.
- mov (AMD_RESET_PARAMS ptr [esi]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_0
- mov (AMD_RESET_PARAMS ptr [esi]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_0
- mov (AMD_RESET_PARAMS ptr [esi + sizeof EXECUTION_CACHE_REGION]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_1
- mov (AMD_RESET_PARAMS ptr [esi + sizeof EXECUTION_CACHE_REGION]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_1
- mov (AMD_RESET_PARAMS ptr [esi + (2 * sizeof EXECUTION_CACHE_REGION)]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_2
- mov (AMD_RESET_PARAMS ptr [esi + (2 * sizeof EXECUTION_CACHE_REGION)]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_2
-
- ; Call in to the AmdInitReset entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS Early initialization completed successfully.
- ;; AGESA_WARNING One or more of the execution cache allocation
- ;; rules were violated, but an adjustment was made
- ;; and space was allocated.
- ;; AGESA_ERROR One or more of the execution cache allocation rules
- ;; were violated, which resulted in a requested cache
- ;; region to not be allocated.
- ;; The storage space allocated for the AMD_RESET_PARAMS
- ;; structure is insufficient.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_RESET_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B1_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
-
- ;; Here are what the MTRRs should look like based off of the CacheRegions specified above:
-
- ;; Fixed-Range MTRRs
- ;; Name Address Value
- ;; ---------------- -------- ----------------
- ;; MTRRfix4k_E0000 0000026C 0505050505050505
- ;; MTRRfix4k_E8000 0000026D 0505050505050505
- ;; MTRRfix4k_F0000 0000026E 0505050505050505
- ;; MTRRfix4k_F8000 0000026F 0505050505050505
- ;; MTRRdefType 000002FF 0000000000000C00
- ;;
- ;; Variable-Range MTRRs and IO Range
- ;; MTRRphysBase(n) MTRRphysMask(n)
- ;; ----------------- -----------------
- ;; n=0 0000000000000000 0000000000000000
- ;; n=1 0000000000000000 0000000000000000
- ;; n=2 0000000000000000 0000000000000000
- ;; n=3 0000000000000000 0000000000000000
- ;; n=4 0000000000000000 0000000000000000
- ;; n=5 Heap Base (Varies by core) 0000FFFFFFFF0800
- ;; n=6 AGESA_B1_ADDRESS | 6 0000FFFFFFFC0800
- ;; n=7 0000000000000000 0000000000000000
-
-
- ;; Because the allocation method is 'ByHost,' the call to AMD_RELEASE_STRUCT is
- ;; not necessary. Stack space reclamation is left up to the host BIOS.
-
- popad
- ret
-
-
-AmdInitResetWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitRecoveryWrapper
-;
-; Entry:
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Perform a minimum initialization of the processor and memory to
-; support a recovery mode flash ROM update.
-; For the BSP, the following actions are performed:
-; Configuration of CPU core for recovery process
-; Minimal initialization of some memory
-; The AP processor cores do not participate in the recovery process.
-; No actions or tasks are performed by the AP cores for this time point.
-;
-; Dependencies:
-; This procedure requires a stack. The host environment must use one of
-; the provided service functions to establish the stack environment prior
-; to making the call to this procedure.
-;
-AmdInitRecoveryWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitRecovery
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B1_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RECOVERY
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterRecovery
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterRecovery
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
-
- ; Call in to the AmdInitRecovery entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_WARNING One or more of the allocation rules were violated,
- ;; but an adjustment was made and space was allocated.
- ;; AGESA_ERROR One or more of the allocation rules were violated,
- ;; which resulted in a requested cache region to not be
- ;; allocated.
- ;; AGESA_FATAL No memory was found in the system.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_RECOVERY_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B1_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitRecovery
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-AmdInitRecoveryWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCalloutRouterRecovery
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The call out router function for AmdInitReset and
-; AmdInitRecovery.
-;
-; Dependencies:
-; None
-;
-AmdCalloutRouterRecovery PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
- xor ax, ax
- mov ds, ax
- mov es, ax
- lea di, cs:CalloutRouterTableRecovery
- mov eax, AGESA_UNSUPPORTED
-
-loopThruTable:
- cmp di, OFFSET cs:CalloutRouterTableRecoveryEnd
- jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
- cmp ecx, cs:[di].sOemCallout.FuncName
- je FoundMatch
- add di, SIZEOF sOemCallout
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemCallout.FuncPtr
- call bx
-
-amdCpuCalloutExit:
- ret
-AmdCalloutRouterRecovery ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the callout dispatch table for the recovery segment
-;----------------------------------------------------------------------------
-
-CalloutRouterTableRecovery LABEL BYTE
- ;; Standard B1 implementations only need the SPD reader call out function to be implemented.
- sOemCallout <AGESA_READ_SPD, OFFSET myReadSPDRecovery>
-CalloutRouterTableRecoveryEnd LABEL BYTE
-
-
-AMD_RECOVERY_END
-
-
-
-;----------------------------------------------------------------------------
-; PRE-MEMORY SEGMENT
-; This segment must be uncompressed in the ROM image.
-;----------------------------------------------------------------------------
-
-AMD_PREMEM_START
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the recovery segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myReadSPDPremem (Required)
-;
-; Entry:
-; ESI - Pointer to an AGESA_READ_SPD_PARAMS structure
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT8 SocketId;
-; IN UINT8 MemChannelId;
-; IN UINT8 DimmId;
-; IN OUT UINT8 *Buffer;
-; IN OUT MEM_DATA_STRUCT *MemData;
-; } AGESA_READ_SPD_PARAMS;
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS Indicates the SPD block for the indicated
-; DIMM was read successfully.
-; AGESA_BOUNDS_CHK The specified DIMM is not present.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function and no memory initialized.
-; AGESA_ERROR The DIMM SPD read process has generated
-; communication errors.
-;
-; Modified:
-; None
-;
-; Purpose:
-; This call out reads a block of memory SPD data and places it
-; into the provided buffer.
-;
-; Dependencies:
-; None
-;
-EXTERN myReadSPDPremem:NEAR
-
-;+-------------------------------------------------------------------------
-;
-; AmdDfltRetPremem
-;
-; Entry:
-; None
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Near stub procedure in the prememory segment. Simply perform a
-; retn instruction.
-;
-EXTERN AmdDfltRetPremem:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myDoReset (Required)
-;
-; Entry:
-; EDX - Reset type
-; 1 - Warm reset whenever
-; 2 - Cold reset whenever
-; 3 - Warm reset immediately
-; 4 - Cold reset immediately
-; ESI - Pointer to an AMD_CONFIG_PARAMS structure.
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function.
-;
-; Modified:
-; None
-;
-; Purpose:
-; This host environment function must initiate the specified type
-; of system reset.
-;
-; Implementation of this function by the host environment is
-; REQUIRED. Some host environments may record this as a request
-; allowing other elements in the system to perform some additional
-; tasks before the actual reset is issued.
-;
-; Dependencies:
-; The AMD processor contains 3 bits (BiosRstDet[2:0]) in a PCI
-; register (F0x6C Link Initialization Control Register) that
-; indicate the reset status. These bits are reserved for use by
-; the AGESA software and should not be modified by the host
-; environment.
-;
-EXTERN myDoReset:NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myGetNonVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; None
-;
-; Exit:
-; EBX - Pointer to the non-volatile S3 context block
-; ECX - Size in bytes of the non-volatile S3 context block
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must return the pointer to the data
-; saved during the mySaveNonVolatileS3Context routine.
-;
-; Dependencies:
-; None
-;
-EXTERN myGetNonVolatileS3Context:NEAR
-
-
-;----------------------------------------------------------------------------
-; Declare the optional external routines in the prememory segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myAgesaHookBeforeExitSelfRefresh (Optional)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 44h
-; ESI - Pointer to a data structure containing the memory information
-;
-; Exit:
-; After returning control to AGESA, AGESA will display: - AGESA_TESTPOINT - 45h
-; EAX - Contains the AGESA_STATUS return code
-; AGESA_SUCCESS The function has completed successfully
-; AGESA_UNSUPPORTED This function is not implemented by the host environment
-; AGESA_WARNING A non-critical issue has occued in the host environment
-;
-; Modified:
-; None
-;
-; Purpose:
-; General purpose hook called before the exiting self refresh
-; This procedure is called once per channel
-;
-; Implementation of this function is optional for the host environment
-; This call-out is an opportunity for the host environment to make dynamic
-; modifications to the memory timing settings specific to the board or host
-; environment before exiting self refresh on S3 resume
-;
-; Dependencies:
-; This procedure is called before the exit self refresh bit is set in the resume
-; sequence. The host environment must initiate the OS restart process. This procedure
-; requires a stack. The host environment must establish the stack environment prior
-; to making the call to this procedure
-;
-EXTERN myAgesaHookBeforeExitSelfRefresh(AmdDfltRetPremem):NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myHookBeforeDramInit (Optional)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 40h
-; ESI - Pointer to a data structure containing the memory information
-;
-; Exit:
-; After returning control to AGESA, AGESA will display - AGESA_TESTPOINT - 41h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This function is not implemented by the host environment
-;
-; Modified:
-; None
-;
-; Purpose:
-; General-purpose hook called before the DRAM_Init bit is set. Called
-; once per MCT
-;
-; Implementation of this function is optional for the host environment
-; This call-out is an opportunity for the host environment to make
-; dynamic modifications to the memory timing settings specific to the
-; board or host environment
-;
-; Dependencies:
-; None
-;
-EXTERN myHookBeforeDramInit(AmdDfltRetPremem):NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myHookBeforeDQSTraining (Optional)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 42h
-; ESI - Pointer to a data structure containing the memory information.
-;
-; Exit:
-; After returning control to AGESA, AGESA will display - AGESA_TESTPOINT - 43h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This function is not implemented by the
-; host environment.
-;
-; Modified:
-; None
-;
-; Purpose:
-; General-purpose hook called just before the memory training processes
-; begin. Called once per MCT.
-;
-; Implementation of this function is optional for the host environment.
-; This call-out is an opportunity for the host environment to make
-; dynamic modifications to the memory timing settings specific to the
-; board or host environment.
-;
-; The host environment may also use this call-out for some board-
-; specific features that should be activated at this time point,
-; such as:
-; Low voltage DIMMs-the host environment should set the recommended
-; voltages found in the memory data structure for each memory
-; channel. This needs to occur before training begins.
-;
-; Dependencies:
-; None
-;
-EXTERN myHookBeforeDQSTraining(AmdDfltRetPremem):NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the prememory segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitEarlyWrapper
-;
-; Entry:
-; On Entry to "AmdInitEarly" AGESA will display AGESA_TESTPOINT - C4h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitEarly" AGESA will display AGESA_TESTPOINT - C5h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; A full initialization of the processor is performed. Action details
-; differ for the BSP and AP processor cores.
-; For the BSP, the following actions are performed:
-; Full HyperTransportT link initialization, coherent and non-coherent
-; Processor register loading
-; Microcode patch load
-; Errata workaround processing
-; Launch all processor cores
-; Configure the processor power management capabilities
-; Request a warm reset if needed
-; For the AP, the following actions are performed:
-; Processor register loading
-; Microcode patch load
-; Errata workaround processing
-; Configure the processor power management capabilities
-;
-; Dependencies:
-; This procedure is expected to be called before main memory initialization
-; and before the system warm reset. Prior to this, the basic configuration
-; done by the AmdInitReset routine must be completed.
-;
-; This procedure requires a stack. The host environment must use one of the
-; provided service functions to establish the stack environment prior to
-; making the call to this procedure.
-;
-; The processes performed at this time point require communication between
-; processor cores.
-;
-; The host environment must recognize that all processor cores are running
-; in parallel and avoid activities that might interfere with the core-to-core
-; communication, such as modifying the MTRR settings or writing to the APIC
-; registers.
-;
-AmdInitEarlyWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitEarly
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_EARLY
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPremem
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPremem
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + (3 * (SIZEOF EXECUTION_CACHE_REGION)))
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitEarly entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ALERT An HyperTransportT link CRC error was observed.
- ;; AGESA_WARNING One of more of the allocation rules were violated,
- ;; but an adjustment was made and space was allocated.
- ;; Or a HyperTransport device does not have the expected
- ;; capabilities, or unusable redundant HyperTransport
- ;; links were found.
- ;; AGESA_ERROR One or more of the allocation rules were violated, which
- ;; resulted in a requested cache region to not be allocated.
- ;; Or, a HyperTransport device failed to initialize.
- ;; AGESA_CRITICAL An illegal or unsupported mixture of processor types was
- ;; found, or the processors installed were found to have an
- ;; insufficient MP capability rating for this platform.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_EARLY_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitEarly
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitEarlyWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitPostWrapper
-;
-; Entry:
-; On Entry to "AmdInitPost" AGESA will display AGESA_TESTPOINT - C6h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitPost" AGESA will display AGESA_TESTPOINT - C7h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The main system memory is located, initialized, and brought on-line.
-; The processor(s) are prepared for full operation and control by the
-; host environment. Action details differ for the BSP and AP processor
-; cores.
-; For the BSP, the following actions are performed:
-; Full memory initialization and configuration. BSP is the master for
-; this process and may delegate some tasks to APs.
-; AP collection of data for use later.
-; Transfer the HOBs including the artifact data out of the pre-memory
-; cache storage into a temporary holding buffer in the main memory.
-; Check the BIST status of the BSP
-; Shut down the APs.
-; Prepare for the host environment to begin main boot activity.
-; Disable the pre-memory stack.
-; For the APs, the following actions are performed:
-; Report core identity information.
-; Execute indicated memory initialization processes as directed.
-; Check the BIST status of the AP
-; Disable the pre-memory stack.
-; Prepare to halt, giving control to host environment.
-; The entire range of system memory is enabled for Write-Back cache.
-; The fixed MTRRs and the variable MTRRs[7:6] are not changed in order
-; to leave in place any flash ROM region currently set for Write-Protect
-; execution cache.
-;
-; Dependencies:
-; This procedure is called after the host environment has determined that
-; a normal boot to operating system should be performed after any system
-; warm reset is completed and after the configuration done by AmdInitEarly
-; has completed.
-;
-; This procedure requires a stack. The host environment must use one of the
-; provided service functions to establish the stack environment prior to
-; making the call to this procedure.
-;
-; The processes performed at this time point require communication between
-; processor cores. The host environment must recognize that all processor
-; cores are running in parallel and avoid activities that might interfere
-; with the core-to-core communication, such as modifying the MTRR settings
-; or writing to the APIC registers.
-;
-AmdInitPostWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitPost
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_POST
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPremem
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPremem
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitPost entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ALERT A BIST error was found on one of the cores.
- ;; AGESA_WARNING HT Assist feature is running sub-optimally.
- ;; AGESA_FATAL Memory initialization failed.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_POST_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitPost
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitPostWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitResumeWrapper
-;
-; Entry:
-; On Entry to "AmdInitResume" AGESA will display AGESA_TESTPOINT - D0h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitResume" AGESA will display AGESA_TESTPOINT - D1h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure initializes or re-initializes the silicon components
-; for the resume boot path. For the processor, main memory is brought
-; out of self-refresh mode. This procedure will use the context data
-; in the NvStorage area of the input structure to re-start the main
-; memory. The host environment must fill the AMD_S3_PARAMS NvStorage
-; and VolatileStorage pointers and related size elements to describe
-; the location of the context data. Note that for this procedure, the
-; two data areas do not need to be contained in one buffer zone, they
-; can be anywhere in the accessible memory address space. If the host
-; environment uses a non-volatile storage device accessed on the system
-; address bus such as flashROM, then the context data does not need to
-; be moved prior to this call. If the host environment uses a non-
-; volatile storage device not located on the system address bus (e.g.
-; CMOS or SSEPROM) then the host environment must transfer the context
-; data to a buffer in main memory prior to calling this procedure.
-;
-; Dependencies:
-; The host environment must have determined that the system should take
-; the resume path prior to calling this procedure. The configuration
-; done by AmdInitEarly and any necessary warm reset must be complete.
-; After this procedure, execution proceeds to general system restoration.
-;
-; This procedure requires a stack. The host environment must use one of
-; the provided service functions to establish the stack environment prior
-; to making the call to this procedure.
-;
-AmdInitResumeWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitResume
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RESUME
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPremem
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPremem
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
- call oemPlatformConfigInit
-
- call myGetNonVolatileS3Context
- mov (AMD_RESUME_PARAMS ptr [esi]).S3DataBlock.NvStorage, ebx
- mov (AMD_RESUME_PARAMS ptr [esi]).S3DataBlock.NvStorageSize, ecx
-
- ; Call in to the AmdInitResume entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS Re-initialization has been completed successfully.
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_RESUME_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
-
- ; Allow AGESA to free the space used by AmdInitResume
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitResumeWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCalloutRouterPremem
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The call out router function for AmdInitEarly,
-; AmdInitPost, and AmdInitResume.
-;
-; Dependencies:
-; None
-;
-AmdCalloutRouterPremem PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
- xor ax, ax
- mov ds, ax
- mov es, ax
- lea di, cs:CalloutRouterTablePremem
- mov eax, AGESA_UNSUPPORTED
-
-loopThruTable:
- cmp di, OFFSET cs:CalloutRouterTablePrememEnd
- jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
- cmp ecx, cs:[di].sOemCallout.FuncName
- je FoundMatch
- add di, SIZEOF sOemCallout
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemCallout.FuncPtr
- call bx
-
-amdCpuCalloutExit:
- ret
-AmdCalloutRouterPremem ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the callout dispatch table for the prememory segment
-;----------------------------------------------------------------------------
-
-CalloutRouterTablePremem LABEL BYTE
- ;; Add entries as desired.
- sOemCallout <AGESA_READ_SPD, OFFSET myReadSPDPremem>
- sOemCallout <AGESA_HOOKBEFORE_DRAM_INIT, OFFSET myHookBeforeDramInit>
- sOemCallout <AGESA_HOOKBEFORE_DQS_TRAINING, OFFSET myHookBeforeDQSTraining>
- sOemCallout <AGESA_HOOKBEFORE_EXIT_SELF_REF, OFFSET myAgesaHookBeforeExitSelfRefresh>
- sOemCallout <AGESA_DO_RESET, OFFSET myDoReset>
-CalloutRouterTablePrememEnd LABEL BYTE
-
-
-
-AMD_PREMEM_END
-
-
-;----------------------------------------------------------------------------
-; POST SEGMENT
-; This segment may be decompressed and run from system RAM.
-;----------------------------------------------------------------------------
-
-AMD_POST_START
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the POST segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myAllocateBuffer (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E2h
-; ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 BufferLength;
-; IN UINT32 BufferHandle;
-; OUT VOID *BufferPointer;
-; } AGESA_BUFFER_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E3h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The requested size of memory has been
-; successfully allocated.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function.
-; AGESA_ERROR Less than the requested amount of memory
-; was allocated.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of memory allocation.
-; This function must allocate a buffer of the requested size or
-; larger. This function is required to be implemented by the host
-; environment.
-;
-; Dependencies:
-; The following call-outs must work together in the host system.
-; Parameters of the same name have the same function and must be
-; treated the same in each function:
-; AgesaAllocateBuffer
-; AgesaDeallocateBuffer
-; AgesaLocateBuffer
-; AgesaRunFcnOnAp
-; The host environment may need to reserve a location in the buffer
-; to store any host environment specific value(s). The returned
-; pointer must not include this reserved space. The host environment
-; on the AgesaDeallocateBuffer call needs to account for the reserved
-; space. This reserved space may be an identifier or the "handle"
-; used to identify the specific memory block.
-;
-EXTERN myAllocateBuffer:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myDeallocateBuffer (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E4h
-; ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 BufferLength;
-; IN UINT32 BufferHandle;
-; OUT VOID *BufferPointer;
-; } AGESA_BUFFER_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E5h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_BOUNDS_CHK The BufferHandle is invalid. The AGESA
-; software continues with its function.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of memory allocation.
-; This function releases a valid working buffer. This function is
-; required for the host environment to implement.
-;
-; Dependencies:
-; The following call-outs must work together in the host system.
-; Parameters of the same name have the same function and must be
-; treated the same in each function:
-; AgesaAllocateBuffer
-; AgesaDeallocateBuffer
-; AgesaLocateBuffer
-; AgesaRunFcnOnAp
-;
-EXTERN myDeallocateBuffer:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myLocateBuffer (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E6h
-; ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 BufferLength;
-; IN UINT32 BufferHandle;
-; OUT VOID *BufferPointer;
-; } AGESA_BUFFER_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E7h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_BOUNDS_CHK The presented handle is invalid or the
-; buffer could not be located.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of memory allocation.
-; This function must locate the buffer related to the indicated
-; handle and return the address of the buffer and its length.
-; This function is required to be implemented in the host
-; environment.
-;
-; Dependencies:
-; The following call-outs must work together in the host system.
-; Parameters of the same name have the same function and must be
-; treated the same in each function:
-; AgesaAllocateBuffer
-; AgesaDeallocateBuffer
-; AgesaLocateBuffer
-; AgesaRunFcnOnAp
-;
-EXTERN myLocateBuffer:NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myRunFuncOnAp (Required)
-;
-; Entry:
-; EDX - Local APIC ID of the target core.
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must route execution to the target AP and
-; have that AP call the AmdLateRunApTaskWrapper routine defined
-; above.
-;
-; Dependencies:
-; None
-;
-EXTERN myRunFuncOnAp:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; mySaveNonVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; EBX - Pointer to the non-volatile S3 context block
-; ECX - Size in bytes of the non-volatile S3 context block
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must save the non-volatile data to an area
-; that will not lose context while in the ACPI S3 sleep state, but
-; cannot be placed in system RAM. This data will need to be
-; available during the call to AmdInitResume.
-;
-; Dependencies:
-; None
-;
-EXTERN mySaveNonVolatileS3Context:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; mySaveVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; EBX - Pointer to the volatile S3 context block
-; ECX - Size in bytes of the volatile S3 context block
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must save the volatile data to an area
-; that will not lose context while in the ACPI S3 sleep state.
-; This data will need to be available during the call to
-; AmdS3LateRestore.
-;
-; Dependencies:
-; None
-;
-EXTERN mySaveVolatileS3Context:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myGetVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; None
-;
-; Exit:
-; EBX - Pointer to the volatile S3 context block
-; ECX - Size in bytes of the volatile S3 context block
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must return the pointer to the data
-; saved during the mySaveVolatileS3Context routine.
-;
-; Dependencies:
-; None
-;
-EXTERN myGetVolatileS3Context:NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the POST segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitEnvWrapper
-;
-; Entry:
-; On Entry to "AmdInitEnv" AGESA will display AGESA_TESTPOINT - C8h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitEnv" AGESA will display AGESA_TESTPOINT - C9h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure uses the AgesaAllocateBuffer call-out to acquire
-; permanent buffer space for the UEFI Hand-Off Blocks (HOBs). This
-; is also known as, or includes, artifact data being used by the
-; AGESA software. Upon entry to this procedure, the data is being
-; held in a temporary memory location and it must be moved to a
-; location controlled and protected by the host environment.
-;
-; These actions are performed by the BSP. The APs are not assigned
-; any tasks at this time point.
-;
-; Dependencies:
-; This procedure must be called after full memory is initialized and
-; the host environment has taken control of main memory allocation.
-; This procedure should be called before the PCI enumeration takes
-; place and as soon as possible after the host environment memory
-; allocation sub-system has started.
-;
-; This procedure requires a stack. The host environment must use one
-; of the provided service functions to establish the stack environment
-; prior to making the call to this procedure.
-;
-AmdInitEnvWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitEnv
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_ENV
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitEnv entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ERROR The artifact data could not be found or the host
- ;; environment failed to allocate sufficient buffer space.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_ENV_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitEnv
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitEnvWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitMidWrapper
-;
-; Entry:
-; On Entry to "AmdInitMid" AGESA will display AGESA_TESTPOINT - CAh
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitMid" AGESA will display AGESA_TESTPOINT - CBh
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure call performs special configuration requirements for
-; the graphics display hardware.
-;
-; These actions are performed by the BSP. The APs are not assigned any
-; tasks at this time point.
-;
-; Dependencies:
-; This procedure must be called after PCI enumeration has allocated
-; resources, but before the video BIOS call is performed.
-;
-; This procedure requires a stack. The host environment must use one
-; of the provided service functions to establish the stack environment
-; prior to making the call to this procedure.
-;
-AmdInitMidWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitMid
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_MID
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitMid entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_MID_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitMid
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-
-AmdInitMidWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitLateWrapper
-;
-; Entry:
-; On Entry to "AmdInitLate" AGESA will display AGESA_TESTPOINT - CCh
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitLate" AGESA will display AGESA_TESTPOINT - CDh
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The main purpose of this function is to generate informational
-; data tables used by the operating system. The individual tables
-; can be selected for generation through the user selection entries
-; on the input parameters.
-;
-; This routine uses the Call-Out AgesaAllocateBuffer to allocate a
-; buffer of the proper size to contain the data.
-;
-; The code path separates the BSP from the APs and perform a separate
-; and appropriate list of tasks for each class of core.
-; For the BSP, the following actions are performed:
-; Allocate buffer space for the tables.
-; Generate the table contents.
-; Make sure that the CPU is in a known good power state before
-; proceeding to boot the OS.
-; For the APs, the following actions are performed:
-; Final register settings preparing for entry to OS.
-; Establish the final PState for entry to OS.
-;
-; Dependencies:
-; This routine is expected to be executed late in the boot sequence
-; after main memory has been initialized, after PCI enumeration has
-; completed, after the host environment ACPI sub-system has started,
-; after the host environment has taken control of the APs, but just
-; before the start of OS boot.
-;
-; The host environment must provide the required call-outs listed in
-; the "Required Call-Out Procedures" section of the AGESA interface
-; specification to provide the buffer space in main memory and execute
-; code on the APs. The host environment must register the created ACPI
-; table in the main ACPI pointer tables. This may require moving the
-; generated tables to another location in memory.
-;
-; This procedure requires a stack. The host environment must establish
-; the stack environment prior to making the call to this procedure.
-; Some functions depend upon the preservation of the heap data across
-; the shift from pre-memory environment to a post-memory environment.
-; If that data was not preserved, then those functions cannot complete
-; and an error is returned.
-;
-AmdInitLateWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitLate
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_LATE
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitLate entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ALERT
- ;; AGESA_ERROR The system could not allocate the needed amount of
- ;; buffer space; or could not locate the artifact data block in
- ;; memory. Likely cause: the host environment may not have preserved
- ;; the data properly.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_LATE_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- push es
- mov ax, SEG AmdAcpiSratPointer
- mov es, ax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiSrat
- mov es:AmdAcpiSratPointer, ebx
- mov eax, DWORD PTR [ebx + 4]
- mov es:AmdAcpiSratSize, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiSlit
- mov es:AmdAcpiSlitPointer, ebx
- mov eax, DWORD PTR [ebx + 4]
- mov es:AmdAcpiSlitSize, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiPState
- mov es:AmdAcpiSsdtPointer, ebx
- mov eax, DWORD PTR [ebx + 4]
- mov es:AmdAcpiSsdtSize, eax
-
- xor eax, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiWheaMce
- mov es:AmdAcpiWheaMcePointer, ebx
- mov ax, WORD PTR [ebx]
- mov es:AmdAcpiWheaMceSize, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiWheaMce
- mov es:AmdAcpiWheaCmcPointer, ebx
- mov ax, WORD PTR [ebx]
- mov es:AmdAcpiWheaCmcSize, eax
-
- mov eax, (AMD_LATE_PARAMS ptr [esi]).DmiTable
- mov es:AmdDmiInfoPointer, eax
- pop es
-
-
- ; Allow AGESA to free the space used by AmdInitLate
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-
-AmdInitLateWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdS3SaveWrapper
-;
-; Entry:
-; On Entry to "AmdS3Save" AGESA will display AGESA_TESTPOINT - CEh
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Entry to "AmdS3Save" AGESA will display AGESA_TESTPOINT - CFh
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure saves critical registers and/or configuration
-; information for preservation across a system suspend mode. All
-; actions needed to prepare the processor for suspend mode is
-; performed, however this procedure does NOT initiate the suspend
-; process. The host environment is expected to perform that duty.
-;
-; These actions are performed by the BSP. The APs are not assigned
-; any tasks at this time point.
-;
-; The initializer routine will NULL out the save area pointers and
-; sizes. This procedure will determine the size of storage needed
-; for all the processor context, and make a call out to the environment
-; for allocation of one buffer to store all of the data. Upon exit, the
-; pointers and sizes within the AMD_S3_PARAMS structure will be updated
-; with the appropriate addresses within the buffer that was allocated.
-; The host environment is expected to then transfer the data pointed to
-; by NvStorage to a non-volatile storage area, and the data pointed to
-; by VolatileStorage to either a non-volatile storage area or system
-; RAM that retains its content across suspend.
-;
-; Dependencies:
-; The host environment must initiate the suspend process.
-;
-; This procedure requires a stack. The host environment must establish
-; the stack environment prior to making the call to this procedure.
-;
-AmdS3SaveWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdS3Save
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_S3_SAVE
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
- call oemPlatformConfigInit
-
- ; Call in to the AmdS3Save entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS All suspend duties have been completed successfully.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_S3SAVE_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- mov ecx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.NvStorageSize
- .if (ecx != 0)
- mov ebx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.NvStorage
- call mySaveNonVolatileS3Context
- .endif
-
- mov ecx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.VolatileStorageSize
- .if (ecx != 0)
- mov ebx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.VolatileStorage
- call mySaveVolatileS3Context
- .endif
-
- ; Allow AGESA to free the space used by AmdS3Save
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-
-AmdS3SaveWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdS3LateRestoreWrapper
-;
-; Entry:
-; On Entry to "AmdS3LateRestore" AGESA will display AGESA_TESTPOINT - D2h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdS3LateRestore" AGESA will display AGESA_TESTPOINT - D3h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure restores the processor state, reloads critical
-; silicon component registers, and performs any re-initialization
-; required by the silicon. This procedure will use the context data
-; in the VolatileStorage area of the input structure to restore the
-; processor registers.
-;
-; The host environment must fill the AMD_S3_PARAMS NvStorage and
-; VolatileStorage pointers and related size elements to describe
-; the location of the context data. Note that for this procedure,
-; the two data areas do not need to be contained in one buffer zone,
-; they can be anywhere in the accessible memory address space. If
-; the host environment uses a non-volatile storage device accessed
-; on the system address bus such as flashROM, then the context data
-; does not need to be moved prior to this call. If the host
-; environment uses a non-volatile storage device not located on the
-; system address bus (e.g. CMOS or SSEPROM) then the host environment
-; must transfer the context data to a buffer in main memory prior to
-; calling this procedure.
-;
-; These actions are performed by the BSP. The APs are not assigned
-; any tasks at this time point.
-;
-; Dependencies:
-; This procedure is called late in the resume sequence, after the
-; PCI control space is restored and just before resuming operating
-; system execution.
-;
-; The host environment must initiate the OS restart process.
-;
-; This procedure requires a stack. The host environment must establish
-; the stack environment prior to making the call to this procedure.
-;
-AmdS3LateRestoreWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdS3LateRestore
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_S3LATE_RESTORE
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
- call oemPlatformConfigInit
-
- call myGetVolatileS3Context
- mov (AMD_S3LATE_PARAMS ptr [esi]).S3DataBlock.VolatileStorage, ebx
- mov (AMD_S3LATE_PARAMS ptr [esi]).S3DataBlock.VolatileStorageSize, ecx
-
- ; Call in to the AmdS3LateRestore entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS All resume processes have been completed successfully.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_S3LATE_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdS3LateRestore
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-AmdS3LateRestoreWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdLateRunApTaskWrapper
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - D4h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - D5h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This entry point is tightly connected with the "AgesaRunFcnOnAp"
-; call out. The AGESA software will call the call-out "AgesaRunFcnOnAp";
-; the host environment will then call this entry point to have the AP
-; execute the requested function. This is needed late in the Post and
-; Resume branches for running an AP task since the AGESA software has
-; relinquished control of the APs to the host environment.
-;
-; Dependencies:
-; The host environment must implement the"AgesaRunFcnOnAp" call-out
-; and route execution to the target AP.
-;
-AmdLateRunApTaskWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdLateRunApTask
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_LATE_RUN_AP_TASK
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- push es
- mov ax, SEG AmdRunCodeOnApDataPointer
- mov es, ax
- mov eax, es:AmdRunCodeOnApDataPointer
- mov (AP_EXE_PARAMS PTR [esi]).RelatedDataBlock, eax
- mov eax, es:AmdRunCodeOnApDataSize
- mov (AP_EXE_PARAMS PTR [esi]).RelatedBlockLength, eax
- mov eax, es:AmdRunCodeOnApFunction
- mov (AP_EXE_PARAMS PTR [esi]).FunctionNumber, eax
- pop es
-
- ; Call in to the AmdLateRunApTask dispatcher
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- push es
- mov bx, SEG AmdRunCodeOnApStatus
- mov es, bx
- mov es:AmdRunCodeOnApStatus, eax
- pop es
-
- ; Allow AGESA to free the space used by AmdLateRunApTask
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-
-AmdLateRunApTaskWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdRunFuncOnAp (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E8h
-; EDX - Local APIC ID of the target core.
-; ESI - Pointer to an AP_EXE_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 FunctionNumber;
-; IN VOID *RelatedDataBlock;
-; IN UINT32 RelatedDataBlockLength;
-; } AP_EXE_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E9h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This is a required function, so this value
-; being returned causes a critical error
-; response value from the AGESAT software
-; function and no memory initialized.
-; AGESA_WARNING The AP did not respond.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of AP task dispatching.
-; This function must cause the indicated function code to be executed
-; upon the specified Application Processor. This procedure must be
-; executed in 32-bit mode. This function is required to be implemented
-; in the host environment.
-;
-; Dependencies:
-; The host environment must route execution to the target AP and
-; have that AP call the"AmdLateRunApTask" entry point.
-;
-AmdRunFuncOnAp PROC NEAR PUBLIC
-
- push es
- mov ax, SEG AmdRunCodeOnApDataPointer
- mov es, ax
- mov eax, (AP_EXE_PARAMS PTR [esi]).RelatedDataBlock
- mov es:AmdRunCodeOnApDataPointer, eax
- mov eax, (AP_EXE_PARAMS PTR [esi]).RelatedBlockLength
- mov es:AmdRunCodeOnApDataSize, eax
- mov eax, (AP_EXE_PARAMS PTR [esi]).FunctionNumber
- mov es:AmdRunCodeOnApFunction, eax
- mov eax, AGESA_UNSUPPORTED
- mov es:AmdRunCodeOnApStatus, eax
- pop es
-
- call myRunFuncOnAp
-
- push es
- mov ax, SEG AmdRunCodeOnApStatus
- mov es, ax
- mov eax, es:AmdRunCodeOnApStatus
- pop es
- ret
-AmdRunFuncOnAp ENDP
-
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCalloutRouterPost
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The call out router function for AmdInitEnv,
-; AmdInitMid, AmdInitLate, AmdS3Save, and
-; AmdS3LateRestore.
-;
-; Dependencies:
-; None
-;
-AmdCalloutRouterPost PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
- xor ax, ax
- mov ds, ax
- mov es, ax
- lea di, cs:CalloutRouterTablePost
- mov eax, AGESA_UNSUPPORTED
-
-loopThruTable:
- cmp di, OFFSET cs:CalloutRouterTablePostEnd
- jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
- cmp ecx, cs:[di].sOemCallout.FuncName
- je FoundMatch
- add di, SIZEOF sOemCallout
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemCallout.FuncPtr
- call bx
-
-amdCpuCalloutExit:
- ret
-AmdCalloutRouterPost ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the callout dispatch table for the POST segment
-;----------------------------------------------------------------------------
-
-CalloutRouterTablePost LABEL BYTE
- ;; Add entries as desired.
- sOemCallout <AGESA_ALLOCATE_BUFFER, OFFSET myAllocateBuffer>
- sOemCallout <AGESA_DEALLOCATE_BUFFER, OFFSET myDeallocateBuffer>
- sOemCallout <AGESA_LOCATE_BUFFER, OFFSET myLocateBuffer>
- sOemCallout <AGESA_RUNFUNC_ONAP, OFFSET AmdRunFuncOnAp>
-CalloutRouterTablePostEnd LABEL BYTE
-
-AMD_POST_END
-
-
-;----------------------------------------------------------------------------
-; CPU DATA SEGMENT
-; This segment must be writable, and present at the time that
-; AmdInitLate is run.
-;----------------------------------------------------------------------------
-
-CPU_DATASEG_START
-
- ;; Data used to store pointers for later use by the host environment.
- PUBLIC AmdAcpiSratPointer
- PUBLIC AmdAcpiSratSize
- PUBLIC AmdAcpiSlitPointer
- PUBLIC AmdAcpiSlitSize
- PUBLIC AmdAcpiSsdtPointer
- PUBLIC AmdAcpiSsdtSize
- PUBLIC AmdAcpiWheaMcePointer
- PUBLIC AmdAcpiWheaMceSize
- PUBLIC AmdAcpiWheaCmcPointer
- PUBLIC AmdAcpiWheaCmcSize
- PUBLIC AmdDmiInfoPointer
- AmdAcpiSratPointer DWORD ?
- AmdAcpiSratSize DWORD ?
- AmdAcpiSlitPointer DWORD ?
- AmdAcpiSlitSize DWORD ?
- AmdAcpiSsdtPointer DWORD ?
- AmdAcpiSsdtSize DWORD ?
- AmdAcpiWheaMcePointer DWORD ?
- AmdAcpiWheaMceSize DWORD ?
- AmdAcpiWheaCmcPointer DWORD ?
- AmdAcpiWheaCmcSize DWORD ?
- AmdDmiInfoPointer DWORD ?
-
- ;; Data used for communication between the AP and the BSP.
- PUBLIC AmdRunCodeOnApDataPointer
- PUBLIC AmdRunCodeOnApDataSize
- PUBLIC AmdRunCodeOnApFunction
- PUBLIC AmdRunCodeOnApStatus
- AmdRunCodeOnApDataPointer DWORD ?
- AmdRunCodeOnApDataSize DWORD ?
- AmdRunCodeOnApFunction DWORD ?
- AmdRunCodeOnApStatus DWORD ?
-
-CPU_DATASEG_END
-
-
-END
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/agesa.inc b/src/vendorcode/amd/agesa/f10/Legacy/agesa.inc
deleted file mode 100644
index c8985b0801..0000000000
--- a/src/vendorcode/amd/agesa/f10/Legacy/agesa.inc
+++ /dev/null
@@ -1,2466 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * Agesa structures and definitions
-; *
-; * Contains AMD AGESA core interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 47176 $ @e \$Date: 2011-02-15 19:56:01 -0700 (Tue, 15 Feb 2011) $
-;
-; ****************************************************************************
-; *
-; * Copyright (c) 2011, Advanced Micro Devices, Inc.
-; * All rights reserved.
-; *
-; * Redistribution and use in source and binary forms, with or without
-; * modification, are permitted provided that the following conditions are met:
-; * * Redistributions of source code must retain the above copyright
-; * notice, this list of conditions and the following disclaimer.
-; * * Redistributions in binary form must reproduce the above copyright
-; * notice, this list of conditions and the following disclaimer in the
-; * documentation and/or other materials provided with the distribution.
-; * * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; * its contributors may be used to endorse or promote products derived
-; * from this software without specific prior written permission.
-; *
-; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; *
-; *
-; **************************************************************************
-
-INCLUDE amd.inc
-UINT64 TEXTEQU <QWORD>
-UINT32 TEXTEQU <DWORD>
-UINT16 TEXTEQU <WORD>
-UINT8 TEXTEQU <BYTE>
-CHAR8 TEXTEQU <BYTE>
-BOOLEAN TEXTEQU <BYTE>
-POINTER TEXTEQU <DWORD>
-
- ; AGESA Types and Definitions
-
-
-
- ; AGESA BASIC CALLOUTS
- AGESA_MEM_RELEASE EQU 00028000h
-
- ; AGESA ADVANCED CALLOUTS, Processor
- AGESA_CHECK_UMA EQU 00028100h
- AGESA_DO_RESET EQU 00028101h
- AGESA_ALLOCATE_BUFFER EQU 00028102h
- AGESA_DEALLOCATE_BUFFER EQU 00028103h
- AGESA_LOCATE_BUFFER EQU 00028104h
- AGESA_RUNFUNC_ONAP EQU 00028105h
-
- ; AGESA ADVANCED CALLOUTS, HyperTransport
-
- ; AGESA ADVANCED CALLOUTS, Memory
- AGESA_READ_SPD EQU 00028140h
- AGESA_HOOKBEFORE_DRAM_INIT EQU 00028141h
- AGESA_HOOKBEFORE_DQS_TRAINING EQU 00028142h
- AGESA_READ_SPD_RECOVERY EQU 00028143h
- AGESA_HOOKBEFORE_EXIT_SELF_REF EQU 00028144h
-
- ; AGESA IDS CALLOUTS
- AGESA_GET_IDS_INIT_DATA EQU 00028200h
-
- ; AGESA GNB CALLOUTS
- AGESA_GNB_PCIE_SLOT_RESET EQU 00028301h
-; ------------------------------------------------------------------------
-
- ; HyperTransport Interface
-
-
-
-; -----------------------------------------------------------------------------
- ; HT DEFINITIONS AND MACROS
-
-; -----------------------------------------------------------------------------
-
-
- ; Width equates for call backs
- HT_WIDTH_8_BITS EQU 8
- HT_WIDTH_16_BITS EQU 16
- HT_WIDTH_4_BITS EQU 4
- HT_WIDTH_2_BITS EQU 2
- HT_WIDTH_NO_LIMIT EQU HT_WIDTH_16_BITS
-
- ; Frequency Limit equates for call backs which take a frequency supported mask.
- HT_FREQUENCY_LIMIT_200M EQU 1
- HT_FREQUENCY_LIMIT_400M EQU 7
- HT_FREQUENCY_LIMIT_600M EQU 1Fh
- HT_FREQUENCY_LIMIT_800M EQU 3Fh
- HT_FREQUENCY_LIMIT_1000M EQU 7Fh
- HT_FREQUENCY_LIMIT_HT1_ONLY EQU 7Fh
- HT_FREQUENCY_LIMIT_1200M EQU 0FFh
- HT_FREQUENCY_LIMIT_1400M EQU 1FFh
- HT_FREQUENCY_LIMIT_1600M EQU 3FFh
- HT_FREQUENCY_LIMIT_1800M EQU 7FFh
- HT_FREQUENCY_LIMIT_2000M EQU 0FFFh
- HT_FREQUENCY_LIMIT_2200M EQU 1FFFh
- HT_FREQUENCY_LIMIT_2400M EQU 3FFFh
- HT_FREQUENCY_LIMIT_2600M EQU 7FFFh
- HT_FREQUENCY_LIMIT_2800M EQU 27FFFh
- HT_FREQUENCY_LIMIT_3000M EQU 67FFFh
- HT_FREQUENCY_LIMIT_3200M EQU 0E7FFFh
- HT_FREQUENCY_LIMIT_3600M EQU 1E7FFFh
- HT_FREQUENCY_LIMIT_MAX EQU HT_FREQUENCY_LIMIT_3600M
- HT_FREQUENCY_NO_LIMIT EQU 0FFFFFFFFh
-
- ; Unit ID Clumping special values
- HT_CLUMPING_DISABLE EQU 00000000h
- HT_CLUMPING_NO_LIMIT EQU 0FFFFFFFFh
-
- HT_LIST_TERMINAL EQU 0FFh
- HT_LIST_MATCH_ANY EQU 0FEh
- HT_LIST_MATCH_INTERNAL_LINK EQU 0FDh
-
- ; Event Notify definitions
-
- ; Event definitions.
-
- ; Coherent subfunction events
- HT_EVENT_COH_EVENTS EQU 10001000h
- HT_EVENT_COH_NO_TOPOLOGY EQU 10011000h
- HT_EVENT_COH_OBSOLETE000 EQU 10021000h
- HT_EVENT_COH_PROCESSOR_TYPE_MIX EQU 10031000h
- HT_EVENT_COH_NODE_DISCOVERED EQU 10041000h
- HT_EVENT_COH_MPCAP_MISMATCH EQU 10051000h
-
- ; Non-coherent subfunction events
- HT_EVENT_NCOH_EVENTS EQU 10002000h
- HT_EVENT_NCOH_BUID_EXCEED EQU 10012000h
- HT_EVENT_NCOH_OBSOLETE000 EQU 10022000h
- HT_EVENT_NCOH_BUS_MAX_EXCEED EQU 10032000h
- HT_EVENT_NCOH_CFG_MAP_EXCEED EQU 10042000h
- HT_EVENT_NCOH_DEVICE_FAILED EQU 10052000h
- HT_EVENT_NCOH_AUTO_DEPTH EQU 10062000h
-
- ; Optimization subfunction events
- HT_EVENT_OPT_EVENTS EQU 10003000h
- HT_EVENT_OPT_REQUIRED_CAP_RETRY EQU 10013000h
- HT_EVENT_OPT_REQUIRED_CAP_GEN3 EQU 10023000h
- HT_EVENT_OPT_UNUSED_LINKS EQU 10033000h
- HT_EVENT_OPT_LINK_PAIR_EXCEED EQU 10043000h
-
- ; HW Fault events
- HT_EVENT_HW_EVENTS EQU 10004000h
- HT_EVENT_HW_SYNCFLOOD EQU 10014000h
- HT_EVENT_HW_HTCRC EQU 10024000h
-
- ; The Recovery HT component uses 0x10005000 for events.
- ; For consistency, we avoid that range here.
-
- HT_MAX_NC_BUIDS EQU 32
-; ----------------------------------------------------------------------------
- ; HT TYPEDEFS, STRUCTURES, ENUMS
-
-; ----------------------------------------------------------------------------
-MATCHED EQU 0 ; < The link matches the requested customization.
-POWERED_OFF EQU 1 ; < Power the link off.
-UNMATCHED EQU 2 ; < The link should be processed according to normal defaults.
-MaxFinalLinkState EQU 3 ; < Not a final link state, use for limit checking.
-FINAL_LINK_STATE TEXTEQU <DWORD>
-
- ; Swap a device from its current id to a new one.
-
-BUID_SWAP_ITEM STRUCT
- FromId UINT8 ? ; < The device responding to FromId,
- ToId UINT8 ? ; < will be moved to ToId.
-BUID_SWAP_ITEM ENDS
-
-
- ; Each Non-coherent chain may have a list of device swaps. After performing the swaps,
- ; the final in order list of device ids is provided. (There can be more swaps than devices.)
- ; The unused entries in both are filled with 0xFF.
-
-BUID_SWAP_LIST STRUCT
- Swaps BUID_SWAP_ITEM (HT_MAX_NC_BUIDS) DUP ({}) ; < The BUID Swaps to perform
- FinalIds UINT8 (HT_MAX_NC_BUIDS) DUP (?) ; < The ordered final BUIDs, resulting from the swaps
-BUID_SWAP_LIST ENDS
-
-
- ; Control Manual Initialization of Non-Coherent Chains
-
- ; This interface is checked every time a non-coherent chain is
- ; processed. BUID assignment may be controlled explicitly on a
- ; non-coherent chain. Provide a swap list. Swaps controls the
- ; BUID assignment and FinalIds provides the device to device
- ; Linking. Device orientation can be detected automatically, or
- ; explicitly. See interface documentation for more details.
-
- ; If a manual swap list is not supplied,
- ; automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
- ; based on each device's unit count.
-
-MANUAL_BUID_SWAP_LIST STRUCT
- ; Match fields
- Socket UINT8 ? ; < The Socket on which this chain is located
- Link UINT8 ? ; < The Link on the host for this chain
- ; Override fields
- SwapList BUID_SWAP_LIST {} ; < The swap list
-MANUAL_BUID_SWAP_LIST ENDS
-
-
- ; Override options for DEVICE_CAP_OVERRIDE.
-
- ; Specify which override actions should be performed. For Checks, 1 means to check the item
- ; and 0 means to skip the check. For the override options, 1 means to apply the override and
- ; 0 means to ignore the override.
-
-DEVICE_CAP_OVERRIDE_OPTIONS STRUCT
- IsCheckDevVenId UINT32 ?
-; IN UINT32 IsCheckDevVenId:1; ; < Check Match on Device/Vendor id
-; IN UINT32 IsCheckRevision:1; ; < Check Match on device Revision
-; IN UINT32 IsOverrideWidthIn:1; ; < Override Width In
-; IN UINT32 IsOverrideWidthOut:1; ; < Override Width Out
-; IN UINT32 IsOverrideFreq:1; ; < Override Frequency
-; IN UINT32 IsOverrideClumping:1; ; < Override Clumping
-; IN UINT32 IsDoCallout:1; ; < Make the optional callout
-DEVICE_CAP_OVERRIDE_OPTIONS ENDS
-
- ; Override capabilities of a device.
-
- ; This interface is checked once for every Link on every IO device.
- ; Provide the width and frequency capability if needed for this device.
- ; This is used along with device capabilities, the limit interfaces, and northbridge
- ; limits to compute the default settings. The components of the device's PCI config
- ; address are provided, so its settings can be consulted if need be.
- ; The optional callout is a catch all.
-
-DEVICE_CAP_OVERRIDE STRUCT
- ; Match fields
- HostSocket UINT8 ? ; < The Socket on which this chain is located.
- HostLink UINT8 ? ; < The Link on the host for this chain.
- Depth UINT8 ? ; < The Depth in the I/O chain from the Host.
- DevVenId UINT32 ? ; < The Device's PCI Vendor + Device ID (offset 0x00).
- Revision UINT8 ? ; < The Device's PCI Revision field (offset 0x08).
- Link UINT8 ? ; < The Device's Link number (0 or 1).
- Options DEVICE_CAP_OVERRIDE_OPTIONS {} ; < The options for this device override.
- ; Override fields
- LinkWidthIn UINT8 ? ; < modify to change the Link Width In.
- LinkWidthOut UINT8 ? ; < modify to change the Link Width Out.
- FreqCap UINT32 ? ; < modify to change the Link's frequency capability.
- Clumping UINT32 ? ; < modify to change Unit ID clumping support.
- Callout CALLOUT_ENTRY ? ; < optional call for really complex cases, or NULL.
-DEVICE_CAP_OVERRIDE ENDS
-
- ; Callout param struct for override capabilities of a device.
-
- ; If the optional callout is implemented this param struct is passed to it.
-
-DEVICE_CAP_CALLOUT_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < The header
- ; Match fields
- HostSocket UINT8 ? ; < The Socket on which this chain is located.
- HostLink UINT8 ? ; < The Link on the host for this chain.
- Depth UINT8 ? ; < The Depth in the I/O chain from the Host.
- DevVenId UINT32 ? ; < The Device's PCI Vendor + Device ID (offset 0x00).
- Revision UINT8 ? ; < The Device's PCI Revision field (offset 0x08).
- Link UINT8 ? ; < The Device's Link number (0 or 1).
- PciAddress PCI_ADDR {} ; < The Device's PCI Address.
- ; Override fields
- LinkWidthIn POINTER ? ; < modify to change the Link Width In.
- LinkWidthOut POINTER ? ; < modify to change the Link Width Out.
- FreqCap POINTER ? ; < modify to change the Link's frequency capability.
- Clumping POINTER ? ; < modify to change Unit ID clumping support.
-DEVICE_CAP_CALLOUT_PARAMS ENDS
-
- ; Limits for CPU to CPU Links.
-
- ; For each coherent connection this interface is checked once.
- ; Provide the frequency and width if needed for this Link (usually based on board
- ; restriction). This is used with CPU device capabilities and northbridge limits
- ; to compute the default settings.
-
-CPU_TO_CPU_PCB_LIMITS STRUCT
- ; Match fields
- SocketA UINT8 ? ; < One Socket on which this Link is located
- LinkA UINT8 ? ; < The Link on this Node
- SocketB UINT8 ? ; < The other Socket on which this Link is located
- LinkB UINT8 ? ; < The Link on that Node
- ; Limit fields
- ABLinkWidthLimit UINT8 ? ; < modify to change the Link Width A->B
- BALinkWidthLimit UINT8 ? ; < modify to change the Link Width B-<A
- PcbFreqCap UINT32 ? ; < modify to change the Link's frequency capability
-CPU_TO_CPU_PCB_LIMITS ENDS
-
- ; Get limits for non-coherent Links.
-
- ; For each non-coherent connection this interface is checked once.
- ; Provide the frequency and width if needed for this Link (usually based on board
- ; restriction). This is used with device capabilities, device overrides, and northbridge limits
- ; to compute the default settings.
-
-IO_PCB_LIMITS STRUCT
- ; Match fields
- HostSocket UINT8 ? ; < The Socket on which this Link is located
- HostLink UINT8 ? ; < The Link about to be initialized
- Depth UINT8 ? ; < The Depth in the I/O chain from the Host
- ; Limit fields
- DownstreamLinkWidthLimit UINT8 ? ; < modify to change the Link Width going away from processor
- UpstreamLinkWidthLimit UINT8 ? ; < modify to change the Link Width moving toward processor
- PcbFreqCap UINT32 ? ; < modify to change the Link's frequency capability
-IO_PCB_LIMITS ENDS
-
- ; Manually control bus number assignment.
-
- ; This interface is checked every time a non-coherent chain is processed.
- ; If a system can not use the auto Bus numbering feature for non-coherent chain bus
- ; assignments, this interface can provide explicit control. For each chain, provide
- ; the bus number range to use.
-
-OVERRIDE_BUS_NUMBERS STRUCT
- ; Match fields
- Socket UINT8 ? ; < The Socket on which this chain is located
- Link UINT8 ? ; < The Link on the host for this chain
- ; Override fields
- SecBus UINT8 ? ; < Secondary Bus number for this non-coherent chain
- SubBus UINT8 ? ; < Subordinate Bus number
-OVERRIDE_BUS_NUMBERS ENDS
-
-
- ; Ignore a Link.
-
- ; This interface is checked every time a coherent Link is found and then every
- ; time a non-coherent Link from a CPU is found.
- ; Any coherent or non-coherent Link from a CPU can be ignored and not used
- ; for discovery or initialization. Useful for connection based systems.
- ; (Note: not checked for IO device to IO Device Links.)
-
-IGNORE_LINK STRUCT
- ; Match fields
- Socket UINT8 ? ; < The Socket on which this Link is located
- Link UINT8 ? ; < The Link about to be initialized
- ; Customization fields
- LinkState FINAL_LINK_STATE ? ; < The link may be left unitialized, or powered off.
-IGNORE_LINK ENDS
-
-
- ; Skip reganging of subLinks.
-
- ; This interface is checked whenever two subLinks are both connected to the same CPUs.
- ; Normally, unganged sublinks between the same two CPUs are reganged.
- ; Provide a matching structure to leave the Links unganged.
-
-SKIP_REGANG STRUCT
- ; Match fields
- SocketA UINT8 ? ; < One Socket on which this Link is located
- LinkA UINT8 ? ; < The Link on this Node
- SocketB UINT8 ? ; < The other Socket on which this Link is located
- LinkB UINT8 ? ; < The Link on that Node
- ; Customization fields
- LinkState FINAL_LINK_STATE ? ; < The paired sublink may be active, or powered off.
-SKIP_REGANG ENDS
-
- ; The System Socket layout, which sockets are physically connected.
-
- ; The hardware method for Socket naming is preferred. Use this software method only
- ; if required.
-
-SYSTEM_PHYSICAL_SOCKET_MAP STRUCT
- CurrentSocket UINT8 ? ; < The socket from which this connection originates.
- CurrentLink UINT8 ? ; < The Link from the source socket connects to another socket.
- TargetSocket UINT8 ? ; < The target socket which is connected on that link.
-SYSTEM_PHYSICAL_SOCKET_MAP ENDS
-
-; ----------------------------------------------------------------------------
-
- ; This is the input structure for AmdHtInitialize.
-
-AMD_HT_INTERFACE STRUCT
- ; Basic level customization
- AutoBusStart UINT8 ? ; < For automatic bus number assignment, starting bus number usually zero.
- AutoBusMax UINT8 ? ; < For automatic bus number assignment, do not assign above max.
- AutoBusIncrement UINT8 ? ; < For automatic bus number assignment, each chain gets this many busses.
-
- ; Advanced Level Customization
- ManualBuidSwapList POINTER ? ; < Provide Manual Swap List, if any.
- DeviceCapOverrideList POINTER ? ; < Provide Device Overrides, if any.
- CpuToCpuPcbLimitsList POINTER ? ; < Provide CPU PCB Limits, if any.
- IoPcbLimitsList POINTER ? ; < Provide IO PCB Limits, if any.
- OverrideBusNumbersList POINTER ? ; < Provide manual Bus Number assignment, if any.
- ; < Use either auto bus numbering or override bus
- ; < numbers, not both.
-
- IgnoreLinkList POINTER ? ; < Provide links to ignore, if any.
- SkipRegangList POINTER ? ; < Provide links to remain unganged, if any.
-
- ; Expert Level Customization
- Topolist POINTER ? ; < Use this topology list in addition to the built in, if not NULL.
- SystemPhysicalSocketMap POINTER ?
- ; < The hardware socket naming method is preferred,
- ; < If it can't be used, this provides a software method.
-AMD_HT_INTERFACE ENDS
-
-; -----------------------------------------------------------------------------
-
- ; HT Recovery Interface
-
-
-
-; -----------------------------------------------------------------------------
-; * HT Recovery DEFINITIONS AND MACROS
-; *
-; *-----------------------------------------------------------------------------
-;
-
- ; BBHT subfunction events
- HT_EVENT_BB_EVENTS EQU 10005000h
- HT_EVENT_BB_BUID_EXCEED EQU 10015000h
- HT_EVENT_BB_DEVICE_FAILED EQU 10055000h
- HT_EVENT_BB_AUTO_DEPTH EQU 10065000h
-
-; ----------------------------------------------------------------------------
-; * HT Recovery TYPEDEFS, STRUCTURES, ENUMS
-; *
-; *----------------------------------------------------------------------------
-;
-
-
- ; The Interface structure to Recovery HT.
-
-AMD_HT_RESET_INTERFACE STRUCT
- ManualBuidSwapList POINTER ? ; < Option to manually control SB link init
- Depth UINT32 ? ; < If auto init was used this is set to the depth of the chain,
- ; < else, for manual init unmodified.
-AMD_HT_RESET_INTERFACE ENDS
-
-; ---------------------------------------------------------------------------
-; CPU Feature related info
-; ---------------------------------------------------------------------------
- ; Build Configuration values for BLDCFG_PLATFORM_C1E_MODE
- C1eModeDisabled EQU 0 ; < Disabled
- C1eModeHardware EQU 1 ; < Hardware method
- C1eModeMsgBased EQU 2 ; < Message-based method
- MaxC1eMode EQU 3 ; < Not a valid value, used for verifying input
-PLATFORM_C1E_MODES TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
- CStateModeDisabled EQU 0 ; < Disabled
- CStateModeC6 EQU 1 ; < C6 State
- MaxCStateMode EQU 2 ; < Not a valid value, used for verifying input
-PLATFORM_CSTATE_MODES TEXTEQU <DWORD>
-
-
-;----------------------------------------------------------------------------
-; GNB PCIe configuration info
-;----------------------------------------------------------------------------
-
-GNB_EVENT_INVALID_CONFIGURATION EQU 20010000h ; User configuration invalid
-GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION EQU 20010001h ; Requested lane allocation for PCIe port can not be supported
-GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION EQU 20010002h ; Requested incorrect PCIe port device address
-GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION EQU 20010003h ; Incorrect parameter in DDI link configuration
-GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION EQU 20010004h ; Invalid with for PCIe port or DDI link
-GNB_EVENT_INVALID_DDI_LANES_CONFIGURATION EQU 20010005h ; DDI lane double subscribe lanes
-GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION EQU 20010006h ; Requested lane allocation for DDI link(s) can not be supported
-GNB_EVENT_LINK_TRAINING_FAIL EQU 20020000h ; PCIe Link training fail
-GNB_EVENT_BROKEN_LANE_RECOVERY EQU 20030000h ; Broken lane workaround applied to recover link training
-GNB_EVENT_GEN2_SUPPORT_RECOVERY EQU 20040000h ; Scale back to GEN1 to recover link training
-
-DESCRIPTOR_TERMINATE_LIST EQU 80000000h
-
-PCIe_PORT_DATA STRUCT
- PortPresent UINT8 ? ; < Enable PCIe port for initialization.
- ChannelType UINT8 ? ; < Channel type.
- ; 0 - "lowLoss",
- ; 1 - "highLoss",
- ; 2 - "mob0db",
- ; 3 - "mob3db",
- ; 4 - "extnd6db"
- ; 5 - "extnd8db"
- ;
- DeviceNumber UINT8 ? ; < Device number for port. Available device numbers may very on different CPUs.
- FunctionNumber UINT8 ? ; < Reserved for future use
- LinkSpeedCapability UINT8 ? ; < Advertised Gen Capability
- ; 0 - Maximum supported by silicon
- ; 1 - Gen1
- ; 2 - Gen2
- ; 3 - Gen3
- ;
- LinkSpeed UINT8 ? ; < Default boot up speed
- ; 0 - Maximum supported by silicon
- ; 1 - Gen1
- ; 2 - Gen2
- ; 3 - Gen3
- ;
- LinkAspm UINT8 ? ; < ASPM control. (see OemPcieLinkAspm for additional option to control ASPM)
- ; 0 - Disabled
- ; 1 - L0s only
- ; 2 - L1 only
- ; 2 - L0s and L1
- ;
- LinkHotplug UINT8 ? ; < Hotplug control.
- ; 0 - Disabled
- ; 1 - Basic
- ; 2 - Server
- ; 3 - Enhanced
- ;
- ResetId UINT8 ? ; < Arbitrary number greater than 0 assigned by platform firmware for GPIO
- ; identification which control reset for given port.
- ; Each port with unique GPIO should have unique ResetId assigned.
- ; All ports use same GPIO to control reset should have same ResetId assigned.
- ; see AgesaPcieSlotResetControl
- ;
- Compliance UINT8 ? ; < Force port into compliance mode (device will not be trained, port output compliance pattern)
-PCIe_PORT_DATA ENDS
-
-; DDI Configuration
-PCIe_DDI_DATA STRUCT
- ConnectorType UINT8 ? ; < Display Connector Type
- ; 0 - DP
- ; 1 - eDP
- ; 2 - Single Link DVI
- ; 3 - Dual Link DVI
- ; 4 - HDMI
- ; 5 - Travis DP-to-VGA
- ; 6 - Travis DP-to-LVDS
- ; 7 - SB900 NutMeg DP-to-VGA
- ;
- AuxIndex UINT8 ? ; < Indicates which AUX or DDC Line is used
- ; 0 - AUX1
- ; 1 - AUX2
- ; 2 - AUX3
- ; 3 - AUX4
- ; 4 - AUX5
- ; 5 - AUX6
- ;
- HdpIndex UINT8 ? ; < Indicates which HDP pin is used
- ; 0 - HDP1
- ; 1 - HDP2
- ; 2 - HDP3
- ; 3 - HDP4
- ; 4 - HDP5
- ; 5 - HDP6
-PCIe_DDI_DATA ENDS
-
-
-; Engine Configuration
-PCIe_ENGINE_DATA STRUCT
- EngineType UINT8 ? ; < Engine type
- ; 0 - Ignore engine configuration
- ; 1 - PCIe port
- ; 2 - DDI
- StartLane UINT16 ? ; < Start lane number (in reversed configuration StartLane > EndLane).
- EndLane UINT16 ? ; < End lane number (in reversed configuration StartLane > EndLane).
-PCIe_ENGINE_DATA ENDS
-
-; PCIe port descriptor
-PCIe_PORT_DESCRIPTOR STRUCT
- Flags UINT32 ? ; < Descriptor flags
- ; Bit31 - last descriptor in complex
- EngineData PCIe_ENGINE_DATA {} ; < Engine data
- Port PCIe_PORT_DATA {} ; < PCIe port specific configuration info
-PCIe_PORT_DESCRIPTOR ENDS
-
-; DDI descriptor
-PCIe_DDI_DESCRIPTOR STRUCT
- Flags UINT32 ? ; < Descriptor flags
- EngineData PCIe_ENGINE_DATA {} ; < Engine data
- Ddi PCIe_DDI_DATA {} ; < DDI port specific configuration info
-PCIe_DDI_DESCRIPTOR ENDS
-
-; Slot Reset Info
-PCIe_SLOT_RESET_INFO STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < AGESA Standard Header
- ResetId UINT8 ? ; < Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
- ResetControl UINT8 ? ; < Reset control as defined by PCIE_RESET_CONTROL
-PCIe_SLOT_RESET_INFO ENDS
-
-
-; PCIe Complex descriptor
-PCIe_COMPLEX_DESCRIPTOR STRUCT
- Flags UINT32 ? ; < Descriptor flags
- ; Bit31 - last descriptor in topology
- ;
- ;
- SocketId UINT32 ? ; < Socket Id
- PciePortList POINTER ? ;< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
- DdiLinkList POINTER ? ;< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
- Reserved POINTER ? ;< Reserved for future use
-PCIe_COMPLEX_DESCRIPTOR ENDS
-
- AssertSlotReset EQU 0
- DeassertSlotReset EQU 1
-PCIE_RESET_CONTROL TEXTEQU <DWORD>
-
- PcieUnusedEngine EQU 0
- PciePortEngine EQU 1
- PcieDdiEngine EQU 2
- MaxPcieEngine EQU 3 ; < Not a valid value, used for verifying input
-PCIE_ENGINE_TYPE TEXTEQU <DWORD>
-
- PcieGenMaxSupported EQU 0
- PcieGen1 EQU 1
- PcieGen2 EQU 2
- MaxPcieGen EQU 3 ; < Not a valid value, used for verifying input
-PCIE_LINK_SPEED_CAP TEXTEQU <DWORD>
-
- PsppDisabled EQU 0
- PsppPerformance EQU 1
- PsppBalanceHigh EQU 2
- PsppBalanceLow EQU 3
- PsppPowerSaving EQU 4
- MaxPspp EQU 5 ; < Not a valid value, used for verifying input
-PCIE_PSPP_POLICY TEXTEQU <DWORD>
-
- ConnectorTypeDP EQU 0
- ConnectorTypeEDP EQU 1
- ConnectorTypeSingleLinkDVI EQU 2
- ConnectorTypeDualLinkDVI EQU 3
- ConnectorTypeHDMI EQU 4
- ConnectorTypeTravisDpToVga EQU 5
- ConnectorTypeTravisDpToLvds EQU 6
- ConnectorTypeNutmegDpToVga EQU 7
- MaxConnectorType EQU 8 ; < Not a valid value, used for verifying input
-PCIE_CONNECTOR_TYPE TEXTEQU <DWORD>
-
- ChannelTypeLowLoss EQU 0
- ChannelTypeHighLoss EQU 1
- ChannelTypeMob0db EQU 2
- ChannelTypeMob3db EQU 3
- ChannelTypeExt6db EQU 4
- ChannelTypeExt8db EQU 5
- MaxChannelType EQU 6 ; < Not a valid value, used for verifying input
-PCIE_CHANNEL_TYPE TEXTEQU <DWORD>
-
- AspmDisabled EQU 0
- AspmL0s EQU 1
- AspmL1 EQU 2
- AspmL0sL1 EQU 3
- MaxAspm EQU 4 ; < Not a valid value, used for verifying input
-PCIE_ASPM_TYPE TEXTEQU <DWORD>
-
- HotplugDisabled EQU 0
- HotplugBasic EQU 1
- HotplugServer EQU 2
- HotplugEnhanced EQU 3
- MaxHotplug EQU 4 ; < Not a valid value, used for verifying input
-PCIE_HOTPLUG_TYPE TEXTEQU <DWORD>
-
- PortDisabled EQU 0
- PortEnabled EQU 1
-PCIE_PORT_ENABLE TEXTEQU <DWORD>
-
- Aux1 EQU 0
- Aux2 EQU 1
- Aux3 EQU 2
- Aux4 EQU 3
- Aux5 EQU 4
- Aux6 EQU 5
- MaxAux EQU 6 ; < Not a valid value, used for verifying input
-PCIE_AUX_TYPE TEXTEQU <DWORD>
-
- Hdp1 EQU 0
- Hdp2 EQU 1
- Hdp3 EQU 2
- Hdp4 EQU 3
- Hdp5 EQU 4
- Hdp6 EQU 5
- MaxHdp EQU 6 ; < Not a valid value, used for verifying input
-PCIE_HDP_TYPE TEXTEQU <DWORD>
-
-;----------------------------------------------------------------------------
-; GNB configuration info
-;----------------------------------------------------------------------------
-;
-
-; GNB configuration info
-GNB_CONFIGURATION STRUCT
- PcieComplexList POINTER ? ; Pointer to array of PCIe_COMPLEX_DESCRIPTOR structures describe PCIe topology on each processor package or NULL.
- ; Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST
- ;
- ;
- ;
- ; Topology organization definition assume PCIe_COMPLEX_DESCRIPTOR defined first following
- ; PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR for given PCIe_COMPLEX_DESCRIPTOR
- ; defined in arbitrary sequence:
- ; Example of topology definition for single socket system:
- ; PlatfromTopology LABEL DWORD
- ;
- ; Port0_2 PCIe_PORT_DESCRIPTOR <>;
- ; Port0_3 PCIe_PORT_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST> ;
- ; ...
- ; Ddi0_A PCIe_DDI_DESCRIPTOR <>;
- ; Ddi0_B PCIe_DDI_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST,>;
- ; ...
- ; Cpu0 PCIe_COMPLEX_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST, 0, Port0_2, Ddi0_A>
- ;
- ;
- PsppPolicy UINT8 ? ;< PSPP (PCIe Speed Power Policy)
- ; @li @b 0 - Disabled
- ; @li @b 1 - Performance
- ; @li @b 2 - Balance-High
- ; @li @b 3 - Balance-Low
- ; @li @b 4 - Power Saving
- ;
-GNB_CONFIGURATION ENDS
-
-
-; ---------------------------------------------------------------------------
-
-; MEMORY-SPECIFIC DATA STRUCTURES
-
-; ---------------------------------------------------------------------------
-
-
- ; AGESA MAXIMIUM VALUES
-
- ; These Max values are used to define array sizes and associated loop
- ; counts in the code. They reflect the maximum values that AGESA
- ; currently supports and does not necessarily reflect the hardware
- ; capabilities of configuration.
-
-
- MAX_SOCKETS_SUPPORTED EQU 8 ; < Max number of sockets in system
- MAX_CHANNELS_PER_SOCKET EQU 4 ; < Max Channels per sockets
- MAX_DIMMS_PER_CHANNEL EQU 4 ; < Max DIMMs on a memory channel (independent of platform)
- NUMBER_OF_DELAY_TABLES EQU 9 ; < Number of tables defined in CH_DEF_STRUCT.
- ; < Eg: UINT16 *RcvEnDlys;
- ; < UINT8 *WrDqsDlys;
- ; < UINT8 *RdDqsDlys;
- ; < UINT8 *WrDatDlys;
- ; < UINT8 *RdDqsMinDlys;
- ; < UINT8 *RdDqsMaxDlys;
- ; < UINT8 *WrDatMinDlys;
- ; < UINT8 *WrDatMaxDlys;
- NUMBER_OF_FAILURE_MASK_TABLES EQU 1 ; < Number of failure mask tables
- MAX_PLATFORM_TYPES EQU 16 ; < Platform types per system
-
- MCT_TRNG_KEEPOUT_START EQU 00004000h ; < base [39:8]
- MCT_TRNG_KEEPOUT_END EQU 00007FFFh ; < base [39:8]
-
- UMA_ATTRIBUTE_INTERLEAVE EQU 80000000h ; < Uma Region is interleaved
-
- PSO_TABLE TEXTEQU <UINT8>; < Platform Configuration Table
-
- ; AGESA DEFINITIONS
-
- ; Many of these are derived from the platform and hardware specific definitions
-
- ; EccSymbolSize override value
- ECCSYMBOLSIZE_USE_BKDG EQU 0 ; < Use BKDG Recommended Value
- ECCSYMBOLSIZE_FORCE_X4 EQU 4 ; < Force to x4
- ECCSYMBOLSIZE_FORCE_X8 EQU 8 ; < Force to x8
- ; CPU Package Type
- PT_L1 EQU 0 ; < L1 Package type
- PT_M2 EQU 1 ; < AM Package type
- PT_S1 EQU 2 ; < S1 Package type
-
- ; Structures use to pass system Logical CPU-ID
-CPU_LOGICAL_ID STRUCT
- Family UINT64 ? ; < Indicates logical ID Family
- Revision UINT64 ? ; < Indicates logical ID Family
-CPU_LOGICAL_ID ENDS
-
- ; Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
-
- AMD_PLATFORM_SERVER EQU 8000h ; < Server
- AMD_PLATFORM_DESKTOP EQU 10000h ; < Desktop
- AMD_PLATFORM_MOBILE EQU 20000h ; < Mobile
-AMD_PLATFORM_TYPE TEXTEQU <DWORD>
-
- ; Dram technology type
-
- DDR2_TECHNOLOGY EQU 0 ; < DDR2 technology
- DDR3_TECHNOLOGY EQU 1 ; < DDR3 technology
-TECHNOLOGY_TYPE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
-
- DDR400_FREQUENCY EQU 200 ; < DDR 400
- DDR533_FREQUENCY EQU 266 ; < DDR 533
- DDR667_FREQUENCY EQU 333 ; < DDR 667
- DDR800_FREQUENCY EQU 400 ; < DDR 800
- DDR1066_FREQUENCY EQU 533 ; < DDR 1066
- DDR1333_FREQUENCY EQU 667 ; < DDR 1333
- DDR1600_FREQUENCY EQU 800 ; < DDR 1600
- DDR1866_FREQUENCY EQU 933 ; < DDR 1866
- UNSUPPORTED_DDR_FREQUENCY EQU 934 ; < Highest limit of DDR frequency
-MEMORY_BUS_SPEED TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
-
- QUADRANK_REGISTERED EQU 0
- QUADRANK_UNBUFFERED EQU 1
-QUANDRANK_TYPE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_TIMING_MODE_SELECT
-
- TIMING_MODE_AUTO EQU 0 ; < Use best rate possible
- TIMING_MODE_LIMITED EQU 1 ; < Set user top limit
- TIMING_MODE_SPECIFIC EQU 2 ; < Set user specified speed
-USER_MEMORY_TIMING_MODE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_POWER_DOWN_MODE
-
- POWER_DOWN_BY_CHANNEL EQU 0
- POWER_DOWN_BY_CHIP_SELECT EQU 1
-POWER_DOWN_MODE TEXTEQU <DWORD>
-
- ; Low voltage support
-
- VOLT1_5 EQU 0 ; < 1.5 Volt
- VOLT1_35 EQU 1 ; < 1.35 Volt
- VOLT1_25 EQU 2 ; < 1.25 Volt
- VOLT_UNSUPPORTED EQU 0xFF ; < No common voltage found
-DIMM_VOLTAGE TEXTEQU <DWORD>
-
- ; UMA Mode
-
- UMA_NONE EQU 0 ; < UMA None
- UMA_SPECIFIED EQU 1 ; < UMA Specified
- UMA_AUTO EQU 2 ; < UMA Auto
-UMA_MODE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_UMA_ALIGNMENT
-
- NO_UMA_ALIGNED EQU 00FFFFFFh
- UMA_128MB_ALIGNED EQU 00FFF800h
- UMA_256MB_ALIGNED EQU 00FFF000h
- UMA_512MB_ALIGNED EQU 00FFE000h
-UMA_ALIGNMENT TEXTEQU <DWORD>
- ; ===============================================================================
- ; Global MCT Configuration Status Word (GStatus)
- ; ===============================================================================
-
- GsbMTRRshort EQU 0 ; < Ran out of MTRRs while mapping memory
- GsbAllECCDimms EQU 1 ; < All banks of all Nodes are ECC capable
- GsbDramECCDis EQU 2 ; < Dram ECC requested but not enabled.
- GsbSoftHole EQU 3 ; < A Node Base gap was created
- GsbHWHole EQU 4 ; < A HW dram remap was created
- GsbNodeIntlv EQU 5 ; < Node Memory interleaving was enabled
- GsbSpIntRemapHole EQU 6 ; < Special condition for Node Interleave and HW remapping
- GsbEnDIMMSpareNW EQU 7 ; < Indicates that DIMM Spare can be used without a warm reset
-
- GsbEOL EQU 8 ; < End of list
-GLOBAL_STATUS_FIELD TEXTEQU <DWORD>
-
-; ===============================================================================
- ; Local Error Status (DIE_STRUCT.ErrStatus[31:0])
-; ===============================================================================
-
- EsbNoDimms EQU 0 ; < No DIMMs
- EsbSpdChkSum EQU 1 ; < SPD Checksum fail
- EsbDimmMismatchM EQU 2 ; < dimm module type(buffer) mismatch
- EsbDimmMismatchT EQU 3 ; < dimm CL/T mismatch
- EsbDimmMismatchO EQU 4 ; < dimm organization mismatch (128-bit)
- EsbNoTrcTrfc EQU 5 ; < SPD missing Trc or Trfc info
- EsbNoCycTime EQU 6 ; < SPD missing byte 23 or 25
- EsbBkIntDis EQU 7 ; < Bank interleave requested but not enabled
- EsbDramECCDis EQU 8 ; < Dram ECC requested but not enabled
- EsbSpareDis EQU 9 ; < Online spare requested but not enabled
- EsbMinimumMode EQU 10 ; < Running in Minimum Mode
- EsbNoRcvrEn EQU 11 ; < No DQS Receiver Enable pass window found
- EsbSmallRcvr EQU 12 ; < DQS Rcvr En pass window too small (far right of dynamic range)
- EsbNoDqsPos EQU 13 ; < No DQS-DQ passing positions
- EsbSmallDqs EQU 14 ; < DQS-DQ passing window too small
- EsbDCBKScrubDis EQU 15 ; < DCache scrub requested but not enabled
-
- EsbEMPNotSupported EQU 16 ; < Processor is not capable for EMP.
- EsbEMPConflict EQU 17 ; < EMP requested but cannot be enabled since
- ; < channel interleaving, bank interleaving, or bank swizzle is enabled.
- EsbEMPDis EQU 18 ; < EMP requested but cannot be enabled since
- ; < memory size of each DCT is not a power of two.
-
- EsbEOL EQU 19 ; < End of list
-ERROR_STATUS_FIELD TEXTEQU <DWORD>
-
-; ===============================================================================
- ; Local Configuration Status (DIE_STRUCT.Status[31:0])
-; ===============================================================================
-
- SbRegistered EQU 0 ; < All DIMMs are Registered
- SbEccDimms EQU 1 ; < All banks ECC capable
- SbParDimms EQU 2 ; < All banks Addr/CMD Parity capable
- SbDiagClks EQU 3 ; < Jedec ALL slots clock enable diag mode
- Sb128bitmode EQU 4 ; < DCT in 128-bit mode operation
- Sb64MuxedMode EQU 5 ; < DCT in 64-bit mux'ed mode.
- Sb2TMode EQU 6 ; < 2T CMD timing mode is enabled.
- SbSWNodeHole EQU 7 ; < Remapping of Node Base on this Node to create a gap.
- SbHWHole EQU 8 ; < Memory Hole created on this Node using HW remapping.
- SbOver400Mhz EQU 9 ; < DCT freq greater than or equal to 400MHz flag
- SbDQSPosPass2 EQU 10 ; < Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
- SbDQSRcvLimit EQU 11 ; < Used for DQSRcvEnTrain to know we have reached the upper bound.
- SbExtConfig EQU 12 ; < Indicate the default setting for extended PCI configuration support
-
- SbEOL EQU 13 ; < End of list
-LOCAL_STATUS_FIELD TEXTEQU <DWORD>
-
-
-; < CPU MSR Register definitions ------------------------------------------
- SYS_CFG EQU 0C0010010h
- TOP_MEM EQU 0C001001Ah
- TOP_MEM2 EQU 0C001001Dh
- HWCR EQU 0C0010015h
- NB_CFG EQU 0C001001Fh
-
- FS_BASE EQU 0C0000100h
- IORR0_BASE EQU 0C0010016h
- IORR0_MASK EQU 0C0010017h
- BU_CFG EQU 0C0011023h
- BU_CFG2 EQU 0C001102Ah
- COFVID_STAT EQU 0C0010071h
- TSC EQU 10h
-
-; ===============================================================================
- ; SPD Data for each DIMM
-; ===============================================================================
-SPD_DEF_STRUCT STRUCT
- DimmPresent BOOLEAN ? ; < Indicates that the DIMM is present and Data is valid
- Data UINT8 (256) DUP (?) ; < Buffer for 256 Bytes of SPD data from DIMM
-SPD_DEF_STRUCT ENDS
-
-; ===============================================================================
- ; Channel Definition Structure
- ; This data structure defines entries that are specific to the channel initialization
-; ===============================================================================
-CH_DEF_STRUCT STRUCT
- ChannelID UINT8 ? ; < Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
- TechType TECHNOLOGY_TYPE ? ; < Technology type of this channel
- ChDimmPresent UINT8 ? ; < For each bit n 0..7, 1 = DIMM n is present.
- ; < DIMM# Select Signal
- ; < 0 MA0_CS_L[0, 1]
- ; < 1 MB0_CS_L[0, 1]
- ; < 2 MA1_CS_L[0, 1]
- ; < 3 MB1_CS_L[0, 1]
- ; < 4 MA2_CS_L[0, 1]
- ; < 5 MB2_CS_L[0, 1]
- ; < 6 MA3_CS_L[0, 1]
- ; < 7 MB3_CS_L[0, 1]
-
- DCTPtr POINTER ? ; < Pointer to the DCT data of this channel.
- MCTPtr POINTER ? ; < Pointer to the node data of this channel.
- SpdPtr POINTER ? ; < Pointer to the SPD data for this channel. (Setup by NB Constructor)
- DimmSpdPtr POINTER (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Array of pointers to
- ; < SPD Data for each Dimm. (Setup by Tech Block Constructor)
- ChDimmValid UINT8 ? ; < For each bit n 0..7, 1 = DIMM n is valid and is/will be configured
- RegDimmPresent UINT8 ? ; < For each bit n 0..7, 1 = DIMM n is a registered DIMM
- SODimmPresent UINT8 ? ; < For each bit n 0..7, 1 = DIMM n is a SO-DIMM
- Loads UINT8 ? ; < Number of devices loading bus
- Dimms UINT8 ? ; < Number of DIMMs loading Channel
- Ranks UINT8 ? ; < Number of ranks loading Channel DATA
- SlowMode BOOLEAN ? ; < 1T or 2T CMD mode (slow access mode)
- ; < FALSE = 1T
- ; < TRUE = 2T
- ; < The following pointers will be pointed to dynamically allocated buffers.
- ; < Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
- ; < Example: If DIMM and Byte based training, then
- ; < XX is a value in Hex
- ; < BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
- ; < Row1 - Logical DIMM0 XX XX XX XX XX XX XX XX XX
- ; < Row2 - Logical DIMM1 XX XX XX XX XX XX XX XX XX
- RcvEnDlys POINTER ? ; < DQS Receiver Enable Delays
- WrDqsDlys POINTER ? ; < Write DQS delays (only valid for DDR3)
- RdDqsDlys POINTER ? ; < Read Dqs delays
- WrDatDlys POINTER ? ; < Write Data delays
- RdDqsMinDlys POINTER ? ; < Minimum Window for Read DQS
- RdDqsMaxDlys POINTER ? ; < Maximum Window for Read DQS
- WrDatMinDlys POINTER ? ; < Minimum Window for Write data
- WrDatMaxDlys POINTER ? ; < Maximum Window for Write data
- RowCount UINT8 ? ; < Number of rows of the allocated buffer.
- ColumnCount UINT8 ? ; < Number of columns of the allocated buffer.
-
- FailingBitMask POINTER ? ; < Table of masks to Track Failing bits
- DctOdcCtl UINT32 ? ; < Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
- DctAddrTmg UINT32 ? ; < Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
- PhyRODTCSLow UINT32 ? ; < Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h)
- PhyRODTCSHigh UINT32 ? ; < Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h)
- PhyWODTCSLow UINT32 ? ; < Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h)
- PhyWODTCSHigh UINT32 ? ; < Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183)
- PhyWLODT UINT8 (4) DUP (?) ; < Write Levelization ODT Pattern for Dimm 0-3 (see BKDG FN2:Offset 9Ch, index 0x8[11:8])
- DctEccDqsLike UINT16 ? ; < DCT DQS ECC UINT8 like...
- DctEccDqsScale UINT8 ? ; < DCT DQS ECC UINT8 scale
- PtrPatternBufA UINT16 ? ; < Ptr on stack to aligned DQS testing pattern
- PtrPatternBufB UINT16 ? ; < Ptr on stack to aligned DQS testing pattern
- ByteLane UINT8 ? ; < Current UINT8 Lane (0..7)
- Direction UINT8 ? ; < Current DQS-DQ training write direction (0=read, 1=write)
- Pattern UINT8 ? ; < Current pattern
- DqsDelay UINT8 ? ; < Current DQS delay value
- HostBiosSrvc1 UINT16 ? ; < UINT16 sized general purpose field for use by host BIOS. Scratch space.
- HostBiosSrvc2 UINT32 ? ; < UINT32 sized general purpose field for use by host BIOS. Scratch space.
- DctMaxRdLat UINT16 ? ; < Max Read Latency (ns) for the DCT
- DIMMValidCh UINT8 ? ; < DIMM# in CH
- MaxCh UINT8 ? ; < Max number of CH in system
- Dct UINT8 ? ; < Dct pointer
- WrDatGrossH UINT8 ? ; < Write Data Gross delay high value
- DqsRcvEnGrossL UINT8 ? ; < DQS Receive Enable Gross Delay low
-
- TrwtWB UINT8 ? ; < Non-SPD timing value for TrwtWB
- CurrRcvrDctADelay UINT8 ? ; < for keep current RcvrEnDly
- T1000 UINT16 ? ; < get the T1000 figure (cycle time (ns) * 1K)
- DqsRcvEnPass UINT8 ? ; < for TrainRcvrEn UINT8 lane pass flag
- DqsRcvEnSaved UINT8 ? ; < for TrainRcvrEn UINT8 lane saved flag
- SeedPass1Remainder UINT8 ? ; < for Phy assisted DQS receiver enable training
-
- ClToNbFlag UINT8 ? ; < is used to restore ClLinesToNbDis bit after memory
- NodeSysBase UINT32 ? ; < for channel interleave usage
- RefRawCard UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Array of rawcards detected
- CtrlWrd02 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 2 values per DIMM
- CtrlWrd03 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 3 values per DIMM
- CtrlWrd04 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 4 values per DIMM
- CtrlWrd05 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 5 values per DIMM
- CtrlWrd08 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 8 values per DIMM
-
- CsPresentDCT UINT16 ? ; < For each bit n 0..7, 1 = Chip-select n is present
- DimmMirrorPresent UINT8 ? ; < For each bit n 0..7, 1 = DIMM n is OnDimmMirror capable
- DimmSpdCse UINT8 ? ; < For each bit n 0..7, 1 = DIMM n SPD checksum error
- DimmExclude UINT8 ? ; < For each bit n 0..7, 1 = DIMM n gets excluded
- DimmYr06 UINT8 ? ; < Bitmap indicating which Dimms have a manufacturer's year code <= 2006
- DimmWk2406 UINT8 ? ; < Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
- DimmPlPresent UINT8 ? ; < Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
- DimmQrPresent UINT8 ? ; < QuadRank DIMM present?
- DimmDrPresent UINT8 ? ; < Bitmap indicating that Dual Rank Dimms are present
- DimmSRPresent UINT8 ? ; < Bitmap indicating that Single Rank Dimms are present
- Dimmx4Present UINT8 ? ; < For each bit n 0..7, 1 = DIMM n contains x4 data devices.
- Dimmx8Present UINT8 ? ; < For each bit n 0..7, 1 = DIMM n contains x8 data devices.
- Dimmx16Present UINT8 ? ; < For each bit n 0..7, 1 = DIMM n contains x16 data devices.
-
- MemClkDisMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
- ; < base on this array to disable unused MemClk to save power.
- ; <
- ; < The array must have 8 entries. Each entry, which associates with
- ; < one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
- ; < Example:
- ; < BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package
- ; < is like below:
- ; < Bit AM3/S1g3 pin name
- ; < 0 M[B,A]_CLK_H/L[0]
- ; < 1 M[B,A]_CLK_H/L[1]
- ; < 2 M[B,A]_CLK_H/L[2]
- ; < 3 M[B,A]_CLK_H/L[3]
- ; < 4 M[B,A]_CLK_H/L[4]
- ; < 5 M[B,A]_CLK_H/L[5]
- ; < 6 M[B,A]_CLK_H/L[6]
- ; < 7 M[B,A]_CLK_H/L[7]
- ; < And platform has the following routing:
- ; < CS0 M[B,A]_CLK_H/L[4]
- ; < CS1 M[B,A]_CLK_H/L[2]
- ; < CS2 M[B,A]_CLK_H/L[3]
- ; < CS3 M[B,A]_CLK_H/L[5]
- ; < Then MemClkDisMap should be pointed to the following array:
- ; < CLK_2 CLK_3 CLK_4 CLK_5
- ; < 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00
- ; < Each entry of the array is the bitmask of 8 chip selects.
-
- CKETriMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of CKE pins to the DIMMs' ranks.
- ; < The array must have 2 entries. Each entry, which associates with
- ; < one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
- ; < AGESA will base on this array to disable unused CKE pins to save power.
-
- ODTTriMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of ODT pins to the DIMMs' ranks.
- ; < The array must have 4 entries. Each entry, which associates with
- ; < one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
- ; < AGESA will base on this array to disable unused ODT pins to save power.
-
- ChipSelTriMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of chip select pins to the DIMMs' ranks.
- ; < The array must have 8 entries. Each entry is a bitmap of 8 CS.
- ; < AGESA will base on this array to disable unused Chip select pins to save power.
-
- ExtendTmp BOOLEAN ? ; < If extended temperature is supported on all dimms on a channel.
-
- Reserved UINT8 (100) DUP (?) ; < Reserved
-CH_DEF_STRUCT ENDS
-
-; ===============================================================================
- ; DCT Channel Timing Parameters
- ; This data structure sets timings that are specific to the channel
-; ===============================================================================
-CH_TIMING_STRUCT STRUCT
- DctDimmValid UINT16 ? ; < For each bit n 0..7, 1=DIMM n is valid and is/will be configured
- DimmMirrorPresent UINT16 ? ; < For each bit n 0..7, 1=DIMM n is OnDimmMirror capable
- DimmSpdCse UINT16 ? ; < For each bit n 0..7, 1=DIMM n SPD checksum error
- DimmExclude UINT16 ? ; < For each bit n 0..7, 1 = DIMM n gets excluded because of no common voltage is found
- CsPresent UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is present
- CsEnabled UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is enabled
- CsTestFail UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is present but disabled
- CsTrainFail UINT16 ? ; < Bitmap showing which chipselects failed training
- DIMM1KPage UINT16 ? ; < For each bit n 0..7, 1=DIMM n contains 1K page devices.
- DimmQrPresent UINT16 ? ; < QuadRank DIMM present?
- DimmDrPresent UINT16 ? ; < Bitmap indicating that Dual Rank Dimms are present
- DimmSRPresent UINT8 ? ; < Bitmap indicating that Single Rank Dimms are present
- Dimmx4Present UINT16 ? ; < For each bit n 0..7, 1=DIMM n contains x4 data devices.
- Dimmx8Present UINT16 ? ; < For each bit n 0..7, 1=DIMM n contains x8 data devices.
- Dimmx16Present UINT16 ? ; < For each bit n 0..7, 1=DIMM n contains x16 data devices.
-
- DIMMTrcd UINT16 ? ; < Minimax Trcd*40 (ns) of DIMMs
- DIMMTrp UINT16 ? ; < Minimax Trp*40 (ns) of DIMMs
- DIMMTrtp UINT16 ? ; < Minimax Trtp*40 (ns) of DIMMs
- DIMMTras UINT16 ? ; < Minimax Tras*40 (ns) of DIMMs
- DIMMTrc UINT16 ? ; < Minimax Trc*40 (ns) of DIMMs
- DIMMTwr UINT16 ? ; < Minimax Twr*40 (ns) of DIMMs
- DIMMTrrd UINT16 ? ; < Minimax Trrd*40 (ns) of DIMMs
- DIMMTwtr UINT16 ? ; < Minimax Twtr*40 (ns) of DIMMs
- DIMMTfaw UINT16 ? ; < Minimax Tfaw*40 (ns) of DIMMs
- TargetSpeed UINT16 ? ; < Target DRAM bus speed in MHz
- Speed UINT16 ? ; < DRAM bus speed in MHz
- ; < 400 (MHz)
- ; < 533 (MHz)
- ; < 667 (MHz)
- ; < 800 (MHz)
- ; < and so on...
- CasL UINT8 ? ; < CAS latency DCT setting (busclocks)
- Trcd UINT8 ? ; < DCT Trcd (busclocks)
- Trp UINT8 ? ; < DCT Trp (busclocks)
- Trtp UINT8 ? ; < DCT Trtp (busclocks)
- Tras UINT8 ? ; < DCT Tras (busclocks)
- Trc UINT8 ? ; < DCT Trc (busclocks)
- Twr UINT8 ? ; < DCT Twr (busclocks)
- Trrd UINT8 ? ; < DCT Trrd (busclocks)
- Twtr UINT8 ? ; < DCT Twtr (busclocks)
- Tfaw UINT8 ? ; < DCT Tfaw (busclocks)
- Trfc0 UINT8 ? ; < DCT Logical DIMM0 Trfc
- ; < 0 = 75ns (for 256Mb devs)
- ; < 1 = 105ns (for 512Mb devs)
- ; < 2 = 127.5ns (for 1Gb devs)
- ; < 3 = 195ns (for 2Gb devs)
- ; < 4 = 327.5ns (for 4Gb devs)
- Trfc1 UINT8 ? ; < DCT Logical DIMM1 Trfc (see Trfc0 for format)
- Trfc2 UINT8 ? ; < DCT Logical DIMM2 Trfc (see Trfc0 for format)
- Trfc3 UINT8 ? ; < DCT Logical DIMM3 Trfc (see Trfc0 for format)
- DctMemSize UINT32 ? ; < Base[47:16], total DRAM size controlled by this DCT.
- SlowMode BOOLEAN ? ; < 1T or 2T CMD mode (slow access mode)
- ; < FALSE = 1T
- ; < TRUE = 2T
- TrwtTO UINT8 ? ; < DCT TrwtTO (busclocks)
- Twrrd UINT8 ? ; < DCT Twrrd (busclocks)
- Twrwr UINT8 ? ; < DCT Twrwr (busclocks)
- Trdrd UINT8 ? ; < DCT Trdrd (busclocks)
- TrwtWB UINT8 ? ; < DCT TrwtWB (busclocks)
- TrdrdSD UINT8 ? ; < DCT TrdrdSD (busclocks)
- TwrwrSD UINT8 ? ; < DCT TwrwrSD (busclocks)
- TwrrdSD UINT8 ? ; < DCT TwrrdSD (busclocks)
- MaxRdLat UINT16 ? ; < Max Read Latency
- WrDatGrossH UINT8 ? ; < Temporary variables must be removed
- DqsRcvEnGrossL UINT8 ? ; < Temporary variables must be removed
-CH_TIMING_STRUCT ENDS
-
-; ===============================================================================
- ; Data for each DCT
- ; This data structure defines data used to configure each DRAM controller
-; ===============================================================================
-DCT_STRUCT STRUCT
- Dct UINT8 ? ; < Current Dct
- Timings CH_TIMING_STRUCT {} ; < Channel Timing structure
- ChData POINTER ? ; < Pointed to a dynamically allocated array of Channel structures
- ChannelCount UINT8 ? ; < Number of channel per this DCT
-DCT_STRUCT ENDS
-
-
-; ===============================================================================
- ; Data Structure defining each Die
- ; This data structure contains information that is used to configure each Die
-; ===============================================================================
-DIE_STRUCT STRUCT
-
- ; Advanced:
-
- NodeId UINT8 ? ; < Node ID of current controller
- SocketId UINT8 ? ; < Socket ID of this Die
- DieId UINT8 ? ; < ID of this die relative to the socket
- PciAddr PCI_ADDR {} ; < Pci bus and device number of this controller.
- ErrCode AGESA_STATUS ? ; < Current error condition of Node
- ; < 0x0 = AGESA_SUCCESS
- ; < 0x1 = AGESA_UNSUPPORTED
- ; < 0x2 = AGESA_BOUNDS_CHK
- ; < 0x3 = AGESA_ALERT
- ; < 0x4 = AGESA_WARNING
- ; < 0x5 = AGESA_ERROR
- ; < 0x6 = AGESA_CRITICAL
- ; < 0x7 = AGESA_FATAL
- ; <
- ErrStatus BOOLEAN (EsbEOL) DUP (?) ; < Error Status bit Field
- Status BOOLEAN (SbEOL) DUP (?) ; < Status bit Field
- NodeMemSize UINT32 ? ; < Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
- NodeSysBase UINT32 ? ; < Base[47:16] (system address) DRAM base address of this Node.
- NodeHoleBase UINT32 ? ; < If not zero, Base[47:16] (system address) of dram hole for HW remapping. Dram hole exists on this Node
- NodeSysLimit UINT32 ? ; < Base[47:16] (system address) DRAM limit address of this Node.
- DimmPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is present.
- ; < DIMM# Select Signal
- ; < 0 MA0_CS_L[0, 1]
- ; < 1 MB0_CS_L[0, 1]
- ; < 2 MA1_CS_L[0, 1]
- ; < 3 MB1_CS_L[0, 1]
- ; < 4 MA2_CS_L[0, 1]
- ; < 5 MB2_CS_L[0, 1]
- ; < 6 MA3_CS_L[0, 1]
- ; < 7 MB3_CS_L[0, 1]
- DimmValid UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
- RegDimmPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is registered DIMM
- DimmEccPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is ECC capable.
- DimmParPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
- DimmTrainFail UINT16 ? ; < Bitmap showing which dimms failed training
- ChannelTrainFail UINT16 ? ; < Bitmap showing the channel information about failed Chip Selects
- ; < 0 in any bit field indicates Channel 0
- ; < 1 in any bit field indicates Channel 1
- Dct UINT8 ? ; < Need to be removed
- ; < DCT pointer
- GangedMode BOOLEAN ? ; < Ganged mode
- ; < 0 = disabled
- ; < 1 = enabled
- LogicalCpuid CPU_LOGICAL_ID {} ; < The logical CPUID of the node
- HostBiosSrvc1 UINT16 ? ; < UINT16 sized general purpose field for use by host BIOS. Scratch space.
- HostBiosSrvc2 UINT32 ? ; < UINT32 sized general purpose field for use by host BIOS. Scratch space.
- MLoad UINT8 ? ; < Need to be removed
- ; < Number of devices loading MAA bus
- MaxAsyncLat UINT8 ? ; < Legacy wrapper
- ChbD3Rcvrdly UINT8 ? ; < Legacy wrapper
- ChaMaxRdLat UINT16 ? ; < Max Read Latency (ns) for DCT 0
- ChbD3BcRcvrdly UINT8 ? ; < CHB DIMM 3 Check UINT8 Receiver Enable Delay
-
- DctData POINTER ? ; < Pointed to a dynamically allocated array of DCT_STRUCTs
- DctCount UINT8 ? ; < Number of DCTs per this Die
- Reserved UINT8 (16) DUP (?) ; < Reserved
-DIE_STRUCT ENDS
-
-; *********************************************************************
-; * S3 Support structure
-; *********************************************************************
- ; AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure
-AMD_S3_PARAMS STRUCT
- Signature UINT32 ? ; < "ASTR" for AMD Suspend-To-RAM
- Version UINT16 ? ; < S3 Params version number
- Flags UINT32 ? ; < Indicates operation
- NvStorage POINTER ? ; < Pointer to memory critical save state data
- NvStorageSize UINT32 ? ; < Size in bytes of the NvStorage region
- VolatileStorage POINTER ? ; < Pointer to remaining AMD save state data
- VolatileStorageSize UINT32 ? ; < Size in bytes of the VolatileStorage region
-AMD_S3_PARAMS ENDS
-
-; ===============================================================================
- ; MEM_PARAMETER_STRUCT
- ; This data structure is used to pass wrapper parameters to the memory configuration code
-; ===============================================================================
-MEM_PARAMETER_STRUCT STRUCT
-
- ; Basic (Return parameters)
- ; (This section contains the outbound parameters from the memory init code)
-
- GStatus BOOLEAN (GsbEOL) DUP (?) ; < Global Status bitfield
- HoleBase UINT32 ? ; < If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping.
- Sub4GCacheTop UINT32 ? ; < If not zero, the 32-bit top of cacheable memory.
- Sub1THoleBase UINT32 ? ; < If not zero Base[47:16] (system address) of sub 1TB dram hole.
- SysLimit UINT32 ? ; < Limit[47:16] (system address)
- DDR3Voltage DIMM_VOLTAGE ? ; < Find support voltage and send back to platform BIOS.
- ; < 0 = 1.5v
- ; < 1 = 1.35v
- ; < 2 = 1.2v
- ; < 0xFF = Mixed 1.5V and 1.2V in the system. 1.5V dimms get excluded
- ; < from the system.
- ; <
-
- MemData POINTER ? ; < Pointer to MEM_DATA_STRUCT
- ; Advanced (Optional parameters)
- ; Optional (all defaults values will be initialized by the
- ; 'AmdMemInitDataStructDef' based on AMD defaults. It is up
- ; to the IBV/OEM to change the defaults after initialization
- ; but prior to the main entry to the memory code):
-
- ; Memory Map/Mgt.
-
- BottomIo UINT16 ? ; < Bottom of 32-bit IO space (8-bits)
- ; < NV_BOTTOM_IO[7:0]=Addr[31:24]
- MemHoleRemapping BOOLEAN ? ; < Memory Hole Remapping (1-bit)
- ; < FALSE = disable
- ; < TRUE = enable
- LimitMemoryToBelow1Tb BOOLEAN ? ; < Limit memory address space to below 1 TB
- ; < FALSE = disable
- ; < TRUE = enable
- ; Dram Timing
-
- UserTimingMode USER_MEMORY_TIMING_MODE ? ; < User Memclock Mode
-
- MemClockValue MEMORY_BUS_SPEED ? ; < Memory Clock Value
-
- ; Dram Configuration
-
- EnableBankIntlv BOOLEAN ? ; < Dram Bank (chip-select) Interleaving (1-bit)
- ; < FALSE =disable (AMD default)
- ; < TRUE =enable
- EnableNodeIntlv BOOLEAN ? ; < Node Memory Interleaving (1-bit)
- ; < FALSE = disable (AMD default)
- ; < TRUE = enable
- EnableChannelIntlv BOOLEAN ? ; < Channel Interleaving (1-bit)
- ; < FALSE = disable (AMD default)
- ; < TRUE = enable
- ; ECC
-
- EnableEccFeature BOOLEAN ? ; < enable ECC error to go into MCE
- ; < FALSE = disable (AMD default)
- ; < TRUE = enable
- ; Dram Power
-
- EnablePowerDown BOOLEAN ? ; < CKE based power down mode (1-bit)
- ; < FALSE =disable (AMD default)
- ; < TRUE =enable
- ; Online Spare
-
- EnableOnLineSpareCtl BOOLEAN ? ; < Chip Select Spare Control bit 0:
- ; < FALSE = disable Spare (AMD default)
- ; < TRUE = enable Spare
- TableBasedAlterations POINTER ? ; < Point to an array of data bytes describing desired modifications to register settings.
-
- PlatformMemoryConfiguration POINTER ?
- ; < Points to a table that contains platform specific settings
- ; < (i.e. MemClk routing, the number of DIMM slots per channel,...)
- ; < AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that
- ; < contains default conservative settings. Platform BIOS can either tweak
- ; < DefaultPlatformMemoryConfiguration or reassign this pointer to its own table.
- ; <
- EnableParity BOOLEAN ? ; < Parity control
- ; < TRUE = enable
- ; < FALSE = disable (AMD default)
- EnableBankSwizzle BOOLEAN ? ; < BankSwizzle control
- ; < FALSE = disable
- ; < TRUE = enable (AMD default)
- EnableMemClr BOOLEAN ? ; < Memory Clear functionality control
- ; < FALSE = disable
- ; < TRUE = enable (AMD default)
- ; Uma Configuration
-
- UmaMode UMA_MODE ? ; < Uma Mode
- ; < 0 = None
- ; < 1 = Specified
- ; < 2 = Auto
- UmaSize UINT32 ? ; < The size of shared graphics dram (16-bits)
- ; < NV_UMA_Size[31:0]=Addr[47:16]
- ; <
- UmaBase UINT32 ? ; < The allocated Uma base address (32-bits)
- ; < NV_UMA_Base[31:0]=Addr[47:16]
- ; <
-
- ; Memory Restore Feature
-
- MemRestoreCtl BOOLEAN ? ; < Memory context restore control
- ; < FALSE = perform memory init as normal (AMD default)
- ; < TRUE = restore memory context and skip training. This requires
- ; < MemContext is valid before AmdInitPost
- SaveMemContextCtl BOOLEAN ? ; < Control switch to save memory context at the end of MemAuto
- ; < TRUE = AGESA will setup MemContext block before exit AmdInitPost
- ; < FALSE = AGESA will not setup MemContext block. Platform is
- ; < expected to call S3Save later in POST if it wants to
- ; < use memory context restore feature.
- MemContext AMD_S3_PARAMS {} ; < Memory context block describes the data that platform needs to
- ; < save and restore for memory context restore feature to work.
- ; < It uses the subset of S3Save block to save/restore. Hence platform
- ; < may save only S3 block and uses it for both S3 resume and
- ; < memory context restore.
- ; < - If MemRestoreCtl is TRUE, platform needs to pass in MemContext
- ; < before AmdInitPost.
- ; < - If SaveMemContextCtl is TRUE, platform needs to save MemContext
- ; < right after AmdInitPost.
-MEM_PARAMETER_STRUCT ENDS
-
-
-; ===============================================================================
- ; Function definition
- ; This data structure passes function pointers to the memory configuration code.
- ; The wrapper can use this structure with customized versions
-; ================================================================================
-MEM_FUNCTION_STRUCT STRUCT
-
- ; PUBLIC required Internal functions
-
- amdMemGetPsCfgU POINTER ? ; < Proc for Unbuffered DIMMs, platform specific
- amdMemGetPsCfgR POINTER ? ; < Proc for Registered DIMMs, platform specific
-
- ; PUBLIC optional functions
-
- amdMemEccInit POINTER ? ; < NB proc for ECC feature
- amdMemChipSelectInterleaveInit POINTER ? ; < NB proc for CS interleave feature
- amdMemDctInterleavingInit POINTER ? ; < NB proc for Channel interleave feature
- amdMemMctInterleavingInit POINTER ? ; < NB proc for Node interleave feature
- amdMemParallelTraining POINTER ? ; < NB proc for parallel training feature
- amdMemEarlySampleSupport POINTER ? ; < NB code for early sample support feature
- amdMemMultiPartInitSupport POINTER ? ; < NB code for 'multi-part'
- amdMemOnlineSpareSupport POINTER ? ; < NB code for On-Line Spare feature
- amdMemUDimmInit POINTER ? ; < NB code for UDIMMs
- amdMemRDimmInit POINTER ? ; < NB code for RDIMMs
-
- Reserved UINT32 (100) DUP (?) ; < Reserved for later function definition
-MEM_FUNCTION_STRUCT ENDS
-
-; ===============================================================================
- ; Socket Structure
-
-; ===============================================================================
-MEM_SOCKET_STRUCT STRUCT
- ChannelPtr POINTER (MAX_CHANNELS_PER_SOCKET) DUP (?) ; < Pointers to each channels training data
-
- TimingsPtr POINTER (MAX_CHANNELS_PER_SOCKET) DUP (?) ; < Pointers to each channels timing data
-
-MEM_SOCKET_STRUCT ENDS
-
-; ===============================================================================
- ; MEM_DATA_STRUCT
-; ===============================================================================
-MEM_DATA_STRUCT STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < AGESA Standard Header
-
- ParameterListPtr POINTER ? ; < List of input Parameters
-
- FunctionList MEM_FUNCTION_STRUCT {} ; < List of function Pointers
-
- GetPlatformCfg POINTER (MAX_PLATFORM_TYPES) DUP (?) ; < look-up platform info
-
- ErrorHandling POINTER ? ; < Error Handling
-
- ; SocketList is a shortcut for IBVs to retrieve training
- ; and timing data for each channel indexed by socket/channel,
- ; eliminating their need to parse die/dct/channel etc.
- ; It contains pointers to the populated data structures for
- ; each channel and skips the channel structures that are
- ; unpopulated. In the case of channels sharing the same DCT,
- ; the pTimings pointers will point to the same DCT Timing data.
-
- SocketList MEM_SOCKET_STRUCT (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Socket list for memory code
-
- DiesPerSystem POINTER ? ; < Pointed to an array of DIE_STRUCTs
- DieCount UINT8 ? ; < Number of MCTs in the system.
-
- SpdDataStructure POINTER ? ; < Pointer to SPD Data structure
-
- PlatFormConfig POINTER ? ; < Pointer to Platform profile/build option config structure
-MEM_DATA_STRUCT ENDS
-
-; ===============================================================================
-; UMA_INFO_STRUCT
-; ===============================================================================
-UMA_INFO STRUCT
- UmaBase UINT64 ? ; < UmaBase[63:0] = Addr[63:0]
- UmaSize UINT32 ? ; < UmaSize[31:0] = Addr[31:0]
- UmaAttributes UINT32 ? ; < Indicate the attribute of Uma
- UmaMode UINT8 ? ; < Indicate the mode of Uma
- MemClock UINT16 ? ; < Indicate memory running speed in MHz
- Reserved UINT8 (3) DUP (?) ; < Reserved for future usage
-UMA_INFO ENDS
-
- ; AGESA MEMORY ERRORS
-
- ; AGESA_ALERT Memory Errors
-MEM_ALERT_USER_TMG_MODE_OVERRULED EQU 04010000h ; < TIMING_MODE_SPECIFIC is requested but
- ; < cannot be applied to current configurations.
-MEM_ALERT_ORG_MISMATCH_DIMM EQU 04010100h ; < DIMM organization miss-match
-MEM_ALERT_BK_INT_DIS EQU 04010200h ; < Bank interleaving disable for internal issue
-
- ; AGESA_ERROR Memory Errors
-MEM_ERROR_NO_DQS_POS_RD_WINDOW EQU 04010300h ; < No DQS Position window for RD DQS
-MEM_ERROR_SMALL_DQS_POS_RD_WINDOW EQU 04020300h ; < Small DQS Position window for RD DQS
-MEM_ERROR_NO_DQS_POS_WR_WINDOW EQU 04030300h ; < No DQS Position window for WR DQS
-MEM_ERROR_SMALL_DQS_POS_WR_WINDOW EQU 04040300h ; < Small DQS Position window for WR DQS
-MEM_ERROR_ECC_DIS EQU 04010400h ; < ECC has been disabled as a result of an internal issue
-MEM_ERROR_DIMM_SPARING_NOT_ENABLED EQU 04010500h ; < DIMM sparing has not been enabled for an internal issues
-MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE EQU 04050300h ; < Receive Enable value is too large
-MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW EQU 04060300h ; < There is no DQS receiver enable window
-MEM_ERROR_DRAM_ENABLED_TIME_OUT EQU 04010600h ; < Time out when polling DramEnabled bit
-MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT EQU 04010700h ; < Time out when polling DctAccessDone bit
-MEM_ERROR_SEND_CTRL_WORD_TIME_OUT EQU 04010800h ; < Time out when polling SendCtrlWord bit
-MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT EQU 04010900h ; < Time out when polling PrefDramTrainMode bit
-MEM_ERROR_ENTER_SELF_REF_TIME_OUT EQU 04010A00h ; < Time out when polling EnterSelfRef bit
-MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT EQU 04010B00h ; < Time out when polling FreqChgInProg bit
-MEM_ERROR_EXIT_SELF_REF_TIME_OUT EQU 04020A00h ; < Time out when polling ExitSelfRef bit
-MEM_ERROR_SEND_MRS_CMD_TIME_OUT EQU 04010C00h ; < Time out when polling SendMrsCmd bit
-MEM_ERROR_SEND_ZQ_CMD_TIME_OUT EQU 04010D00h ; < Time out when polling SendZQCmd bit
-MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT EQU 04010E00h ; < Time out when polling DctExtraAccessDone bit
-MEM_ERROR_MEM_CLR_BUSY_TIME_OUT EQU 04010F00h ; < Time out when polling MemClrBusy bit
-MEM_ERROR_MEM_CLEARED_TIME_OUT EQU 04020F00h ; < Time out when polling MemCleared bit
-MEM_ERROR_FLUSH_WR_TIME_OUT EQU 04011000h ; < Time out when polling FlushWr bit
-MEM_ERROR_MAX_LAT_NO_WINDOW EQU 04070300h ; < Fail to find pass during Max Rd Latency training
-MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL EQU 04080300h ; < Fail to launch training code on an AP
-MEM_ERROR_PARALLEL_TRAINING_TIME_OUT EQU 04090300h ; < Fail to finish parallel training
-MEM_ERROR_NO_ADDRESS_MAPPING EQU 04011100h ; < No address mapping found for a dimm
-MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT EQU 040A0300h ; < There is no DQS receiver enable window and the value is equal to the largest value
-MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE EQU 040B0300h ; < Receive Enable value is too large and is 1 less than limit
-MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR EQU 04011200h ; < SPD Checksum error for NV_SPDCHK_RESTRT
-MEM_ERROR_NO_CHIPSELECT EQU 04011300h ; < No chipselects found
-MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM EQU 04011500h ; < Unbuffered dimm is not supported at 333MHz
-
- ; AGESA_WARNING Memory Errors
- MEM_WARNING_UNSUPPORTED_QRDIMM EQU 04011600h ; < QR DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_UDIMM EQU 04021600h ; < U DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_SODIMM EQU 04031600h ; < SO-DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_X4DIMM EQU 04041600h ; < x4 DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_RDIMM EQU 04051600h ; < R DIMMs detected but not supported
- MEM_WARNING_EMP_NOT_SUPPORTED EQU 04011700h ; < Processor is not capable for EMP
- MEM_WARNING_EMP_CONFLICT EQU 04021700h ; < EMP cannot be enabled if channel interleaving,
- ; < bank interleaving, or bank swizzle is enabled.
- MEM_WARNING_EMP_NOT_ENABLED EQU 04031700h ; < Memory size is not power of two.
- MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED EQU 04011800h ; < Performance has been enabled, but battery life is preferred.
- MEM_WARNING_NO_SPDTRC_FOUND EQU 04011900h ; < No Trc timing value found in SPD of a dimm.
- MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED EQU 04012000h ; < Node Interleaveing Requested, but could not be enabled
- MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED EQU 04012100h ; < Channel Interleaveing Requested, but could not be enabled
- MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED EQU 04012200h ; < Bank Interleaveing Requested, but could not be enabled
- MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED EQU 04012300h ; < Voltage 1.35 determined, but could not be supported
-
- ; AGESA_FATAL Memory Errors
- MEM_ERROR_MINIMUM_MODE EQU 04011A00h ; < Running in minimum mode
- MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM EQU 04011B00h ; < DIMM modules are miss-matched
- MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM EQU 04011C00h ; < No DIMMs have been found on system
- MEM_ERROR_MISMATCH_DIMM_CLOCKS EQU 04011D00h ; < DIMM clocks miss-matched
- MEM_ERROR_NO_CYC_TIME EQU 04011E00h ; < No cycle time found
- MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS EQU 04011F00h ; < Heap allocation error with dynamic storing of trained timings
- MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs EQU 04021F00h ; < Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
- MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV EQU 04031F00h ; < Heap allocation error with REMOTE_TRAINING_ENV
- MEM_ERROR_HEAP_ALLOCATE_FOR_SPD EQU 04041F00h ; < Heap allocation error for SPD data
- MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA EQU 04051F00h ; < Heap allocation error for RECEIVED_DATA during parallel training
- MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS EQU 04061F00h ; < Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
- MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA EQU 04071F00h ; < Heap allocation error for Training Data
- MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK EQU 04081F00h ; < Heap allocation error for DIMM Identify "MEM_NB_BLOCK
- MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM EQU 04022300h ; < No Constructor for DIMM Identify
- MEM_ERROR_VDDIO_UNSUPPORTED EQU 04022500h ; < VDDIO of the dimms on the board is not supported
-
-
- ; AGESA_CRITICAL Memory Errors
- MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 EQU 04091F00h ; < Heap allocation error for DMI table for DDR3
- MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 EQU 040A1F00h ; < Heap allocation error for DMI table for DDR2
- MEM_ERROR_UNSUPPORTED_DIMM_CONFIG EQU 04011400h ; < Dimm population is not supported
-
-
-; ----------------------------------------------------------------------------
-; *
-; * END OF MEMORY-SPECIFIC DATA STRUCTURES
-; *
-; *----------------------------------------------------------------------------
-;
-
-
-; ----------------------------------------------------------------------------
-; *
-; * CPU RELATED DEFINITIONS
-; *
-; *----------------------------------------------------------------------------
-;
-
-; CPU Event definitions.
-
-; Defines used to filter CPU events based on functional blocks
-CPU_EVENT_PM_EVENT_MASK EQU 0FF00FF00h
-CPU_EVENT_PM_EVENT_CLASS EQU 008000400h
-
-;================================================================
-; CPU General events
-; Heap allocation (AppFunction = 01h)
-CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT EQU 008000100h
-CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED EQU 008010100h
-CPU_ERROR_HEAP_IS_FULL EQU 008020100h
-CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED EQU 008030100h
-CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT EQU 008040100h
-; BrandId (AppFunction = 02h)
-CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE EQU 008000200h
-; Micro code patch (AppFunction = 03h)
-CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED EQU 008000300h
-; Power management (AppFunction = 04h)
-CPU_EVENT_PM_PSTATE_OVERCURRENT EQU 008000400h
-CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT EQU 008010400h
-CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE EQU 008020400h
-; BIST (AppFunction = 05h)
-CPU_EVENT_BIST_ERROR EQU 008000500h
-;=================================================================
-; CPU Feature events
-; Execution cache (AppFunction = 21h)
-; AGESA_CACHE_SIZE_REDUCED 2101
-; AGESA_CACHE_REGIONS_ACROSS_1MB 2102
-; AGESA_CACHE_REGIONS_ACROSS_4GB 2103
-; AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 2104
-; AGESA_CACHE_START_ADDRESS_LESS_D0000 2105
-; AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 2106
-; AGESA_DEALLOCATE_CACHE_REGIONS 2107
-CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR EQU 008002100h
-; Core Leveling (AppFunction = 22h)
-CPU_WARNING_ADJUSTED_LEVELING_MODE EQU 008002200h
-; HT Assist (AppFunction = 23h)
-CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG EQU 008002300h
-
-; CPU Build Configuration structures and definitions
-
-; Build Configuration values for BLDGCFG_AP_MTRR_SETTINGS
-AP_MTRR_SETTINGS STRUCT
- MsrAddr UINT32 ? ; < Fixed-Sized MTRR address
- MsrData UINT64 ? ; < MTRR Settings
-AP_MTRR_SETTINGS ENDS
-
-AMD_AP_MTRR_FIX64k_00000 EQU 000000250h
-AMD_AP_MTRR_FIX16k_80000 EQU 000000258h
-AMD_AP_MTRR_FIX16k_A0000 EQU 000000259h
-AMD_AP_MTRR_FIX4k_C0000 EQU 000000268h
-AMD_AP_MTRR_FIX4k_C8000 EQU 000000269h
-AMD_AP_MTRR_FIX4k_D0000 EQU 00000026Ah
-AMD_AP_MTRR_FIX4k_D8000 EQU 00000026Bh
-AMD_AP_MTRR_FIX4k_E0000 EQU 00000026Ch
-AMD_AP_MTRR_FIX4k_E8000 EQU 00000026Dh
-AMD_AP_MTRR_FIX4k_F0000 EQU 00000026Eh
-AMD_AP_MTRR_FIX4k_F8000 EQU 00000026Fh
-CPU_LIST_TERMINAL EQU 0FFFFFFFFh
-
-; ***********************************************************************
-; *
-; * AGESA interface Call-Out function parameter structures
-; *
-; **********************************************************************
-
- ; Parameters structure for interface call-out AgesaAllocateBuffer
-AGESA_BUFFER_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- BufferLength UINT32 ? ; < Size of buffer to allocate
- BufferHandle UINT32 ? ; < Identifier or name for the buffer
- BufferPointer POINTER ? ; < location of the created buffer
-AGESA_BUFFER_PARAMS ENDS
-
- ; Parameters structure for interface call-out AgesaRunCodeOnAp
-AP_EXE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- FunctionNumber UINT32 ? ; < Index of the procedure to execute
- RelatedDataBlock POINTER ? ; < Location of data structure the procedure will use
- RelatedBlockLength UINT32 ? ; < Size of the related data block
-AP_EXE_PARAMS ENDS
-
- ; Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery
-AGESA_READ_SPD_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < standard header
- SocketId UINT8 ? ; < Address of SPD - socket ID
- MemChannelId UINT8 ? ; < Address of SPD - memory channel ID
- DimmId UINT8 ? ; < Address of SPD - DIMM ID
- Buffer POINTER ? ; < Location where to place the SPD content
- MemData POINTER ? ; < Location of the MemData structure, for reference
-AGESA_READ_SPD_PARAMS ENDS
-
- ; Buffer Handles
- AMD_DMI_INFO_BUFFER_HANDLE EQU 000D000h ; < Assign 0x000D000 buffer handle to DMI function
- AMD_PSTATE_DATA_BUFFER_HANDLE EQU 000D001h ; < Assign 0x000D001 buffer handle to Pstate data
- AMD_PSTATE_ACPI_BUFFER_HANDLE EQU 000D002h ; < Assign 0x000D002 buffer handle to Pstate table
- AMD_BRAND_ID_BUFFER_HANDLE EQU 000D003h ; < Assign 0x000D003 buffer handle to Brand ID
- AMD_ACPI_SLIT_BUFFER_HANDLE EQU 000D004h ; < Assign 0x000D004 buffer handle to SLIT function
- AMD_SRAT_INFO_BUFFER_HANDLE EQU 000D005h ; < Assign 0x000D005 buffer handle to SRAT function
- AMD_WHEA_BUFFER_HANDLE EQU 000D006h ; < Assign 0x000D006 buffer handle to WHEA function
- AMD_S3_INFO_BUFFER_HANDLE EQU 000D007h ; < Assign 0x000D007 buffer handle to S3 function
- AMD_S3_NB_INFO_BUFFER_HANDLE EQU 000D008h ; < Assign 0x000D008 buffer handle to S3 NB device info
-AMD_BUFFER_HANDLE TEXTEQU <DWORD>
-; ***********************************************************************
-; *
-; * AGESA interface Call-Out function prototypes
-; *
-; **********************************************************************
-
-; ***********************************************************************
-; *
-; * AGESA interface structure definition and function prototypes
-; *
-; **********************************************************************
-
-; *********************************************************************
-; * Platform Configuration: The parameters in boot branch function
-; *********************************************************************
-
-; The possible platform control flow settings.
- Nfcm EQU 0 ; < Normal Flow Control Mode.
- UmaDr EQU 1 ; < UMA using Display Refresh flow control.
- UmaIfcm EQU 2 ; < UMA using Isochronous Flow Control.
- Ifcm EQU 3 ; < Isochronous Flow Control Mode (other than for UMA).
- Iommu EQU 4 ; < An IOMMU is in use in the system.
- MaxControlFlow EQU 5 ; < Not a control flow mode, use for limit checking.
-PLATFORM_CONTROL_FLOW TEXTEQU <DWORD>
-
-; Platform Deemphasis Levels.
- DeemphasisLevelNone EQU 0 ; < No Deemphasis.
- DeemphasisLevelMinus3 EQU 1 ; < Minus 3 db deemphasis.
- DeemphasisLevelMinus6 EQU 2 ; < Minus 6 db deemphasis.
- DeemphasisLevelMinus8 EQU 3 ; < Minus 8 db deemphasis.
- DeemphasisLevelMinus11 EQU 4 ; < Minus 11 db deemphasis.
- DeemphasisLevelMinus11pre8 EQU 5 ; < Minus 11, Minus 8 precursor db deemphasis.
- DcvLevelNone EQU 16 ; < No DCV Deemphasis.
- DcvLevelMinus2 EQU 17 ; < Minus 2 db DCV deemphasis.
- DcvLevelMinus3 EQU 18 ; < Minus 3 db DCV deemphasis.
- DcvLevelMinus5 EQU 19 ; < Minus 5 db DCV deemphasis.
- DcvLevelMinus6 EQU 20 ; < Minus 6 db DCV deemphasis.
- DcvLevelMinus7 EQU 21 ; < Minus 7 db DCV deemphasis.
- DcvLevelMinus8 EQU 22 ; < Minus 8 db DCV deemphasis.
- DcvLevelMinus9 EQU 23 ; < Minus 9 db DCV deemphasis.
- DcvLevelMinus11 EQU 24 ; < Minus 11 db DCV deemphasis.
- MaxPlatformDeemphasisLevel EQU 25 ; < Not a deemphasis level, use for limit checking.
-PLATFORM_DEEMPHASIS_LEVEL TEXTEQU <DWORD>
-
-; Provide Deemphasis Levels for HT Links.
-;
-; For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will
-; be checked for a match. The item matches for a Socket, Link if the link frequency is
-; is in the inclusive range HighFreq:LoFreq.
-; AGESA does not set deemphasis in IO devices, only in processors.
-
-CPU_HT_DEEMPHASIS_LEVEL STRUCT
- ; Match fields
- Socket UINT8 ? ; < One Socket on which this Link is located
- Link UINT8 ? ; < The Link on this Processor.
- LoFreq UINT8 ? ; < If the link is set to this frequency or greater, apply these levels, and
- HighFreq UINT8 ? ; < If the link is set to this frequency or less, apply these levels.
- ; Value fields
- ReceiverDeemphasis PLATFORM_DEEMPHASIS_LEVEL ? ; < The deemphasis level for this link
- DcvDeemphasis PLATFORM_DEEMPHASIS_LEVEL ? ; < The DCV, or far transmitter deemphasis level.
-CPU_HT_DEEMPHASIS_LEVEL ENDS
-
-; The possible platform power policy settings.
- Performance EQU 0 ; < Optimize for performance.
- BatteryLife EQU 1 ; < Optimize for battery life.
- MaxPowerPolicy EQU 2 ; < Not a power policy mode, use for limit checking.
-PLATFORM_POWER_POLICY TEXTEQU <DWORD>
-
-; Platform performance settings for optimized settings.
-; Several configuration settings for the processor depend upon other parts and
-; general designer choices for the system. The determination of these data points
-; is not standard for all platforms, so the host environment needs to provide these
-; to specify how the system is to be configured.
-PERFORMANCE_PROFILE STRUCT
- PlatformControlFlowMode PLATFORM_CONTROL_FLOW ? ; < The platform's control flow mode for optimum platform performance.
- UseHtAssist BOOLEAN ? ; < HyperTransport link traffic optimization.
- Use32ByteRefresh BOOLEAN ? ; < Display Refresh traffic generates 32 byte requests.
- UseVariableMctIsocPriority BOOLEAN ? ; < The Memory controller will be set to Variable Isoc Priority.
- PlatformPowerPolicy PLATFORM_POWER_POLICY ? ; < The platform's desired power policy
-PERFORMANCE_PROFILE ENDS
-
-; Platform settings that describe the voltage regulator modules of the system.
-; Many power management settings are dependent upon the characteristics of the
-; on-board voltage regulator module (VRM). The host environment needs to provide
-; these to specify how the system is to be configured.
-PLATFORM_VRM_CONFIGURATION STRUCT
- CurrentLimit UINT32 ? ; < Vrm Current Limit.
- LowPowerThreshold UINT32 ? ; < Vrm Low Power Threshold.
- SlewRate UINT32 ? ; < Vrm Slew Rate.
- AdditionalDelay UINT32 ? ; < Vrm Additional Delay.
- HiSpeedEnable BOOLEAN ? ; < Select high speed VRM.
- InrushCurrentLimit UINT32 ? ; < Vrm Inrush Current Limit.
-PLATFORM_VRM_CONFIGURATION ENDS
-
-; Build Option/Configuration Boolean Structure
-BUILD_OPT_CFG STRUCT
- ; Build Option Area
- VersionString AMD_CODE_HEADER {} ; < AMD embedded code version string
- OptionUDimms BOOLEAN ? ; < UDIMMS
- OptionRDimms BOOLEAN ? ; < RDIMMS
- OptionEcc BOOLEAN ? ; < ECC
- OptionBankInterleave BOOLEAN ? ; < BANK_INTERLEAVE
- OptionDctInterleave BOOLEAN ? ; < DCT_INTERLEAVE
- OptionNodeInterleave BOOLEAN ? ; < NODE_INTERLEAVE
- OptionParallelTraining BOOLEAN ? ; < PARALLEL_TRAINING
- OptionOnlineSpare BOOLEAN ? ; < ONLINE_SPARE
- OptionMemRestore BOOLEAN ? ; < MEM CONTEXT RESTORE
- OptionMultisocket BOOLEAN ? ; < MULTISOCKET
- OptionAcpiPstates BOOLEAN ? ; < ACPI_PSTATES
- OptionSrat BOOLEAN ? ; < SRAT
- OptionSlit BOOLEAN ? ; < SLIT
- OptionWhea BOOLEAN ? ; < WHEA
- OptionDmi BOOLEAN ? ; < DMI
- OptionEarlySamples BOOLEAN ? ; < EARLY_SAMPLES
- OptionAddrToCsTranslator BOOLEAN ? ; < ADDR_TO_CS_TRANSLATOR
-
- ; Build Configuration Area
- CfgPciMmioAddress UINT64 ? ; < PciMmioBase
- CfgPciMmioSize UINT32 ? ; < PciMmioSize
- CfgPlatVrmCfg PLATFORM_VRM_CONFIGURATION {} ; < Several configuration settings for the voltage regulator module.
- CfgPlatNumIoApics UINT32 ? ; < PlatformApicIoNumber
- CfgMemInitPstate UINT32 ? ; < MemoryInitPstate
- CfgPlatformC1eMode PLATFORM_C1E_MODES ? ; < PlatformC1eMode
- CfgPlatformC1eOpData UINT32 ? ; < PlatformC1eOpData
- CfgPlatformCStateMode PLATFORM_CSTATE_MODES ? ; < PlatformCStateMode
- CfgPlatformCStateOpData UINT32 ? ; < PlatformCStateOpData
- CfgCoreLevelingMode UINT32 ? ; < CoreLevelingCofig
- CfgPerformanceProfile PERFORMANCE_PROFILE {} ; < The platform's control flow mode and platform performance settings.
- CfgPlatformDeemphasisList POINTER ? ; < HT Deemphasis
- CfgAmdPlatformType UINT32 ? ; < AmdPlatformType
- CfgAmdPstateCapValue UINT32 ? ; < Amd pstate ceiling enabling deck
-
- CfgMemoryBusFrequencyLimit MEMORY_BUS_SPEED ? ; < Memory Bus Frequency Limit
- CfgMemoryModeUnganged BOOLEAN ? ; < Memory Mode Unganged
- CfgMemoryQuadRankCapable BOOLEAN ? ; < Memory Quad Rank Capable
- CfgMemoryQuadrankType QUANDRANK_TYPE ? ; < Memory Quadrank Type
- CfgMemoryRDimmCapable BOOLEAN ? ; < Memory RDIMM Capable
- CfgMemoryUDimmCapable BOOLEAN ? ; < Memory UDIMM Capable
- CfgMemorySODimmCapable BOOLEAN ? ; < Memory SODimm Capable
- CfgLimitMemoryToBelow1Tb BOOLEAN ? ; < Limit memory address space to below 1TB
- CfgMemoryEnableBankInterleaving BOOLEAN ? ; < Memory Enable Bank Interleaving
- CfgMemoryEnableNodeInterleaving BOOLEAN ? ; < Memory Enable Node Interleaving
- CfgMemoryChannelInterleaving BOOLEAN ? ; < Memory Channel Interleaving
- CfgMemoryPowerDown BOOLEAN ? ; < Memory Power Down
- CfgPowerDownMode POWER_DOWN_MODE ? ; < Power Down Mode
- CfgOnlineSpare BOOLEAN ? ; < Online Spare
- CfgMemoryParityEnable BOOLEAN ? ; < Memory Parity Enable
- CfgBankSwizzle BOOLEAN ? ; < Bank Swizzle
- CfgTimingModeSelect USER_MEMORY_TIMING_MODE ? ; < Timing Mode Select
- CfgMemoryClockSelect MEMORY_BUS_SPEED ? ; < Memory Clock Select
- CfgDqsTrainingControl BOOLEAN ? ; < Dqs Training Control
- CfgIgnoreSpdChecksum BOOLEAN ? ; < Ignore Spd Checksum
- CfgUseBurstMode BOOLEAN ? ; < Use Burst Mode
- CfgMemoryAllClocksOn BOOLEAN ? ; < Memory All Clocks On
- CfgEnableEccFeature BOOLEAN ? ; < Enable ECC Feature
- CfgEccRedirection BOOLEAN ? ; < ECC Redirection
- CfgScrubDramRate UINT16 ? ; < Scrub Dram Rate
- CfgScrubL2Rate UINT16 ? ; < Scrub L2Rate
- CfgScrubL3Rate UINT16 ? ; < Scrub L3Rate
- CfgScrubIcRate UINT16 ? ; < Scrub Ic Rate
- CfgScrubDcRate UINT16 ? ; < Scrub Dc Rate
- CfgEccSyncFlood BOOLEAN ? ; < ECC Sync Flood
- CfgEccSymbolSize UINT16 ? ; < ECC Symbol Size
- CfgHeapDramAddress UINT64 ? ; < Heap contents will be temporarily stored in this address during the transition
- CfgNodeMem1GBAlign BOOLEAN ? ; < Node Mem 1GB boundary Alignment
- CfgS3LateRestore BOOLEAN ? ; < S3 Late Restore
- CfgAcpiPstateIndependent BOOLEAN ? ; < PSD method dependent/Independent
- CfgApMtrrSettingsList POINTER ? ; < The AP's MTRR settings before final halt
- CfgUmaMode UMA_MODE ? ; < Uma Mode
- CfgUmaSize UINT32 ? ; < Uma Size [31:0]=Addr[47:16]
- CfgUmaAbove4G BOOLEAN ? ; < Uma Above 4G Support
- CfgUmaAlignment UMA_ALIGNMENT ? ; < Uma alignment
- CfgProcessorScopeInSb BOOLEAN ? ; < ACPI Processor Object in \_SB scope
- CfgProcessorScopeName0 CHAR8 ? ; < OEM specific 1st character of processor scope name.
- CfgProcessorScopeName1 CHAR8 ? ; < OEM specific 2nd character of processor scope name.
- CfgGnbHdAudio UINT8 ? ; < Gnb HD Audio Enable
- CfgAbmSupport UINT8 ? ; < ABM support
- CfgDynamicRefreshRate UINT8 ? ; < Dynamic refresh rate
- CfgLcdBackLightControl UINT8 ? ; < Lcd back light control
- CfgTempPcieMmioBaseAddress UINT32 ? ; < Temp pcie MMIO base address
-
- Reserved BOOLEAN ? ; < reserved...
-BUILD_OPT_CFG ENDS
-
- ; A structure containing platform specific operational characteristics. This
- ; structure is initially populated by the initializer with a copy of the same
- ; structure that was created at build time using the build configuration controls.
-PLATFORM_CONFIGURATION STRUCT
- PlatformProfile PERFORMANCE_PROFILE {} ; < Several configuration settings for the processor.
- PlatformDeemphasisList POINTER ? ; < Deemphasis levels for the platform's HT links.
- CoreLevelingMode UINT8 ? ; < Indicates how to balance the number of cores per processor.
- C1eMode PLATFORM_C1E_MODES ? ; < Specifies the method of C1e enablement - Disabled, HW, or message based.
- C1ePlatformData UINT32 ? ; < If C1eMode is HW, specifies the P_LVL3 I/O port of the platform.
- CStateMode PLATFORM_CSTATE_MODES ? ; < Specifies the method of C-State enablement - Disabled, or C6.
- CStatePlatformData UINT32 ? ; < If CStateMode is C6, specifies a block of 8 free I/O ports to be used for
- ; < placing the CPU in C6.
- UserOptionDmi BOOLEAN ? ; < When set to TRUE, the DMI data table is generated.
- UserOptionPState BOOLEAN ? ; < When set to TRUE, the PState data tables are generated.
- UserOptionSrat BOOLEAN ? ; < When set to TRUE, the SRAT data table is generated.
- UserOptionSlit BOOLEAN ? ; < When set to TRUE, the SLIT data table is generated.
- UserOptionWhea BOOLEAN ? ; < When set to TRUE, the WHEA data table is generated.
- PowerCeiling UINT32 ? ; < P-State Ceiling Enabling Deck - Max power milli-watts.
- ForcePstateIndependent BOOLEAN ? ; < P-State _PSD independence or dependence.
- NumberOfIoApics UINT32 ? ; < Number of I/O APICs in the system
- VrmProperties PLATFORM_VRM_CONFIGURATION {} ; < Several configuration settings for the voltage regulator module.
- ProcessorScopeInSb BOOLEAN ? ; < ACPI Processor Object in \_SB scope
- ProcessorScopeName0 CHAR8 ? ; < OEM specific 1st character of processor scope name.
- ProcessorScopeName1 CHAR8 ? ; < OEM specific 2nd character of processor scope name.
-PLATFORM_CONFIGURATION ENDS
-
- ; P-state structure for each state
-S_PSTATE_VALUES STRUCT
- PStateEnable UINT32 ? ; < Pstate enable
- CoreFreq UINT32 ? ; < MHz
- Power UINT32 ? ; < milliWatts
- IddValue UINT32 ? ; < Current value field
- IddDiv UINT32 ? ; < Current divisor field
-S_PSTATE_VALUES ENDS
-
- ; P-state structure for each core
-S_PSTATE STRUCT
- PStateMaxValue UINT8 ? ; < Max p-state number in this core
- HtcPstateLimit UINT8 ? ; < Htc limit
- HtcCapable UINT8 ? ; < Htc capable
- Reserved UINT8 ? ; < Reserved
- PStateStruct S_PSTATE_VALUES (1) DUP ({}) ; < P state struc
-S_PSTATE ENDS
-
- ; P-state structure for each node
-PSTATE_LEVELING STRUCT
- SetPState0 UINT8 ? ; < If value = 0x55 (Don't set PState0)
- TotalCoresInNode UINT8 ? ; < core number per node
- PStateLevelingSizeOfBytes UINT16 ? ; < Size
- OnlyOneEnabledPState BOOLEAN ? ; < Only P0
- InitStruct UINT8 ? ; < Init struc
- AllCpusHaveIdenticalPStates BOOLEAN ? ; < Have Identical p state
- CreateAcpiTables UINT8 ? ; < Create table flag
- SocketNumber UINT8 ? ; < Physical socket number of this socket
- Reserved UINT8 (3) DUP (?) ; < Reserved.
- PStateCoreStruct S_PSTATE (1) DUP ({}) ; < P state core struc
-PSTATE_LEVELING ENDS
-
- ; P-state structure for whole system
-S_CPU_AMD_PSTATE STRUCT
- TotalSocketInSystem UINT32 ? ; < Total node number in system
- SizeOfBytes UINT32 ? ; < Structure size
- PStateLevelingStruc PSTATE_LEVELING (1) DUP ({}) ; < P state level structure
-S_CPU_AMD_PSTATE ENDS
-
-; *********************************************************************
-; * Structures for: AmdInitLate
-; *********************************************************************
- PROC_VERSION_LENGTH EQU 3h
- MAX_DIMMS_PER_SOCKET EQU 16
-
-
- ; Interface Parameter Structures
- ; DMI Type4 - Processor ID
-TYPE4_PROC_ID STRUCT
- ProcIdLsd UINT32 ? ; < Lower half of 64b ID
- ProcIdMsd UINT32 ? ; < Upper half of 64b ID
-TYPE4_PROC_ID ENDS
-
- ; DMI Type 4 - Processor information
-TYPE4_DMI_INFO STRUCT
- T4ProcType UINT8 ? ; < CPU Type
- T4ProcFamily UINT8 ? ; < Family 1
- T4ProcId TYPE4_PROC_ID {} ; < Id
- T4Voltage UINT8 ? ; < Voltage
- T4ExternalClock UINT16 ? ; < External clock
- T4MaxSpeed UINT16 ? ; < Max speed
- T4CurrentSpeed UINT16 ? ; < Current speed
- T4Status UINT8 ? ; < Status
- T4ProcUpgrade UINT8 ? ; < Up grade
- T4CoreCount UINT8 ? ; < Core count
- T4CoreEnabled UINT8 ? ; < Core Enable
- T4ThreadCount UINT8 ? ; < Thread count
- T4ProcCharacteristics UINT16 ? ; < Characteristics
- T4ProcFamily2 UINT16 ? ; < Family 2
- T4ProcVersion CHAR8 (PROC_VERSION_LENGTH) DUP (?) ; < Cpu version
-TYPE4_DMI_INFO ENDS
-
- ; DMI Type 7 - Cache information
-TYPE7_DMI_INFO STRUCT
- T7CacheCfg UINT16 ? ; < Cache cfg
- T7MaxCacheSize UINT16 ? ; < Max size
- T7InstallSize UINT16 ? ; < Install size
- T7SupportedSramType UINT16 ? ; < Supported Sram Type
- T7CurrentSramType UINT16 ? ; < Current type
- T7CacheSpeed UINT8 ? ; < Speed
- T7ErrorCorrectionType UINT8 ? ; < ECC type
- T7SystemCacheType UINT8 ? ; < Cache type
- T7Associativity UINT8 ? ; < Associativity
-TYPE7_DMI_INFO ENDS
-
- ; DMI Type 16 offset 04h - Location
-
- OtherLocation EQU 01h ; < Assign 01 to Other
- UnknownLocation EQU 2 ; < Assign 02 to Unknown
- SystemboardOrMotherboard EQU 3 ; < Assign 03 to systemboard or motherboard
- IsaAddonCard EQU 4 ; < Assign 04 to ISA add-on card
- EisaAddonCard EQU 5 ; < Assign 05 to EISA add-on card
- PciAddonCard EQU 6 ; < Assign 06 to PCI add-on card
- McaAddonCard EQU 7 ; < Assign 07 to MCA add-on card
- PcmciaAddonCard EQU 8 ; < Assign 08 to PCMCIA add-on card
- ProprietaryAddonCard EQU 9 ; < Assign 09 to proprietary add-on card
- NuBus EQU 10 ; < Assign 0A to NuBus
- Pc98C20AddonCard EQU 11 ; < Assign 0A0 to PC-98/C20 add-on card
- Pc98C24AddonCard EQU 12 ; < Assign 0A1 to PC-98/C24 add-on card
- Pc98EAddoncard EQU 13 ; < Assign 0A2 to PC-98/E add-on card
- Pc98LocalBusAddonCard EQU 14 ; < Assign 0A3 to PC-98/Local bus add-on card
-DMI_T16_LOCATION TEXTEQU <DWORD> ;} DMI_T16_LOCATION;
-
- ; DMI Type 16 offset 05h - Memory Error Correction
-
- OtherUse EQU 01h ; < Assign 01 to Other
- UnknownUse EQU 2 ; < Assign 02 to Unknown
- SystemMemory EQU 3 ; < Assign 03 to system memory
- VideoMemory EQU 4 ; < Assign 04 to video memory
- FlashMemory EQU 5 ; < Assign 05 to flash memory
- NonvolatileRam EQU 6 ; < Assign 06 to non-volatile RAM
- CacheMemory EQU 7 ; < Assign 07 to cache memory
-DMI_T16_USE TEXTEQU <DWORD> ;} DMI_T16_USE;
-
- ; DMI Type 16 offset 07h - Maximum Capacity
-
- Dmi16OtherErrCorrection EQU 01h ; < Assign 01 to Other
- Dmi16UnknownErrCorrection EQU 2 ; < Assign 02 to Unknown
- Dmi16NoneErrCorrection EQU 3 ; < Assign 03 to None
- Dmi16Parity EQU 4 ; < Assign 04 to parity
- Dmi16SingleBitEcc EQU 5 ; < Assign 05 to Single-bit ECC
- Dmi16MultiBitEcc EQU 6 ; < Assign 06 to Multi-bit ECC
- Dmi16Crc EQU 7 ; < Assign 07 to CRC
-DMI_T16_ERROR_CORRECTION TEXTEQU <DWORD> ;} DMI_T16_ERROR_CORRECTION;
-
- ; DMI Type 16 - Physical Memory Array
-TYPE16_DMI_INFO STRUCT
- Location DMI_T16_LOCATION ? ; < The physical location of the Memory Array,
- ; < whether on the system board or an add-in board.
- Use DMI_T16_USE ? ; < Identifies the function for which the array
- ; < is used.
- MemoryErrorCorrection DMI_T16_ERROR_CORRECTION ? ; < The primary hardware error correction or
- ; < detection method supported by this memory array.
- MaximumCapacity UINT32 ? ; < The maximum memory capacity, in kilobytes,
- ; < for the array.
- NumberOfMemoryDevices UINT16 ? ; < The number of slots or sockets available
- ; < for memory devices in this array.
-TYPE16_DMI_INFO ENDS
-
- ; DMI Type 17 offset 0Eh - Form Factor
- OtherFormFactor EQU 01h ; < Assign 01 to Other
- UnknowFormFactor EQU 2 ; < Assign 02 to Unknown
- SimmFormFactor EQU 3 ; < Assign 03 to SIMM
- SipFormFactor EQU 4 ; < Assign 04 to SIP
- ChipFormFactor EQU 5 ; < Assign 05 to Chip
- DipFormFactor EQU 6 ; < Assign 06 to DIP
- ZipFormFactor EQU 7 ; < Assign 07 to ZIP
- ProprietaryCardFormFactor EQU 8 ; < Assign 08 to Proprietary Card
- DimmFormFactorFormFactor EQU 9 ; < Assign 09 to DIMM
- TsopFormFactor EQU 10 ; < Assign 10 to TSOP
- RowOfChipsFormFactor EQU 11 ; < Assign 11 to Row of chips
- RimmFormFactor EQU 12 ; < Assign 12 to RIMM
- SodimmFormFactor EQU 13 ; < Assign 13 to SODIMM
- SrimmFormFactor EQU 14 ; < Assign 14 to SRIMM
- FbDimmFormFactor EQU 15 ; < Assign 15 to FB-DIMM
-DMI_T17_FORM_FACTOR TEXTEQU <DWORD>
-
- ; DMI Type 17 offset 12h - Memory Type
- OtherMemType EQU 01h ; < Assign 01 to Other
- UnknownMemType EQU 2 ; < Assign 02 to Unknown
- DramMemType EQU 3 ; < Assign 03 to DRAM
- EdramMemType EQU 4 ; < Assign 04 to EDRAM
- VramMemType EQU 5 ; < Assign 05 to VRAM
- SramMemType EQU 6 ; < Assign 06 to SRAM
- RamMemType EQU 7 ; < Assign 07 to RAM
- RomMemType EQU 8 ; < Assign 08 to ROM
- FlashMemType EQU 9 ; < Assign 09 to Flash
- EepromMemType EQU 10 ; < Assign 10 to EEPROM
- FepromMemType EQU 11 ; < Assign 11 to FEPROM
- EpromMemType EQU 12 ; < Assign 12 to EPROM
- CdramMemType EQU 13 ; < Assign 13 to CDRAM
- ThreeDramMemType EQU 14 ; < Assign 14 to 3DRAM
- SdramMemType EQU 15 ; < Assign 15 to SDRAM
- SgramMemType EQU 16 ; < Assign 16 to SGRAM
- RdramMemType EQU 17 ; < Assign 17 to RDRAM
- DdrMemType EQU 18 ; < Assign 18 to DDR
- Ddr2MemType EQU 19 ; < Assign 19 to DDR2
- Ddr2FbdimmMemType EQU 20 ; < Assign 20 to DDR2 FB-DIMM
- Ddr3MemType EQU 24 ; < Assign 24 to DDR3
- Fbd2MemType EQU 25 ; < Assign 25 to FBD2
-DMI_T17_MEMORY_TYPE TEXTEQU <DWORD>
-
- ; DMI Type 17 offset 13h - Type Detail
-DMI_T17_TYPE_DETAIL STRUCT
- Reserved1 UINT16 ?
-; OUT UINT16 Reserved1:1; ; < Reserved
-; OUT UINT16 Other:1; ; < Other
-; OUT UINT16 Unknown:1; ; < Unknown
-; OUT UINT16 FastPaged:1; ; < Fast-Paged
-; OUT UINT16 StaticColumn:1; ; < Static column
-; OUT UINT16 PseudoStatic:1; ; < Pseudo-static
-; OUT UINT16 Rambus:1; ; < RAMBUS
-; OUT UINT16 Synchronous:1; ; < Synchronous
-; OUT UINT16 Cmos:1; ; < CMOS
-; OUT UINT16 Edo:1; ; < EDO
-; OUT UINT16 WindowDram:1; ; < Window DRAM
-; OUT UINT16 CacheDram:1; ; < Cache Dram
-; OUT UINT16 NonVolatile:1; ; < Non-volatile
-; OUT UINT16 Reserved2:3; ; < Reserved
-DMI_T17_TYPE_DETAIL ENDS
-
- ; DMI Type 17 - Memory Device
-TYPE17_DMI_INFO STRUCT
- TotalWidth UINT16 ? ; < Total Width, in bits, of this memory device, including any check or error-correction bits.
- DataWidth UINT16 ? ; < Data Width, in bits, of this memory device.
- MemorySize UINT16 ? ; < The size of the memory device.
- FormFactor DMI_T17_FORM_FACTOR ? ; < The implementation form factor for this memory device.
- DeviceSet UINT8 ? ; < Identifies when the Memory Device is one of a set of
- ; < Memory Devices that must be populated with all devices of
- ; < the same type and size, and the set to which this device belongs.
- DeviceLocator CHAR8 (8) DUP (?) ; < The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
- BankLocator CHAR8 (10) DUP (?) ; < The string number of the string that identifies the physically labeled bank where the memory device is located.
- MemoryType DMI_T17_MEMORY_TYPE ? ; < The type of memory used in this device.
- TypeDetail DMI_T17_TYPE_DETAIL {} ; < Additional detail on the memory device type
- Speed UINT16 ? ; < Identifies the speed of the device, in megahertz (MHz).
- ManufacturerIdCode UINT64 ? ; < Manufacturer ID code.
- SerialNumber CHAR8 (9) DUP (?) ; < Serial Number.
- PartNumber CHAR8 (19) DUP (?) ; < Part Number.
- Attributes UINT8 ? ; < Bits 7-4: Reserved, Bits 3-0: rank.
-TYPE17_DMI_INFO ENDS
-
- ; Memory DMI Type 17 and 20 - for memory use
-MEM_DMI_INFO STRUCT
- TotalWidth UINT16 ? ; ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
- DataWidth UINT16 ? ; ///< Data Width, in bits, of this memory device.
- MemorySize UINT16 ? ; ///< The size of the memory device.
- FormFactor DMI_T17_FORM_FACTOR ? ; ///< The implementation form factor for this memory device.
- DeviceLocator UINT8 ? ; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
- BankLocator UINT8 ? ; ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
- Speed UINT16 ? ; ///< Identifies the speed of the device, in megahertz (MHz).
- ManufacturerIdCode UINT64 ? ; ///< Manufacturer ID code.
- SerialNumber UINT8 (4) DUP (?) ; ///< Serial Number.
- PartNumber UINT8 (18) DUP (?) ; ///< Part Number.
- Attributes UINT8 ? ; ///< Bits 7-4: Reserved, Bits 3-0: rank.
- Socket UINT8 ?
-; OUT UINT8 Socket:3 ; ///< Socket ID
-; OUT UINT8 Channel:2 ; ///< Channel ID
-; OUT UINT8 Dimm:2 ; ///< DIMM ID
-; OUT UINT8 DimmPresent:1 ; ///< Dimm Present
- StartingAddr UINT32 ? ; ///< The physical address, in kilobytes, of a range
- ; ///< of memory mapped to the referenced Memory Device.
- EndingAddr UINT32 ? ; ///< The handle, or instance number, associated with
- ; ///< the Memory Device structure to which this address
- ; ///< range is mapped.
-MEM_DMI_INFO ENDS
-
- ; DMI Type 19 - Memory Array Mapped Address
-TYPE19_DMI_INFO STRUCT
- StartingAddr UINT32 ? ; < The physical address, in kilobytes,
- ; < of a range of memory mapped to the
- ; < specified physical memory array.
- EndingAddr UINT32 ? ; < The physical ending address of the
- ; < last kilobyte of a range of addresses
- ; < mapped to the specified physical memory array.
- MemoryArrayHandle UINT16 ? ; < The handle, or instance number, associated
- ; < with the physical memory array to which this
- ; < address range is mapped.
- PartitionWidth UINT8 ? ; < Identifies the number of memory devices that
- ; < form a single row of memory for the address
- ; < partition defined by this structure.
-TYPE19_DMI_INFO ENDS
-
-; DMI Type 20 - Memory Device Mapped Address
-TYPE20_DMI_INFO STRUCT
- StartingAddr UINT32 ? ; < The physical address, in kilobytes, of a range
- ; < of memory mapped to the referenced Memory Device.
- EndingAddr UINT32 ? ; < The handle, or instance number, associated with
- ; < the Memory Device structure to which this address
- ; < range is mapped.
- MemoryDeviceHandle UINT16 ? ; < The handle, or instance number, associated with
- ; < the Memory Device structure to which this address
- ; < range is mapped.
- MemoryArrayMappedAddressHandle UINT16 ? ; < The handle, or instance number, associated
- ; < with the Memory Array Mapped Address structure to
- ; < which this device address range is mapped.
- PartitionRowPosition UINT8 ? ; < Identifies the position of the referenced Memory
- ; < Device in a row of the address partition.
- InterleavePosition UINT8 ? ; < The position of the referenced Memory Device in
- ; < an interleave.
- InterleavedDataDepth UINT8 ? ; < The maximum number of consecutive rows from the
- ; < referenced Memory Device that are accessed in a
- ; < single interleaved transfer.
-TYPE20_DMI_INFO ENDS
-
- ; Collection of pointers to the DMI records
-DMI_INFO STRUCT
- T4 TYPE4_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 4 struc
- T7L1 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 1
- T7L2 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 2
- T7L3 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 3
- T16 TYPE16_DMI_INFO {} ; < Type 16 struc
- T17 TYPE17_DMI_INFO (MAX_SOCKETS_SUPPORTED * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL) DUP ({}) ; < Type 17 struc
- T19 TYPE19_DMI_INFO {} ; < Type 19 struc
- T20 TYPE20_DMI_INFO (MAX_SOCKETS_SUPPORTED * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL) DUP ({}) ; < Type 20 struc
-DMI_INFO ENDS
-
-
-
-; *********************************************************************
-; * Interface call: AllocateExecutionCache
-; *********************************************************************
- MAX_CACHE_REGIONS EQU 3
-
- ; AllocateExecutionCache sub param structure for cached memory region
-EXECUTION_CACHE_REGION STRUCT
- ExeCacheStartAddr UINT32 ? ; < Start address
- ExeCacheSize UINT32 ? ; < Size
-EXECUTION_CACHE_REGION ENDS
-
-; *********************************************************************
-; * Interface call: AmdGetAvailableExeCacheSize
-; *********************************************************************
- ; Get available Cache remain
-AMD_GET_EXE_SIZE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- AvailableExeCacheSize UINT32 ? ; < Remain size
-AMD_GET_EXE_SIZE_PARAMS ENDS
-
-
-
-
-
-
- ; Selection type for core leveling
- CORE_LEVEL_LOWEST EQU 0 ; < Level to lowest common denominator
- CORE_LEVEL_TWO EQU 1 ; < Level to 2 cores
- CORE_LEVEL_POWER_OF_TWO EQU 2 ; < Level to 1,2,4 or 8
- CORE_LEVEL_NONE EQU 3 ; < Do no leveling
- CORE_LEVEL_ONE EQU 4 ; < Level to 1 core
- CORE_LEVEL_THREE EQU 5 ; < Level to 3 cores
- CORE_LEVEL_FOUR EQU 6 ; < Level to 4 cores
- CORE_LEVEL_FIVE EQU 7 ; < Level to 5 cores
- CORE_LEVEL_SIX EQU 8 ; < Level to 6 cores
- CORE_LEVEL_SEVEN EQU 9 ; < Level to 7 cores
- CORE_LEVEL_EIGHT EQU 10 ; < Level to 8 cores
- CORE_LEVEL_NINE EQU 11 ; < Level to 9 cores
- CORE_LEVEL_TEN EQU 12 ; < Level to 10 cores
- CORE_LEVEL_ELEVEN EQU 13 ; < Level to 11 cores
- CORE_LEVEL_TWELVE EQU 14 ; < Level to 12 cores
- CORE_LEVEL_THIRTEEN EQU 15 ; < Level to 13 cores
- CORE_LEVEL_FOURTEEN EQU 16 ; < Level to 14 cores
- CORE_LEVEL_FIFTEEN EQU 17 ; < Level to 15 cores
- CoreLevelModeMax EQU 18 ; < Used for bounds checking
-CORE_LEVELING_TYPE TEXTEQU <DWORD>
-
-
-; ***********************************************************************
-; *
-; * AGESA Basic Level interface structure definition and function prototypes
-; *
-; **********************************************************************
-
-; *********************************************************************
-; * Interface call: AmdCreateStruct
-; *********************************************************************
-
-; *********************************************************************
-; * Interface call: AmdReleaseStruct
-; *********************************************************************
-
-; *********************************************************************
-; * Interface call: AmdInitReset
-; *********************************************************************
- ; AmdInitReset param structure
-AMD_RESET_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < The cached memory region
- HtConfig AMD_HT_RESET_INTERFACE {} ; < The interface for Ht Recovery
-AMD_RESET_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitEarly
-; *********************************************************************
- ; InitEarly param structure
-
- ; Provide defaults or customizations to each service performed in AmdInitEarly.
-
-AMD_EARLY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < The standard header
- CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < Execution Map Interface
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- HtConfig AMD_HT_INTERFACE {} ; < HyperTransport Interface
- GnbConfig GNB_CONFIGURATION {} ; < GNB configuration
-AMD_EARLY_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitPost
-; *********************************************************************
- ; AmdInitPost param structure
-AMD_POST_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- MemConfig MEM_PARAMETER_STRUCT {} ; < Memory post param
-AMD_POST_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitEnv
-; *********************************************************************
- ; AmdInitEnv param structure
-AMD_ENV_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
-AMD_ENV_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitMid
-; *********************************************************************
- ; AmdInitMid param structure
-AMD_MID_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
-AMD_MID_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitLate
-; *********************************************************************
- ; AmdInitLate param structure
-AMD_LATE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- DmiTable POINTER ? ; < DMI Interface
- AcpiPState POINTER ? ; < Acpi Pstate SSDT Table
- AcpiSrat POINTER ? ; < SRAT Table
- AcpiSlit POINTER ? ; < SLIT Table
- AcpiWheaMce POINTER ? ; < WHEA MCE Table
- AcpiWheaCmc POINTER ? ; < WHEA CMC Table
-AMD_LATE_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitRecovery
-; *********************************************************************
- ; CPU Recovery Parameters
-AMD_CPU_RECOVERY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard Header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics
-AMD_CPU_RECOVERY_PARAMS ENDS
-
- ; AmdInitRecovery param structure
-AMD_RECOVERY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- MemConfig MEM_PARAMETER_STRUCT {} ; < Memory post param
- CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < The cached memory region. And the max cache region is 3
- CpuRecoveryParams AMD_CPU_RECOVERY_PARAMS {} ; < Params for CPU related recovery init.
-AMD_RECOVERY_PARAMS ENDS
-
-
-; *********************************************************************
-; * Interface call: AmdInitResume
-; *********************************************************************
- ; AmdInitResume param structure
-AMD_RESUME_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < Platform operational characteristics
- S3DataBlock AMD_S3_PARAMS {} ; < Save state data
-AMD_RESUME_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdS3LateRestore
-; *********************************************************************
- ; AmdS3LateRestore param structure
-AMD_S3LATE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- S3DataBlock AMD_S3_PARAMS {} ; < Save state data
-AMD_S3LATE_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdS3Save
-; *********************************************************************
- ; AmdS3Save param structure
-AMD_S3SAVE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- S3DataBlock AMD_S3_PARAMS {} ; < Standard header
-AMD_S3SAVE_PARAMS ENDS
-
- ; General Services API
-
-
-; *********************************************************************
-; * Interface service call: AmdGetApicId
-; *********************************************************************
- ; Request the APIC ID of a particular core.
-
-AMD_APIC_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- Socket UINT8 ? ; < The Core's Socket.
- Core UINT8 ? ; < The Core id.
- IsPresent BOOLEAN ? ; < The Core is present, and ApicAddress is valid.
- ApicAddress UINT8 ? ; < The Core's APIC ID.
-AMD_APIC_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdGetPciAddress
-; *********************************************************************
- ; Request the PCI Address of a Processor Module (that is, its Northbridge)
-
-AMD_GET_PCI_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- Socket UINT8 ? ; < The Processor's socket
- Module UINT8 ? ; < The Module in that Processor
- IsPresent BOOLEAN ? ; < The Core is present, and PciAddress is valid.
- PciAddress PCI_ADDR {} ; < The Processor's PCI Config Space address (Function 0, Register 0)
-AMD_GET_PCI_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdIdentifyCore
-; *********************************************************************
- ; Request the identity (Socket, Module, Core) of the current Processor Core
-
-AMD_IDENTIFY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- Socket UINT8 ? ; < The current Core's Socket
- Module UINT8 ? ; < The current Core's Processor Module
- Core UINT8 ? ; < The current Core's core id.
-AMD_IDENTIFY_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdReadEventLog
-; *********************************************************************
- ; An Event Log Entry.
-EVENT_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- EventClass UINT32 ? ; < The severity of this event, matches AGESA_STATUS.
- EventInfo UINT32 ? ; < The unique event identifier, zero means "no event".
- DataParam1 UINT32 ? ; < Data specific to the Event.
- DataParam2 UINT32 ? ; < Data specific to the Event.
- DataParam3 UINT32 ? ; < Data specific to the Event.
- DataParam4 UINT32 ? ; < Data specific to the Event.
-EVENT_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdIdentifyDimm
-; *********************************************************************
- ; Request the identity of dimm from system address
-
-AMD_IDENTIFY_DIMM STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- MemoryAddress UINT64 ? ; < System Address that needs to be translated to dimm identification.
- SocketId UINT8 ? ; < The socket on which the targeted address locates.
- MemChannelId UINT8 ? ; < The channel on which the targeted address locates.
- DimmId UINT8 ? ; < The dimm on which the targeted address locates.
-AMD_IDENTIFY_DIMM ENDS
-
- ; Data structure for the Mapping Item between Unified ID for IDS Setup Option
- ; and the option value.
-
-IDS_NV_ITEM STRUCT
- IdsNvId UINT16 ? ; < Unified ID for IDS Setup Option.
- IdsNvValue UINT16 ? ; < The value of IDS Setup Option.
-IDS_NV_ITEM ENDS
-
- ; Data Structure for IDS CallOut Function
-IDS_CALLOUT_STRUCT STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < The Standard Header for AGESA Service
- IdsNvPtr POINTER ? ; < Memory Pointer of IDS NV Table
- Reserved UINT32 ? ; < reserved
-IDS_CALLOUT_STRUCT ENDS
-
-
- ; AGESA IDS NV ID Definitions
- AGESA_IDS_DFT_VAL EQU 0FFFFh; < Default value of every uninitlized NV item, the action for it will be ignored
- AGESA_IDS_NV_END EQU 0FFFFh; < Flag specify end of option structure
-
- AGESA_IDS_EXT_ID_START EQU 0000h; < specify the start of external NV id
-
- AGESA_IDS_NV_UCODE EQU 0001h; < Enable or disable microcode patching
-
- AGESA_IDS_NV_TARGET_PSTATE EQU 0002h; < Set the P-state required to be activated
- AGESA_IDS_NV_POSTPSTATE EQU 0003h; < Set the P-state required to be activated through POST
-
- AGESA_IDS_NV_CHANNEL_INTERLEAVE EQU 0004h; < Enable or disable Channel Interleave
-
- AGESA_IDS_NV_SCRUB_REDIRECTION EQU 0005h; < Enable or disable a write to dram with corrected data
- AGESA_IDS_NV_DRAM_SCRUB EQU 0006h; < Set the rate of background scrubbing for DRAM
- AGESA_IDS_NV_DCACHE_SCRUB EQU 0007h; < Set the rate of background scrubbing for the DCache.
- AGESA_IDS_NV_L2_SCRUB EQU 0008h; < Set the rate of background scrubbing for the L2 cache
- AGESA_IDS_NV_L3_SCRUB EQU 0009h; < Set the rate of background scrubbing for the L3 cache
- AGESA_IDS_NV_SYNC_ON_ECC_ERROR EQU 000Ah; < Enable or disable the sync flood on un-correctable ECC error
- AGESA_IDS_NV_ECC_SYMBOL_SIZE EQU 000Bh; < Set ECC symbol size
-
- AGESA_IDS_NV_ALL_MEMCLKS EQU 000Ch; < Enable or disable all memory clocks enable
- AGESA_IDS_NV_DCT_GANGING_MODE EQU 000Dh; < Set the Ganged mode
- AGESA_IDS_NV_DRAM_BURST_LENGTH32 EQU 000Eh; < Set the DRAM Burst Length 32
- AGESA_IDS_NV_MEMORY_POWER_DOWN EQU 000Fh; < Enable or disable Memory power down mode
- AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE EQU 0010h; < Set the Memory power down mode
- AGESA_IDS_NV_DLL_SHUT_DOWN EQU 0011h; < Enable or disable DLLShutdown
-
- AGESA_IDS_NV_PROBEFILTER EQU 0012h; < Enable or Disable ProbeFilter
-
- AGESA_IDS_NV_HDTOUT EQU 0013h; < Enable or disable HDTOUT feature
-
- AGESA_IDS_NV_HTLINKSOCKET EQU 0014h; < HT Link Socket
- AGESA_IDS_NV_HTLINKPORT EQU 0015h; < HT Link Port
- AGESA_IDS_NV_HTLINKFREQ EQU 0016h; < HT Link Frequency
- AGESA_IDS_NV_HTLINKWIDTHIN EQU 0017h; < HT Link In Width
- AGESA_IDS_NV_HTLINKWIDTHOUT EQU 0018h; < HT Link Out Width
-
- AGESA_IDS_NV_GNBHDAUDIOEN EQU 0019h; < Enable or disable GNB HD Audio
- AGESA_IDS_EXT_ID_END EQU 001Ah; < specify the end of external NV ID
-
- IDS_EX_NV_ID TEXTEQU <DWORD>
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/amd.inc b/src/vendorcode/amd/agesa/f10/Legacy/amd.inc
deleted file mode 100644
index d84e44d868..0000000000
--- a/src/vendorcode/amd/agesa/f10/Legacy/amd.inc
+++ /dev/null
@@ -1,461 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * Agesa structures and definitions
-; *
-; * Contains AMD AGESA core interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
-;
-; ****************************************************************************
-; *
-; * Copyright (c) 2011, Advanced Micro Devices, Inc.
-; * All rights reserved.
-; *
-; * Redistribution and use in source and binary forms, with or without
-; * modification, are permitted provided that the following conditions are met:
-; * * Redistributions of source code must retain the above copyright
-; * notice, this list of conditions and the following disclaimer.
-; * * Redistributions in binary form must reproduce the above copyright
-; * notice, this list of conditions and the following disclaimer in the
-; * documentation and/or other materials provided with the distribution.
-; * * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; * its contributors may be used to endorse or promote products derived
-; * from this software without specific prior written permission.
-; *
-; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; *
-; *
-; **************************************************************************
-
-
-UINT64 TEXTEQU <QWORD>
-UINT32 TEXTEQU <DWORD>
-UINT16 TEXTEQU <WORD>
-UINT8 TEXTEQU <BYTE>
-CHAR8 TEXTEQU <BYTE>
-BOOLEAN TEXTEQU <BYTE>
-POINTER TEXTEQU <DWORD>
-
- ; AGESA Types and Definitions
-
- AGESA_REVISION EQU "Arch2008"
- AGESA_ID EQU "AGESA"
-
- LAST_ENTRY EQU 0FFFFFFFFh
- IMAGE_SIGNATURE EQU 'DMA$'
- IOCF8 EQU 0CF8h
- IOCFC EQU 0CFCh
-
- ; The return status for all AGESA public services.
-
- ; Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
- ; will have log entries with more detail.
-
- AGESA_SUCCESS EQU 0 ; < The service completed normally. Info may be logged.
- AGESA_UNSUPPORTED EQU 1 ; < The dispatcher or create struct had an unimplemented function requested.
- ; < Not logged.
- AGESA_BOUNDS_CHK EQU 2 ; < A dynamic parameter was out of range and the service was not provided.
- ; < Example, memory address not installed, heap buffer handle not found.
- ; < Not Logged.
- ; AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
- AGESA_ALERT EQU 3 ; < An observed condition, but no loss of function.
- ; < See log. Example, HT CRC.
- AGESA_WARNING EQU 4 ; < Possible or minor loss of function. See Log.
- AGESA_ERROR EQU 5 ; < Significant loss of function, boot may be possible. See Log.
- AGESA_CRITICAL EQU 6 ; < Continue boot only to notify user. See Log.
- AGESA_FATAL EQU 7 ; < Halt booting. See Log.
- AgesaStatusMax EQU 8 ; < Not a status, use for limit checking.
-AGESA_STATUS TEXTEQU <DWORD>
-
-; For checking whether a status is at or above the mandatory log level.
-AGESA_STATUS_LOG_LEVEL EQU AGESA_ALERT
-
- CALLOUT_ENTRY TEXTEQU <POINTER>
- IMAGE_ENTRY TEXTEQU <POINTER>
- MODULE_ENTRY TEXTEQU <POINTER>
-
-; This allocation type is used by the AmdCreateStruct entry point
- PreMemHeap EQU 0 ; < Create heap in cache.
- PostMemDram EQU 1 ; < Create heap in memory.
- ByHost EQU 2 ; < Create heap by Host.
-ALLOCATION_METHOD TEXTEQU <DWORD>
-
- ; These width descriptors are used by the library function, and others, to specify the data size
- AccessWidth8 EQU 1 ; < Access width is 8 bits.
- AccessWidth16 EQU 2 ; < Access width is 16 bits.
- AccessWidth32 EQU 3 ; < Access width is 32 bits.
- AccessWidth64 EQU 4 ; < Access width is 64 bits.
-
- AccessS3SaveWidth8 EQU 81h ; < Save 8 bits data.
- AccessS3SaveWidth16 EQU 130 ; < Save 16 bits data.
- AccessS3SaveWidth32 EQU 131 ; < Save 32 bits data.
- AccessS3SaveWidth64 EQU 132 ; < Save 64 bits data.
-ACCESS_WIDTH TEXTEQU <DWORD>
-
- ; AGESA struct name
-
- ; AGESA BASIC FUNCTIONS
- AMD_INIT_RECOVERY EQU 00020000h
- AMD_CREATE_STRUCT EQU 00020001h
- AMD_INIT_EARLY EQU 00020002h
- AMD_INIT_ENV EQU 00020003h
- AMD_INIT_LATE EQU 00020004h
- AMD_INIT_MID EQU 00020005h
- AMD_INIT_POST EQU 00020006h
- AMD_INIT_RESET EQU 00020007h
- AMD_INIT_RESUME EQU 00020008h
- AMD_RELEASE_STRUCT EQU 00020009h
- AMD_S3LATE_RESTORE EQU 0002000Ah
- AMD_S3_SAVE EQU 0002000Bh
- AMD_GET_APIC_ID EQU 0002000Ch
- AMD_GET_PCI_ADDRESS EQU 0002000Dh
- AMD_IDENTIFY_CORE EQU 0002000Eh
- AMD_READ_EVENT_LOG EQU 0002000Fh
- AMD_LATE_RUN_AP_TASK EQU 00020010h
- AMD_IDENTIFY_DIMMS EQU 00020011h
-AGESA_STRUCT_NAME TEXTEQU <DWORD>
-
-
- ; ResetType constant values
- WARM_RESET_WHENEVER EQU 1
- COLD_RESET_WHENEVER EQU 2
- WARM_RESET_IMMEDIATELY EQU 3
- COLD_RESET_IMMEDIATELY EQU 4
-
-
- ; AGESA Structures
-
- ; The standard header for all AGESA services.
-AMD_CONFIG_PARAMS STRUCT
- ImageBasePtr UINT32 ? ; < The AGESA Image base address.
- Func UINT32 ? ; < The service desired, @sa dispatch.h.
- AltImageBasePtr UINT32 ? ; < Alternate Image location
- CalloutPtr CALLOUT_ENTRY ? ; < For Callout from AGESA
- HeapStatus UINT8 ? ; < For heap status from boot time slide.
- HeapBasePtr UINT64 ? ; < Location of the heap
- Reserved UINT8 (7) DUP (?) ; < This space is reserved for future use.
-AMD_CONFIG_PARAMS ENDS
-
-
- ; Create Struct Interface.
-AMD_INTERFACE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Config header
- AgesaFunctionName AGESA_STRUCT_NAME ? ; < The service to init, @sa dispatch.h
- AllocationMethod ALLOCATION_METHOD ? ; < How to handle buffer allocation
- NewStructSize UINT32 ? ; < The size of the allocated data, in for ByHost, else out only.
- NewStructPtr POINTER ? ; < The struct for the service.
- ; < The struct to init for ByHost allocation,
- ; < the initialized struct on return.
-AMD_INTERFACE_PARAMS ENDS
-
- FUNC_0 EQU 0 ; bit-placed for PCI address creation
- FUNC_1 EQU 1
- FUNC_2 EQU 2
- FUNC_3 EQU 3
- FUNC_4 EQU 4
- FUNC_5 EQU 5
- FUNC_6 EQU 6
- FUNC_7 EQU 7
-
- ; AGESA Binary module header structure
-AMD_IMAGE_HEADER STRUCT
- Signature UINT32 ? ; < Binary Signature
- CreatorID CHAR8 (8) DUP (?) ; < 8 characters ID
- Version CHAR8 (12) DUP (?) ; < 12 characters version
- ModuleInfoOffset UINT32 ? ; < Offset of module
- EntryPointAddress UINT32 ? ; < Entry address
- ImageBase UINT32 ? ; < Image base
- RelocTableOffset UINT32 ? ; < Relocate Table offset
- ImageSize UINT32 ? ; < Size
- Checksum UINT16 ? ; < Checksum
- ImageType UINT8 ? ; < Type
- V_Reserved UINT8 ? ; < Reserved
-AMD_IMAGE_HEADER ENDS
- ; AGESA Binary module header structure
-AMD_MODULE_HEADER STRUCT
- ModuleHeaderSignature UINT32 ? ; < Module signature
- ModuleIdentifier CHAR8 (8) DUP (?) ; < 8 characters ID
- ModuleVersion CHAR8 (12) DUP (?) ; < 12 characters version
- ModuleDispatcher POINTER ? ; < A pointer point to dispatcher
- NextBlock POINTER ? ; < Next module header link
-AMD_MODULE_HEADER ENDS
-
-; AMD_CODE_HEADER Signatures.
-AGESA_CODE_SIGNATURE TEXTEQU <'!', '!', 'A', 'G', 'E', 'S', 'A', ' '>
-CIMXNB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'>
-CIMXSB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'>
-
-; AGESA_CODE_SIGNATURE
-AMD_CODE_HEADER STRUCT
- Signature CHAR8 (8) DUP (?) ; < code header Signature
- ComponentName CHAR8 (8) DUP (?) ; < 8 character name of the code module
- Version CHAR8 (12) DUP (?) ; < 12 character version string
- TerminatorNull CHAR8 ? ; < null terminated string
- VerReserved CHAR8 (7) DUP (?) ; < reserved space
-AMD_CODE_HEADER ENDS
-
- ; Extended PCI address format
-EXT_PCI_ADDR STRUCT
- Register UINT32 ?
-; IN OUT UINT32 Register:12; ; < Register offset
-; IN OUT UINT32 Function:3; ; < Function number
-; IN OUT UINT32 Device:5; ; < Device number
-; IN OUT UINT32 Bus:8; ; < Bus number
-; IN OUT UINT32 Segment:4; ; < Segment
-EXT_PCI_ADDR ENDS
-
- ; Union type for PCI address
-PCI_ADDR UNION
- AddressValue UINT32 ? ; < Formal address
- Address EXT_PCI_ADDR {} ; < Extended address
-PCI_ADDR ENDS
-
- ; SBDFO - Segment Bus Device Function Offset
- ; 31:28 Segment (4-bits)
- ; 27:20 Bus (8-bits)
- ; 19:15 Device (5-bits)
- ; 14:12 Function(3-bits)
- ; 11:00 Offset (12-bits)
-
-
-
- ILLEGAL_SBDFO EQU 0FFFFFFFFh
-
- ; CPUID data received registers format
-CPUID_DATA STRUCT
- EAX_Reg UINT32 ? ; < CPUID instruction result in EAX
- EBX_Reg UINT32 ? ; < CPUID instruction result in EBX
- ECX_Reg UINT32 ? ; < CPUID instruction result in ECX
- EDX_Reg UINT32 ? ; < CPUID instruction result in EDX
-CPUID_DATA ENDS
-
- ; HT frequency for external callbacks
-;typedef enum {
- HT_FREQUENCY_200M EQU 0 ; < HT speed 200 for external callbacks
- HT_FREQUENCY_400M EQU 2 ; < HT speed 400 for external callbacks
- HT_FREQUENCY_600M EQU 4 ; < HT speed 600 for external callbacks
- HT_FREQUENCY_800M EQU 5 ; < HT speed 800 for external callbacks
- HT_FREQUENCY_1000M EQU 6 ; < HT speed 1000 for external callbacks
- HT_FREQUENCY_1200M EQU 7 ; < HT speed 1200 for external callbacks
- HT_FREQUENCY_1400M EQU 8 ; < HT speed 1400 for external callbacks
- HT_FREQUENCY_1600M EQU 9 ; < HT speed 1600 for external callbacks
- HT_FREQUENCY_1800M EQU 10 ; < HT speed 1800 for external callbacks
- HT_FREQUENCY_2000M EQU 11 ; < HT speed 2000 for external callbacks
- HT_FREQUENCY_2200M EQU 12 ; < HT speed 2200 for external callbacks
- HT_FREQUENCY_2400M EQU 13 ; < HT speed 2400 for external callbacks
- HT_FREQUENCY_2600M EQU 14 ; < HT speed 2600 for external callbacks
- HT_FREQUENCY_2800M EQU 17 ; < HT speed 2800 for external callbacks
- HT_FREQUENCY_3000M EQU 18 ; < HT speed 3000 for external callbacks
- HT_FREQUENCY_3200M EQU 19 ; < HT speed 3200 for external callbacks
- HT_FREQUENCY_MAX EQU 20 ; < Limit Check.
-HT_FREQUENCIES TEXTEQU <DWORD> ;} HT_FREQUENCIES;
-
-HT3_FREQUENCY_MIN EQU HT_FREQUENCY_1200M
-
-IFNDEF BIT0
- BIT0 EQU 0000000000000001h
-ENDIF
-IFNDEF BIT1
- BIT1 EQU 0000000000000002h
-ENDIF
-IFNDEF BIT2
- BIT2 EQU 0000000000000004h
-ENDIF
-IFNDEF BIT3
- BIT3 EQU 0000000000000008h
-ENDIF
-IFNDEF BIT4
- BIT4 EQU 0000000000000010h
-ENDIF
-IFNDEF BIT5
- BIT5 EQU 0000000000000020h
-ENDIF
-IFNDEF BIT6
- BIT6 EQU 0000000000000040h
-ENDIF
-IFNDEF BIT7
- BIT7 EQU 0000000000000080h
-ENDIF
-IFNDEF BIT8
- BIT8 EQU 0000000000000100h
-ENDIF
-IFNDEF BIT9
- BIT9 EQU 0000000000000200h
-ENDIF
-IFNDEF BIT10
- BIT10 EQU 0000000000000400h
-ENDIF
-IFNDEF BIT11
- BIT11 EQU 0000000000000800h
-ENDIF
-IFNDEF BIT12
- BIT12 EQU 0000000000001000h
-ENDIF
-IFNDEF BIT13
- BIT13 EQU 0000000000002000h
-ENDIF
-IFNDEF BIT14
- BIT14 EQU 0000000000004000h
-ENDIF
-IFNDEF BIT15
- BIT15 EQU 0000000000008000h
-ENDIF
-IFNDEF BIT16
- BIT16 EQU 0000000000010000h
-ENDIF
-IFNDEF BIT17
- BIT17 EQU 0000000000020000h
-ENDIF
-IFNDEF BIT18
- BIT18 EQU 0000000000040000h
-ENDIF
-IFNDEF BIT19
- BIT19 EQU 0000000000080000h
-ENDIF
-IFNDEF BIT20
- BIT20 EQU 0000000000100000h
-ENDIF
-IFNDEF BIT21
- BIT21 EQU 0000000000200000h
-ENDIF
-IFNDEF BIT22
- BIT22 EQU 0000000000400000h
-ENDIF
-IFNDEF BIT23
- BIT23 EQU 0000000000800000h
-ENDIF
-IFNDEF BIT24
- BIT24 EQU 0000000001000000h
-ENDIF
-IFNDEF BIT25
- BIT25 EQU 0000000002000000h
-ENDIF
-IFNDEF BIT26
- BIT26 EQU 0000000004000000h
-ENDIF
-IFNDEF BIT27
- BIT27 EQU 0000000008000000h
-ENDIF
-IFNDEF BIT28
- BIT28 EQU 0000000010000000h
-ENDIF
-IFNDEF BIT29
- BIT29 EQU 0000000020000000h
-ENDIF
-IFNDEF BIT30
- BIT30 EQU 0000000040000000h
-ENDIF
-IFNDEF BIT31
- BIT31 EQU 0000000080000000h
-ENDIF
-IFNDEF BIT32
- BIT32 EQU 0000000100000000h
-ENDIF
-IFNDEF BIT33
- BIT33 EQU 0000000200000000h
-ENDIF
-IFNDEF BIT34
- BIT34 EQU 0000000400000000h
-ENDIF
-IFNDEF BIT35
- BIT35 EQU 0000000800000000h
-ENDIF
-IFNDEF BIT36
- BIT36 EQU 0000001000000000h
-ENDIF
-IFNDEF BIT37
- BIT37 EQU 0000002000000000h
-ENDIF
-IFNDEF BIT38
- BIT38 EQU 0000004000000000h
-ENDIF
-IFNDEF BIT39
- BIT39 EQU 0000008000000000h
-ENDIF
-IFNDEF BIT40
- BIT40 EQU 0000010000000000h
-ENDIF
-IFNDEF BIT41
- BIT41 EQU 0000020000000000h
-ENDIF
-IFNDEF BIT42
- BIT42 EQU 0000040000000000h
-ENDIF
-IFNDEF BIT43
- BIT43 EQU 0000080000000000h
-ENDIF
-IFNDEF BIT44
- BIT44 EQU 0000100000000000h
-ENDIF
-IFNDEF BIT45
- BIT45 EQU 0000200000000000h
-ENDIF
-IFNDEF BIT46
- BIT46 EQU 0000400000000000h
-ENDIF
-IFNDEF BIT47
- BIT47 EQU 0000800000000000h
-ENDIF
-IFNDEF BIT48
- BIT48 EQU 0001000000000000h
-ENDIF
-IFNDEF BIT49
- BIT49 EQU 0002000000000000h
-ENDIF
-IFNDEF BIT50
- BIT50 EQU 0004000000000000h
-ENDIF
-IFNDEF BIT51
- BIT51 EQU 0008000000000000h
-ENDIF
-IFNDEF BIT52
- BIT52 EQU 0010000000000000h
-ENDIF
-IFNDEF BIT53
- BIT53 EQU 0020000000000000h
-ENDIF
-IFNDEF BIT54
- BIT54 EQU 0040000000000000h
-ENDIF
-IFNDEF BIT55
- BIT55 EQU 0080000000000000h
-ENDIF
-IFNDEF BIT56
- BIT56 EQU 0100000000000000h
-ENDIF
-IFNDEF BIT57
- BIT57 EQU 0200000000000000h
-ENDIF
-IFNDEF BIT58
- BIT58 EQU 0400000000000000h
-ENDIF
-IFNDEF BIT59
- BIT59 EQU 0800000000000000h
-ENDIF
-IFNDEF BIT60
- BIT60 EQU 1000000000000000h
-ENDIF
-IFNDEF BIT61
- BIT61 EQU 2000000000000000h
-ENDIF
-IFNDEF BIT62
- BIT62 EQU 4000000000000000h
-ENDIF
-IFNDEF BIT63
- BIT63 EQU 8000000000000000h
-ENDIF
-
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/bridge32.inc b/src/vendorcode/amd/agesa/f10/Legacy/bridge32.inc
deleted file mode 100644
index 5a26195316..0000000000
--- a/src/vendorcode/amd/agesa/f10/Legacy/bridge32.inc
+++ /dev/null
@@ -1,577 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * Agesa structures and definitions
-; *
-; * Contains AMD AGESA core interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
-;
-; ****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-PARAM1 textequ <[bp+8]>
-PARAM2 textequ <[bp+12]>
-PARAM3 textequ <[bp+16]>
-RETAddress textequ <[bp+4]>
-
-AMD_PRIVATE_PARAMS STRUCT
- Gate16_CS DW ? ; Segment of AMD_BRIDGE_32 and AMD_CALLOUT_16
- Gate16_SS DW ? ; RM stack segment
- Router_Seg DW ? ; Segment of oem router
- Router_Off DW ? ; Offset of oem router
-AMD_PRIVATE_PARAMS ENDS
-
-; OEM may pre-define the GDT and selector offsets. If they do not, use our defaults.
-IFNDEF AGESA_SELECTOR_GDT
- AGESA_SELECTOR_GDT EQU 00h
-ENDIF
-IFNDEF AGESA_SELECTOR_CODE16
- AGESA_SELECTOR_CODE16 EQU 08h
-ENDIF
-IFNDEF AGESA_SELECTOR_DATA16
- AGESA_SELECTOR_DATA16 EQU 10h
-ENDIF
-IFNDEF AGESA_SELECTOR_CODE32
- AGESA_SELECTOR_CODE32 EQU 18h
-ENDIF
-IFNDEF AGESA_SELECTOR_DATA32
- AGESA_SELECTOR_DATA32 EQU 20h
-ENDIF
-
-
-AMD_BRIDGE_32_GDT MACRO GDT_Name:REQ
-
- GDT_Name LABEL BYTE
- DD 000000000h, 000000000h ; NULL descriptor
- DD 00000ffffh, 000009b00h ; 16-bit code, fixed up
- DD 00000ffffh, 000009300h ; 16-bit data, fixed up
- DD 00000ffffh, 000CF9B00h ; 32-bit protected mode code
- DD 00000ffffh, 000CF9300h ; 32-bit protected mode data
- GDT_Length EQU ($-GDT_Name)
-
-ENDM
-
-;+-------------------------------------------------------------------------
-;
-; AMD_BRIDGE_32 - Execute Agesa through Pushhigh interface
-;
-; Processing:
-; The following steps are taken:
-; 1) Enter 32bit Protected Mode (PM32)
-; 2) Run AGESA code
-; 3) Restore Real Mode (RM)
-;
-; Entry:
-; [big real mode] : ds, es set to base 0 limit 4G segment
-; EDX - if not 0, provides a FAR PTR to oem router (Seg | Offset)
-; ESI - configuration block pointer
-;
-; Exit:
-; EAX - return value
-; ESI - configuration block pointer
-; ds, es, fs, gs - Set to 4GB segment limit for Big Real Mode
-;
-; Modified:
-; None
-;
-
-AMD_BRIDGE_32 MACRO GDT_Name
-
- local copyGDT
- local flushTo16PM
- local agesaReturnAddress
- local leave32bitPM
- local flush2RM
-
- push gs
- push fs
- push ebx
- push ecx
- push edi
- mov eax, esp
- push eax
- movzx esp, sp
-;
-; Do not use any locals here, BP will be changed frequently during RM->PM32->RM
-;
- pushf
- cli ; Disable interrupts during AGESA
- cld ; Need known direction flag during AGESA
-
-;
-; Save the FAR PTR input parameter
-;
- mov gs, dx ; Offset
- shr edx, 16
- mov fs, dx ; Segment
-;
-; Determine where our binary file is and get entry point
-;
- mov edx, (AMD_CONFIG_PARAMS PTR [esi]).ImageBasePtr
- add edx, (AMD_IMAGE_HEADER PTR [edx]).EntryPointAddress
-;
-; Figure out the return address we will use after calling AGESA
-; and store it in ebx until we have our stack set up properly
-;
- mov ebx, cs
- shl ebx, 4
- add ebx, OFFSET agesaReturnAddress
-;
-; Save our current RM stack AND entry EBP
-;
- push ebp
-; push esp
- push ss
-
-;
-; BEGIN --- STACK MUST BE BALANCED AT THIS POINT --- BEGIN
-;
-; Copy the GDT onto the stack for modification
-;
- mov cx, GDT_Length
- sub sp, cx
- mov bp, sp
- lea di, GDT_Name
-copyGDT:
- mov al, cs:[di]
- mov [bp], al
- inc di
- inc bp
- loop copyGDT
-;
-; Patch 16-bit code and data descriptors on stack. We will
-; fix up CS and SS for PM16 during the callout if applicable.
-;
- mov bp, sp
-
- mov eax, cs
- shl eax, 4
- mov [bp+AGESA_SELECTOR_CODE16+2], ax
- shr eax, 16
- mov [bp+AGESA_SELECTOR_CODE16+4], al
-
- mov eax, ss
- shl eax, 4
- mov [bp+AGESA_SELECTOR_DATA16+2], ax
- shr eax, 16
- mov [bp+AGESA_SELECTOR_DATA16+4], al
-;
-; Need to place Length and Address on GDT
-;
- mov eax, ss
- shl eax, 4
- add eax, esp
- push eax
- push WORD PTR (GDT_Length-1)
-;
-; Load the GDT
-;
- mov bp, sp
- lgdt FWORD PTR [bp]
-;
-; TABLE 1
-;
-; Place PRIVATE DATA on stack DIRECTLY following GDT
-; During this routine, stack data is critical. If
-; order is changed or additional added, bad things
-; will happen!
-;
-; HIGHEST PHYSICAL ADDRESS
-;
-; | ... |
-; ------------------------
-; | old RM SP |
-; | old RM SS |
-; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS + (SIZEOF GDT_LENGTH + 6 {size, address})
-; | GDT_DATA32 |
-; | ... |
-; | GDT_NULL |
-; | GDT Addr, Length |
-; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS
-; | Priv.Gate16_SS |
-; | Priv.Gate16_CS |
-; ------------------------ sp
-; ------ THEN PUSH -------
-; | Return to 16-bit CS |
-; | Return to 16-bit Off |
-; | ... |
-;
-; LOWEST PHYSICAL ADDRESS
-;
- mov edi, esp
- sub edi, SIZEOF AMD_PRIVATE_PARAMS
- mov ax, cs
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS, ax
- mov ax, ss
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS, ax
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off, gs
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg, fs
-
- mov esp, edi
-;
-; Save an address for returning to 16 bit real mode on stack,
-; we'll use it in a far ret after turning off CR0.PE so that
-; we can take our address off and force a far jump. Be sure
-; no unexpected data is on the stack after this!
-;
- mov ax, cs
- push cs
- lea ax, flush2RM
- push ax
-;
-; Convert ss:esp to "flat"
-;
-
- mov ax, sp
- push ax
- mov eax, ss
- shl eax, 4
- add eax, esp
- mov esp, eax ; Load the zero based ESP
-
-;
-; Set CR0.PE
-;
- mov eax, CR0 ; Get CPU control word 0
- or al, 01 ; Enable CPU protected mode
- mov CR0, eax ; Write back to CPU control word 0
- jmp flushTo16PM
-
-flushTo16PM:
-;
-; 16-bit protected mode
-;
- mov ax, AGESA_SELECTOR_DATA32
- mov ds, ax
- mov es, ax
- mov fs, ax
- mov gs, ax
- mov ss, ax
-;
-; Push our parameters RIGHT TO LEFT, and then return address
-;
- push esi ; AGESA configuration block pointer (data)
- push ebx ; after AGESA return offset (32PM flat) - consumed by dispatcher ret
- pushd AGESA_SELECTOR_CODE32 ; AGESA entry selector (32PM flat)
- push edx ; AGESA entry point (32PM flat)
-
- DB 066h
- retf ; <><><> Enter AGESA 32-bit code!!! <><><>
-
-agesaReturnAddress:
-;
-; Returns from the Agesa 32-bit code still PM32
-;
- DB 0EAh
- DD OFFSET leave32bitPM
- DW AGESA_SELECTOR_CODE16
-
-leave32bitPM:
-;
-; Now in 16-bit PM
-;
- add esp, 4 ; +4 to remove our config block pointer
-;
-; Eax reserve AGESA_STATUS return code, save it
-;
- mov ebx, eax
-;
-; Turn off CR0.PE, restore 64K stack limit
-;
- pop ax
- mov sp, ax
- mov ax, AGESA_SELECTOR_DATA16
- mov ss, ax
-
- mov eax, CR0
- and al, NOT 1 ; Disable protected mode
- mov CR0, eax ; Write back CR0.PE
-;
-; Jump far to enter RM, we saved this address on the stack
-; already. Hopefully stack is balanced through AGESA
-; nor were any params added by pushing them on the stack and
-; not removing them between BEGIN-END comments.
-;
- retf
-
-flush2RM:
-;
-; Set segments registers for big real mode before returning
-;
- xor ax, ax
- mov ds, ax
- mov es, ax
- mov fs, ax
- mov gs, ax
-;
-; Discard GDT, +6 for GDT pointer/size, privates
-;
- add esp, GDT_Length + 6 + SIZEOF AMD_PRIVATE_PARAMS
-;
-; Restore real mode stack and entry EBP
-;
- pop cx
-; mov esp, [esp]
- mov ss, cx
- pop ebp
-;
-; Restore AGESA_STATUS return code to eax
-;
- mov eax, ebx
-;
-; END --- STACK MUST BE BALANCED TO THIS POINT --- END
-;
-
- popf
- pop ebx
- mov esp, ebx
- pop edi
- pop ecx
- pop ebx
- pop fs
- pop gs
- ; EXIT AMD_BRIDGE_32
-ENDM
-;+-------------------------------------------------------------------------
-;
-; AMD_CALLOUT_16 - Execute Callback from Pushhigh interface
-;
-; Processing:
-; The following steps are taken:
-; 1) Enter PM16
-; 2) Setup stack, get private params
-; 3) Enter RM
-; 4) Get 3 params
-; 5) Call oemCallout OR oem router
-; 6) Enter PM32
-; 7) Return to Agesa PH
-;
-; Entry:
-; [32-bit protected mode]
-; [esp+8] Func
-; [esp+12] Data
-; [esp+16] Configuration Block
-; [esp+4] return address to Agesa
-;
-; Exit:
-; [32-bit protected mode]
-;
-; Modified:
-; None
-;
-AMD_CALLOUT_16 MACRO LocalOemCalloutRouter
-;
-; Note that we are still PM32, so MASM may work strangely
-;
-
- push bp ; Save our original SP to access params
- mov bp, sp
- push bx
- push si
- push di
- push cx
- push dx
- push di
-
- DB 066h, 0EAh
- DW OFFSET PM16Entry
- DW AGESA_SELECTOR_CODE16
-
-PM16Entry:
-;
-; PM16 CS, but still PM32 SS, as we need to access our private params
-; before we enter RM.
-;
-; Note: we are working below the stack temporarily, and and it will
-; not affect our ability to get entry params
-;
- xor ecx, ecx
- xor edx, edx
-;
-; SGDT will give us the original location of the GDT on our CAS stack.
-; We need this value because our private parameters are located just
-; below the GDT.
-;
- mov edi, esp
- sub edi, GDT_Length + 6
- sgdt FWORD PTR [edi] ; [edi] = word size, dword address
- mov edi, DWORD PTR [edi+2] ; Get the PM32 address only
- sub edi, SIZEOF AMD_PRIVATE_PARAMS + 6
-;
-; cx = code segment of this code in RM
-; dx = stack segment of CAS in RM
-; fs = code segment of oem router (save for later)
-; gs = offset of oem router (save for later)
-; fs and gs are loaded after switch to real mode because we can't
-; use them as scratch pad registers in protected mode
-;
- mov cx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS
- mov dx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS
-
- mov eax, edi ; Save edi in eax for after RM switch
- mov edi, esp ; Save our current ESP for RM
-
- movzx ebx, dx
- shl ebx, 4
- sub esp, ebx
-
-;
-; We had been accessing the stack in PM32, we will now change to PM16 so we
-; will make the stack segment 64KB limit so SP needs to be fixed made PM16
-; compatible.
-;
- mov bx, AGESA_SELECTOR_DATA16
- mov ss, bx
-
-;
-; Save the RM segment and RM offset of the jump we will need to make in
-; order to enter RM so that code in this segment is relocatable.
-;
-; BEGIN --- Don't unbalance the stack --- BEGIN
-;
- push cx
- pushw OFFSET RMEntry
-
- mov ebx, CR0
- and bl, NOT 1
- mov CR0, ebx ; CR0.PE cleared
-;
-; Far jump to clear segment descriptor cache and enter RM
-;
- retf
-
-RMEntry:
-;
-; We are in RM, setup RM stack
-;
- movzx ebx, dx ; Get RM SS in ebx
- shl ebx, 4 ; Get our stack top on entry in EBP to
- sub ebp, ebx ; access our entry parameters
- sub eax, ebx ; save copy of parameters address
- mov ss, dx ; Set stack segment
-;
-; We are going to figure out the address to use when we return
-; and have to go back into PM32 while we have access to it
-;
- movzx ebx, cx ; Get original CS in ebx
- shl ebx, 4
- add ebx, OFFSET PM32Entry
-;
-; Now we put our data, func, block params into calling convention
-; for our hook
-;
-; ECX = Func
-; EDX = Data
-; ESI = config pointer
-;
- mov ecx, PARAM1 ; Func
- mov edx, PARAM2 ; Data
- mov esi, PARAM3 ; pointer
-
- push ebx ; Save PM32 mode switch address
- push edi ; Save PM32 stack pointer
- pushf
-;
-; Get Router Function Address
-;
- mov edi, eax
- mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg
- mov fs, ax
- mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off
- mov gs, ax
-
- mov eax, AGESA_UNSUPPORTED ; Default return value
-;
-; If AMD_BRIDGE_32 EDX == 0 call oemCallout
-; otherwise call FAR PTR EDX
-;
-; Critical:
-; sp+2 - EDI aka PM32 stack address
-; sp+4 - address of PM32Entry in PM32
-;
- mov bx, fs
- shl ebx, 16
- mov bx, gs
-
- .if (ebx == 0)
- call LocalOemCalloutRouter
- .else
-;
-; Make far call to Router function
-;
- push cs
- push offset CalloutReturn
- push ebx
- retf
-CalloutReturn:
- .endif
-;
-; Restore PM32 esp from RM stack
-;
- popf
- pop edi ; Our PM32 stack pointer
- pop edx ; Our PM32 mode switch address
-
- mov ebx, CR0
- or bl, 1 ; CR0.PE set
- mov CR0, ebx
-
- mov ebx, AGESA_SELECTOR_DATA32
- pushd AGESA_SELECTOR_CODE32 ; PM32 selector
- push edx ; PM32 entry point
-
- DB 066h
- retf ; Far jump to enter PM32
-
-PM32Entry:
-;
-; END --- Don't unbalance the stack --- END
-; We are now PM32, so remember MASM is assembling in 16-bit again
-;
- mov ss, bx
- mov ds, bx
- mov es, bx
- mov fs, bx
- mov gs, bx
-
- mov sp, di
- pop di
- pop dx
- pop cx
- pop di
- pop si
- pop bx
- pop bp
- ; EXIT AMD_CALLOUT_16
-ENDM
diff --git a/src/vendorcode/amd/agesa/f10/Lib/IA32/amdlib32.asm b/src/vendorcode/amd/agesa/f10/Lib/IA32/amdlib32.asm
deleted file mode 100644
index a35ecdf0af..0000000000
--- a/src/vendorcode/amd/agesa/f10/Lib/IA32/amdlib32.asm
+++ /dev/null
@@ -1,624 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa library 32bit
-; *
-; * Contains AMD AGESA Library
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Lib
-; * @e \$Revision: 17071 $ @e \$Date: 2009-07-30 10:13:11 -0700 (Thu, 30 Jul 2009) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-.586p
-.model flat
-ASSUME FS:NOTHING
-.code
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write IO byte
-; *
-; * @param[in] Address IO port address
-; * @param[in] Data IO port Value
-; */
-
-public WriteIo8
-WriteIo8 PROC NEAR C USES DX AX Address:WORD, Data:Byte
- mov dx, Address
- mov al, Data
- out dx, al
- ret
-WriteIo8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write IO word
-; *
-; * @param[in] Address IO port address
-; * @param[in] Data IO port Value
-; */
-public WriteIo16
-WriteIo16 PROC NEAR C USES DX AX Address:WORD, Data:WORD
- mov dx, Address
- mov ax, Data
- out dx, ax
- ret
-WriteIo16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write IO dword
-; *
-; * @param[in] Address IO port address
-; * @param[in] Data IO port Value
-; */
-
-public WriteIo32
-WriteIo32 PROC NEAR C USES DX EAX Address:WORD, Data:DWORD
- mov dx, Address
- mov eax, Data
- out dx, eax
- ret
-WriteIo32 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read IO byte
-; *
-; * @param[in] - IO port address
-; * @retval IO port Value
-; */
-public ReadIo8
-ReadIo8 PROC NEAR C USES DX Address:WORD
- mov dx, Address
- in al, dx
- ret
-ReadIo8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read IO word
-; *
-; * @param[in] Address IO port address
-; * @retval IO port Value
-; */
-public ReadIo16
-ReadIo16 PROC NEAR C USES DX Address:WORD
- mov dx, Address
- in ax, dx
- ret
-ReadIo16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read IO dword
-; *
-; * @param[in] Address IO port address
-; * @retval IO port Value
-; */
-public ReadIo32
-ReadIo32 PROC NEAR C USES DX Address:WORD
- mov dx, Address
- in eax, dx
- ret
-ReadIo32 ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read MSR
-; *
-; * @param[in] Address MSR Address
-; * @param[in] Data Pointer to data
-; * @param[in] ConfigPtr (Optional)
-; */
-public LibAmdMsrRead
-LibAmdMsrRead PROC NEAR C USES ECX ESI EDX Address:DWORD, Value:PTR, ConfigPtr:PTR
- mov esi, ConfigPtr ;Dummy read to avoid compilation warning
- mov ecx, Address
- rdmsr
- mov esi, Value
- mov [esi], eax
- mov [esi+4], edx
- ret
-LibAmdMsrRead ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write MSR
-; *
-; * @param[in] Address MSR Address
-; * @param[in] Data Pointer to data
-; * @param[in] ConfigPtr (Optional)
-; */
-public LibAmdMsrWrite
-LibAmdMsrWrite PROC NEAR C USES ECX ESI EDX Address:DWORD, Data:PTR, ConfigPtr:PTR
- mov esi, ConfigPtr ;Dummy read to avoid compilation warning
- mov ecx, Address
- mov esi, Data
- mov eax, [esi]
- mov edx, [esi+4]
- wrmsr
- ret
-LibAmdMsrWrite ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read CPUID
-; *
-; * @param[in] Func CPUID function
-; * @param[in] DATA Pointer to CPUID_DATA to save cpuid data
-; * @param[in] ConfigPtr (Optional)
-; */
-public LibAmdCpuidRead
-LibAmdCpuidRead PROC NEAR C Func:DWORD, DATA:PTR, ConfigPtr:PTR
- pushad
- mov esi, ConfigPtr ;Dummy read to avoid compilation warning
- mov eax, Func
- cpuid
- mov esi, DATA
- mov [esi], eax
- mov [esi+4], ebx
- mov [esi+8], ecx
- mov [esi+12],edx
- popad
- ret
-LibAmdCpuidRead ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read TSC
-; *
-; *
-; *
-; */
-
-public ReadTSC
-ReadTSC PROC NEAR C
- rdtsc
- ret
-ReadTSC ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Set FS_BASE
-; *
-; *
-; *
-; * @param[in] esi - Low Dword of physical address
-; * @param[in] edi - High Dword of physical address
-; */
-SetFsBase PROC NEAR PUBLIC USES EAX EBX ECX EDX EDI
-
- mov eax, ecx
- mov ecx, 0C0010015h ; HWCR
- rdmsr
- mov ebx, eax
- bts eax, 17 ; HWCR.Wrap32Dis
- wrmsr
- xchg edx, edi
- mov eax, esi
- mov esi, ebx
-
- mov ecx, 0C0000100h ; FS_BASE
- wrmsr
- ret
-
-SetFsBase ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Restore MSR0C001_0015
-; *
-; * @param[in] esi - Low Dword
-; * @param[in] edi - High Dword
-; */
-RestoreHwcr PROC NEAR PUBLIC USES EAX ECX EDX
-
- mov ecx, 0C0010015h
- mov eax, esi
- mov edx, edi
- wrmsr
- ret
-
-RestoreHwcr ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read memory/MMIO byte
-; *
-; * @param[in] Address - Memory Address
-; * @retval Memory byte at given address
-; */
-Read64Mem8 PROC NEAR C PUBLIC USES EBX EDI ESI FS Address:QWORD
-
- mov esi, DWORD PTR Address[0]
- mov edi, DWORD PTR Address[4]
- test edi, edi
- jz AccesBelow4G
- call SetFsBase
- xor ebx, ebx
- mov al, fs:[ebx]
- call RestoreHwcr
- jmp Done
-AccesBelow4G:
- mov al, ds:[esi]
-Done:
- ret
-
-Read64Mem8 ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read memory/MMIO word
-; *
-; * @param[in] Address - Memory Address
-; * @retval Memory word at given address
-; */
-Read64Mem16 PROC NEAR C PUBLIC USES EBX EDI ESI FS Address:QWORD
-
- mov esi, DWORD PTR Address[0]
- mov edi, DWORD PTR Address[4]
- test edi, edi
- jz AccesBelow4G
-
- call SetFsBase
- xor ebx, ebx
- mov ax, fs:[ebx]
- call RestoreHwcr
- jmp Done
-AccesBelow4G:
- mov ax, ds:[esi]
-Done:
-
- ret
-
-Read64Mem16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read memory/MMIO dword
-; *
-; * @param[in] Address - Memory Address
-; * @retval Memory dword at given address
-; */
-Read64Mem32 PROC NEAR C PUBLIC USES EBX EDI ESI FS Address:QWORD
-
- mov esi, DWORD PTR Address[0]
- mov edi, DWORD PTR Address[4]
- test edi, edi
- jz AccesBelow4G
-
- call SetFsBase
- xor ebx, ebx
- mov eax, fs:[ebx]
- call RestoreHwcr
- jmp Done
-AccesBelow4G:
- mov eax, ds:[esi]
-Done:
- ret
-
-Read64Mem32 ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write memory/MMIO byte
-; *
-; * @param[in] Address - Memory Address
-; * @param[in] Value - Value to write
-; */
-
-Write64Mem8 PROC NEAR C PUBLIC USES EBX EDI ESI FS Address:QWORD, Data:BYTE
-
- mov esi, DWORD PTR Address[0]
- mov edi, DWORD PTR Address[4]
- test edi, edi
- jz AccesBelow4G
-
- call SetFsBase
- xor ebx, ebx
- mov al, Data
- mov fs:[ebx], al
- call RestoreHwcr
- jmp Done
-AccesBelow4G:
- mov al, Data
- mov ds:[esi], al
-Done:
-
- ret
-
-Write64Mem8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write memory/MMIO word
-; *
-; * @param[in] Address - Memory Address
-; * @param[in] Value - Value to write
-; */
-Write64Mem16 PROC NEAR C PUBLIC USES EBX EDI ESI FS Address:QWORD, Data:WORD
-
- mov esi, DWORD PTR Address[0]
- mov edi, DWORD PTR Address[4]
- test edi, edi
- jz AccesBelow4G
-
- call SetFsBase
- xor ebx, ebx
- mov ax, Data
- mov fs:[ebx], ax
- call RestoreHwcr
- jmp Done
-AccesBelow4G:
- mov ax, Data
- mov ds:[esi], ax
-Done:
- ret
-
-Write64Mem16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write memory/MMIO dword
-; *
-; * @param[in] Address - Memory Address
-; * @param[in] Value - Value to write
-; */
-Write64Mem32 PROC NEAR C PUBLIC USES EBX EDI ESI FS Address:QWORD, Data:DWORD
-
- mov esi, DWORD PTR Address[0]
- mov edi, DWORD PTR Address[4]
- test edi, edi
- jz AccesBelow4G
-
- call SetFsBase
- xor ebx, ebx
- mov eax, Data
- mov fs:[ebx], eax
- call RestoreHwcr
- jmp Done
-AccesBelow4G:
- mov eax, Data
- mov ds:[esi], eax
-
-Done:
-
- ret
-
-Write64Mem32 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read various CPU registers
-; *
-; * @param[in] Reg Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
-; * @param[in] Value Value to write
-; */
-
-LibAmdReadCpuReg PROC NEAR C Reg:BYTE, Value:NEAR PTR DWORD
- pushad
- push ds
-
- .if(Reg == 00h)
- mov eax, cr0
- .elseif(Reg == 04h)
- mov eax, cr4
- .elseif(Reg == 10h)
- mov eax, dr0
- .elseif(Reg == 11h)
- mov eax, dr1
- .elseif(Reg == 12h)
- mov eax, dr2
- .elseif(Reg == 13h)
- mov eax, dr3
- .elseif(Reg == 17h)
- mov eax, dr7
- .else
- xor eax,eax
- .endif
-
- mov edi, Value
- mov [edi], eax
-
- pop ds
- popad
- ret
-LibAmdReadCpuReg ENDP
-
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write various CPU registers
-; *
-; * @param[in] Reg Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
-; * @param[in] Value Value to write
-; */
-
-LibAmdWriteCpuReg PROC NEAR C Reg:BYTE, Value:DWORD
- mov eax, Value
-
- .if(Reg == 00h)
- mov cr0, eax
- .elseif(Reg == 4)
- mov cr4, eax
- .elseif(Reg == 10h)
- mov dr0, eax
- .elseif(Reg == 11h)
- mov dr1, eax
- .elseif(Reg == 12h)
- mov dr2, eax
- .elseif(Reg == 13h)
- mov dr3, eax
- .elseif(Reg == 17h)
- mov dr7, eax
- .endif
- ret
-LibAmdWriteCpuReg ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write back invalidate caches using wbinvd.
-; *
-; *
-; *
-; */
-
-PUBLIC LibAmdWriteBackInvalidateCache
-LibAmdWriteBackInvalidateCache PROC NEAR C
- wbinvd
- ret
-LibAmdWriteBackInvalidateCache ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Stop CPU
-; *
-; *
-; *
-; */
-
-PUBLIC StopHere
-StopHere PROC NEAR C
-@@:
- jmp short @b
-StopHere ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Enter debugger on SimNow
-; *
-; *
-; *
-; */
-PUBLIC LibAmdSimNowEnterDebugger
-LibAmdSimNowEnterDebugger PROC NEAR C
- pushad
- mov eax, 0BACCD00Bh ; Backdoor in SimNow
- mov ebx, 2 ; Select breakpoint feature
- cpuid
-@@:
- jmp short @b
- popad
- ret
-LibAmdSimNowEnterDebugger ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * IDS IO port write
-; *
-; * @param[in] Address IO Port Address
-; * @param[in] Value Value to write
-; * @param[in] Flag IDS flags
-; *
-; */
-
-PUBLIC IdsOutPort
-IdsOutPort PROC NEAR C Address:DWORD, Value:DWORD ,Flag:DWORD
- push edx
- push eax
- push ebx
- mov edx, Address
- mov eax, Value
- mov ebx, Flag
- out dx, eax
- pop ebx
- pop eax
- pop edx
- ret
-IdsOutPort ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Force breakpoint on HDT
-; *
-; *
-; */
-PUBLIC LibAmdHDTBreakPoint
-LibAmdHDTBreakPoint PROC NEAR C
-
- pushad
-
- mov ecx, 0C001100Ah ;bit 0 = HDT redirect
- mov edi, 09C5A203Ah ;Password
- RDMSR ;
- or al, 1 ;
- WRMSR ;
- mov al, 0B2h ;Marker = B2
- db 0F1h ;ICEBP
-
- popad
- ret
-
-LibAmdHDTBreakPoint ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Find the most right hand side non-zero bit with .
-; *
-; * @param[in] Value Value
-; */
-PUBLIC LibAmdBitScanForward
-LibAmdBitScanForward PROC NEAR C Value:DWORD
- mov eax, Value
- bsf eax, Value
- .if (Zero?)
- mov al,32
- .endif
- ret
-LibAmdBitScanForward ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Find the most left hand side non-zero bit.
-; *
-; * @param[in] Value Value
-; */
-PUBLIC LibAmdBitScanReverse
-LibAmdBitScanReverse PROC NEAR C Value:DWORD
- mov eax, Value
- bsr eax, Value
- .if (Zero?)
- mov al,0FFh
- .endif
- ret
-LibAmdBitScanReverse ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f10/Lib/IA32/ms_shift.asm b/src/vendorcode/amd/agesa/f10/Lib/IA32/ms_shift.asm
deleted file mode 100644
index 7fe47c0382..0000000000
--- a/src/vendorcode/amd/agesa/f10/Lib/IA32/ms_shift.asm
+++ /dev/null
@@ -1,110 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa library 32bit
-; *
-; * Contains AMD AGESA Library
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Lib
-; * @e \$Revision: 9201 $ @e \$Date: 2008-10-31 03:36:20 -0500 (Fri, 31 Oct 2008) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-.586p
-.model flat
-ASSUME FS:NOTHING
-.code
-;/*++
-;
-;Routine Description:
-;
-; Shifts a UINT64 to the right.
-;
-;Arguments:
-;
-; EDX:EAX - UINT64 value to be shifted
-; CL - Shift count
-;
-;Returns:
-;
-; EDX:EAX - shifted value
-;
-;--*/
-_aullshr PROC NEAR C PUBLIC
- .if (cl < 64)
- .if (cl >= 32)
- sub cl, 32
- mov eax, edx
- xor edx, edx
- .endif
- shrd eax, edx, cl
- shr edx, cl
- .else
- xor eax, eax
- xor edx, edx
- .endif
- ret
-_aullshr ENDP
-
-;/*++
-;
-;Routine Description:
-;
-; Shifts a UINT64 to the left.
-;
-;Arguments:
-;
-; EDX:EAX - UINT64 value to be shifted
-; CL - Shift count
-;
-;Returns:
-;
-; EDX:EAX - shifted value
-;
-;--*/
-_allshl PROC NEAR C PUBLIC USES CX
- .if (cl < 64)
- .if (cl >= 32)
- sub cl, 32
- mov edx, eax
- xor eax, eax
- .endif
- shld edx, eax, cl
- shl eax, cl
- .else
- xor eax, eax
- xor edx, edx
- .endif
- ret
-_allshl ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f10/Lib/IA32/msmemcpy.asm b/src/vendorcode/amd/agesa/f10/Lib/IA32/msmemcpy.asm
deleted file mode 100644
index bd8bc61100..0000000000
--- a/src/vendorcode/amd/agesa/f10/Lib/IA32/msmemcpy.asm
+++ /dev/null
@@ -1,84 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa library 32bit
-; *
-; * Contains AMD AGESA Library
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Lib
-; * @e \$Revision: 9201 $ @e \$Date: 2008-10-31 03:36:20 -0500 (Fri, 31 Oct 2008) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-.586p
-.model flat
-ASSUME FS:NOTHING
-.code
-; void *memcpy( void *dest, void *src, size_t count );
-;
-; Copy count bytes from src to dest, returning dest.
-; ("c" is not legal as an assembly parameter name, replaced with value.)
-; Assume ES is set appropriately, 32 bit flat.
-;
-public memcpy
-memcpy PROC NEAR C PUBLIC USES ECX EDI ESI dest:DWORD, src:DWORD, count:DWORD
- pushf
- cld ; We will increment through *dest
- mov edi, dest
- mov esi, src
- mov ecx, count
- rep movsb
- mov eax, dest
- popf
- ret
-memcpy ENDP
-
-; void *memset( void *dest, int c, size_t count );
-;
-; At dest, set count bytes to byte value, returning dest.
-; ("c" is not legal as an assembly parameter name, replaced with value.)
-; Assume ES is set appropriately, 32 bit flat.
-;
-public memset
-memset PROC NEAR C PUBLIC USES ECX EDI dest:DWORD, value:DWORD, count:DWORD
- pushf
- cld ; We will increment through *dest
- mov edi, dest
- mov eax, value
- mov ecx, count
- rep stosb
- mov eax, edi
- popf
- ret
-memset ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f10/Lib/x64/amdlib64.asm b/src/vendorcode/amd/agesa/f10/Lib/x64/amdlib64.asm
deleted file mode 100644
index 7ed3d1005a..0000000000
--- a/src/vendorcode/amd/agesa/f10/Lib/x64/amdlib64.asm
+++ /dev/null
@@ -1,569 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa library 64bit
-; *
-; * Contains AMD AGESA Library
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Lib
-; * @e \$Revision: 17071 $ @e \$Date: 2009-07-30 10:13:11 -0700 (Thu, 30 Jul 2009) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-.code
-;/*++
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write IO byte
-; *
-; * @param[in] CX IO port address
-; * @param[in] DL IO port Value
-; */
-
-PUBLIC WriteIo8
-WriteIo8 PROC
- mov al, dl
- mov dx, cx
- out dx, al
- ret
-WriteIo8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write IO word
-; *
-; * @param[in] CX IO port address
-; * @param[in] DX IO port Value
-; */
-PUBLIC WriteIo16
-WriteIo16 PROC
- mov ax, dx
- mov dx, cx
- out dx, ax
- ret
-WriteIo16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write IO dword
-; *
-; * @param[in] CX IO port address
-; * @param[in] EDX IO port Value
-; */
-
-PUBLIC WriteIo32
-WriteIo32 PROC
- mov eax, edx
- mov dx, cx
- out dx, eax
- ret
-WriteIo32 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read IO byte
-; *
-; * @param[in] CX IO port address
-; * @retval AL IO port Value
-; */
-PUBLIC ReadIo8
-ReadIo8 PROC
- mov dx, cx
- in al, dx
- ret
-ReadIo8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read IO word
-; *
-; * @param[in] CX IO port address
-; * @retval AX IO port Value
-; */
-PUBLIC ReadIo16
-ReadIo16 PROC
- mov dx, cx
- in ax, dx
- ret
-ReadIo16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read IO dword
-; *
-; * @param[in] CX IO port address
-; * @retval EAX IO port Value
-; */
-PUBLIC ReadIo32
-ReadIo32 PROC
- mov dx, cx
- in eax, dx
- ret
-ReadIo32 ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read MSR
-; *
-; * @param[in] RCX MSR Address
-; * @param[in] RDX Pointer to data
-; * @param[in] R8D ConfigPtr (Optional)
-; */
-PUBLIC LibAmdMsrRead
-LibAmdMsrRead PROC
- push rsi
- mov rsi, rdx
- rdmsr
- mov [rsi], eax
- mov [rsi+4], edx
- pop rsi
- ret
-LibAmdMsrRead ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write MSR
-; *
-; * @param[in] RCX MSR Address
-; * @param[in] RDX Pointer to data
-; * @param[in] R8D ConfigPtr (Optional)
-; */
-PUBLIC LibAmdMsrWrite
-LibAmdMsrWrite PROC
- push rsi
- mov rsi, rdx
- mov eax, [rsi]
- and rax, 0ffffffffh
- mov edx, [rsi+4]
- and rdx, 0ffffffffh
- wrmsr
- pop rsi
- ret
-LibAmdMsrWrite ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read CPUID
-; *
-; * @param[in] RCX CPUID function
-; * @param[in] RDX Pointer to CPUID_DATA to save cpuid data
-; * @param[in] R8D ConfigPtr (Optional)
-; */
-PUBLIC LibAmdCpuidRead
-LibAmdCpuidRead PROC
-
- push rbx
- push rsi
- mov rsi, rdx
- mov rax, rcx
- cpuid
- mov [rsi], eax
- mov [rsi+4], ebx
- mov [rsi+8], ecx
- mov [rsi+12],edx
- pop rsi
- pop rbx
- ret
-
-LibAmdCpuidRead ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read TSC
-; *
-; *
-; * @retval RAX Time stamp counter value
-; */
-
-PUBLIC ReadTSC
-ReadTSC PROC
- rdtsc
- and rax, 0ffffffffh
- shl rdx, 32
- or rax, rdx
- ret
-ReadTSC ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read memory/MMIO byte
-; *
-; * @param[in] RCX - Memory Address
-; * @retval Memory byte at given address
-; */
-PUBLIC Read64Mem8
-Read64Mem8 PROC
-
- xor rax, rax
- mov al, [rcx]
- ret
-
-Read64Mem8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read memory/MMIO word
-; *
-; * @param[in] RCX - Memory Address
-; * @retval Memory word at given address
-; */
-PUBLIC Read64Mem16
-Read64Mem16 PROC
-
- xor rax, rax
- mov ax, [rcx]
- ret
-
-Read64Mem16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read memory/MMIO dword
-; *
-; * @param[in] RCX - Memory Address
-; * @retval Memory dword at given address
-; */
-PUBLIC Read64Mem32
-Read64Mem32 PROC
-
- xor rax, rax
- mov eax, [rcx]
- ret
-
-Read64Mem32 ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write memory/MMIO byte
-; *
-; * @param[in] RCX Memory Address
-; * @param[in] DL Value to write
-; */
-
-PUBLIC Write64Mem8
-Write64Mem8 PROC
-
- xor rax, rax
- mov rax, rdx
- mov [rcx], al
- ret
-
-Write64Mem8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write memory/MMIO word
-; *
-; * @param[in] RCX Memory Address
-; * @param[in] DX Value to write
-; */
-PUBLIC Write64Mem16
-Write64Mem16 PROC
-
- xor rax, rax
- mov rax, rdx
- mov [rcx], ax
- ret
-
-Write64Mem16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write memory/MMIO dword
-; *
-; * @param[in] RCX Memory Address
-; * @param[in] EDX Value to write
-; */
-PUBLIC Write64Mem32
-Write64Mem32 PROC
-
- xor rax, rax
- mov rax, rdx
- mov [rcx], eax
- ret
-
-Write64Mem32 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read various CPU registers
-; *
-; * @param[in] CL Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
-; * @param[in] RDX Pointer to value
-; */
-
-PUBLIC LibAmdReadCpuReg
-LibAmdReadCpuReg PROC
-
- push rax
- xor rax, rax
-Reg00h:
- cmp cl, 00h
- jne Reg04h
- mov rax, cr0
- jmp RegRead
-Reg04h:
- cmp cl, 04h
- jne Reg10h
- mov rax, cr4
- jmp RegRead
-Reg10h:
- cmp cl, 10h
- jne Reg11h
- mov rax, dr0
- jmp RegRead
-Reg11h:
- cmp cl, 11h
- jne Reg12h
- mov rax, dr1
- jmp RegRead
-Reg12h:
- cmp cl, 12h
- jne Reg13h
- mov rax, dr2
- jmp RegRead
-Reg13h:
- cmp cl, 13h
- jne Reg17h
- mov rax, dr3
- jmp RegRead
-Reg17h:
- cmp cl, 17h
- jne RegRead
- mov rax, dr7
-RegRead:
- mov [rdx], eax
- pop rax
- ret
-LibAmdReadCpuReg ENDP
-
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write various CPU registers
-; *
-; * @param[in] CL Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
-; * @param[in] RDX Value to write
-; */
-
-PUBLIC LibAmdWriteCpuReg
-LibAmdWriteCpuReg PROC
-
- push rax
-Reg00h:
- cmp cl, 00h
- jne Reg04h
- mov rax, cr0
- mov eax, edx
- mov cr0, rax
- jmp Done
-Reg04h:
- cmp cl, 04h
- jne Reg10h
- mov rax, cr4
- mov eax, edx
- mov cr4, rax
- jmp Done
-Reg10h:
- cmp cl, 10h
- jne Reg11h
- mov rax, dr0
- mov eax, edx
- mov dr0, rax
- jmp Done
-Reg11h:
- cmp cl, 11h
- jne Reg12h
- mov rax, dr1
- mov eax, edx
- mov dr1, rax
- jmp Done
-Reg12h:
- cmp cl, 12h
- jne Reg13h
- mov rax, dr2
- mov eax, edx
- mov dr2, rax
- jmp Done
-Reg13h:
- cmp cl, 13h
- jne Reg17h
- mov rax, dr3
- mov eax, edx
- mov dr3, rax
- jmp Done
-Reg17h:
- cmp cl, 17h
- jne Done
- mov rax, dr7
- mov eax, edx
- mov dr7, rax
-Done:
- pop rax
- ret
-LibAmdWriteCpuReg ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write back invalidate caches using wbinvd.
-; *
-; *
-; *
-; */
-
-PUBLIC LibAmdWriteBackInvalidateCache
-LibAmdWriteBackInvalidateCache PROC
- wbinvd
- ret
-LibAmdWriteBackInvalidateCache ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Stop CPU
-; *
-; *
-; *
-; */
-
-PUBLIC StopHere
-StopHere PROC
-@@:
- jmp short @b
-StopHere ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Enter debugger on SimNow
-; *
-; *
-; *
-; */
-PUBLIC LibAmdSimNowEnterDebugger
-LibAmdSimNowEnterDebugger PROC
- pushfq
- mov rax, 0BACCD00Bh ; Backdoor in SimNow
- mov rbx, 2 ; Select breakpoint feature
- cpuid
-@@:
- jmp short @b
- popfq
- ret
-LibAmdSimNowEnterDebugger ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * IDS IO port write
-; *
-; * @param[in] ECX IO Port Address
-; * @param[in] EDX Value to write
-; * @param[in] R8D IDS flags
-; *
-; */
-
-PUBLIC IdsOutPort
-IdsOutPort PROC
- push rbx
- push rax
-
- mov ebx, r8d
- mov eax, edx
- mov edx, ecx
- out dx, eax
-
- pop rax
- pop rbx
- ret
-IdsOutPort ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Force breakpoint on HDT
-; *
-; *
-; */
-PUBLIC LibAmdHDTBreakPoint
-LibAmdHDTBreakPoint PROC
-
- push rbx
-
- mov rcx, 0C001100Ah ;bit 0 = HDT redirect
- mov rdi, 09C5A203Ah ;Password
- rdmsr
- and rax, 0ffffffffh
- or rax, 1
-
- wrmsr
-
- mov rax, 0B2h ;Marker = B2
- db 0F1h ;ICEBP
-
- pop rbx
- ret
-
-LibAmdHDTBreakPoint ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Find the most right hand side non-zero bit with
-; *
-; * @param[in] ECX Value
-; */
-PUBLIC LibAmdBitScanForward
-LibAmdBitScanForward PROC
- bsf eax, ecx
- jnz nonZeroSource
- mov al,32
-nonZeroSource:
- ret
-LibAmdBitScanForward ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Find the most left hand side non-zero bit.
-; *
-; * @param[in] ECX Value
-; */
-PUBLIC LibAmdBitScanReverse
-LibAmdBitScanReverse PROC
- bsr eax, ecx
- jnz nonZeroSource
- mov al,0FFh
-nonZeroSource:
- ret
-LibAmdBitScanReverse ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD32.asm b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD32.asm
deleted file mode 100644
index ddd937ab66..0000000000
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD32.asm
+++ /dev/null
@@ -1,113 +0,0 @@
-;/**
-; * @file
-; *
-; * AGESA Family 10h Revision D support routines.
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: CPU/F10
-; * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- .XLIST
- .LIST
-
- .586P
-
-;===============================================
-;===============================================
-;==
-;== M E M O R Y P R E S E N T S E G M E N T
-;==
-;===============================================
-;===============================================
- .MODEL flat
- .CODE
-
-;======================================================================
-; F10RevDProbeFilterCritical: Performs critical sequence for probe
-; filter initialization.
-;
-; In:
-; PciAddress Full PCI address of the node to init
-; PciRegister Current value of F3x1D4
-;
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-F10RevDProbeFilterCritical PROC NEAR C PUBLIC USES EAX ECX EDX, PciAddress:DWORD, PciRegister:DWORD
-
- mov ecx, 0C001001Fh
- rdmsr
- push eax
- push ecx
- push edx
- or dh, 40h
- wrmsr
-
- mov eax, 810003D4h
-
- mov ecx, PciRegister
- mov edx, PciAddress
- shr edx, 4
- and dh, 0F8h
- or ah, dh
-
- or cl, 2
- db 0Fh, 0AEh, 0F0h ; MFENCE
-
- mov dx, 0CF8h ; Set Reg Config Space
- db 0Fh, 0AEh, 0F0h ; MFENCE
-
- out dx, eax
- db 0Fh, 0AEh, 0F0h ; MFENCE
-
- mov dl, 0FCh ; Set DX to Pci Config Data
- mov eax, ecx ;Set config Reg data
- db 0Fh, 0AEh, 0F0h ; MFENCE
-
- out dx, eax ; move data to return position
- db 0Fh, 0AEh, 0F0h ; MFENCE
-
- pop edx
- pop ecx
- pop eax
- wrmsr
- ret
-
-F10RevDProbeFilterCritical ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD64.asm b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD64.asm
deleted file mode 100644
index 2804d29153..0000000000
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD64.asm
+++ /dev/null
@@ -1,127 +0,0 @@
-;/**
-; * @file
-; *
-; * AGESA Family 10h Revision D support routines.
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: CPU/F10
-; * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- .XLIST
- .LIST
-
-;===============================================
-;===============================================
-;==
-;== M E M O R Y P R E S E N T S E G M E N T
-;==
-;===============================================
-;===============================================
- .CODE
-
-;======================================================================
-; F10RevDProbeFilterCritical: Performs critical sequence for probe
-; filter initialization.
-;
-; In:
-; PciAddress Full PCI address of the node to init
-; PciRegister Current value of F3x1D4
-;
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-PUBLIC F10RevDProbeFilterCritical
-F10RevDProbeFilterCritical PROC
-
- push rax
- push rcx
- push rdx
- push rsi
- push rdi
-
- mov esi, ecx
- mov edi, edx
-
- mov ecx, 0C001001Fh
- rdmsr
- push rax
- push rcx
- push rdx
- or dh, 40h
- wrmsr
-
- mov eax, 810003D4h
-
- mov ecx, edi
- mov edx, esi
-
- shr edx, 4
- and dh, 0F8h
- or ah, dh
-
- or cl, 2
- mfence
-
- mov dx, 0CF8h ; Set Reg Config Space
- mfence
-
- out dx, eax
- mfence
-
- mov dl, 0FCh ; Set DX to Pci Config Data
- mov eax, ecx ;Set config Reg data
- mfence
-
- out dx, eax ; move data to return position
- mfence
-
- pop rdx
- pop rcx
- pop rax
- wrmsr
-
- pop rdi
- pop rsi
- pop rdx
- pop rcx
- pop rax
- ret
-
-F10RevDProbeFilterCritical ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm
deleted file mode 100644
index e92c94517f..0000000000
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm
+++ /dev/null
@@ -1,319 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa pre-memory miscellaneous support, including ap halt loop.
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: CPU
-; * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- .XLIST
- INCLUDE agesa.inc
- INCLUDE cpcarmac.inc
- .LIST
-
- .586P
-
-;===============================================
-;===============================================
-;==
-;== M E M O R Y A B S E N T S E G M E N T
-;==
-;===============================================
-;===============================================
- .MODEL flat
- .CODE
-;======================================================================
-; ExecuteFinalHltInstruction: Disables the stack and performs
-; a hlt instruction on an AP.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; eax, ebx, ecx, edx, esp
-;
-;======================================================================
-ExecuteFinalHltInstruction PROC NEAR C PUBLIC
-
- pop esi ; StdHeader
- pop esi ; pointer to ApMtrrSettingsList, set through build configuration
-
- mov eax, CR0 ; Make sure cache is disabled for all APs
- or eax, CR0_CD OR CR0_NW ; Disable cache
- mov cr0, eax ; Write back to CR0
-
- ; Configure the MTRRs on the AP so
- ; when it runs remote code it will execute
- ; out of RAM instead of ROM.
-
- ; Disable MTRRs and turn on modification enable bit
- mov ecx, MTRR_SYS_CFG
- _RDMSR
- btr eax, MtrrVarDramEn ; Disable
- bts eax, MtrrFixDramModEn ; Enable
- btr eax, MtrrFixDramEn ; Disable
- bts eax, SysUcLockEn
- _WRMSR
-
- ; Setup default values for Fixed-Sized MTRRs
- ; Set 7FFFh-00000h as WB
- mov ecx, AMD_AP_MTRR_FIX64k_00000
- mov eax, 1E1E1E1Eh
- mov edx, eax
- _WRMSR
-
- ; Set 9FFFFh-80000h also as WB
- mov ecx, AMD_AP_MTRR_FIX16k_80000
- _WRMSR
-
- ; Set BFFFFh-A0000h as Uncacheable Memory-mapped IO
- mov ecx, AMD_AP_MTRR_FIX16k_A0000
- xor eax, eax
- xor edx, edx
- _WRMSR
-
- ; Set DFFFFh-C0000h as Uncacheable Memory-mapped IO
- xor eax, eax
- xor edx, edx
- mov ecx, AMD_AP_MTRR_FIX4k_C0000
-
-CDLoop:
- _WRMSR
- inc ecx
- cmp ecx, AMD_AP_MTRR_FIX4k_D8000
- jbe CDLoop
-
- ; Set FFFFFh-E0000h as Uncacheable Memory
- mov eax, 18181818h
- mov edx, eax
-
- mov ecx, AMD_AP_MTRR_FIX4k_E0000
-
-EFLoop:
- _WRMSR
- inc ecx
- cmp ecx, AMD_AP_MTRR_FIX4k_F8000
- jbe EFLoop
-
- ; If IBV provided settings for Fixed-Sized MTRRs,
- ; overwrite the default settings.
- .if (esi != 0)
- mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
- ; While we are not at the end of the list
- .while (ecx != CPU_LIST_TERMINAL)
- ; Ensure that the MSR address is valid for Fixed-Sized MTRRs
- .if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \
- (ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || (ecx == AMD_AP_MTRR_FIX16k_A0000))
- mov eax, dword ptr (AP_MTRR_SETTINGS ptr [esi]).MsrData
- mov edx, dword ptr (AP_MTRR_SETTINGS ptr [esi+4]).MsrData
- _WRMSR
- .endif
- add esi, sizeof (AP_MTRR_SETTINGS)
- mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
- .endw
- .endif
-
- ; restore variable MTRR6 and MTRR7 to default states
- mov ecx, AMD_MTRR_VARIABLE_BASE6 ; clear MTRRPhysBase6 MTRRPhysMask6
- xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7
- xor edx, edx
- .while (cl < 010h)
- _WRMSR
- inc cl
- .endw
-
- ; Enable fixed-range and variable-range MTRRs
- mov ecx, AMD_MTRR_DEFTYPE
- _RDMSR
- or ax, 0C00h ; Set Fixed-Range Enable (FE) and MTRR Enable (E) bits
- _WRMSR
-
- ; Enable Top-of-Memory setting
- ; Enable use of RdMem/WrMem bits attributes
- mov ecx, MTRR_SYS_CFG
- _RDMSR
- bts eax, MtrrVarDramEn ; Enable
- btr eax, MtrrFixDramModEn ; Disable
- bts eax, MtrrFixDramEn ; Enable
- _WRMSR
-
- ; Enable the self modifying code check buffer and Enable hardware prefetches
- mov ecx, 0C0011022h
- _RDMSR
- btr eax, DC_DIS_SPEC_TLB_RLD ; Disable speculative TLB reloads bit
- btr eax, DIS_CLR_WBTOL2_SMC_HIT ; Disable the self modifying code check buffer bit
- btr eax, DIS_HW_PF ; Disable hardware prefetches bit
- _WRMSR
-
- dec cx ; MSRC001_1021 Instruction Cache Configuration Register (IC_CFG)
- _RDMSR
- btr eax, IC_DIS_SPEC_TLB_RLD ; turn on Disable speculative TLB reloads bit
- _WRMSR
-
- AMD_DISABLE_STACK_FAMILY_HOOK ; Re-Enable L3 cache to accept clear lines
-
- xor eax, eax
-
-@@:
- cli
- hlt
- jmp @B ;ExecuteHltInstruction
-ExecuteFinalHltInstruction ENDP
-
-;======================================================================
-; ExecuteHltInstruction: Performs a hlt instruction.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; eax, ebx, ecx, edx, esp
-;
-;======================================================================
-ExecuteHltInstruction PROC NEAR C PUBLIC
- cli
- hlt
- ret
-ExecuteHltInstruction ENDP
-
-;======================================================================
-; NmiHandler: Simply performs an IRET.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-NmiHandler PROC NEAR C PUBLIC
- iretd
-NmiHandler ENDP
-
-;======================================================================
-; GetCsSelector: Returns the current protected mode CS selector.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-GetCsSelector PROC NEAR C PUBLIC, CsSelector:PTR
- push ax
- push ebx
-
- call FarCallGetCs
- mov ebx, CsSelector
- mov [ebx], ax
- pop ebx
- pop ax
- ret
-GetCsSelector ENDP
-
-;======================================================================
-; FarCallGetCs:
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; none
-;
-; WARNING: This routine has a mirror routine in the PREMEM segment.
-; These two routines MUST be sync'd for content.
-;======================================================================
-FarCallGetCs PROC FAR PRIVATE
-
- mov ax, ss:[esp + 4]
- retf
-
-FarCallGetCs ENDP
-
-;======================================================================
-; SetIdtr:
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; none
-;
-; WARNING: This routine has a mirror routine in the PREMEM segment.
-; These two routines MUST be sync'd for content.
-;======================================================================
-SetIdtr PROC NEAR C PUBLIC USES EBX, IdtPtr:PTR
- mov ebx, IdtPtr
- lidt fword ptr ss:[ebx]
- ret
-SetIdtr ENDP
-
-;======================================================================
-; ExecuteWbinvdInstruction: Performs a wbinvd instruction.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-ExecuteWbinvdInstruction PROC NEAR C PUBLIC
- wbinvd ; Write back the cache tag RAMs
- ret
-ExecuteWbinvdInstruction ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib32.asm b/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib32.asm
deleted file mode 100644
index 6cd8a28a96..0000000000
--- a/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib32.asm
+++ /dev/null
@@ -1,138 +0,0 @@
-;/**
-; * @file
-; *
-; * Ids Assembly library 32bit
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: IDS
-; * @e \$Revision: 14305 $ @e \$Date: 2009-05-24 02:20:55 +0800 (Sun, 24 May 2009) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-.586p
-.model flat
-ASSUME FS:NOTHING
-.code
-public IdsDelay
-IdsDelay PROC NEAR C USES EAX EDX
-Local targetedx:dword, targeteax:dword
- rdtsc
-;set target time
- add eax,1500000000
- adc edx,0
- mov targetedx,edx
- mov targeteax,eax
-
- rdtsc
-;set "Si!=0" skip below loop
- .while(1)
- .if(si != 0)
- jmp delay_exit
- .endif
- .if(edx > targetedx)
- jmp delay_exit
- .elseif (edx == targetedx)
- .if(eax > targeteax)
- jmp delay_exit
- .endif
- .endif
- rdtsc
- .endw
-delay_exit:
- ret
-IdsDelay ENDP
-;/*++
-;
-;Routine Description:
-;
-; IdsErrorStop -- Function for Assert
-;
-;Arguments:
-; Filecode
-;
-;Returns:
-;
-; None
-;
-;--*/
-public IdsErrorStop
-IdsErrorStop PROC NEAR C filecode:dword
-local tmpebx:dword,tmpedx:dword
- pushad
-
- mov si,0 ; Si is used as control flag, "Si!=0" skip postcode loop
-; send debug port 1st, then fire SimNow breakpoint
- mov ax, 0deadh
- out 0e0h, ax
- mov eax, filecode
- out 84h, eax
- mov eax, 0BACCD00Bh ; Backdoor in SimNow
- mov ebx, 2 ; Select breakpoint feature
- cpuid
-
- mov ebx,0dead0000h
- mov edx,filecode
- ror edx,16
- mov bx,dx
- mov dx,0
-;ebx:edx = deadxxxxyyyy0000 xxxx is the filecode yyyy is the line num
- mov tmpebx,ebx
- mov tmpedx,edx
-
- xor eax,eax
- mov cl,6
-
- .while((cl != 0) && (si == 0))
- .if(cl <= 2)
- shld eax,edx,8
- shl edx,8
- .else
- shld eax,ebx,8
- shl ebx,8
- .endif
-
- out 80h,eax
- call IdsDelay
- dec cl
- .if(cl == 0)
- mov cl,6
- mov ebx,tmpebx
- mov edx,tmpedx
- .endif
- .endw
-
- popad
- xor eax,eax
- ret
-IdsErrorStop endp
-
-
-END
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib64.asm b/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib64.asm
deleted file mode 100644
index cec2bd8a32..0000000000
--- a/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib64.asm
+++ /dev/null
@@ -1,143 +0,0 @@
-;/**
-; * @file
-; *
-; * Ids Assembly library 64bit
-; *
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: IDS
-; * @e \$Revision: 14126 $ @e \$Date: 2009-05-21 23:02:32 +0800 (Thu, 21 May 2009) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-.code
-IdsDelay PROC
- push rax
- push rdx
- push rbx
- xor rax,rax
- xor rdx,rdx
- rdtsc
-;set target time
- add eax,1500000000
- adc edx,0
- shl rdx,32
- add rdx,rax
- mov rbx,rdx
-;rbx store the target
-;set "Si!=0" skip below loop
-__loop:
- cmp si,0
- jnz __loopexit
- rdtsc
- shl rdx,32
- add rdx,rax
- cmp rdx,rbx
- jae __loopexit
- jmp __loop
-__loopexit:
- pop rbx
- pop rdx
- pop rax
- ret
-IdsDelay ENDP
-;/*++
-;
-;Routine Description:
-;
-; IdsErrorStop -- Function for Assert
-;
-;Arguments:
-; Filecode
-;
-;Returns:
-;
-; None
-;
-;--*/
-public IdsErrorStop
-IdsErrorStop PROC
-;As x64 calling convention RCX is used as input parameters
- push rcx
- push rbx
- push si
- push dx
- push rbx
-
- mov si,0 ; Si is used as control flag, "Si!=0" skip postcode loop
-; send debug port 1st, then fire SimNow breakpoint
- mov ax, 0deadh
- out 0e0h, ax
- mov eax, ecx
- out 84h, eax
- mov eax, 0BACCD00Bh ; Backdoor in SimNow
- mov ebx, 2 ; Select breakpoint feature
- cpuid
-
- mov rax,0dead00000000h
- or rcx,rax
-;rcx= 0dead__FILECODE
- shl rcx,16
-;rcx= 0dead__FILECODE__0000
- mov rbx,rcx
-
- xor rax,rax
- mov dl,6
-
-IdsErrorStopLoop:
- cmp dl,0
- jz IdsErrorStopExit
- cmp si,0
- jnz IdsErrorStopExit
-
- shld rax,rcx,8
- shl rcx,8
- out 80h,eax
- call IdsDelay
-
- dec dl
- cmp dl,0
- jnz _nextloop
- mov dl,6
- mov rcx,rbx
-_nextloop:
- jmp IdsErrorStopLoop
-IdsErrorStopExit:
- pop rbx
- pop dx
- pop si
- pop rbx
- pop rcx
- xor rax,rax
- ret
-IdsErrorStop endp
-END
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mu.asm b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mu.asm
deleted file mode 100644
index fe4c86b604..0000000000
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mu.asm
+++ /dev/null
@@ -1,483 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; $Workfile:: mu.asm $ $Revision:: 443#$ $Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
-; Description: Main memory controller system configuration for AGESA
-;
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-;============================================================================
-
-
- .XLIST
- .LIST
-
- .686p
- .MODEL FLAT
- .CODE
- ASSUME FS: NOTHING
-
-; Define the calling convention used for the C library modules
-;@attention - This should be in a central include file
-CALLCONV EQU NEAR C
-
-
-;===============================================================================
-;memUOutPort:
-;
-; Do a 32 Bit IO Out operation using edx.
-; NOTE: This function will be obsolete in the future.
-;
-; In: Port - port number
-; Value - value to be written
-;
-; Out:
-;
-; All registers preserved.
-;===============================================================================
-MemUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD
- pushad
- mov edx,Port
- mov eax,Value
- out dx,al
- popad
- ret
-MemUOutPort ENDP
-
-
-;----------------------------------------------------------------------------
-; _SFENCE();
-;
-_SFENCE macro
- db 0Fh,0AEh,0F8h
- endm
-
-;----------------------------------------------------------------------------
-; _MFENCE();
-;
-_MFENCE macro
- db 0Fh,0AEh,0F0h
- endm
-
-;----------------------------------------------------------------------------
-; _EXECFENCE();
-;
-_EXECFENCE macro
- out 0EDh,al ;prevent speculative execution of following instructions
- endm
-
-;===============================================================================
-;MemUWriteCachelines:
-; Write a test pattern to DRAM
-;
-; In: Pattern - pointer to the write pattern
-; Address - Physical address to be read
-; ClCount - number of cachelines to be read
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUWriteCachelines PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD, ClCount:WORD
- pushad
- push ds
-
- mov eax,Address
- push ss
- pop ds
- xor edx,edx
- mov edx, DWORD PTR Pattern
- mov esi,edx
- mov edx,16
- _EXECFENCE
- xor ecx, ecx
- mov cx,ClCount
- shl ecx,2
- @@:
- db 66h, 0Fh,6Fh,06 ;MOVDQA xmm0,[esi]
- db 64h, 66h, 0Fh,0E7h,00 ;MOVNTDQ fs:[eax],xmm0 (xmm0 is 128 bits)
- add eax,edx
- add esi,edx
- loop @B
-
- pop ds
- popad
- ret
-MemUWriteCachelines ENDP
-
-;===============================================================================
-;MemUReadCachelines:
-;
-; Read a pattern of 72 bit times (per DQ), to test dram functionality. The
-;pattern is a stress pattern which exercises both ISI and crosstalk. The number
-;of cache lines to fill is dependent on DCT width mode and burstlength.
-;
-; In: Buffer - pointer to a buffer where read data will be stored
-; Address - Physical address to be read
-; ClCount - number of cachelines to be read
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUReadCachelines PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
-LOCAL Count:BYTE
- pushad
- ; First, issue continuous dummy reads to fill up the cache
- mov eax,Address
- .if (ClCount > 18)
- mov cx,ClCount
- shr cx,4
- mov Count,cl
- .while (Count != 0)
- push eax
- mov edi,eax
- add edi,128 ;bias value (to account for signed displacement)
- ;clflush opcode=0F AE /7
- mov esi,edi
- mov ebx,esi
- mov ecx,esi
- mov edx,esi
- add edi,4*64 ;TestAddr+4 cache lines
- add ebx,8*64 ;TestAddr+8 cache lines
- add ecx,12*64 ;TestAddr+12 cache lines
- add edx,16*64 ;TestAddr+16 cache lines
- sub edx,128
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- mov eax,fs:[edi] ;TestAddr+6 cache lines
- _MFENCE
- mov eax,fs:[edi+64] ;TestAddr+7 cache lines
- _MFENCE
- mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
- _MFENCE
- mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
- _MFENCE
- mov eax,fs:[ebx] ;TestAddr+10 cache lines
- _MFENCE
- mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
- _MFENCE
- mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
- _MFENCE
- mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
- _MFENCE
- mov eax,fs:[ecx] ;TestAddr+14 cache lines
- _MFENCE
- mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
- _MFENCE
- pop eax
- add eax,(16*64) ;Next 16CL
- dec Count
- .endw
- .else
- mov edi,eax
- add edi,128 ;bias value (to account for signed displacement)
- ;clflush opcode=0F AE /7
- mov esi,edi
- mov ebx,esi
- mov ecx,esi
- mov edx,esi
- add edi,4*64 ;TestAddr+4 cache lines
- add ebx,8*64 ;TestAddr+8 cache lines
- add ecx,12*64 ;TestAddr+12 cache lines
- add edx,16*64 ;TestAddr+16 cache lines
- sub edx,128
- .if(ClCount == 1)
- _MFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- .elseif(ClCount == 3)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- .elseif(ClCount == 6)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- .elseif(ClCount == 9)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- mov eax,fs:[edi] ;TestAddr+6 cache lines
- _MFENCE
- mov eax,fs:[edi+64] ;TestAddr+7 cache lines
- _MFENCE
- mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
- _MFENCE
- .elseif(ClCount == 18)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- mov eax,fs:[edi] ;TestAddr+6 cache lines
- _MFENCE
- mov eax,fs:[edi+64] ;TestAddr+7 cache lines
- _MFENCE
- mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
- _MFENCE
- mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
- _MFENCE
- mov eax,fs:[ebx] ;TestAddr+10 cache lines
- _MFENCE
- mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
- _MFENCE
- mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
- _MFENCE
- mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
- _MFENCE
- mov eax,fs:[ecx] ;TestAddr+14 cache lines
- _MFENCE
- mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
- _MFENCE
- mov eax,fs:[edx] ;TestAddr+16 cache lines
- _MFENCE
- mov eax,fs:[edx+64] ;TestAddr+17 cache lines
- _MFENCE
- .endif
- .endif
- _MFENCE
-
- ; Then, copy data to buffer
- mov esi,Address
- xor edx,edx
- mov edx,DWORD PTR Buffer
- mov edi,edx
- xor ecx, ecx
- mov cx,ClCount
- shl ecx,6
- @@:
- mov al,fs:[esi]
- mov ss:[edi],al
- inc esi
- inc edi
- loop @B
-
- popad
- ret
-MemUReadCachelines ENDP
-
-;===============================================================================
-;MemUDummyCLRead:
-;
-; Perform a single cache line read from a given physical address.
-;
-; In: Address - Physical address to be read
-; ClCount - number of cachelines to be read
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUDummyCLRead PROC CALLCONV PUBLIC Address:DWORD
- _SFENCE
- pushad
- mov eax,Address
- mov dl,fs:[eax]
- popad
- ret
-MemUDummyCLRead ENDP
-
-;===============================================================================
-;MemUFlushPattern:
-;
-; Flush a pattern of 72 bit times (per DQ) from cache. This procedure is used
-;to ensure cache miss on the next read training.
-;
-; In: Address - Physical address to be flushed
-; ClCount - number of cachelines to be flushed
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUFlushPattern PROC CALLCONV PUBLIC Address:DWORD, ClCount:WORD
- pushad
- mov edi,Address
- movzx ecx,ClCount
- @@:
- _MFENCE ; Force strong ordering of clflush
- db 64h,0Fh,0AEh,3Fh ; MemUClFlush fs:[edi]
- _MFENCE
- add edi,64
- loop @B
- popad
- ret
-MemUFlushPattern ENDP
-
-
-;===============================================================================
-;MemUGetWrLvNblErr:
-; Read ClCount number of cachelines then return the bitmap that indicates
-; the write leveling result of each byte lane.
-;
-; IN: ErrBitmap - pointer to a DWORD that will be assigned with WL result
-; Address - Physical address to be sampled
-; ClCount - number of cachelines to be read
-;
-; OUT: ErrBitmap - WL result
-;
-;All registers preserved
-;===============================================================================
-MemUGetWrLvNblErr PROC CALLCONV PUBLIC ErrBitmap:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
-LOCAL ZeroCount[32]:WORD
-
- pushad
- mov esi,Address
- _EXECFENCE
- ;Cache fill
- movzx ecx,ClCount
- @@:
- mov eax,fs:[esi]
- add esi,64
- loop @B
- _MFENCE
-
- ; Then, count the number of 0's
- ;push es
- ;push ss
- ;pop es
- lea edi,ZeroCount
- mov cx,SIZEOF ZeroCount
- mov al,0
- rep stosb
- ;pop es
-
- mov esi,Address
- lea edi,ZeroCount
- mov cx,ClCount
- shl cx,6
- .while(cx > 0)
- mov al,fs:[esi]
- test al,00Fh ;check lower nibble
- .if(ZERO?)
- inc WORD PTR [edi]
- .endif
- add edi,2
- test al,0F0h ;check upper nibble
- .if(ZERO?)
- inc WORD PTR [edi]
- .endif
- add edi,2
- inc esi
- dec cx
- test cx,07h
- .if(ZERO?)
- sub edi,(16*2)
- sub cx,8
- add esi,8
- .endif
- .endw
-
- ; Then, average and compress data to error bits
- lea esi,ZeroCount
- mov dx,ClCount
- shl dx,1
- xor eax,eax
- xor ecx,ecx
- mov cl,0
- .while(cl<16)
- .if(WORD PTR [esi] < dx)
- bts eax,ecx
- .endif
- add esi,2
- inc cl
- .endw
- xor edx,edx
- mov dx,WORD PTR ErrBitmap
- mov [edx], ax
-
- popad
- ret
-MemUGetWrLvNblErr ENDP
-
-;===============================================================================
-;AlignPointerTo16Byte:
-; Modifies BufferPtr to be 16 byte aligned
-;
-; In: BufferPtrPtr - Pointer to buffer pointer
-; Out: BufferPtrPtr - Pointer to buffer pointer that has been 16 byte aligned
-;
-;All registers preserved.
-;===============================================================================
-AlignPointerTo16Byte PROC CALLCONV PUBLIC BufferPtrPtr:NEAR PTR DWORD
- push edx
- push eax
- mov edx, BufferPtrPtr
- mov eax, [edx]
- add eax, 16
- and ax, 0FFF0h
- mov [edx], eax
- pop eax
- pop edx
- ret
-AlignPointerTo16Byte ENDP
-
- END
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.asm b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.asm
deleted file mode 100644
index 725bd94261..0000000000
--- a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.asm
+++ /dev/null
@@ -1,187 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; $Workfile:: mu.asm $ $Revision:: 443#$ $Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
-; Description: Main memory controller system configuration for AGESA DDR 2
-;
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-;============================================================================
-
-
- .XLIST
- .LIST
- .686p
- .MODEL FLAT
- .CODE
- ASSUME FS: NOTHING
-
-
-; Define the calling convention used for the C library modules
-;@attention - This should be in a central include file
-CALLCONV EQU NEAR C
-
-
-;===============================================================================
-;MemRecUOutPort:
-;
-; Do a 32 Bit IO Out operation using edx.
-; NOTE: This function will be obsolete in the future.
-;
-; In: Port - port number
-; Value - value to be written to port
-;
-; Out:
-;
-;All registers preserved except for "Out:"
-;===============================================================================
-MemRecUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD
- pushad
- mov edx,Port
- mov eax,Value
- out dx,al
- popad
- ret
-MemRecUOutPort ENDP
-
-
-
-;----------------------------------------------------------------------------
-; _MFENCE();
-;
-_MFENCE macro
- db 0Fh,0AEh,0F0h
- endm
-
-;----------------------------------------------------------------------------
-; _EXECFENCE();
-;
-_EXECFENCE macro
- out 0EDh,al ;prevent speculative execution of following instructions
- endm
-
-;===============================================================================
-;MemRecUWrite1CL:
-;
-; Write data from buffer to a system address
-;
-; In: Address - System address to read from
-; Pattern - pointer pattern.
-;
-; Out:
-;
-;All registers preserved except for "Out:"
-;===============================================================================
-MemRecUWrite1CL PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD
- pushad
- push ds
-
- mov eax,Address
- push ss
- pop ds
- xor edx,edx
- mov edx, DWORD PTR Pattern
- mov esi,edx
- mov edx,16
- _EXECFENCE
- mov ecx,4
- @@:
- db 66h,0Fh,6Fh,06 ;MOVDQA xmm0,[esi]
- db 64h,66h,0Fh,0E7h,00 ;MOVNTDQ fs:[eax],xmm0 (xmm0 is 128 bits)
- add eax,edx
- add esi,edx
- loop @B
-
- pop ds
- popad
- ret
-MemRecUWrite1CL ENDP
-
-;===============================================================================
-;MemRecURead1CL:
-;
-; Read one cacheline to buffer
-;
-; In: Buffer - pointer buffer.
-; : Address - System address to read from
-;
-; Out:
-;
-;All registers preserved except for "Out:"
-;===============================================================================
-MemRecURead1CL PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD
-
- pushad
-
- mov esi,Address
- xor edx,edx
- mov edx,DWORD PTR Buffer
- mov edi,edx
- mov ecx,64
- @@:
- mov al,fs:[esi]
- mov ss:[edi],al
- inc esi
- inc edi
- loop @B
-
- popad
- ret
-MemRecURead1CL ENDP
-
-
-;===============================================================================
-;MemRecUFlushPattern:
-;
-; Flush one cache line
-;
-; In: Address - System address [31:0]
-; Out:
-;
-;All registers preserved except for "Out:"
-;===============================================================================
-MemRecUFlushPattern PROC CALLCONV PUBLIC Address:DWORD
- pushad
- mov eax,Address
- _EXECFENCE
- ;clflush fs:[eax]
- db 064h ;access relative to FS BASE prefix
- db 00Fh ;opcode
- db 0AEh ;opcode
- db 038h ;eax indirect addressing
- _MFENCE
- popad
- ret
-MemRecUFlushPattern ENDP
-
-
-
- END
-
diff --git a/src/vendorcode/amd/agesa/f10/cpcarmac.inc b/src/vendorcode/amd/agesa/f10/cpcarmac.inc
deleted file mode 100644
index e893d1ef8b..0000000000
--- a/src/vendorcode/amd/agesa/f10/cpcarmac.inc
+++ /dev/null
@@ -1,406 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; Workfile: cpcarmac.inc $Revision:: 44323 $ $Date:: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
-;
-; Description: Code to setup and break down cache-as-stack
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- .XLIST
- INCLUDE cpcar.inc
- .LIST
- .586P
-
-;======================================================================
-; AMD_ENABLE_STACK: Setup a stack
-;
-; In:
-; none
-;
-; Out:
-; SS:ESP - Our new private stack location
-; 4000:3FFC - for BSP (16K Stack)
-; 4000:7FFC - for core0 of node1 (16K Stack)
-; 4000:BFFC - for core0 of node2 (16K Stack)
-; 4000:FFFC - for core0 of node3 (16K Stack)
-; 5000:3FFC - for core0 of node4 (16K Stack)
-; 5000:7FFC - for core0 of node5 (16K Stack)
-; 5000:BFFC - for core0 of node6 (16K Stack)
-; 5000:FFFC - for core0 of node7 (16K Stack)
-;
-; 6000:1FFC - for core1 node0 (4k stack)
-; 6000:2FFC - for core2 node0 (4k stack)
-; ...
-; 9000:8FFC - for core7 of node7 (4k stack) ......... max of 64 cores in system
-;
-; EAX = AGESA_STATUS
-;
-; ECX = Stack size in bytes
-;
-; Requirements:
-; * This routine presently is limited to a max of 64 processors
-;
-; Preserved:
-; ebx
-; Destroyed:
-; eax, ecx, edx, edi, esi, ds, es
-;
-;======================================================================
-AMD_ENABLE_STACK MACRO
-
- local SetupStack
- local SetupDramMap
- local get_SS_ESP
- local r16bmode
- local p32mode
- local init_stack
-
-; Note that SS:ESP will be default stack. Note that this stack
-; routine will not be used after memory has been initialized. Because
-; of its limited lifetime, it will not conflict with typical PCI devices.
-
- mov esp, ebx ; put return address in a safe place
-
- ; get node id and core id of current executing core
- mov si, -1
- GET_NODE_ID_CORE_ID
- movzx edi, di
-
- ; determine if stack is already enabled.
- mov eax, cr0
- test eax, 60000000h
- jnz SetupStack
- mov ecx, AMD_MTRR_DEFTYPE
- _RDMSR
- test ah, 0Ch
- jz SetupStack
- or edi, 0FFFF0000h ; indicate stack has already been initialized
- jmp get_SS_ESP
-
-SetupStack:
- ; Enable routing tables on BSP (just in case the HT init code has not yet enabled them)
- mov eax, 8000C06Ch
- mov dx, 0CF8h
- out dx, eax
- add dx, 4
- in eax, dx
- btr eax, 0
- out dx, eax
-
- ; Setup temporary DRAM map for CAS on all nodes
- mov eax, 8000C060h ; Get NodeCnt from BSP
- mov dx, 0CF8h
- out dx, eax
- add dx, 4
- in al, dx
- shr ax, 4
- and al, 7
- mov cl, al
-
- mov ebx, 8000C144h
-SetupDramMap:
- mov eax, ebx ; Set 0000_0000 to 00FF_FFFF as DRAM
- mov dx, 0CF8h
- out dx, eax
- add dx, 4
- mov eax, 0
- out dx, eax
-
- mov eax, ebx
- sub eax, 4
- mov dx, 0CF8h
- out dx, eax
- add dx, 4
- mov eax, 3
- out dx, eax
-
- add bh, 8
- dec cl
- jns SetupDramMap
-
- ; Disable the self modifying code check buffer and Disable hardware prefetches
- mov ecx, 0C0011022h
- _RDMSR
- bts eax, DC_DIS_SPEC_TLB_RLD ; turn on Disable speculative TLB reloads bit
- bts eax, DIS_CLR_WBTOL2_SMC_HIT ; turn on Disable the self modifying code check buffer bit
- bts eax, DIS_HW_PF ; turn on Disable hardware prefetches bit
- _WRMSR
- dec cx ; MSRC001_1021 Instruction Cache Configuration Register (IC_CFG)
- _RDMSR
- bts eax, IC_DIS_SPEC_TLB_RLD ; turn on Disable speculative TLB reloads bit
- _WRMSR
-
- AMD_ENABLE_STACK_FAMILY_HOOK ; Disable L3 cache to accept clear lines
-
- ; Init CPU MSRs for our init routines
- mov ecx, MTRR_SYS_CFG ; SYS_CFG
- _RDMSR
- and eax, 0FFE3FFFFh ; turn off MTRR enable bits
- bts eax, MtrrFixDramModEn ; turn on modification enable bit
- _WRMSR
-
- ; clear all variable and Fixed MTRRs
- mov ecx, 200h
- xor eax, eax
- xor edx, edx
- .while (cl != 10h) ; MTRRphysBasen and MTRRphysMaskn
- _WRMSR
- inc cl
- .endw
- mov cl, 50h ; MTRRfix64K_00000
- _WRMSR
- mov cl, 58h ; MTRRfix16K_80000
- _WRMSR
- mov cl, 59h ; MTRRfix16K_A0000
- _WRMSR
- mov cl, 68h ; MTRRfix4K_C0000 to MTRRfix4K_F8000
- .while (cl != 70h)
- _WRMSR
- inc cl
- .endw
-
- ; setup MTRR for stacks
- mov ebx, WB_DRAM_TYPE
- .if (di == 0) ;core 0
- .if (si > 3) ; node 0 to 3 located at 40000h, node 4 to 7 located at 50000h
- shl ebx, 8
- .endif
- mov ecx, AMD_MTRR_FIX64k_00000
- _RDMSR
- or edx, ebx
- _WRMSR
- .else ;core 1 to core 7 start at 60000h
- .if (si < 4) ; node 0 to 3 using AMD_MTRR_FIX64K_6000 and AMD_MTRR_FIX64K_7000 MTRR
- shl ebx, 16
- .if (si > 1)
- shl ebx, 8
- .endif
- mov ecx, AMD_MTRR_FIX64k_00000
- _RDMSR
- or edx, ebx
- _WRMSR
- .else ; node 4 to 7 uses AMD_MTRR_FIX16K_80000 and AMD_MTRR_FIX16K_9000 MTRR
- mov ecx, AMD_MTRR_FIX16k_80000
- _RDMSR
- .if (si < 6) ; node 4 and node 5
- .if (si == 4) ; node 4
- .if (di >= 4)
- shl ebx, 8
- .endif
- .else ; node 5
- shl ebx, 16
- .if (di >= 4)
- shl ebx, 8
- .endif
- .endif
- or eax, ebx
- _WRMSR
- .else ; node 6 and node 7
- .if (si == 6) ; node 6
- .if (di >= 4)
- shl ebx, 8
- .endif
- .else ; node 7
- shl ebx, 16
- .if (di >= 4)
- shl ebx, 8
- .endif
- .endif
- or edx, ebx
- _WRMSR
- .endif
- .endif
- .endif
-
- ; Clear IORRs, TOP_MEM and TOM2
- xor eax, eax
- xor edx, edx
-
- mov ecx, 0C0010016h ;IORRBase0
- .while (cl != 1Bh)
- _WRMSR
- inc cl
- .endw
- mov cl, 1Dh
- _WRMSR
-
- ; Enable MTRRs
- mov ecx, 02FFh ; MTRRdefType
- mov ah, 0Ch ; MtrrDefTypeEn and MtrrDefTypeFixEn
- _WRMSR
-
- mov ecx, MTRR_SYS_CFG ; SYS_CFG
- _RDMSR
- bts eax, MtrrFixDramEn ; MtrrFixDramEn
- btr eax, MtrrFixDramModEn ; turn off modification enable bit
- _WRMSR
-
- ; Enable caching in CR0
- mov eax, CR0 ; Enable WT/WB cache
- btr eax, 31 ; make sure paging is disabled
- btr eax, 30 ; Clear CR0 NW and CD
- btr eax, 29
- mov CR0, eax
-
-get_SS_ESP:
- ; allocate space for stacks
- xor cx, cx
- xor edx, edx
- .if (di == 0) ;core 0
- mov eax, CORE0_STACK_BASE_ADDR
- .while (cx <= si)
- add eax, 4000h
- inc cx
- .endw
- mov edx, eax
- sub eax, 4000h
- and eax, 0F0000h
- sub edx, 4
- and edx, 0FFFFh
- mov bx, CORE0_STACK_SIZE / 4
- .else ;core 1 to core 7 start at 60000h
- mov eax, CORE1_STACK_BASE_ADDR ; core 1 stack starts at 60000h
- .while (cx <= si)
- add eax, 8000h ; 32k for each node
- inc cx
- .endw
- sub eax, 8000h
- mov dx, ax
- and eax, 0F0000h
- xor cx, cx
- .while (cx <= di)
- add edx, 1000h ; 4k for APs
- inc cx
- .endw
- sub edx, 4
- mov bx, CORE1_STACK_SIZE / 4
- .endif
-
- ; Allocate stack and set ESP
- mov ecx, CR0 ; check for 32-bit protect mode
- test ecx, 1 ; PE bit
- jz r16bmode ; PE=0, real mode
- mov cx, cs ; PE=1
- cmp cx, 0D000h ; check for CS
- jb p32mode ; if CS < D000, it is a selector instead of a segment
-r16bmode:
- shr eax, 4 ; ax = ss, ds, es
- mov ss, ax
- mov ds, ax
- mov es, ax
- jmp init_stack
-p32mode:
- add edx, eax ; linear address of the stack
-init_stack:
-
- .if ( !(edi & 0FFFF0000h))
- std
- xor ecx, ecx
- mov cx, bx
- mov esi, edx
- rep lods DWORD PTR [esi]
- xor eax, eax
- mov cx, bx
- mov edi, edx
- rep stos DWORD PTR [edi]
- cld
- xor eax, eax ; eax = 0 : no error
- .else
- mov eax, 40000001h ; eax = AGESA_WARNING (Stack has already been set up)
- .endif
-
- mov cx, bx ; ecx = size in dwords
- shl ecx, 2 ; ecx = size in bytes
-
- mov ebx, esp
- mov esp, edx
-
-
-ENDM
-
-;======================================================================
-; AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine
-; should only be executed on the BSP
-;
-; In:
-; none
-;
-; Out:
-; EAX = AGESA_STATUS
-;
-; Preserved:
-; ebx
-; Destroyed:
-; eax, ecx, edx, esp
-;======================================================================
-AMD_DISABLE_STACK MACRO
-
- mov esp, ebx ; save return address
-
- ; Turn on modification enable bit
- mov ecx, MTRR_SYS_CFG
- _RDMSR
- bts eax, MtrrFixDramModEn ; Enable
- _WRMSR
-
- ; Disable MTRRs and turn on modification enable bit
- mov ecx,AMD_MTRR_FIX64k_00000
- mov eax,1E1E1E1Eh
- mov edx,eax
- _WRMSR ; 0 - 512K = WB Mem
- mov cl,58h
- _WRMSR ; 512K - 640K = WB Mem
-
- ; Turn off modification enable bit
- mov ecx, MTRR_SYS_CFG
- _RDMSR
- btr eax, MtrrFixDramModEn ; Disable
- _WRMSR
-
- ; Enable the self modifying code check buffer and Enable hardware prefetches
- mov ecx, 0C0011022h
- _RDMSR
- btr eax, DC_DIS_SPEC_TLB_RLD ; Disable speculative TLB reloads bit
- btr eax, DIS_CLR_WBTOL2_SMC_HIT ; Disable the self modifying code check buffer bit
- btr eax, DIS_HW_PF ; Disable hardware prefetches bit
- _WRMSR
-
- dec cx ; MSRC001_1021 Instruction Cache Configuration Register (IC_CFG)
- _RDMSR
- btr eax, IC_DIS_SPEC_TLB_RLD ; turn on Disable speculative TLB reloads bit
- _WRMSR
-
- AMD_DISABLE_STACK_FAMILY_HOOK ; Re-Enable L3 cache to accept clear lines
-
- mov ebx, esp
- xor eax, eax
-
-ENDM
diff --git a/src/vendorcode/amd/agesa/f12/Legacy/PlatformMemoryConfiguration.inc b/src/vendorcode/amd/agesa/f12/Legacy/PlatformMemoryConfiguration.inc
deleted file mode 100644
index 35c0d7cd67..0000000000
--- a/src/vendorcode/amd/agesa/f12/Legacy/PlatformMemoryConfiguration.inc
+++ /dev/null
@@ -1,420 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * AMD Platform Specific Memory Configuration
-; *
-; * Contains AMD AGESA Memory Configuration Override Interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 22910 $ @e \$Date: 2009-11-27 04:50:20 -0600 (Fri, 27 Nov 2009) $
-;
-; ****************************************************************************
-; *
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; *
-; **************************************************************************
-IFNDEF PSO_ENTRY
- PSO_ENTRY TEXTEQU <UINT8>; < Platform Configuration Table Entry
-ENDIF
-; *****************************************************************************************
-; *
-; * PLATFORM SPECIFIC MEMORY DEFINITIONS
-; *
-; *****************************************************************************************
-; */
-;
-; < Memory Speed and DIMM Population Masks
-;
-; < DDR Speed Masks
-;
-ANY_SPEED EQU 0FFFFFFFFh
-DDR400 EQU ( 1 SHL (DDR400_FREQUENCY / 66))
-DDR533 EQU ( 1 SHL (DDR533_FREQUENCY / 66))
-DDR667 EQU ( 1 SHL (DDR667_FREQUENCY / 66))
-DDR800 EQU ( 1 SHL (DDR800_FREQUENCY / 66))
-DDR1066 EQU ( 1 SHL (DDR1066_FREQUENCY / 66))
-DDR1333 EQU ( 1 SHL (DDR1333_FREQUENCY / 66))
-DDR1600 EQU ( 1 SHL (DDR1600_FREQUENCY / 66))
-DDR1866 EQU ( 1 SHL (DDR1866_FREQUENCY / 66))
-DDR2133 EQU ( 1 SHL (DDR2133_FREQUENCY / 66))
-DDR2400 EQU ( 1 SHL (DDR2400_FREQUENCY / 66))
-; <
-; < DIMM POPULATION MASKS
-;
-ANY_ EQU 0FFh
-SR_DIMM0 EQU 0001h
-SR_DIMM1 EQU 0010h
-SR_DIMM2 EQU 0100h
-SR_DIMM3 EQU 1000h
-DR_DIMM0 EQU 0002h
-DR_DIMM1 EQU 0020h
-DR_DIMM2 EQU 0200h
-DR_DIMM3 EQU 2000h
-QR_DIMM0 EQU 0004h
-QR_DIMM1 EQU 0040h
-QR_DIMM2 EQU 0400h
-QR_DIMM3 EQU 4000h
-ANY_DIMM0 EQU 000Fh
-ANY_DIMM1 EQU 00F0h
-ANY_DIMM2 EQU 0F00h
-ANY_DIMM3 EQU 0F000h
-;
-; Number of Dimms
-;
-ANY_NUM EQU 0FFh
-NO_DIMM EQU 00h
-ONE_DIMM EQU 01h
-TWO_DIMM EQU 02h
-THREE_DIMM EQU 04h
-FOUR_DIMM EQU 08h
-; *****************************************************************************************
-; *
-; * Platform Specific Override Definitions for Socket, Channel and Dimm
-; * This indicates where a platform override will be applied.
-; *
-; *****************************************************************************************
-;
-; SOCKET MASKS
-;
-ANY_SOCKET EQU 0FFh
-SOCKET0 EQU 01h
-SOCKET1 EQU 02h
-SOCKET2 EQU 04h
-SOCKET3 EQU 08h
-SOCKET4 EQU 10h
-SOCKET5 EQU 20h
-SOCKET6 EQU 40h
-SOCKET7 EQU 80h
-;
-; CHANNEL MASKS
-;
-ANY_CHANNEL EQU 0FFh
-CHANNEL_A EQU 01h
-CHANNEL_B EQU 02h
-CHANNEL_C EQU 04h
-CHANNEL_D EQU 08h
-;
-; DIMM MASKS
-;
-ALL_DIMMS EQU 0FFh
-DIMM0 EQU 01h
-DIMM1 EQU 02h
-DIMM2 EQU 04h
-DIMM3 EQU 08h
-;
-; REGISTER ACCESS MASKS
-;
-ACCESS_NB0 EQU 0h
-ACCESS_NB1 EQU 01h
-ACCESS_NB2 EQU 02h
-ACCESS_NB3 EQU 03h
-ACCESS_NB4 EQU 04h
-ACCESS_PHY EQU 05h
-ACCESS_DCT_XT EQU 06h
-; *****************************************************************************************
-; *
-; * Platform Specific Overriding Table Definitions
-; *
-; *****************************************************************************************
-PSO_END EQU 0 ; < Table End
-PSO_CKE_TRI EQU 1 ; < CKE Tristate Map
-PSO_ODT_TRI EQU 2 ; < ODT Tristate Map
-PSO_CS_TRI EQU 3 ; < CS Tristate Map
-PSO_MAX_DIMMS EQU 4 ; < Max Dimms per channel
-PSO_CLK_SPEED EQU 5 ; < Clock Speed
-PSO_DIMM_TYPE EQU 6 ; < Dimm Type
-PSO_MEMCLK_DIS EQU 7 ; < MEMCLK Disable Map
-PSO_MAX_CHNLS EQU 8 ; < Max Channels per Socket
-PSO_BUS_SPEED EQU 9 ; < Max Memory Bus Speed
-PSO_MAX_CHIPSELS EQU 10 ; < Max Chipsel per Channel
-PSO_MEM_TECH EQU 11 ; < Channel Memory Type
-PSO_WL_SEED EQU 12 ; < DDR3 Write Levelization Seed delay
-PSO_RXEN_SEED EQU 13 ; < Hardwared based RxEn seed
-PSO_NO_LRDIMM_CS67_ROUTING EQU 14 ; < CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
-PSO_SOLDERED_DOWN_SODIMM_TYPE EQU 15 ; < Soldered down SODIMM type
-PSO_LVDIMM_VOLT1_5_SUPPORT EQU 16 ; < Force LvDimm voltage to 1.5V
-; **********************************
-; * CONDITIONAL PSO SPECIFIC ENTRIES
-; **********************************
-; Condition Types
-CONDITIONAL_PSO_MIN EQU 100 ; < Start of Conditional Entry Types
-PSO_CONDITION_AND EQU 100 ; < And Block - Start of Conditional block
-PSO_CONDITION_LOC EQU 101 ; < Location - Specify Socket, Channel, Dimms to be affected
-PSO_CONDITION_SPD EQU 102 ; < SPD - Specify a specific SPD value on a Dimm on the channel
-PSO_CONDITION_REG EQU 103 ; Reserved
-PSO_CONDITION_MAX EQU 103 ; < End Of Condition Entry Types
-; Action Types
-PSO_ACTION_MIN EQU 120 ; < Start of Action Entry Types
-PSO_ACTION_ODT EQU 120 ; < ODT values to override
-PSO_ACTION_ADDRTMG EQU 121 ; < Address/Timing values to override
-PSO_ACTION_ODCCONTROL EQU 122 ; < ODC Control values to override
-PSO_ACTION_SLEWRATE EQU 123 ; < Slew Rate value to override
-PSO_ACTION_REG EQU 124 ; Reserved
-PSO_ACTION_SPEEDLIMIT EQU 125 ; < Memory Bus speed Limit based on configuration
-PSO_ACTION_MAX EQU 125 ; < End of Action Entry Types
-CONDITIONAL_PSO_MAX EQU 139 ; < End of Conditional Entry Types
-; *****************************************************************************************
-; *
-; * CONDITIONAL OVERRIDE TABLE MACROS
-; *
-; *****************************************************************************************
-MEMCLK_DIS_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
- DB PSO_MEMCLK_DIS
- DB 10
- DB SocketID
- DB ChannelID
- DB Bit0Map
- DB Bit1Map
- DB Bit2Map
- DB Bit3Map
- DB Bit4Map
- DB Bit5Map
- DB Bit6Map
- DB Bit7Map
-ENDM
-
-CKE_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ
- DB PSO_CKE_TRI
- DB 4
- DB SocketID
- DB ChannelID
- DB Bit0Map
- DB Bit1Map
-ENDM
-
-ODT_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ
- DB PSO_ODT_TRI
- DB 6
- DB SocketID
- DB ChannelID
- DB Bit0Map
- DB Bit1Map
- DB Bit2Map
- DB Bit3Map
-ENDM
-
-CS_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
- DB PSO_CS_TRI
- DB 10
- DB SocketID
- DB ChannelID
- DB Bit0Map
- DB Bit1Map
- DB Bit2Map
- DB Bit3Map
- DB Bit4Map
- DB Bit5Map
- DB Bit6Map
- DB Bit7Map
-ENDM
-
-NUMBER_OF_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfDimmSlotsPerChannel:REQ
- DB PSO_MAX_DIMMS
- DB 3
- DB SocketID
- DB ChannelID
- DB NumberOfDimmSlotsPerChannel
-ENDM
-
-NUMBER_OF_CHIP_SELECTS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfChipSelectsPerChannel:REQ
- DB PSO_MAX_CHIPSELS
- DB 3
- DB SocketID
- DB ChannelID
- DB NumberOfChipSelectsPerChannel
-ENDM
-
-NUMBER_OF_CHANNELS_SUPPORTED MACRO SocketID:REQ, NumberOfChannelsPerSocket:REQ
- DB PSO_MAX_CHNLS
- DB 3
- DB SocketID
- DB ANY_CHANNEL
- DB NumberOfChannelsPerSocket
-ENDM
-
-OVERRIDE_DDR_BUS_SPEED MACRO SocketID:REQ, ChannelID:REQ, TimingMode:REQ, BusSpeed:REQ
- PSO_BUS_SPEED
- DB 10
- DB SocketID
- DB ChannelID
- DD TimingMode
- DD BusSpeed
-ENDM
-
-DRAM_TECHNOLOGY MACRO SocketID:REQ, MemTechType:REQ
- DB PSO_MEM_TECH
- DB 6
- DB SocketID
- DB ANY_CHANNEL
- DD MemTechType
-ENDM
-
-WRITE_LEVELING_SEED MACRO SocketID:REQ, ChannelID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
-Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
- DB PSO_WL_SEED
- DB 11
- DB SocketID
- DB ChannelID
- DB Byte0Seed
- DB Byte1Seed
- DB Byte2Seed
- DB Byte3Seed
- DB Byte4Seed
- DB Byte5Seed
- DB Byte6Seed
- DB Byte7Seed
- DB ByteEccSeed
-ENDM
-
-HW_RXEN_SEED MACRO SocketID:REQ, ChannelID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
-Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
- DB PSO_RXEN_SEED
- DB 20
- DB SocketID
- DB ChannelID
- DW Byte0Seed
- DW Byte1Seed
- DW Byte2Seed
- DW Byte3Seed
- DW Byte4Seed
- DW Byte5Seed
- DW Byte6Seed
- DW Byte7Seed
- DW ByteEccSeed
-ENDM
-
-NO_LRDIMM_CS67_ROUTING MACRO SocketID:REQ, ChannelID:REQ
- DB PSO_NO_LRDIMM_CS67_ROUTING
- DB 3
- DB SocketID
- DB ChannelID
- DB 1
-ENDM
-
-SOLDERED_DOWN_SODIMM_TYPE MACRO SocketID:REQ, ChannelID:REQ
- DB PSO_SOLDERED_DOWN_SODIMM_TYPE
- DB 3
- DB SocketID
- DB ChannelID
- DB 1
-ENDM
-
-LVDIMM_FORCE_VOLT1_5_FOR_D0 MACRO
- DB PSO_LVDIMM_VOLT1_5_SUPPORT
- DB 3
- DB ANY_SOCKET
- DB ANY_CHANNEL
- DB 1
-ENDM
-
-; *****************************************************************************************
-; *
-; * CONDITIONAL OVERRIDE TABLE MACROS
-; *
-; *****************************************************************************************
-CONDITION_AND MACRO
- DB PSO_CONDITION_AND
- DB 0
-ENDM
-
-COND_LOC MACRO SocketMsk:REQ, ChannelMsk:REQ, DimmMsk:REQ
- DB PSO_CONDITION_LOC
- DB 3
- DB SocketMsk
- DB ChannelMsk
- DB DimmMsk
-ENDM
-
-COND_SPD MACRO Byte:REQ, Mask:REQ, Value:REQ
- DB PSO_CONDITION_SPD
- DB 3
- DB Byte
- DB Mask
- DB Value
-ENDM
-
-COND_REG MACRO Access:REQ, Offset:REQ, Mask:REQ, Value:REQ
- DB PSO_CONDITION_REG
- DB 11
- DB Access
- DW Offset
- DD Mask
- DD Value
-ENDM
-
-ACTION_ODT MACRO Frequency:REQ, Dimms:REQ, QrDimms:REQ, DramOdt:REQ, QrDramOdt:REQ, DramDynOdt:REQ
- DB PSO_ACTION_ODT
- DB 9
- DD Frequency
- DB Dimms
- DB QrDimms
- DB DramOdt
- DB QrDramOdt
- DB DramDynOdt
-ENDM
-
-ACTION_ADDRTMG MACRO Frequency:REQ, DimmConfig:REQ, AddrTmg:REQ
- DB PSO_ACTION_ADDRTMG
- DB 10
- DD Frequency
- DW DimmConfig
- DD AddrTmg
-ENDM
-
-ACTION_ODCCTRL MACRO Frequency:REQ, DimmConfig:REQ, OdcCtrl:REQ
- DB PSO_ACTION_ODCCONTROL
- DB 10
- DD Frequency
- DW DimmConfig
- DD OdcCtrl
-ENDM
-
-ACTION_SLEWRATE MACRO Frequency:REQ, DimmConfig:REQ, SlewRate:REQ
- DB PSO_ACTION_SLEWRATE
- DB 10
- DD Frequency
- DW DimmConfig
- DD SlewRate
-ENDM
-
-ACTION_SPEEDLIMIT MACRO DimmConfig:REQ, Dimms:REQ, SpeedLimit15:REQ, SpeedLimit135:REQ, SpeedLimit125:REQ
- DB PSO_ACTION_SPEEDLIMIT
- DB 9
- DW DimmConfig
- DB Dimms
- DW SpeedLimit15
- DW SpeedLimit135
- DW SpeedLimit125
-ENDM
-
-; *****************************************************************************************
-; *
-; * END OF CONDITIONAL OVERRIDE TABLE MACROS
-; *
-; *****************************************************************************************
diff --git a/src/vendorcode/amd/agesa/f12/Legacy/Proc/arch2008.asm b/src/vendorcode/amd/agesa/f12/Legacy/Proc/arch2008.asm
deleted file mode 100644
index 1c56b86d76..0000000000
--- a/src/vendorcode/amd/agesa/f12/Legacy/Proc/arch2008.asm
+++ /dev/null
@@ -1,2674 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; Workfile: arch2008.asm $Revision: 44324 $ $Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
-;
-; Description: ARCH2008.ASM - AGESA Architecture 2008 Wrapper Template
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*****************************************************************************
-
- .XLIST
- INCLUDE agesa.inc
- INCLUDE acwrapg.inc ; Necessary support file as part of wrapper, including but not limited to segment start/end macros.
- INCLUDE acwrap.inc ; IBVs may specify host BIOS-specific include files required when building.
- INCLUDE cpcarmac.inc
- INCLUDE bridge32.inc
- .LIST
- .586p
- .mmx
-
-
-;----------------------------------------------------------------------------
-; Local definitions
-;----------------------------------------------------------------------------
-
-sOemCallout STRUCT
- FuncName DD ? ; Call out function name
- FuncPtr DW ? ; Call out function pointer
-sOemCallout ENDS
-
-sOemEventHandler STRUCT
- ClassCode DD ? ; AGESA event log sub-class code
- FuncPtr DW ? ; Event handler function pointer
-sOemEventHandler ENDS
-
-;; A typical legacy BIOS implementation may require the E000 and F000 segments
-;; to be cached.
-EXE_CACHE_REGION_BASE_0 EQU 0E0000h
-EXE_CACHE_REGION_SIZE_0 EQU 20000h
-
-;; In this sample implementation, the B1 and B2 images are placed next to each
-;; other in the BIOS ROM to help with the maximization of cached code.
-EXE_CACHE_REGION_BASE_1 EQU AGESA_B1_ADDRESS
-EXE_CACHE_REGION_SIZE_1 EQU 40000h
-
-;; The third region is not needed in our example.
-EXE_CACHE_REGION_BASE_2 EQU 0
-EXE_CACHE_REGION_SIZE_2 EQU 0
-
-
-;----------------------------------------------------------------------------
-; PERSISTENT SEGMENT
-; This segment is required to be present throughout all BIOS execution.
-;----------------------------------------------------------------------------
-
-AMD_PERSISTENT_START
-
-
-;----------------------------------------------------------------------------
-; Instantiate the global descriptor table
-;----------------------------------------------------------------------------
-
-AMD_BRIDGE_32_GDT AMD_GDT ; Instantiate the global descriptor table
- ; required by the push-high mechanism.
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the persistent segment
-;----------------------------------------------------------------------------
-
-;+-------------------------------------------------------------------------
-;
-; AmdDfltRet
-;
-; Entry:
-; None
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Near stub procedure. Simply perform a retn instruction.
-;
-EXTERN AmdDfltRet:NEAR
-
-
-;+-------------------------------------------------------------------------
-;
-; AmdDfltRetFar
-;
-; Entry:
-; None
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Far stub procedure. Simply perform a retf instruction.
-;
-EXTERN AmdDfltRetFar:FAR
-
-
-;----------------------------------------------------------------------------
-; Declare the optional external routines in the persistent segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myModuleTypeMismatchHandler (Example)
-;
-; Entry:
-; ESI - Pointer to the EVENT_PARAMS structure of the failure.
-; [ESI].DataParam1 - Socket
-; [ESI].DataParam2 - DCT
-; [ESI].DataParam3 - Channel
-; [ESI].DataParam4 - 0x00000000
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure can be used to react to a memory module type
-; mismatch error discovered by the AGESA code. Actions taken
-; may include, but are not limited to:
-; Logging the event to NV for display later
-; Reset, excluding the mismatch on subsequent reboot
-; Do nothing
-;
-; Dependencies:
-; None
-;
-EXTERN myModuleTypeMismatchHandler(AmdDfltRet):NEAR
-
-;+---------------------------------------------------------------------------
-;
-; oemPlatformConfigInit (Optional)
-;
-; Entry:
-; EDI - 32-bit flat pointer to the PLATFORM_CONFIGURATION to be
-; passed in to the next AGESA entry point.
-;
-; typedef struct {
-; IN PERFORMANCE_PROFILE PlatformProfile;
-; IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList;
-; IN UINT8 CoreLevelingMode;
-; IN PLATFORM_C1E_MODES C1eMode;
-; IN UINT32 C1ePlatformData;
-; IN UINT32 C1ePlatformData1;
-; IN UINT32 C1ePlatformData2;
-; IN UINT32 C1ePlatformData3;
-; IN BOOLEAN UserOptionDmi;
-; IN BOOLEAN UserOptionPState;
-; IN BOOLEAN UserOptionSrat;
-; IN BOOLEAN UserOptionSlit;
-; IN BOOLEAN UserOptionWhea;
-; IN UINT32 PowerCeiling;
-; IN BOOLEAN PstateIndependent;
-; } PLATFORM_CONFIGURATION;
-;
-; typedef struct {
-; IN UINT8 Socket;
-; IN UINT8 Link;
-; IN UINT8 LoFreq;
-; IN UINT8 HighFreq;
-; IN PLATFORM_DEEMPHASIS_LEVEL ReceiverDeemphasis;
-; IN PLATFORM_DEEMPHASIS_LEVEL DcvDeemphasis;
-; } CPU_HT_DEEMPHASIS_LEVEL;
-;
-; typedef struct {
-; IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode;
-; IN BOOLEAN UseHtAssist;
-; IN BOOLEAN UseAtmMode;
-; IN BOOLEAN Use32ByteRefresh;
-; IN BOOLEAN UseVariableMctIsocPriority;
-; } PERFORMANCE_PROFILE;
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Provide a single hook routine to modify the parameters of a
-; PLATFORM_CONFIGURATION structure before any entry point that
-; has such a structure as an input.
-;
-; Dependencies:
-; None
-;
-; Example:
-; If your platform is running in UMA mode, the following code
-; may be added:
-; mov (PLATFORM_CONFIGURATION PTR [edi]).PlatformProfile.PlatformControlFlowMode, UmaDr
-;
-EXTERN oemPlatformConfigInit(AmdDfltRetFar):FAR
-
-;+---------------------------------------------------------------------------
-;
-; oemCallout (Optional)
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The default call out router function which resides in the same
-; segment as the push-high bridge code.
-;
-; Dependencies:
-; None
-;
-EXTERN oemCallout(AmdDfltRet):NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the persistent segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdBridge32
-;
-; Entry:
-; EDX - A Real Mode FAR pointer using seg16:Offset16 format that
-; points to a local host environment call-out router. If
-; this pointer is not equal to zero, then this pointer is
-; used as the call-out router instead of the standard
-; OemCallout. This may be useful when the call-out router
-; is not located in the same segment as the AmdBridge32 and
-; AmdCallout16 routines.
-; ESI - A Flat Mode pointer (32-bit address) that points to the
-; configuration block (AMD_CONFIG_PARAMS) for the AGESA
-; software function.
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; Execute an AGESA software function through the Push-High interface.
-;
-; Dependencies:
-; This procedure requires a stack. The host environment must use the
-; provided service function to establish the stack environment prior
-; to making the call to this procedure.
-;
-AmdBridge32 PROC FAR PUBLIC
- AMD_BRIDGE_32 AMD_GDT ; use the macro for the body
- ret
-AmdBridge32 ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdEnableStack
-;
-; Entry:
-; BX - Return address
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; SS:ESP - Points to the private stack location for this processor core.
-; ECX - Upon success, contains this processor core's stack size in bytes.
-;
-; Modified:
-; EAX, ECX, EDX, EDI, ESI, ESP, DS, ES
-;
-; Purpose:
-; This procedure is used to establish the stack within the host environment.
-;
-; Dependencies:
-; The host environment must use this procedure and not rely on any other
-; sources to create the stack region.
-;
-AmdEnableStack PROC NEAR PUBLIC
- AMD_ENABLE_STACK
- ;; EAX = AGESA_SUCCESS, The stack space has been allocated for this core.
- ;; EAX = AGESA_WARNING, The stack has already been set up. SS:ESP is set
- ;; to stack top, and ECX is the stack size in bytes.
- jmp bx
-AmdEnableStack ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdDisableStack
-;
-; Entry:
-; BX - Return address
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; EAX, ECX, EDX, ESI, ESP
-;
-; Purpose:
-; This procedure is used to remove the pre-memory stack from within the
-; host environment.
-; The exit state for the BSP is described as follows:
-; Memory region 00000-9FFFF MTRRS are set as WB memory.
-; Processor Cache is enabled (CD bit is cleared).
-; MTRRs used for execution cache are kept.
-; Cache content is flushed (invalidated without write-back).
-; Any family-specific clean-up done.
-; The exit state for the APs is described as follows:
-; Memory region 00000-9FFFF MTRRS are set as WB memory.
-; Memory region A0000-DFFFF MTRRS are set as UC IO.
-; Memory region E0000-FFFFF MTRRS are set as UC memory.
-; MTRRs used for execution cache are cleared.
-; Processor Cache is disabled (CD bit is set).
-; Top-of-Memory (TOM) set to the system top of memory as determined
-; by the memory initialization routines.
-; System lock command is enabled.
-; Any family-specific clean-up done.
-;
-; Dependencies:
-; The host environment must use this procedure and not rely on any other
-; sources to break down the stack region.
-; If executing in 16-bit code, the host environment must establish the
-; "Big Real" mode of 32-bit addressing of data.
-;
-AmdDisableStack PROC NEAR PUBLIC
- AMD_DISABLE_STACK
- ;; EAX = AGESA_SUCCESS, The stack space has been disabled for this core.
- jmp bx
-AmdDisableStack ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCallout16
-;
-; Entry:
-; [esp+8] - Func
-; [esp+12] - Data
-; [esp+16] - Configuration Block
-; [esp+4] - Return address to AGESA
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; Execute callback from the push-high interface.
-;
-; Dependencies:
-; None
-;
-AmdCallout16 PROC FAR PUBLIC ; declare the procedure
- AMD_CALLOUT_16 oemCallout ; use the macro for the body
- ret
-AmdCallout16 ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdProcessAgesaErrors (Optional)
-;
-; Entry:
-; AL - Heap status of the AGESA entry point that was just invoked.
-; EBX - AGESA image base address.
-; EDX - Segment / Offset of the appropriate callout router function.
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure is used to handle any errors that may have occurred
-; during an AGESA entry point.
-;
-; Dependencies:
-; None
-;
-AmdProcessAgesaErrors PROC FAR PUBLIC
- LOCAL localCpuInterfaceBlock:EVENT_PARAMS
-
- pushad
- xor edi, edi
- mov di, ss
- shl edi, 4
- lea esi, localCpuInterfaceBlock
- add esi, edi
-
- ; Fill default config block
- mov (EVENT_PARAMS PTR [esi]).StdHeader.Func, AMD_READ_EVENT_LOG
- mov (EVENT_PARAMS PTR [esi]).StdHeader.ImageBasePtr, ebx
- mov (EVENT_PARAMS PTR [esi]).StdHeader.AltImageBasePtr, 0
- mov (EVENT_PARAMS PTR [esi]).StdHeader.HeapStatus, al
- mov edi, SEG AmdCallout16
- shl edi, 4
- add edi, OFFSET AmdCallout16
- mov (EVENT_PARAMS PTR [esi]).StdHeader.CalloutPtr, edi
-
- ; Flush the event log searching for, and handling all monitored events
- xor eax, eax
- .while (eax == 0)
- push edx
- call AmdBridge32
- pop edx
- .if (eax == AGESA_SUCCESS)
- mov eax, (EVENT_PARAMS PTR [esi]).EventInfo
- .if (eax != 0)
- lea di, cs:AgesaEventTable
-
-loopThruTable:
- cmp di, OFFSET cs:AgesaEventTableEnd
- jae unhandledEvent
-
- cmp eax, cs:[di].sOemEventHandler.ClassCode
- je FoundMatch
- add di, SIZEOF sOemEventHandler
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemEventHandler.FuncPtr
- call bx
-
-unhandledEvent:
- xor eax, eax
- .else
- mov al, 1
- .endif
- .endif
- .endw
- popad
- ret
-
-AmdProcessAgesaErrors ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the error handler table
-;----------------------------------------------------------------------------
-
-AgesaEventTable LABEL BYTE
- ;; Add entries as desired
- ;;---------
- ;; EXAMPLE
- ;;---------
- sOemEventHandler <MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, OFFSET myModuleTypeMismatchHandler>
-AgesaEventTableEnd LABEL BYTE
-
-
-AMD_PERSISTENT_END
-
-
-
-
-;----------------------------------------------------------------------------
-; RECOVERY SEGMENT
-; This segment resides in the classic 'boot-block,' and is used
-; for recovery.
-;----------------------------------------------------------------------------
-
-AMD_RECOVERY_START
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the recovery segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myReadSPDRecovery (Required for proper recovery mode operation)
-;
-; Entry:
-; ESI - Pointer to an AGESA_READ_SPD_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT8 SocketId;
-; IN UINT8 MemChannelId;
-; IN UINT8 DimmId;
-; IN OUT UINT8 *Buffer;
-; IN OUT MEM_DATA_STRUCT *MemData;
-; } AGESA_READ_SPD_PARAMS;
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS Indicates the SPD block for the indicated
-; DIMM was read successfully.
-; AGESA_BOUNDS_CHK The specified DIMM is not present.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function and no memory initialized.
-; AGESA_ERROR The DIMM SPD read process has generated
-; communication errors.
-;
-; Modified:
-; None
-;
-; Purpose:
-; This call out reads a block of memory SPD data and places it
-; into the provided buffer.
-;
-; Dependencies:
-; None
-;
-EXTERN myReadSPDRecovery:NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the recovery segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitResetWrapper
-;
-; Entry:
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; A minimal initialization of the processor core is performed. This
-; procedure must be called by all processor cores. The code path
-; separates the BSP from the APs and performs a separate and appropriate
-; list of tasks for each class of core.
-; For the BSP, the following actions are performed:
-; Internal heap sub-system initialization
-; Primary non-coherent HyperTransportT link initialization
-; Return to the host environment to test for Recovery Mode.
-; The AP processor cores do not participate in the recovery process.
-; However, they execute this routine after being released to execute
-; by the BSP during the main boot process. Their actions include the
-; following:
-; Internal heap sub-system initialization
-; Proceed to a wait loop waiting for commands from the BSP
-;
-; For the cache regions, up to three regions of execution cache can be
-; allocated following the following rules:
-; 1. Once a region is allocated, it cannot be de-allocated. However, it
-; can be expanded.
-; 2. At most, two of the three regions can be located above 1 MByte. A
-; region failing this rule is ignored.
-; 3. All region addresses must be at or above the 0x000D0000 linear
-; address. A region failing this rule is ignored.
-; 4. The address is aligned on a 32-KByte boundary. Starting addresses
-; is rounded down to the nearest 32-Kbyte boundary.
-; 5. The execution cache size must be a multiple of 32 KByte. Size is
-; rounded up to the next multiple of 32 KByte.
-; 6. A region must not span either the 1-MByte boundary or the 4-GByte
-; boundary. Allocated size is truncated to not span the boundary.
-; 7. The granted cached execution regions, address, and size are calculated
-; based on the available cache resources of the processor core.
-; Allocations are made up to the limit of cache available on the
-; installed processor.
-; Warning: Enabling instruction cache outside of this interface can cause
-; data corruption.
-;
-; Dependencies:
-; This procedure is expected to be executed soon after a system reset
-; for the main boot path or resume path of execution.
-;
-; This procedure requires a stack.
-;
-; Because the heap system is not yet operational at the point of the
-; interface call, the host environment must allocate the storage for
-; the AMD_RESET_PARAMS structure before making the first call to
-; AmdCreateStruct. This is the ByHost method of allocation.
-;
-AmdInitResetWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
- local localResetParams:AMD_RESET_PARAMS
-
- pushad
-
- ; Prepare for the call to initialize the input parameters for AmdInitReset
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B1_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- ; Use the 'ByHost' allocation method because the heap has not been initialized as of yet.
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RESET
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, ByHost
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, sizeof AMD_RESET_PARAMS
- lea edx, localResetParams
- add edx, eax
- push edx
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr, edx
- mov dx, SEG AmdCalloutRouterRecovery
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterRecovery
- push edx
- call AmdBridge32
- pop edx
- pop esi
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- ; Allocate the execution cache to maximize the amount of code in ROM that is cached.
- ; Placing the B1 and B2 images near one another is a good way to ensure the AGESA code
- ; is cached.
- mov (AMD_RESET_PARAMS ptr [esi]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_0
- mov (AMD_RESET_PARAMS ptr [esi]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_0
- mov (AMD_RESET_PARAMS ptr [esi + sizeof EXECUTION_CACHE_REGION]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_1
- mov (AMD_RESET_PARAMS ptr [esi + sizeof EXECUTION_CACHE_REGION]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_1
- mov (AMD_RESET_PARAMS ptr [esi + (2 * sizeof EXECUTION_CACHE_REGION)]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_2
- mov (AMD_RESET_PARAMS ptr [esi + (2 * sizeof EXECUTION_CACHE_REGION)]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_2
-
- ; Call in to the AmdInitReset entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS Early initialization completed successfully.
- ;; AGESA_WARNING One or more of the execution cache allocation
- ;; rules were violated, but an adjustment was made
- ;; and space was allocated.
- ;; AGESA_ERROR One or more of the execution cache allocation rules
- ;; were violated, which resulted in a requested cache
- ;; region to not be allocated.
- ;; The storage space allocated for the AMD_RESET_PARAMS
- ;; structure is insufficient.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_RESET_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B1_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
-
- ;; Here are what the MTRRs should look like based off of the CacheRegions specified above:
-
- ;; Fixed-Range MTRRs
- ;; Name Address Value
- ;; ---------------- -------- ----------------
- ;; MTRRfix4k_E0000 0000026C 0505050505050505
- ;; MTRRfix4k_E8000 0000026D 0505050505050505
- ;; MTRRfix4k_F0000 0000026E 0505050505050505
- ;; MTRRfix4k_F8000 0000026F 0505050505050505
- ;; MTRRdefType 000002FF 0000000000000C00
- ;;
- ;; Variable-Range MTRRs and IO Range
- ;; MTRRphysBase(n) MTRRphysMask(n)
- ;; ----------------- -----------------
- ;; n=0 0000000000000000 0000000000000000
- ;; n=1 0000000000000000 0000000000000000
- ;; n=2 0000000000000000 0000000000000000
- ;; n=3 0000000000000000 0000000000000000
- ;; n=4 0000000000000000 0000000000000000
- ;; n=5 Heap Base (Varies by core) 0000FFFFFFFF0800
- ;; n=6 AGESA_B1_ADDRESS | 6 0000FFFFFFFC0800
- ;; n=7 0000000000000000 0000000000000000
-
-
- ;; Because the allocation method is 'ByHost,' the call to AMD_RELEASE_STRUCT is
- ;; not necessary. Stack space reclamation is left up to the host BIOS.
-
- popad
- ret
-
-
-AmdInitResetWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitRecoveryWrapper
-;
-; Entry:
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Perform a minimum initialization of the processor and memory to
-; support a recovery mode flash ROM update.
-; For the BSP, the following actions are performed:
-; Configuration of CPU core for recovery process
-; Minimal initialization of some memory
-; The AP processor cores do not participate in the recovery process.
-; No actions or tasks are performed by the AP cores for this time point.
-;
-; Dependencies:
-; This procedure requires a stack. The host environment must use one of
-; the provided service functions to establish the stack environment prior
-; to making the call to this procedure.
-;
-AmdInitRecoveryWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitRecovery
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B1_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RECOVERY
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterRecovery
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterRecovery
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
-
- ; Call in to the AmdInitRecovery entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_WARNING One or more of the allocation rules were violated,
- ;; but an adjustment was made and space was allocated.
- ;; AGESA_ERROR One or more of the allocation rules were violated,
- ;; which resulted in a requested cache region to not be
- ;; allocated.
- ;; AGESA_FATAL No memory was found in the system.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_RECOVERY_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B1_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitRecovery
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-AmdInitRecoveryWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCalloutRouterRecovery
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The call out router function for AmdInitReset and
-; AmdInitRecovery.
-;
-; Dependencies:
-; None
-;
-AmdCalloutRouterRecovery PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
- xor ax, ax
- mov ds, ax
- mov es, ax
- lea di, cs:CalloutRouterTableRecovery
- mov eax, AGESA_UNSUPPORTED
-
-loopThruTable:
- cmp di, OFFSET cs:CalloutRouterTableRecoveryEnd
- jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
- cmp ecx, cs:[di].sOemCallout.FuncName
- je FoundMatch
- add di, SIZEOF sOemCallout
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemCallout.FuncPtr
- call bx
-
-amdCpuCalloutExit:
- ret
-AmdCalloutRouterRecovery ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the callout dispatch table for the recovery segment
-;----------------------------------------------------------------------------
-
-CalloutRouterTableRecovery LABEL BYTE
- ;; Standard B1 implementations only need the SPD reader call out function to be implemented.
- sOemCallout <AGESA_READ_SPD, OFFSET myReadSPDRecovery>
-CalloutRouterTableRecoveryEnd LABEL BYTE
-
-
-AMD_RECOVERY_END
-
-
-
-;----------------------------------------------------------------------------
-; PRE-MEMORY SEGMENT
-; This segment must be uncompressed in the ROM image.
-;----------------------------------------------------------------------------
-
-AMD_PREMEM_START
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the recovery segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myReadSPDPremem (Required)
-;
-; Entry:
-; ESI - Pointer to an AGESA_READ_SPD_PARAMS structure
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT8 SocketId;
-; IN UINT8 MemChannelId;
-; IN UINT8 DimmId;
-; IN OUT UINT8 *Buffer;
-; IN OUT MEM_DATA_STRUCT *MemData;
-; } AGESA_READ_SPD_PARAMS;
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS Indicates the SPD block for the indicated
-; DIMM was read successfully.
-; AGESA_BOUNDS_CHK The specified DIMM is not present.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function and no memory initialized.
-; AGESA_ERROR The DIMM SPD read process has generated
-; communication errors.
-;
-; Modified:
-; None
-;
-; Purpose:
-; This call out reads a block of memory SPD data and places it
-; into the provided buffer.
-;
-; Dependencies:
-; None
-;
-EXTERN myReadSPDPremem:NEAR
-
-;+-------------------------------------------------------------------------
-;
-; AmdDfltRetPremem
-;
-; Entry:
-; None
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Near stub procedure in the prememory segment. Simply perform a
-; retn instruction.
-;
-EXTERN AmdDfltRetPremem:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myDoReset (Required)
-;
-; Entry:
-; EDX - Reset type
-; 1 - Warm reset whenever
-; 2 - Cold reset whenever
-; 3 - Warm reset immediately
-; 4 - Cold reset immediately
-; ESI - Pointer to an AMD_CONFIG_PARAMS structure.
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function.
-;
-; Modified:
-; None
-;
-; Purpose:
-; This host environment function must initiate the specified type
-; of system reset.
-;
-; Implementation of this function by the host environment is
-; REQUIRED. Some host environments may record this as a request
-; allowing other elements in the system to perform some additional
-; tasks before the actual reset is issued.
-;
-; Dependencies:
-; The AMD processor contains 3 bits (BiosRstDet[2:0]) in a PCI
-; register (F0x6C Link Initialization Control Register) that
-; indicate the reset status. These bits are reserved for use by
-; the AGESA software and should not be modified by the host
-; environment.
-;
-EXTERN myDoReset:NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myGetNonVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; None
-;
-; Exit:
-; EBX - Pointer to the non-volatile S3 context block
-; ECX - Size in bytes of the non-volatile S3 context block
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must return the pointer to the data
-; saved during the mySaveNonVolatileS3Context routine.
-;
-; Dependencies:
-; None
-;
-EXTERN myGetNonVolatileS3Context:NEAR
-
-
-;----------------------------------------------------------------------------
-; Declare the optional external routines in the prememory segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myAgesaHookBeforeExitSelfRefresh (Optional)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 44h
-; ESI - Pointer to a data structure containing the memory information
-;
-; Exit:
-; After returning control to AGESA, AGESA will display: - AGESA_TESTPOINT - 45h
-; EAX - Contains the AGESA_STATUS return code
-; AGESA_SUCCESS The function has completed successfully
-; AGESA_UNSUPPORTED This function is not implemented by the host environment
-; AGESA_WARNING A non-critical issue has occued in the host environment
-;
-; Modified:
-; None
-;
-; Purpose:
-; General purpose hook called before the exiting self refresh
-; This procedure is called once per channel
-;
-; Implementation of this function is optional for the host environment
-; This call-out is an opportunity for the host environment to make dynamic
-; modifications to the memory timing settings specific to the board or host
-; environment before exiting self refresh on S3 resume
-;
-; Dependencies:
-; This procedure is called before the exit self refresh bit is set in the resume
-; sequence. The host environment must initiate the OS restart process. This procedure
-; requires a stack. The host environment must establish the stack environment prior
-; to making the call to this procedure
-;
-EXTERN myAgesaHookBeforeExitSelfRefresh(AmdDfltRetPremem):NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myHookBeforeDramInit (Optional)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 40h
-; ESI - Pointer to a data structure containing the memory information
-;
-; Exit:
-; After returning control to AGESA, AGESA will display - AGESA_TESTPOINT - 41h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This function is not implemented by the host environment
-;
-; Modified:
-; None
-;
-; Purpose:
-; General-purpose hook called before the DRAM_Init bit is set. Called
-; once per MCT
-;
-; Implementation of this function is optional for the host environment
-; This call-out is an opportunity for the host environment to make
-; dynamic modifications to the memory timing settings specific to the
-; board or host environment
-;
-; Dependencies:
-; None
-;
-EXTERN myHookBeforeDramInit(AmdDfltRetPremem):NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myHookBeforeDQSTraining (Optional)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 42h
-; ESI - Pointer to a data structure containing the memory information.
-;
-; Exit:
-; After returning control to AGESA, AGESA will display - AGESA_TESTPOINT - 43h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This function is not implemented by the
-; host environment.
-;
-; Modified:
-; None
-;
-; Purpose:
-; General-purpose hook called just before the memory training processes
-; begin. Called once per MCT.
-;
-; Implementation of this function is optional for the host environment.
-; This call-out is an opportunity for the host environment to make
-; dynamic modifications to the memory timing settings specific to the
-; board or host environment.
-;
-; The host environment may also use this call-out for some board-
-; specific features that should be activated at this time point,
-; such as:
-; Low voltage DIMMs-the host environment should set the recommended
-; voltages found in the memory data structure for each memory
-; channel. This needs to occur before training begins.
-;
-; Dependencies:
-; None
-;
-EXTERN myHookBeforeDQSTraining(AmdDfltRetPremem):NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the prememory segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitEarlyWrapper
-;
-; Entry:
-; On Entry to "AmdInitEarly" AGESA will display AGESA_TESTPOINT - C4h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitEarly" AGESA will display AGESA_TESTPOINT - C5h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; A full initialization of the processor is performed. Action details
-; differ for the BSP and AP processor cores.
-; For the BSP, the following actions are performed:
-; Full HyperTransportT link initialization, coherent and non-coherent
-; Processor register loading
-; Microcode patch load
-; Errata workaround processing
-; Launch all processor cores
-; Configure the processor power management capabilities
-; Request a warm reset if needed
-; For the AP, the following actions are performed:
-; Processor register loading
-; Microcode patch load
-; Errata workaround processing
-; Configure the processor power management capabilities
-;
-; Dependencies:
-; This procedure is expected to be called before main memory initialization
-; and before the system warm reset. Prior to this, the basic configuration
-; done by the AmdInitReset routine must be completed.
-;
-; This procedure requires a stack. The host environment must use one of the
-; provided service functions to establish the stack environment prior to
-; making the call to this procedure.
-;
-; The processes performed at this time point require communication between
-; processor cores.
-;
-; The host environment must recognize that all processor cores are running
-; in parallel and avoid activities that might interfere with the core-to-core
-; communication, such as modifying the MTRR settings or writing to the APIC
-; registers.
-;
-AmdInitEarlyWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitEarly
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_EARLY
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPremem
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPremem
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + (3 * (SIZEOF EXECUTION_CACHE_REGION)))
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitEarly entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ALERT An HyperTransportT link CRC error was observed.
- ;; AGESA_WARNING One of more of the allocation rules were violated,
- ;; but an adjustment was made and space was allocated.
- ;; Or a HyperTransport device does not have the expected
- ;; capabilities, or unusable redundant HyperTransport
- ;; links were found.
- ;; AGESA_ERROR One or more of the allocation rules were violated, which
- ;; resulted in a requested cache region to not be allocated.
- ;; Or, a HyperTransport device failed to initialize.
- ;; AGESA_CRITICAL An illegal or unsupported mixture of processor types was
- ;; found, or the processors installed were found to have an
- ;; insufficient MP capability rating for this platform.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_EARLY_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitEarly
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitEarlyWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitPostWrapper
-;
-; Entry:
-; On Entry to "AmdInitPost" AGESA will display AGESA_TESTPOINT - C6h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitPost" AGESA will display AGESA_TESTPOINT - C7h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The main system memory is located, initialized, and brought on-line.
-; The processor(s) are prepared for full operation and control by the
-; host environment. Action details differ for the BSP and AP processor
-; cores.
-; For the BSP, the following actions are performed:
-; Full memory initialization and configuration. BSP is the master for
-; this process and may delegate some tasks to APs.
-; AP collection of data for use later.
-; Transfer the HOBs including the artifact data out of the pre-memory
-; cache storage into a temporary holding buffer in the main memory.
-; Check the BIST status of the BSP
-; Shut down the APs.
-; Prepare for the host environment to begin main boot activity.
-; Disable the pre-memory stack.
-; For the APs, the following actions are performed:
-; Report core identity information.
-; Execute indicated memory initialization processes as directed.
-; Check the BIST status of the AP
-; Disable the pre-memory stack.
-; Prepare to halt, giving control to host environment.
-; The entire range of system memory is enabled for Write-Back cache.
-; The fixed MTRRs and the variable MTRRs[7:6] are not changed in order
-; to leave in place any flash ROM region currently set for Write-Protect
-; execution cache.
-;
-; Dependencies:
-; This procedure is called after the host environment has determined that
-; a normal boot to operating system should be performed after any system
-; warm reset is completed and after the configuration done by AmdInitEarly
-; has completed.
-;
-; This procedure requires a stack. The host environment must use one of the
-; provided service functions to establish the stack environment prior to
-; making the call to this procedure.
-;
-; The processes performed at this time point require communication between
-; processor cores. The host environment must recognize that all processor
-; cores are running in parallel and avoid activities that might interfere
-; with the core-to-core communication, such as modifying the MTRR settings
-; or writing to the APIC registers.
-;
-AmdInitPostWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitPost
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_POST
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPremem
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPremem
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitPost entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ALERT A BIST error was found on one of the cores.
- ;; AGESA_WARNING HT Assist feature is running sub-optimally.
- ;; AGESA_FATAL Memory initialization failed.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_POST_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitPost
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitPostWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitResumeWrapper
-;
-; Entry:
-; On Entry to "AmdInitResume" AGESA will display AGESA_TESTPOINT - D0h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitResume" AGESA will display AGESA_TESTPOINT - D1h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure initializes or re-initializes the silicon components
-; for the resume boot path. For the processor, main memory is brought
-; out of self-refresh mode. This procedure will use the context data
-; in the NvStorage area of the input structure to re-start the main
-; memory. The host environment must fill the AMD_S3_PARAMS NvStorage
-; and VolatileStorage pointers and related size elements to describe
-; the location of the context data. Note that for this procedure, the
-; two data areas do not need to be contained in one buffer zone, they
-; can be anywhere in the accessible memory address space. If the host
-; environment uses a non-volatile storage device accessed on the system
-; address bus such as flashROM, then the context data does not need to
-; be moved prior to this call. If the host environment uses a non-
-; volatile storage device not located on the system address bus (e.g.
-; CMOS or SSEPROM) then the host environment must transfer the context
-; data to a buffer in main memory prior to calling this procedure.
-;
-; Dependencies:
-; The host environment must have determined that the system should take
-; the resume path prior to calling this procedure. The configuration
-; done by AmdInitEarly and any necessary warm reset must be complete.
-; After this procedure, execution proceeds to general system restoration.
-;
-; This procedure requires a stack. The host environment must use one of
-; the provided service functions to establish the stack environment prior
-; to making the call to this procedure.
-;
-AmdInitResumeWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitResume
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RESUME
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPremem
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPremem
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
- call oemPlatformConfigInit
-
- call myGetNonVolatileS3Context
- mov (AMD_RESUME_PARAMS ptr [esi]).S3DataBlock.NvStorage, ebx
- mov (AMD_RESUME_PARAMS ptr [esi]).S3DataBlock.NvStorageSize, ecx
-
- ; Call in to the AmdInitResume entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS Re-initialization has been completed successfully.
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_RESUME_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
-
- ; Allow AGESA to free the space used by AmdInitResume
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitResumeWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCalloutRouterPremem
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The call out router function for AmdInitEarly,
-; AmdInitPost, and AmdInitResume.
-;
-; Dependencies:
-; None
-;
-AmdCalloutRouterPremem PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
- xor ax, ax
- mov ds, ax
- mov es, ax
- lea di, cs:CalloutRouterTablePremem
- mov eax, AGESA_UNSUPPORTED
-
-loopThruTable:
- cmp di, OFFSET cs:CalloutRouterTablePrememEnd
- jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
- cmp ecx, cs:[di].sOemCallout.FuncName
- je FoundMatch
- add di, SIZEOF sOemCallout
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemCallout.FuncPtr
- call bx
-
-amdCpuCalloutExit:
- ret
-AmdCalloutRouterPremem ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the callout dispatch table for the prememory segment
-;----------------------------------------------------------------------------
-
-CalloutRouterTablePremem LABEL BYTE
- ;; Add entries as desired.
- sOemCallout <AGESA_READ_SPD, OFFSET myReadSPDPremem>
- sOemCallout <AGESA_HOOKBEFORE_DRAM_INIT, OFFSET myHookBeforeDramInit>
- sOemCallout <AGESA_HOOKBEFORE_DQS_TRAINING, OFFSET myHookBeforeDQSTraining>
- sOemCallout <AGESA_HOOKBEFORE_EXIT_SELF_REF, OFFSET myAgesaHookBeforeExitSelfRefresh>
- sOemCallout <AGESA_DO_RESET, OFFSET myDoReset>
-CalloutRouterTablePrememEnd LABEL BYTE
-
-
-
-AMD_PREMEM_END
-
-
-;----------------------------------------------------------------------------
-; POST SEGMENT
-; This segment may be decompressed and run from system RAM.
-;----------------------------------------------------------------------------
-
-AMD_POST_START
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the POST segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myAllocateBuffer (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E2h
-; ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 BufferLength;
-; IN UINT32 BufferHandle;
-; OUT VOID *BufferPointer;
-; } AGESA_BUFFER_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E3h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The requested size of memory has been
-; successfully allocated.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function.
-; AGESA_ERROR Less than the requested amount of memory
-; was allocated.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of memory allocation.
-; This function must allocate a buffer of the requested size or
-; larger. This function is required to be implemented by the host
-; environment.
-;
-; Dependencies:
-; The following call-outs must work together in the host system.
-; Parameters of the same name have the same function and must be
-; treated the same in each function:
-; AgesaAllocateBuffer
-; AgesaDeallocateBuffer
-; AgesaLocateBuffer
-; AgesaRunFcnOnAp
-; The host environment may need to reserve a location in the buffer
-; to store any host environment specific value(s). The returned
-; pointer must not include this reserved space. The host environment
-; on the AgesaDeallocateBuffer call needs to account for the reserved
-; space. This reserved space may be an identifier or the "handle"
-; used to identify the specific memory block.
-;
-EXTERN myAllocateBuffer:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myDeallocateBuffer (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E4h
-; ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 BufferLength;
-; IN UINT32 BufferHandle;
-; OUT VOID *BufferPointer;
-; } AGESA_BUFFER_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E5h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_BOUNDS_CHK The BufferHandle is invalid. The AGESA
-; software continues with its function.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of memory allocation.
-; This function releases a valid working buffer. This function is
-; required for the host environment to implement.
-;
-; Dependencies:
-; The following call-outs must work together in the host system.
-; Parameters of the same name have the same function and must be
-; treated the same in each function:
-; AgesaAllocateBuffer
-; AgesaDeallocateBuffer
-; AgesaLocateBuffer
-; AgesaRunFcnOnAp
-;
-EXTERN myDeallocateBuffer:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myLocateBuffer (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E6h
-; ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 BufferLength;
-; IN UINT32 BufferHandle;
-; OUT VOID *BufferPointer;
-; } AGESA_BUFFER_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E7h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_BOUNDS_CHK The presented handle is invalid or the
-; buffer could not be located.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of memory allocation.
-; This function must locate the buffer related to the indicated
-; handle and return the address of the buffer and its length.
-; This function is required to be implemented in the host
-; environment.
-;
-; Dependencies:
-; The following call-outs must work together in the host system.
-; Parameters of the same name have the same function and must be
-; treated the same in each function:
-; AgesaAllocateBuffer
-; AgesaDeallocateBuffer
-; AgesaLocateBuffer
-; AgesaRunFcnOnAp
-;
-EXTERN myLocateBuffer:NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myRunFuncOnAp (Required)
-;
-; Entry:
-; EDX - Local APIC ID of the target core.
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must route execution to the target AP and
-; have that AP call the AmdLateRunApTaskWrapper routine defined
-; above.
-;
-; Dependencies:
-; None
-;
-EXTERN myRunFuncOnAp:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; mySaveNonVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; EBX - Pointer to the non-volatile S3 context block
-; ECX - Size in bytes of the non-volatile S3 context block
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must save the non-volatile data to an area
-; that will not lose context while in the ACPI S3 sleep state, but
-; cannot be placed in system RAM. This data will need to be
-; available during the call to AmdInitResume.
-;
-; Dependencies:
-; None
-;
-EXTERN mySaveNonVolatileS3Context:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; mySaveVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; EBX - Pointer to the volatile S3 context block
-; ECX - Size in bytes of the volatile S3 context block
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must save the volatile data to an area
-; that will not lose context while in the ACPI S3 sleep state.
-; This data will need to be available during the call to
-; AmdS3LateRestore.
-;
-; Dependencies:
-; None
-;
-EXTERN mySaveVolatileS3Context:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myGetVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; None
-;
-; Exit:
-; EBX - Pointer to the volatile S3 context block
-; ECX - Size in bytes of the volatile S3 context block
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must return the pointer to the data
-; saved during the mySaveVolatileS3Context routine.
-;
-; Dependencies:
-; None
-;
-EXTERN myGetVolatileS3Context:NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the POST segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitEnvWrapper
-;
-; Entry:
-; On Entry to "AmdInitEnv" AGESA will display AGESA_TESTPOINT - C8h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitEnv" AGESA will display AGESA_TESTPOINT - C9h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure uses the AgesaAllocateBuffer call-out to acquire
-; permanent buffer space for the UEFI Hand-Off Blocks (HOBs). This
-; is also known as, or includes, artifact data being used by the
-; AGESA software. Upon entry to this procedure, the data is being
-; held in a temporary memory location and it must be moved to a
-; location controlled and protected by the host environment.
-;
-; These actions are performed by the BSP. The APs are not assigned
-; any tasks at this time point.
-;
-; Dependencies:
-; This procedure must be called after full memory is initialized and
-; the host environment has taken control of main memory allocation.
-; This procedure should be called before the PCI enumeration takes
-; place and as soon as possible after the host environment memory
-; allocation sub-system has started.
-;
-; This procedure requires a stack. The host environment must use one
-; of the provided service functions to establish the stack environment
-; prior to making the call to this procedure.
-;
-AmdInitEnvWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitEnv
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_ENV
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitEnv entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ERROR The artifact data could not be found or the host
- ;; environment failed to allocate sufficient buffer space.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_ENV_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitEnv
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitEnvWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitMidWrapper
-;
-; Entry:
-; On Entry to "AmdInitMid" AGESA will display AGESA_TESTPOINT - CAh
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitMid" AGESA will display AGESA_TESTPOINT - CBh
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure call performs special configuration requirements for
-; the graphics display hardware.
-;
-; These actions are performed by the BSP. The APs are not assigned any
-; tasks at this time point.
-;
-; Dependencies:
-; This procedure must be called after PCI enumeration has allocated
-; resources, but before the video BIOS call is performed.
-;
-; This procedure requires a stack. The host environment must use one
-; of the provided service functions to establish the stack environment
-; prior to making the call to this procedure.
-;
-AmdInitMidWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitMid
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_MID
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitMid entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_MID_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitMid
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-
-AmdInitMidWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitLateWrapper
-;
-; Entry:
-; On Entry to "AmdInitLate" AGESA will display AGESA_TESTPOINT - CCh
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitLate" AGESA will display AGESA_TESTPOINT - CDh
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The main purpose of this function is to generate informational
-; data tables used by the operating system. The individual tables
-; can be selected for generation through the user selection entries
-; on the input parameters.
-;
-; This routine uses the Call-Out AgesaAllocateBuffer to allocate a
-; buffer of the proper size to contain the data.
-;
-; The code path separates the BSP from the APs and perform a separate
-; and appropriate list of tasks for each class of core.
-; For the BSP, the following actions are performed:
-; Allocate buffer space for the tables.
-; Generate the table contents.
-; Make sure that the CPU is in a known good power state before
-; proceeding to boot the OS.
-; For the APs, the following actions are performed:
-; Final register settings preparing for entry to OS.
-; Establish the final PState for entry to OS.
-;
-; Dependencies:
-; This routine is expected to be executed late in the boot sequence
-; after main memory has been initialized, after PCI enumeration has
-; completed, after the host environment ACPI sub-system has started,
-; after the host environment has taken control of the APs, but just
-; before the start of OS boot.
-;
-; The host environment must provide the required call-outs listed in
-; the "Required Call-Out Procedures" section of the AGESA interface
-; specification to provide the buffer space in main memory and execute
-; code on the APs. The host environment must register the created ACPI
-; table in the main ACPI pointer tables. This may require moving the
-; generated tables to another location in memory.
-;
-; This procedure requires a stack. The host environment must establish
-; the stack environment prior to making the call to this procedure.
-; Some functions depend upon the preservation of the heap data across
-; the shift from pre-memory environment to a post-memory environment.
-; If that data was not preserved, then those functions cannot complete
-; and an error is returned.
-;
-AmdInitLateWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitLate
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_LATE
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitLate entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ALERT
- ;; AGESA_ERROR The system could not allocate the needed amount of
- ;; buffer space; or could not locate the artifact data block in
- ;; memory. Likely cause: the host environment may not have preserved
- ;; the data properly.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_LATE_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- push es
- mov ax, SEG AmdAcpiSratPointer
- mov es, ax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiSrat
- mov es:AmdAcpiSratPointer, ebx
- mov eax, DWORD PTR [ebx + 4]
- mov es:AmdAcpiSratSize, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiSlit
- mov es:AmdAcpiSlitPointer, ebx
- mov eax, DWORD PTR [ebx + 4]
- mov es:AmdAcpiSlitSize, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiPState
- mov es:AmdAcpiSsdtPointer, ebx
- mov eax, DWORD PTR [ebx + 4]
- mov es:AmdAcpiSsdtSize, eax
-
- xor eax, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiWheaMce
- mov es:AmdAcpiWheaMcePointer, ebx
- mov ax, WORD PTR [ebx]
- mov es:AmdAcpiWheaMceSize, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiWheaMce
- mov es:AmdAcpiWheaCmcPointer, ebx
- mov ax, WORD PTR [ebx]
- mov es:AmdAcpiWheaCmcSize, eax
-
- mov eax, (AMD_LATE_PARAMS ptr [esi]).DmiTable
- mov es:AmdDmiInfoPointer, eax
- pop es
-
-
- ; Allow AGESA to free the space used by AmdInitLate
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-
-AmdInitLateWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdS3SaveWrapper
-;
-; Entry:
-; On Entry to "AmdS3Save" AGESA will display AGESA_TESTPOINT - CEh
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Entry to "AmdS3Save" AGESA will display AGESA_TESTPOINT - CFh
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure saves critical registers and/or configuration
-; information for preservation across a system suspend mode. All
-; actions needed to prepare the processor for suspend mode is
-; performed, however this procedure does NOT initiate the suspend
-; process. The host environment is expected to perform that duty.
-;
-; These actions are performed by the BSP. The APs are not assigned
-; any tasks at this time point.
-;
-; The initializer routine will NULL out the save area pointers and
-; sizes. This procedure will determine the size of storage needed
-; for all the processor context, and make a call out to the environment
-; for allocation of one buffer to store all of the data. Upon exit, the
-; pointers and sizes within the AMD_S3_PARAMS structure will be updated
-; with the appropriate addresses within the buffer that was allocated.
-; The host environment is expected to then transfer the data pointed to
-; by NvStorage to a non-volatile storage area, and the data pointed to
-; by VolatileStorage to either a non-volatile storage area or system
-; RAM that retains its content across suspend.
-;
-; Dependencies:
-; The host environment must initiate the suspend process.
-;
-; This procedure requires a stack. The host environment must establish
-; the stack environment prior to making the call to this procedure.
-;
-AmdS3SaveWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdS3Save
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_S3_SAVE
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
- call oemPlatformConfigInit
-
- ; Call in to the AmdS3Save entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS All suspend duties have been completed successfully.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_S3SAVE_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- mov ecx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.NvStorageSize
- .if (ecx != 0)
- mov ebx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.NvStorage
- call mySaveNonVolatileS3Context
- .endif
-
- mov ecx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.VolatileStorageSize
- .if (ecx != 0)
- mov ebx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.VolatileStorage
- call mySaveVolatileS3Context
- .endif
-
- ; Allow AGESA to free the space used by AmdS3Save
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-
-AmdS3SaveWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdS3LateRestoreWrapper
-;
-; Entry:
-; On Entry to "AmdS3LateRestore" AGESA will display AGESA_TESTPOINT - D2h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdS3LateRestore" AGESA will display AGESA_TESTPOINT - D3h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure restores the processor state, reloads critical
-; silicon component registers, and performs any re-initialization
-; required by the silicon. This procedure will use the context data
-; in the VolatileStorage area of the input structure to restore the
-; processor registers.
-;
-; The host environment must fill the AMD_S3_PARAMS NvStorage and
-; VolatileStorage pointers and related size elements to describe
-; the location of the context data. Note that for this procedure,
-; the two data areas do not need to be contained in one buffer zone,
-; they can be anywhere in the accessible memory address space. If
-; the host environment uses a non-volatile storage device accessed
-; on the system address bus such as flashROM, then the context data
-; does not need to be moved prior to this call. If the host
-; environment uses a non-volatile storage device not located on the
-; system address bus (e.g. CMOS or SSEPROM) then the host environment
-; must transfer the context data to a buffer in main memory prior to
-; calling this procedure.
-;
-; These actions are performed by the BSP. The APs are not assigned
-; any tasks at this time point.
-;
-; Dependencies:
-; This procedure is called late in the resume sequence, after the
-; PCI control space is restored and just before resuming operating
-; system execution.
-;
-; The host environment must initiate the OS restart process.
-;
-; This procedure requires a stack. The host environment must establish
-; the stack environment prior to making the call to this procedure.
-;
-AmdS3LateRestoreWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdS3LateRestore
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_S3LATE_RESTORE
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
- call oemPlatformConfigInit
-
- call myGetVolatileS3Context
- mov (AMD_S3LATE_PARAMS ptr [esi]).S3DataBlock.VolatileStorage, ebx
- mov (AMD_S3LATE_PARAMS ptr [esi]).S3DataBlock.VolatileStorageSize, ecx
-
- ; Call in to the AmdS3LateRestore entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS All resume processes have been completed successfully.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_S3LATE_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdS3LateRestore
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-AmdS3LateRestoreWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdLateRunApTaskWrapper
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - D4h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - D5h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This entry point is tightly connected with the "AgesaRunFcnOnAp"
-; call out. The AGESA software will call the call-out "AgesaRunFcnOnAp";
-; the host environment will then call this entry point to have the AP
-; execute the requested function. This is needed late in the Post and
-; Resume branches for running an AP task since the AGESA software has
-; relinquished control of the APs to the host environment.
-;
-; Dependencies:
-; The host environment must implement the"AgesaRunFcnOnAp" call-out
-; and route execution to the target AP.
-;
-AmdLateRunApTaskWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdLateRunApTask
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_LATE_RUN_AP_TASK
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- push es
- mov ax, SEG AmdRunCodeOnApDataPointer
- mov es, ax
- mov eax, es:AmdRunCodeOnApDataPointer
- mov (AP_EXE_PARAMS PTR [esi]).RelatedDataBlock, eax
- mov eax, es:AmdRunCodeOnApDataSize
- mov (AP_EXE_PARAMS PTR [esi]).RelatedBlockLength, eax
- mov eax, es:AmdRunCodeOnApFunction
- mov (AP_EXE_PARAMS PTR [esi]).FunctionNumber, eax
- pop es
-
- ; Call in to the AmdLateRunApTask dispatcher
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- push es
- mov bx, SEG AmdRunCodeOnApStatus
- mov es, bx
- mov es:AmdRunCodeOnApStatus, eax
- pop es
-
- ; Allow AGESA to free the space used by AmdLateRunApTask
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-
-AmdLateRunApTaskWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdRunFuncOnAp (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E8h
-; EDX - Local APIC ID of the target core.
-; ESI - Pointer to an AP_EXE_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 FunctionNumber;
-; IN VOID *RelatedDataBlock;
-; IN UINT32 RelatedDataBlockLength;
-; } AP_EXE_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E9h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This is a required function, so this value
-; being returned causes a critical error
-; response value from the AGESAT software
-; function and no memory initialized.
-; AGESA_WARNING The AP did not respond.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of AP task dispatching.
-; This function must cause the indicated function code to be executed
-; upon the specified Application Processor. This procedure must be
-; executed in 32-bit mode. This function is required to be implemented
-; in the host environment.
-;
-; Dependencies:
-; The host environment must route execution to the target AP and
-; have that AP call the"AmdLateRunApTask" entry point.
-;
-AmdRunFuncOnAp PROC NEAR PUBLIC
-
- push es
- mov ax, SEG AmdRunCodeOnApDataPointer
- mov es, ax
- mov eax, (AP_EXE_PARAMS PTR [esi]).RelatedDataBlock
- mov es:AmdRunCodeOnApDataPointer, eax
- mov eax, (AP_EXE_PARAMS PTR [esi]).RelatedBlockLength
- mov es:AmdRunCodeOnApDataSize, eax
- mov eax, (AP_EXE_PARAMS PTR [esi]).FunctionNumber
- mov es:AmdRunCodeOnApFunction, eax
- mov eax, AGESA_UNSUPPORTED
- mov es:AmdRunCodeOnApStatus, eax
- pop es
-
- call myRunFuncOnAp
-
- push es
- mov ax, SEG AmdRunCodeOnApStatus
- mov es, ax
- mov eax, es:AmdRunCodeOnApStatus
- pop es
- ret
-AmdRunFuncOnAp ENDP
-
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCalloutRouterPost
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The call out router function for AmdInitEnv,
-; AmdInitMid, AmdInitLate, AmdS3Save, and
-; AmdS3LateRestore.
-;
-; Dependencies:
-; None
-;
-AmdCalloutRouterPost PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
- xor ax, ax
- mov ds, ax
- mov es, ax
- lea di, cs:CalloutRouterTablePost
- mov eax, AGESA_UNSUPPORTED
-
-loopThruTable:
- cmp di, OFFSET cs:CalloutRouterTablePostEnd
- jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
- cmp ecx, cs:[di].sOemCallout.FuncName
- je FoundMatch
- add di, SIZEOF sOemCallout
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemCallout.FuncPtr
- call bx
-
-amdCpuCalloutExit:
- ret
-AmdCalloutRouterPost ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the callout dispatch table for the POST segment
-;----------------------------------------------------------------------------
-
-CalloutRouterTablePost LABEL BYTE
- ;; Add entries as desired.
- sOemCallout <AGESA_ALLOCATE_BUFFER, OFFSET myAllocateBuffer>
- sOemCallout <AGESA_DEALLOCATE_BUFFER, OFFSET myDeallocateBuffer>
- sOemCallout <AGESA_LOCATE_BUFFER, OFFSET myLocateBuffer>
- sOemCallout <AGESA_RUNFUNC_ONAP, OFFSET AmdRunFuncOnAp>
-CalloutRouterTablePostEnd LABEL BYTE
-
-AMD_POST_END
-
-
-;----------------------------------------------------------------------------
-; CPU DATA SEGMENT
-; This segment must be writable, and present at the time that
-; AmdInitLate is run.
-;----------------------------------------------------------------------------
-
-CPU_DATASEG_START
-
- ;; Data used to store pointers for later use by the host environment.
- PUBLIC AmdAcpiSratPointer
- PUBLIC AmdAcpiSratSize
- PUBLIC AmdAcpiSlitPointer
- PUBLIC AmdAcpiSlitSize
- PUBLIC AmdAcpiSsdtPointer
- PUBLIC AmdAcpiSsdtSize
- PUBLIC AmdAcpiWheaMcePointer
- PUBLIC AmdAcpiWheaMceSize
- PUBLIC AmdAcpiWheaCmcPointer
- PUBLIC AmdAcpiWheaCmcSize
- PUBLIC AmdDmiInfoPointer
- AmdAcpiSratPointer DWORD ?
- AmdAcpiSratSize DWORD ?
- AmdAcpiSlitPointer DWORD ?
- AmdAcpiSlitSize DWORD ?
- AmdAcpiSsdtPointer DWORD ?
- AmdAcpiSsdtSize DWORD ?
- AmdAcpiWheaMcePointer DWORD ?
- AmdAcpiWheaMceSize DWORD ?
- AmdAcpiWheaCmcPointer DWORD ?
- AmdAcpiWheaCmcSize DWORD ?
- AmdDmiInfoPointer DWORD ?
-
- ;; Data used for communication between the AP and the BSP.
- PUBLIC AmdRunCodeOnApDataPointer
- PUBLIC AmdRunCodeOnApDataSize
- PUBLIC AmdRunCodeOnApFunction
- PUBLIC AmdRunCodeOnApStatus
- AmdRunCodeOnApDataPointer DWORD ?
- AmdRunCodeOnApDataSize DWORD ?
- AmdRunCodeOnApFunction DWORD ?
- AmdRunCodeOnApStatus DWORD ?
-
-CPU_DATASEG_END
-
-
-END
diff --git a/src/vendorcode/amd/agesa/f12/Legacy/agesa.inc b/src/vendorcode/amd/agesa/f12/Legacy/agesa.inc
deleted file mode 100644
index 9c287dcc92..0000000000
--- a/src/vendorcode/amd/agesa/f12/Legacy/agesa.inc
+++ /dev/null
@@ -1,2776 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * Agesa structures and definitions
-; *
-; * Contains AMD AGESA core interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 49979 $ @e \$Date: 2011-03-31 12:08:42 +0800 (Thu, 31 Mar 2011) $
-;
-; ****************************************************************************
-; *
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; *
-; **************************************************************************
-
-INCLUDE amd.inc
-UINT64 TEXTEQU <QWORD>
-UINT32 TEXTEQU <DWORD>
-UINT16 TEXTEQU <WORD>
-UINT8 TEXTEQU <BYTE>
-CHAR8 TEXTEQU <BYTE>
-BOOLEAN TEXTEQU <BYTE>
-POINTER TEXTEQU <DWORD>
-
- ; AGESA Types and Definitions
-
-
-
- ; AGESA BASIC CALLOUTS
- AGESA_MEM_RELEASE EQU 00028000h
-
- ; AGESA ADVANCED CALLOUTS, Processor
- AGESA_CHECK_UMA EQU 00028100h
- AGESA_DO_RESET EQU 00028101h
- AGESA_ALLOCATE_BUFFER EQU 00028102h
- AGESA_DEALLOCATE_BUFFER EQU 00028103h
- AGESA_LOCATE_BUFFER EQU 00028104h
- AGESA_RUNFUNC_ONAP EQU 00028105h
-
- ; AGESA ADVANCED CALLOUTS, HyperTransport
-
- ; AGESA ADVANCED CALLOUTS, Memory
- AGESA_READ_SPD EQU 00028140h
- AGESA_HOOKBEFORE_DRAM_INIT EQU 00028141h
- AGESA_HOOKBEFORE_DQS_TRAINING EQU 00028142h
- AGESA_READ_SPD_RECOVERY EQU 00028143h
- AGESA_HOOKBEFORE_EXIT_SELF_REF EQU 00028144h
- AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY EQU 00028145h
-
- ; AGESA IDS CALLOUTS
- AGESA_GET_IDS_INIT_DATA EQU 00028200h
-
- ; AGESA GNB CALLOUTS
- AGESA_GNB_PCIE_SLOT_RESET EQU 00028301h
-
- ; AGESA FCH CALLOUTS
- AGESA_FCH_OEM_CALLOUT EQU 00028401h
-
-; ------------------------------------------------------------------------
-
- ; HyperTransport Interface
-
-
-
-; -----------------------------------------------------------------------------
- ; HT DEFINITIONS AND MACROS
-
-; -----------------------------------------------------------------------------
-
-
- ; Width equates for call backs
- HT_WIDTH_8_BITS EQU 8
- HT_WIDTH_16_BITS EQU 16
- HT_WIDTH_4_BITS EQU 4
- HT_WIDTH_2_BITS EQU 2
- HT_WIDTH_NO_LIMIT EQU HT_WIDTH_16_BITS
-
- ; Frequency Limit equates for call backs which take a frequency supported mask.
- HT_FREQUENCY_LIMIT_200M EQU 1
- HT_FREQUENCY_LIMIT_400M EQU 7
- HT_FREQUENCY_LIMIT_600M EQU 1Fh
- HT_FREQUENCY_LIMIT_800M EQU 3Fh
- HT_FREQUENCY_LIMIT_1000M EQU 7Fh
- HT_FREQUENCY_LIMIT_HT1_ONLY EQU 7Fh
- HT_FREQUENCY_LIMIT_1200M EQU 0FFh
- HT_FREQUENCY_LIMIT_1400M EQU 1FFh
- HT_FREQUENCY_LIMIT_1600M EQU 3FFh
- HT_FREQUENCY_LIMIT_1800M EQU 7FFh
- HT_FREQUENCY_LIMIT_2000M EQU 0FFFh
- HT_FREQUENCY_LIMIT_2200M EQU 1FFFh
- HT_FREQUENCY_LIMIT_2400M EQU 3FFFh
- HT_FREQUENCY_LIMIT_2600M EQU 7FFFh
- HT_FREQUENCY_LIMIT_2800M EQU 27FFFh
- HT_FREQUENCY_LIMIT_3000M EQU 67FFFh
- HT_FREQUENCY_LIMIT_3200M EQU 0E7FFFh
- HT_FREQUENCY_LIMIT_3600M EQU 1E7FFFh
- HT_FREQUENCY_LIMIT_MAX EQU HT_FREQUENCY_LIMIT_3600M
- HT_FREQUENCY_NO_LIMIT EQU 0FFFFFFFFh
-
- ; Unit ID Clumping special values
- HT_CLUMPING_DISABLE EQU 00000000h
- HT_CLUMPING_NO_LIMIT EQU 0FFFFFFFFh
-
- HT_LIST_TERMINAL EQU 0FFh
- HT_LIST_MATCH_ANY EQU 0FEh
- HT_LIST_MATCH_INTERNAL_LINK EQU 0FDh
-
- ; Event Notify definitions
-
- ; Event definitions.
-
- ; Coherent subfunction events
- HT_EVENT_COH_EVENTS EQU 10001000h
- HT_EVENT_COH_NO_TOPOLOGY EQU 10011000h
- HT_EVENT_COH_OBSOLETE000 EQU 10021000h
- HT_EVENT_COH_PROCESSOR_TYPE_MIX EQU 10031000h
- HT_EVENT_COH_NODE_DISCOVERED EQU 10041000h
- HT_EVENT_COH_MPCAP_MISMATCH EQU 10051000h
-
- ; Non-coherent subfunction events
- HT_EVENT_NCOH_EVENTS EQU 10002000h
- HT_EVENT_NCOH_BUID_EXCEED EQU 10012000h
- HT_EVENT_NCOH_OBSOLETE000 EQU 10022000h
- HT_EVENT_NCOH_BUS_MAX_EXCEED EQU 10032000h
- HT_EVENT_NCOH_CFG_MAP_EXCEED EQU 10042000h
- HT_EVENT_NCOH_DEVICE_FAILED EQU 10052000h
- HT_EVENT_NCOH_AUTO_DEPTH EQU 10062000h
-
- ; Optimization subfunction events
- HT_EVENT_OPT_EVENTS EQU 10003000h
- HT_EVENT_OPT_REQUIRED_CAP_RETRY EQU 10013000h
- HT_EVENT_OPT_REQUIRED_CAP_GEN3 EQU 10023000h
- HT_EVENT_OPT_UNUSED_LINKS EQU 10033000h
- HT_EVENT_OPT_LINK_PAIR_EXCEED EQU 10043000h
-
- ; HW Fault events
- HT_EVENT_HW_EVENTS EQU 10004000h
- HT_EVENT_HW_SYNCFLOOD EQU 10014000h
- HT_EVENT_HW_HTCRC EQU 10024000h
-
- ; The Recovery HT component uses 0x10005000 for events.
- ; For consistency, we avoid that range here.
-
- HT_MAX_NC_BUIDS EQU 32
-; ----------------------------------------------------------------------------
- ; HT TYPEDEFS, STRUCTURES, ENUMS
-
-; ----------------------------------------------------------------------------
-MATCHED EQU 0 ; < The link matches the requested customization.
-POWERED_OFF EQU 1 ; < Power the link off.
-UNMATCHED EQU 2 ; < The link should be processed according to normal defaults.
-MaxFinalLinkState EQU 3 ; < Not a final link state, use for limit checking.
-FINAL_LINK_STATE TEXTEQU <DWORD>
-
- ; Swap a device from its current id to a new one.
-
-BUID_SWAP_ITEM STRUCT
- FromId UINT8 ? ; < The device responding to FromId,
- ToId UINT8 ? ; < will be moved to ToId.
-BUID_SWAP_ITEM ENDS
-
-
- ; Each Non-coherent chain may have a list of device swaps. After performing the swaps,
- ; the final in order list of device ids is provided. (There can be more swaps than devices.)
- ; The unused entries in both are filled with 0xFF.
-
-BUID_SWAP_LIST STRUCT
- Swaps BUID_SWAP_ITEM (HT_MAX_NC_BUIDS) DUP ({}) ; < The BUID Swaps to perform
- FinalIds UINT8 (HT_MAX_NC_BUIDS) DUP (?) ; < The ordered final BUIDs, resulting from the swaps
-BUID_SWAP_LIST ENDS
-
-
- ; Control Manual Initialization of Non-Coherent Chains
-
- ; This interface is checked every time a non-coherent chain is
- ; processed. BUID assignment may be controlled explicitly on a
- ; non-coherent chain. Provide a swap list. Swaps controls the
- ; BUID assignment and FinalIds provides the device to device
- ; Linking. Device orientation can be detected automatically, or
- ; explicitly. See interface documentation for more details.
-
- ; If a manual swap list is not supplied,
- ; automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
- ; based on each device's unit count.
-
-MANUAL_BUID_SWAP_LIST STRUCT
- ; Match fields
- Socket UINT8 ? ; < The Socket on which this chain is located
- Link UINT8 ? ; < The Link on the host for this chain
- ; Override fields
- SwapList BUID_SWAP_LIST {} ; < The swap list
-MANUAL_BUID_SWAP_LIST ENDS
-
-
- ; Override options for DEVICE_CAP_OVERRIDE.
-
- ; Specify which override actions should be performed. For Checks, 1 means to check the item
- ; and 0 means to skip the check. For the override options, 1 means to apply the override and
- ; 0 means to ignore the override.
-
-DEVICE_CAP_OVERRIDE_OPTIONS STRUCT
- IsCheckDevVenId UINT32 ?
-; IN UINT32 IsCheckDevVenId:1; ; < Check Match on Device/Vendor id
-; IN UINT32 IsCheckRevision:1; ; < Check Match on device Revision
-; IN UINT32 IsOverrideWidthIn:1; ; < Override Width In
-; IN UINT32 IsOverrideWidthOut:1; ; < Override Width Out
-; IN UINT32 IsOverrideFreq:1; ; < Override Frequency
-; IN UINT32 IsOverrideClumping:1; ; < Override Clumping
-; IN UINT32 IsDoCallout:1; ; < Make the optional callout
-DEVICE_CAP_OVERRIDE_OPTIONS ENDS
-
- ; Override capabilities of a device.
-
- ; This interface is checked once for every Link on every IO device.
- ; Provide the width and frequency capability if needed for this device.
- ; This is used along with device capabilities, the limit interfaces, and northbridge
- ; limits to compute the default settings. The components of the device's PCI config
- ; address are provided, so its settings can be consulted if need be.
- ; The optional callout is a catch all.
-
-DEVICE_CAP_OVERRIDE STRUCT
- ; Match fields
- HostSocket UINT8 ? ; < The Socket on which this chain is located.
- HostLink UINT8 ? ; < The Link on the host for this chain.
- Depth UINT8 ? ; < The Depth in the I/O chain from the Host.
- DevVenId UINT32 ? ; < The Device's PCI Vendor + Device ID (offset 0x00).
- Revision UINT8 ? ; < The Device's PCI Revision field (offset 0x08).
- Link UINT8 ? ; < The Device's Link number (0 or 1).
- Options DEVICE_CAP_OVERRIDE_OPTIONS {} ; < The options for this device override.
- ; Override fields
- LinkWidthIn UINT8 ? ; < modify to change the Link Width In.
- LinkWidthOut UINT8 ? ; < modify to change the Link Width Out.
- FreqCap UINT32 ? ; < modify to change the Link's frequency capability.
- Clumping UINT32 ? ; < modify to change Unit ID clumping support.
- Callout CALLOUT_ENTRY ? ; < optional call for really complex cases, or NULL.
-DEVICE_CAP_OVERRIDE ENDS
-
- ; Callout param struct for override capabilities of a device.
-
- ; If the optional callout is implemented this param struct is passed to it.
-
-DEVICE_CAP_CALLOUT_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < The header
- ; Match fields
- HostSocket UINT8 ? ; < The Socket on which this chain is located.
- HostLink UINT8 ? ; < The Link on the host for this chain.
- Depth UINT8 ? ; < The Depth in the I/O chain from the Host.
- DevVenId UINT32 ? ; < The Device's PCI Vendor + Device ID (offset 0x00).
- Revision UINT8 ? ; < The Device's PCI Revision field (offset 0x08).
- Link UINT8 ? ; < The Device's Link number (0 or 1).
- PciAddress PCI_ADDR {} ; < The Device's PCI Address.
- ; Override fields
- LinkWidthIn POINTER ? ; < modify to change the Link Width In.
- LinkWidthOut POINTER ? ; < modify to change the Link Width Out.
- FreqCap POINTER ? ; < modify to change the Link's frequency capability.
- Clumping POINTER ? ; < modify to change Unit ID clumping support.
-DEVICE_CAP_CALLOUT_PARAMS ENDS
-
- ; Limits for CPU to CPU Links.
-
- ; For each coherent connection this interface is checked once.
- ; Provide the frequency and width if needed for this Link (usually based on board
- ; restriction). This is used with CPU device capabilities and northbridge limits
- ; to compute the default settings.
-
-CPU_TO_CPU_PCB_LIMITS STRUCT
- ; Match fields
- SocketA UINT8 ? ; < One Socket on which this Link is located
- LinkA UINT8 ? ; < The Link on this Node
- SocketB UINT8 ? ; < The other Socket on which this Link is located
- LinkB UINT8 ? ; < The Link on that Node
- ; Limit fields
- ABLinkWidthLimit UINT8 ? ; < modify to change the Link Width A->B
- BALinkWidthLimit UINT8 ? ; < modify to change the Link Width B-<A
- PcbFreqCap UINT32 ? ; < modify to change the Link's frequency capability
-CPU_TO_CPU_PCB_LIMITS ENDS
-
- ; Get limits for non-coherent Links.
-
- ; For each non-coherent connection this interface is checked once.
- ; Provide the frequency and width if needed for this Link (usually based on board
- ; restriction). This is used with device capabilities, device overrides, and northbridge limits
- ; to compute the default settings.
-
-IO_PCB_LIMITS STRUCT
- ; Match fields
- HostSocket UINT8 ? ; < The Socket on which this Link is located
- HostLink UINT8 ? ; < The Link about to be initialized
- Depth UINT8 ? ; < The Depth in the I/O chain from the Host
- ; Limit fields
- DownstreamLinkWidthLimit UINT8 ? ; < modify to change the Link Width going away from processor
- UpstreamLinkWidthLimit UINT8 ? ; < modify to change the Link Width moving toward processor
- PcbFreqCap UINT32 ? ; < modify to change the Link's frequency capability
-IO_PCB_LIMITS ENDS
-
- ; Manually control bus number assignment.
-
- ; This interface is checked every time a non-coherent chain is processed.
- ; If a system can not use the auto Bus numbering feature for non-coherent chain bus
- ; assignments, this interface can provide explicit control. For each chain, provide
- ; the bus number range to use.
-
-OVERRIDE_BUS_NUMBERS STRUCT
- ; Match fields
- Socket UINT8 ? ; < The Socket on which this chain is located
- Link UINT8 ? ; < The Link on the host for this chain
- ; Override fields
- SecBus UINT8 ? ; < Secondary Bus number for this non-coherent chain
- SubBus UINT8 ? ; < Subordinate Bus number
-OVERRIDE_BUS_NUMBERS ENDS
-
-
- ; Ignore a Link.
-
- ; This interface is checked every time a coherent Link is found and then every
- ; time a non-coherent Link from a CPU is found.
- ; Any coherent or non-coherent Link from a CPU can be ignored and not used
- ; for discovery or initialization. Useful for connection based systems.
- ; (Note: not checked for IO device to IO Device Links.)
-
-IGNORE_LINK STRUCT
- ; Match fields
- Socket UINT8 ? ; < The Socket on which this Link is located
- Link UINT8 ? ; < The Link about to be initialized
- ; Customization fields
- LinkState FINAL_LINK_STATE ? ; < The link may be left unitialized, or powered off.
-IGNORE_LINK ENDS
-
-
- ; Skip reganging of subLinks.
-
- ; This interface is checked whenever two subLinks are both connected to the same CPUs.
- ; Normally, unganged sublinks between the same two CPUs are reganged.
- ; Provide a matching structure to leave the Links unganged.
-
-SKIP_REGANG STRUCT
- ; Match fields
- SocketA UINT8 ? ; < One Socket on which this Link is located
- LinkA UINT8 ? ; < The Link on this Node
- SocketB UINT8 ? ; < The other Socket on which this Link is located
- LinkB UINT8 ? ; < The Link on that Node
- ; Customization fields
- LinkState FINAL_LINK_STATE ? ; < The paired sublink may be active, or powered off.
-SKIP_REGANG ENDS
-
- ; The System Socket layout, which sockets are physically connected.
-
- ; The hardware method for Socket naming is preferred. Use this software method only
- ; if required.
-
-SYSTEM_PHYSICAL_SOCKET_MAP STRUCT
- CurrentSocket UINT8 ? ; < The socket from which this connection originates.
- CurrentLink UINT8 ? ; < The Link from the source socket connects to another socket.
- TargetSocket UINT8 ? ; < The target socket which is connected on that link.
-SYSTEM_PHYSICAL_SOCKET_MAP ENDS
-
-; ----------------------------------------------------------------------------
-
- ; This is the input structure for AmdHtInitialize.
-
-AMD_HT_INTERFACE STRUCT
- ; Basic level customization
- AutoBusStart UINT8 ? ; < For automatic bus number assignment, starting bus number usually zero.
- AutoBusMax UINT8 ? ; < For automatic bus number assignment, do not assign above max.
- AutoBusIncrement UINT8 ? ; < For automatic bus number assignment, each chain gets this many busses.
-
- ; Advanced Level Customization
- ManualBuidSwapList POINTER ? ; < Provide Manual Swap List, if any.
- DeviceCapOverrideList POINTER ? ; < Provide Device Overrides, if any.
- CpuToCpuPcbLimitsList POINTER ? ; < Provide CPU PCB Limits, if any.
- IoPcbLimitsList POINTER ? ; < Provide IO PCB Limits, if any.
- OverrideBusNumbersList POINTER ? ; < Provide manual Bus Number assignment, if any.
- ; < Use either auto bus numbering or override bus
- ; < numbers, not both.
-
- IgnoreLinkList POINTER ? ; < Provide links to ignore, if any.
- SkipRegangList POINTER ? ; < Provide links to remain unganged, if any.
-
- ; Expert Level Customization
- Topolist POINTER ? ; < Use this topology list in addition to the built in, if not NULL.
- SystemPhysicalSocketMap POINTER ?
- ; < The hardware socket naming method is preferred,
- ; < If it can't be used, this provides a software method.
-AMD_HT_INTERFACE ENDS
-
-; -----------------------------------------------------------------------------
-
- ; HT Recovery Interface
-
-
-
-; -----------------------------------------------------------------------------
-; * HT Recovery DEFINITIONS AND MACROS
-; *
-; *-----------------------------------------------------------------------------
-;
-
- ; BBHT subfunction events
- HT_EVENT_BB_EVENTS EQU 10005000h
- HT_EVENT_BB_BUID_EXCEED EQU 10015000h
- HT_EVENT_BB_DEVICE_FAILED EQU 10055000h
- HT_EVENT_BB_AUTO_DEPTH EQU 10065000h
-
-; ----------------------------------------------------------------------------
-; * HT Recovery TYPEDEFS, STRUCTURES, ENUMS
-; *
-; *----------------------------------------------------------------------------
-;
-
-
- ; The Interface structure to Recovery HT.
-
-AMD_HT_RESET_INTERFACE STRUCT
- ManualBuidSwapList POINTER ? ; < Option to manually control SB link init
- Depth UINT32 ? ; < If auto init was used this is set to the depth of the chain,
- ; < else, for manual init unmodified.
-AMD_HT_RESET_INTERFACE ENDS
-
-
-;-----------------------------------------------------------------------------
-; FCH DEFINITIONS AND MACROS
-;
-;-----------------------------------------------------------------------------
-
-; Configuration values for SdConfig
- SdDisable EQU 0 ; Disabled
- SdAmda EQU 1 ; AMDA, set 24,18,16, default
- SdDma EQU 2 ; DMA clear 24, 16, set 18
- SdPio EQU 3 ; PIO clear 24,18,16
-SD_MODE TEXTEQU <DWORD>
-
-; Configuration values for AzaliaController
- AzAuto EQU 0 ; Auto - Detect Azalia controller automatically
- AzDisable EQU 1 ; Diable - Disable Azalia controller
- AzEnable EQU 2 ; Enable - Enable Azalia controller
-HDA_CONFIG TEXTEQU <DWORD>
-
-; Configuration values for IrConfig
- IrDisable EQU 0 ; Disable
- IrRxTx0 EQU 1 ; Rx and Tx0
- IrRxTx1 EQU 2 ; Rx and Tx1
- IrRxTx0Tx1 EQU 3 ; Rx and both Tx0,Tx1
-IR_CONFIG TEXTEQU <DWORD>
-
-; Configuration values for SataClass
- SataNativeIde EQU 0 ; Native IDE mode
- SataRaid EQU 1 ; RAID mode
- SataAhci EQU 2 ; AHCI mode
- SataLegacyIde EQU 3 ; Legacy IDE mode
- SataIde2Ahci EQU 4 ; IDE->AHCI mode
- SataAhci7804 EQU 5 ; AHCI mode as 7804 ID (AMD driver)
- SataIde2Ahci7804 EQU 6 ; IDE->AHCI mode as 7804 ID (AMD driver)
-SATA_CLASS TEXTEQU <DWORD>
-
-; Configuration values for GppLinkConfig
- PortA4 EQU 0 ; 4:0:0:0
- PortA2B2 EQU 2 ; 2:2:0:0
- PortA2B1C1 EQU 3 ; 2:1:1:0
- PortA1B1C1D1 EQU 4 ; 1:1:1:1
-GPP_LINKMODE TEXTEQU <DWORD>
-
-; Configuration values for FchPowerFail
- AlwaysOff EQU 0 ; Always power off after power resumes
- AlwaysOn EQU 1 ; Always power on after power resumes
- UsePrevious EQU 3 ; Resume to same setting when power fails
-POWER_FAIL TEXTEQU <DWORD>
-
-;
-; FCH Component Data Structure in InitReset stage
-;
-FCH_RESET_INTERFACE STRUCT
- UmiGen2 BOOLEAN ? ; Enable Gen2 data rate of UMI
- ; FALSE - Disable Gen2
- ; TRUE - Enable Gen2
-
- SataEnable BOOLEAN ? ; SATA controller function
- ; FALSE - SATA controller is disabled
- ; TRUE - SATA controller is enabled
-
- IdeEnable BOOLEAN ? ; SATA IDE controller mode enabled/disabled
- ; FALSE - IDE controller is disabled
- ; TRUE - IDE controller is enabled
-
- GppEnable BOOLEAN ? ; Master switch of GPP function
-FCH_RESET_INTERFACE ENDS
-
-
-;
-; FCH Component Data Structure from InitEnv stage
-;
-FCH_INTERFACE STRUCT
- SdConfig SD_MODE ? ; Secure Digital (SD) controller mode
- AzaliaController HDA_CONFIG ? ; Azalia HD Audio Controller
- IrConfig IR_CONFIG ? ; Infrared (IR) Configuration
- UmiGen2 BOOLEAN ? ; Enable Gen2 data rate of UMI
- ; FALSE - Disable Gen2
- ; TRUE - Enable Gen2
- SataClass SATA_CLASS ? ; SATA controller mode
- SataEnable BOOLEAN ? ; SATA controller function
- ; FALSE - SATA controller is disabled
- ; TRUE - SATA controller is enabled
- IdeEnable BOOLEAN ? ; SATA IDE controller mode enabled/disabled
- ; FALSE - IDE controller is disabled
- ; TRUE - IDE controller is enabled
- SataIdeMode BOOLEAN ? ; Native mode of SATA IDE controller
- ; FALSE - Legacy IDE mode
- ; TRUE - Native IDE mode
- Ohci1Enable BOOLEAN ? ; OHCI controller #1 Function
- ; FALSE - OHCI1 is disabled
- ; TRUE - OHCI1 is enabled
- Ohci2Enable BOOLEAN ? ; OHCI controller #2 Function
- ; FALSE - OHCI2 is disabled
- ; TRUE - OHCI2 is enabled
- Ohci3Enable BOOLEAN ? ; OHCI controller #3 Function
- ; FALSE - OHCI3 is disabled
- ; TRUE - OHCI3 is enabled
- Ohci4Enable BOOLEAN ? ; OHCI controller #4 Function
- ; FALSE - OHCI4 is disabled
- ; TRUE - OHCI4 is enabled
- XhciSwitch BOOLEAN ? ; XHCI controller Function
- ; FALSE - XHCI is disabled
- ; TRUE - XHCI is enabled
- GppEnable BOOLEAN ? ; Master switch of GPP function
- FchPowerFail POWER_FAIL ? ; FCH power failure option
-FCH_INTERFACE ENDS
-
-
-; ---------------------------------------------------------------------------
-; CPU Feature related info
-; ---------------------------------------------------------------------------
- ; Build Configuration values for BLDCFG_PLATFORM_C1E_MODE
- C1eModeDisabled EQU 0 ; < Disabled
- C1eModeAuto EQU 1 ; < Auto mode enables the best C1e method for the
- ; < currently installed processor
- C1eModeHardware EQU 2 ; < Hardware method
- C1eModeMsgBased EQU 3 ; < Message-based method
- C1eModeSoftwareDeprecated EQU 4 ; < Deprecated software SMI method
- C1eModeHardwareSoftwareDeprecated EQU 5 ; < Hardware or Deprecated software SMI method
- MaxC1eMode EQU 6 ; < Not a valid value, used for verifying input
-PLATFORM_C1E_MODES TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
- CStateModeDisabled EQU 0 ; < Disabled
- CStateModeC6 EQU 1 ; < C6 State
- MaxCStateMode EQU 2 ; < Not a valid value, used for verifying input
-PLATFORM_CSTATE_MODES TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_PLATFORM_CPB_MODE
- CpbModeAuto EQU 0 ; < Auto
- CpbModeDisabled EQU 1 ; < Disabled
- MaxCpbMode EQU 2 ; < Not a valid value, used for verifying input
-PLATFORM_CPB_MODES TEXTEQU <DWORD>
-
-
-;----------------------------------------------------------------------------
-; GNB PCIe configuration info
-;----------------------------------------------------------------------------
-
-GNB_EVENT_INVALID_CONFIGURATION EQU 20010000h ; User configuration invalid
-GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION EQU 20010001h ; Requested lane allocation for PCIe port can not be supported
-GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION EQU 20010002h ; Requested incorrect PCIe port device address
-GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION EQU 20010003h ; Incorrect parameter in DDI link configuration
-GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION EQU 20010004h ; Invalid with for PCIe port or DDI link
-GNB_EVENT_INVALID_LANES_CONFIGURATION EQU 20010005h ; Lane double subscribe lanes
-GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION EQU 20010006h ; Requested lane allocation for DDI link(s) can not be supported
-GNB_EVENT_LINK_TRAINING_FAIL EQU 20020000h ; PCIe Link training fail
-GNB_EVENT_BROKEN_LANE_RECOVERY EQU 20030000h ; Broken lane workaround applied to recover link training
-GNB_EVENT_GEN2_SUPPORT_RECOVERY EQU 20040000h ; Scale back to GEN1 to recover link training
-
-DESCRIPTOR_TERMINATE_LIST EQU 80000000h
-
-PCIe_PORT_MISC_CONTROL STRUCT
- LinkComplianceMode UINT8 ?
- ;IN UINT8 LinkComplianceMode :1; ;< Force port into compliance mode (device will not be trained, port output compliance pattern)
-PCIe_PORT_MISC_CONTROL ENDS
-
-PCIe_PORT_DATA STRUCT
- PortPresent UINT8 ? ; < Enable PCIe port for initialization.
- ChannelType UINT8 ? ; < Channel type.
- ; 0 - "lowLoss",
- ; 1 - "highLoss",
- ; 2 - "mob0db",
- ; 3 - "mob3db",
- ; 4 - "extnd6db"
- ; 5 - "extnd8db"
- ;
- DeviceNumber UINT8 ? ; < Device number for port. Available device numbers may very on different CPUs.
- FunctionNumber UINT8 ? ; < Reserved for future use
- LinkSpeedCapability UINT8 ? ; < Advertised Gen Capability
- ; 0 - Maximum supported by silicon
- ; 1 - Gen1
- ; 2 - Gen2
- ; 3 - Gen3
- ;
- LinkAspm UINT8 ? ; < ASPM control. (see OemPcieLinkAspm for additional option to control ASPM)
- ; 0 - Disabled
- ; 1 - L0s only
- ; 2 - L1 only
- ; 2 - L0s and L1
- ;
- LinkHotplug UINT8 ? ; < Hotplug control.
- ; 0 - Disabled
- ; 1 - Basic
- ; 2 - Server
- ; 3 - Enhanced
- ;
- ResetId UINT8 ? ; < Arbitrary number greater than 0 assigned by platform firmware for GPIO
- ; identification which control reset for given port.
- ; Each port with unique GPIO should have unique ResetId assigned.
- ; All ports use same GPIO to control reset should have same ResetId assigned.
- ; see AgesaPcieSlotResetControl
- ;
- MiscControls PCIe_PORT_MISC_CONTROL {} ; < Misc extended controls
-PCIe_PORT_DATA ENDS
-
-;DDI channel lane mapping
-
-CHANNEL_MAPPING STRUCT ;
- Lane0 UINT8 ? ;
- ;IN UINT8 Lane0 :2; ;
- ;IN UINT8 Lane1 :2; ///< Lane 1 mapping (see "Lane 0 mapping")
- ;IN UINT8 Lane2 :2; ///< Lane 2 mapping (see "Lane 0 mapping")
- ;IN UINT8 Lane3 :2; ///< Lane 3 mapping (see "Lane 0 mapping")
-CHANNEL_MAPPING ENDS ;
-
-CONN_CHANNEL_MAPPING UNION
- ChannelMappingValue UINT8 ? ; < Raw lane mapping
- ChannelMapping CHANNEL_MAPPING {} ;
-CONN_CHANNEL_MAPPING ENDS ;
-
-; DDI Configuration
-PCIe_DDI_DATA STRUCT
- ConnectorType UINT8 ? ; < Display Connector Type
- ; 0 - DP
- ; 1 - eDP
- ; 2 - Single Link DVI
- ; 3 - Dual Link DVI
- ; 4 - HDMI
- ; 5 - Travis DP-to-VGA
- ; 6 - Travis DP-to-LVDS
- ; 7 - Hudson-2 NutMeg DP-to-VGA
- ; 8 - Single Link DVI-I
- ; 9 - CRT (VGA)
- ; 10 - LVDS
- ; 11 - VBIOS auto detect connector type
- AuxIndex UINT8 ? ; < Indicates which AUX or DDC Line is used
- ; 0 - AUX1
- ; 1 - AUX2
- ; 2 - AUX3
- ; 3 - AUX4
- ; 4 - AUX5
- ; 5 - AUX6
- ;
- HdpIndex UINT8 ? ; < Indicates which HDP pin is used
- ; 0 - HDP1
- ; 1 - HDP2
- ; 2 - HDP3
- ; 3 - HDP4
- ; 4 - HDP5
- ; 5 - HDP6
- Mapping CONN_CHANNEL_MAPPING (2) DUP ({}) ;< Set specific mapping of lanes to connector pins
- ;Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane
- ;Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only
- ;applicable for Dual DDI link)
- ;if Mapping[x] set to 0 than default mapping assumed
- LanePnInversionMask UINT8 ? ; < Specifies whether to invert the state of P and N for each lane. Each bit represents a PCIe lane on the DDI port
- ; 0 - Do not invert (default)
- ; 1 - Invert P and N on this lane
-PCIe_DDI_DATA ENDS
-
-
-; Engine Configuration
-PCIe_ENGINE_DATA STRUCT
- EngineType UINT8 ? ; < Engine type
- ; 0 - Ignore engine configuration
- ; 1 - PCIe port
- ; 2 - DDI
- StartLane UINT16 ? ; < Start lane number (in reversed configuration StartLane > EndLane).
- EndLane UINT16 ? ; < End lane number (in reversed configuration StartLane > EndLane).
-PCIe_ENGINE_DATA ENDS
-
-; PCIe port descriptor
-PCIe_PORT_DESCRIPTOR STRUCT
- Flags UINT32 ? ; < Descriptor flags
- ; Bit31 - last descriptor in complex
- EngineData PCIe_ENGINE_DATA {} ; < Engine data
- Port PCIe_PORT_DATA {} ; < PCIe port specific configuration info
-PCIe_PORT_DESCRIPTOR ENDS
-
-; DDI descriptor
-PCIe_DDI_DESCRIPTOR STRUCT
- Flags UINT32 ? ; < Descriptor flags
- EngineData PCIe_ENGINE_DATA {} ; < Engine data
- Ddi PCIe_DDI_DATA {} ; < DDI port specific configuration info
-PCIe_DDI_DESCRIPTOR ENDS
-
-; Slot Reset Info
-PCIe_SLOT_RESET_INFO STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < AGESA Standard Header
- ResetId UINT8 ? ; < Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
- ResetControl UINT8 ? ; < Reset control as defined by PCIE_RESET_CONTROL
-PCIe_SLOT_RESET_INFO ENDS
-
-
-; PCIe Complex descriptor
-PCIe_COMPLEX_DESCRIPTOR STRUCT
- Flags UINT32 ? ; < Descriptor flags
- ; Bit31 - last descriptor in topology
- ;
- ;
- SocketId UINT32 ? ; < Socket Id
- PciePortList POINTER ? ;< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
- DdiLinkList POINTER ? ;< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
- Reserved POINTER ? ;< Reserved for future use
-PCIe_COMPLEX_DESCRIPTOR ENDS
-
- AssertSlotReset EQU 0
- DeassertSlotReset EQU 1
-PCIE_RESET_CONTROL TEXTEQU <DWORD>
-
- PcieUnusedEngine EQU 0
- PciePortEngine EQU 1
- PcieDdiEngine EQU 2
- MaxPcieEngine EQU 3 ; < Not a valid value, used for verifying input
-PCIE_ENGINE_TYPE TEXTEQU <DWORD>
-
- PcieGenMaxSupported EQU 0
- PcieGen1 EQU 1
- PcieGen2 EQU 2
- MaxPcieGen EQU 3 ; < Not a valid value, used for verifying input
-PCIE_LINK_SPEED_CAP TEXTEQU <DWORD>
-
- PsppDisabled EQU 0
- PsppPerformance EQU 1
- PsppBalanceHigh EQU 2
- PsppBalanceLow EQU 3
- PsppPowerSaving EQU 4
- MaxPspp EQU 5 ; < Not a valid value, used for verifying input
-PCIE_PSPP_POLICY TEXTEQU <DWORD>
-
- ConnectorTypeDP EQU 0
- ConnectorTypeEDP EQU 1
- ConnectorTypeSingleLinkDVI EQU 2
- ConnectorTypeDualLinkDVI EQU 3
- ConnectorTypeHDMI EQU 4
- ConnectorTypeTravisDpToVga EQU 5
- ConnectorTypeTravisDpToLvds EQU 6
- ConnectorTypeNutmegDpToVga EQU 7
- ConnectorTypeSingleLinkDviI EQU 8
- ConnectorTypeCrt EQU 9
- ConnectorTypeLvds EQU 10
- ConnectorTypeAutoDetect EQU 11
- MaxConnectorType EQU 12 ; < Not a valid value, used for verifying input
-PCIE_CONNECTOR_TYPE TEXTEQU <DWORD>
-
- ChannelTypeLowLoss EQU 0
- ChannelTypeHighLoss EQU 1
- ChannelTypeMob0db EQU 2
- ChannelTypeMob3db EQU 3
- ChannelTypeExt6db EQU 4
- ChannelTypeExt8db EQU 5
- MaxChannelType EQU 6 ; < Not a valid value, used for verifying input
-PCIE_CHANNEL_TYPE TEXTEQU <DWORD>
-
- AspmDisabled EQU 0
- AspmL0s EQU 1
- AspmL1 EQU 2
- AspmL0sL1 EQU 3
- MaxAspm EQU 4 ; < Not a valid value, used for verifying input
-PCIE_ASPM_TYPE TEXTEQU <DWORD>
-
- HotplugDisabled EQU 0
- HotplugBasic EQU 1
- HotplugServer EQU 2
- HotplugEnhanced EQU 3
- HotplugInboard EQU 4
- MaxHotplug EQU 5 ; < Not a valid value, used for verifying input
-PCIE_HOTPLUG_TYPE TEXTEQU <DWORD>
-
- PortDisabled EQU 0
- PortEnabled EQU 1
-PCIE_PORT_ENABLE TEXTEQU <DWORD>
-
- Aux1 EQU 0
- Aux2 EQU 1
- Aux3 EQU 2
- Aux4 EQU 3
- Aux5 EQU 4
- Aux6 EQU 5
- MaxAux EQU 6 ; < Not a valid value, used for verifying input
-PCIE_AUX_TYPE TEXTEQU <DWORD>
-
- Hdp1 EQU 0
- Hdp2 EQU 1
- Hdp3 EQU 2
- Hdp4 EQU 3
- Hdp5 EQU 4
- Hdp6 EQU 5
- MaxHdp EQU 6 ; < Not a valid value, used for verifying input
-PCIE_HDP_TYPE TEXTEQU <DWORD>
-
-
-;IOMMU requestor ID
-IOMMU_REQUESTOR_ID STRUCT
- Bus UINT16 ? ; <[15:8] - Bus number, [7:3] - Device number, [2:0] - Function number
-IOMMU_REQUESTOR_ID ENDS
-
-;IVMD exclusion range descriptor
-IOMMU_EXCLUSION_RANGE_DESCRIPTOR STRUCT
- Flags UINT32 ? ; Descriptor flags
- ; @li @b Flags[31] - Terminate descriptor array.
- ; @li @b Flags[30] - Ignore descriptor.
- ; @li @b Flags[0] - Range applies for all requestor IDs.
- RequestorId IOMMU_REQUESTOR_ID {} ; Requestor ID
- RangeBaseAddress UINT64 ? ; Phisical base address of exclusion range
- RangeLength UINT64 ? ; Length of exclusion range in bytes
-IOMMU_EXCLUSION_RANGE_DESCRIPTOR ENDS
-;----------------------------------------------------------------------------
-; GNB configuration info
-;----------------------------------------------------------------------------
-;
-
-; Configuration settings for GNB.
-GNB_ENV_CONFIGURATION STRUCT
- Gnb3dStereoPinIndex UINT8 ? ;< 3D Stereo Pin ID.
- ; @li 0 = Stereo 3D is disabled (default).
- ; @li 1 = Use processor pin HPD1.
- ; @li 2 = Use processor pin HPD2
- ; @li 3 = Use processor pin HPD3
- ; @li 4 = Use processor pin HPD4
- ; @li 5 = Use processor pin HPD5
- ; @li 6 = Use processor pin HPD6
- IommuSupport BOOLEAN ? ; IOMMU support.
- ; TRUE = Disable and hide IOMMU device.
- ; FLASE = Initialize IOMMU subsystem. Generate ACPI IVRS table.
- LvdsSpreadSpectrum UINT16 ? ; Spread spectrum value in 0.01 %
- LvdsSpreadSpectrumRate UINT16 ? ; Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
- LvdsPowerOnSeqDigonToDe UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqDeToVaryBl UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqDeToDigon UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqVaryBlToDe UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqOnToOffDelay UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqVaryBlToBlon UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqBlonToVaryBl UINT8 ? ; This item configures panel initialization timing.
- LvdsMaxPixelClockFreq UINT16 ? ; This item configures the maximum pixel clock frequency supported.
- LcdBitDepthControlValue UINT32 ? ; This item configures the LCD bit depth control settings.
- Lvds24bbpPanelMode UINT8 ? ; This item configures the LVDS 24 BBP mode.
- PcieRefClkSpreadSpectrum UINT16 ? ; Spread spectrum value in 0.01 %
-GNB_ENV_CONFIGURATION ENDS
-
-; GNB configuration info
-GNB_CONFIGURATION STRUCT
- PcieComplexList POINTER ? ; Pointer to array of PCIe_COMPLEX_DESCRIPTOR structures describe PCIe topology on each processor package or NULL.
- ; Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST
- ;
- ;
- ;
- ; Topology organization definition assume PCIe_COMPLEX_DESCRIPTOR defined first following
- ; PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR for given PCIe_COMPLEX_DESCRIPTOR
- ; defined in arbitrary sequence:
- ; Example of topology definition for single socket system:
- ; PlatfromTopology LABEL DWORD
- ;
- ; Port0_2 PCIe_PORT_DESCRIPTOR <>;
- ; Port0_3 PCIe_PORT_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST> ;
- ; ...
- ; Ddi0_A PCIe_DDI_DESCRIPTOR <>;
- ; Ddi0_B PCIe_DDI_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST,>;
- ; ...
- ; Cpu0 PCIe_COMPLEX_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST, 0, Port0_2, Ddi0_A>
- ;
- ;
- PsppPolicy UINT8 ? ;< PSPP (PCIe Speed Power Policy)
- ; @li @b 0 - Disabled
- ; @li @b 1 - Performance
- ; @li @b 2 - Balance-High
- ; @li @b 3 - Balance-Low
- ; @li @b 4 - Power Saving
- ;
-GNB_CONFIGURATION ENDS
-
-
-; ---------------------------------------------------------------------------
-
-; MEMORY-SPECIFIC DATA STRUCTURES
-
-; ---------------------------------------------------------------------------
-
-
- ; AGESA MAXIMIUM VALUES
-
- ; These Max values are used to define array sizes and associated loop
- ; counts in the code. They reflect the maximum values that AGESA
- ; currently supports and does not necessarily reflect the hardware
- ; capabilities of configuration.
-
-
- MAX_SOCKETS_SUPPORTED EQU 8 ; < Max number of sockets in system
- MAX_CHANNELS_PER_SOCKET EQU 4 ; < Max Channels per sockets
- MAX_DIMMS_PER_CHANNEL EQU 4 ; < Max DIMMs on a memory channel (independent of platform)
- NUMBER_OF_DELAY_TABLES EQU 9 ; < Number of tables defined in CH_DEF_STRUCT.
- ; < Eg: UINT16 *RcvEnDlys;
- ; < UINT8 *WrDqsDlys;
- ; < UINT8 *RdDqsDlys;
- ; < UINT8 *WrDatDlys;
- ; < UINT8 *RdDqsMinDlys;
- ; < UINT8 *RdDqsMaxDlys;
- ; < UINT8 *WrDatMinDlys;
- ; < UINT8 *WrDatMaxDlys;
- NUMBER_OF_FAILURE_MASK_TABLES EQU 1 ; < Number of failure mask tables
- MAX_PLATFORM_TYPES EQU 16 ; < Platform types per system
-
- MCT_TRNG_KEEPOUT_START EQU 00004000h ; < base [39:8]
- MCT_TRNG_KEEPOUT_END EQU 00007FFFh ; < base [39:8]
-
- UMA_ATTRIBUTE_INTERLEAVE EQU 80000000h ; < Uma Region is interleaved
- UMA_ATTRIBUTE_ON_DCT0 EQU 40000000h ; < UMA resides on memory that belongs to DCT0
- UMA_ATTRIBUTE_ON_DCT1 EQU 20000000h ; < UMA resides on memory that belongs to DCT1
-
- PSO_TABLE TEXTEQU <UINT8>; < Platform Configuration Table
-
- ; AGESA DEFINITIONS
-
- ; Many of these are derived from the platform and hardware specific definitions
-
- ; EccSymbolSize override value
- ECCSYMBOLSIZE_USE_BKDG EQU 0 ; < Use BKDG Recommended Value
- ECCSYMBOLSIZE_FORCE_X4 EQU 4 ; < Force to x4
- ECCSYMBOLSIZE_FORCE_X8 EQU 8 ; < Force to x8
- ; CPU Package Type
- PT_L1 EQU 0 ; < L1 Package type
- PT_M2 EQU 1 ; < AM Package type
- PT_S1 EQU 2 ; < S1 Package type
-
- ; Structures use to pass system Logical CPU-ID
-CPU_LOGICAL_ID STRUCT
- Family UINT64 ? ; < Indicates logical ID Family
- Revision UINT64 ? ; < Indicates logical ID Family
-CPU_LOGICAL_ID ENDS
-
- ; Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
-
- AMD_PLATFORM_SERVER EQU 8000h ; < Server
- AMD_PLATFORM_DESKTOP EQU 10000h ; < Desktop
- AMD_PLATFORM_MOBILE EQU 20000h ; < Mobile
-AMD_PLATFORM_TYPE TEXTEQU <DWORD>
-
- ; Dram technology type
-
- DDR2_TECHNOLOGY EQU 0 ; < DDR2 technology
- DDR3_TECHNOLOGY EQU 1 ; < DDR3 technology
-TECHNOLOGY_TYPE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
-
- DDR400_FREQUENCY EQU 200 ; < DDR 400
- DDR533_FREQUENCY EQU 266 ; < DDR 533
- DDR667_FREQUENCY EQU 333 ; < DDR 667
- DDR800_FREQUENCY EQU 400 ; < DDR 800
- DDR1066_FREQUENCY EQU 533 ; < DDR 1066
- DDR1333_FREQUENCY EQU 667 ; < DDR 1333
- DDR1600_FREQUENCY EQU 800 ; < DDR 1600
- DDR1866_FREQUENCY EQU 933 ; < DDR 1866
- DDR2100_FREQUENCY EQU 1050 ; < DDR 2100
- DDR2133_FREQUENCY EQU 1066 ; < DDR 2133
- DDR2400_FREQUENCY EQU 1200 ; < DDR 2400
- UNSUPPORTED_DDR_FREQUENCY EQU 1201 ; < Highest limit of DDR frequency
-MEMORY_BUS_SPEED TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
-
- QUADRANK_REGISTERED EQU 0
- QUADRANK_UNBUFFERED EQU 1
-QUANDRANK_TYPE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_TIMING_MODE_SELECT
-
- TIMING_MODE_AUTO EQU 0 ; < Use best rate possible
- TIMING_MODE_LIMITED EQU 1 ; < Set user top limit
- TIMING_MODE_SPECIFIC EQU 2 ; < Set user specified speed
-USER_MEMORY_TIMING_MODE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_POWER_DOWN_MODE
-
- POWER_DOWN_BY_CHANNEL EQU 0
- POWER_DOWN_BY_CHIP_SELECT EQU 1
- POWER_DOWN_AUTO EQU 2
-POWER_DOWN_MODE TEXTEQU <DWORD>
-
- ; Low voltage support
-
- VOLT_INITIAL EQU 0 ; < Initial value for VDDIO
- VOLT1_5 EQU 1 ; < 1.5 Volt
- VOLT1_35 EQU 2 ; < 1.35 Volt
- VOLT1_25 EQU 3 ; < 1.25 Volt
- VOLT_UNSUPPORTED EQU 0xFF ; < No common voltage found
-DIMM_VOLTAGE TEXTEQU <DWORD>
-
- ; UMA Mode
-
- UMA_NONE EQU 0 ; < UMA None
- UMA_SPECIFIED EQU 1 ; < UMA Specified
- UMA_AUTO EQU 2 ; < UMA Auto
-UMA_MODE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_UMA_ALIGNMENT
-
- NO_UMA_ALIGNED EQU 00FFFFFFh
- UMA_4MB_ALIGNED EQU 00FFFFC0h
- UMA_128MB_ALIGNED EQU 00FFF800h
- UMA_256MB_ALIGNED EQU 00FFF000h
- UMA_512MB_ALIGNED EQU 00FFE000h
-UMA_ALIGNMENT TEXTEQU <DWORD>
- ; ===============================================================================
- ; Global MCT Configuration Status Word (GStatus)
- ; ===============================================================================
-
- GsbMTRRshort EQU 0 ; < Ran out of MTRRs while mapping memory
- GsbAllECCDimms EQU 1 ; < All banks of all Nodes are ECC capable
- GsbDramECCDis EQU 2 ; < Dram ECC requested but not enabled.
- GsbSoftHole EQU 3 ; < A Node Base gap was created
- GsbHWHole EQU 4 ; < A HW dram remap was created
- GsbNodeIntlv EQU 5 ; < Node Memory interleaving was enabled
- GsbSpIntRemapHole EQU 6 ; < Special condition for Node Interleave and HW remapping
- GsbEnDIMMSpareNW EQU 7 ; < Indicates that DIMM Spare can be used without a warm reset
-
- GsbEOL EQU 8 ; < End of list
-GLOBAL_STATUS_FIELD TEXTEQU <DWORD>
-
-; ===============================================================================
- ; Local Error Status (DIE_STRUCT.ErrStatus[31:0])
-; ===============================================================================
-
- EsbNoDimms EQU 0 ; < No DIMMs
- EsbSpdChkSum EQU 1 ; < SPD Checksum fail
- EsbDimmMismatchM EQU 2 ; < dimm module type(buffer) mismatch
- EsbDimmMismatchT EQU 3 ; < dimm CL/T mismatch
- EsbDimmMismatchO EQU 4 ; < dimm organization mismatch (128-bit)
- EsbNoTrcTrfc EQU 5 ; < SPD missing Trc or Trfc info
- EsbNoCycTime EQU 6 ; < SPD missing byte 23 or 25
- EsbBkIntDis EQU 7 ; < Bank interleave requested but not enabled
- EsbDramECCDis EQU 8 ; < Dram ECC requested but not enabled
- EsbSpareDis EQU 9 ; < Online spare requested but not enabled
- EsbMinimumMode EQU 10 ; < Running in Minimum Mode
- EsbNoRcvrEn EQU 11 ; < No DQS Receiver Enable pass window found
- EsbSmallRcvr EQU 12 ; < DQS Rcvr En pass window too small (far right of dynamic range)
- EsbNoDqsPos EQU 13 ; < No DQS-DQ passing positions
- EsbSmallDqs EQU 14 ; < DQS-DQ passing window too small
- EsbDCBKScrubDis EQU 15 ; < DCache scrub requested but not enabled
-
- EsbEMPNotSupported EQU 16 ; < Processor is not capable for EMP.
- EsbEMPConflict EQU 17 ; < EMP requested but cannot be enabled since
- ; < channel interleaving, bank interleaving, or bank swizzle is enabled.
- EsbEMPDis EQU 18 ; < EMP requested but cannot be enabled since
- ; < memory size of each DCT is not a power of two.
-
- EsbEOL EQU 19 ; < End of list
-ERROR_STATUS_FIELD TEXTEQU <DWORD>
-
-; ===============================================================================
- ; Local Configuration Status (DIE_STRUCT.Status[31:0])
-; ===============================================================================
-
- SbRegistered EQU 0 ; < All DIMMs are Registered
- SbEccDimms EQU 1 ; < All banks ECC capable
- SbParDimms EQU 2 ; < All banks Addr/CMD Parity capable
- SbDiagClks EQU 3 ; < Jedec ALL slots clock enable diag mode
- Sb128bitmode EQU 4 ; < DCT in 128-bit mode operation
- Sb64MuxedMode EQU 5 ; < DCT in 64-bit mux'ed mode.
- Sb2TMode EQU 6 ; < 2T CMD timing mode is enabled.
- SbSWNodeHole EQU 7 ; < Remapping of Node Base on this Node to create a gap.
- SbHWHole EQU 8 ; < Memory Hole created on this Node using HW remapping.
- SbOver400Mhz EQU 9 ; < DCT freq greater than or equal to 400MHz flag
- SbDQSPosPass2 EQU 10 ; < Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
- SbDQSRcvLimit EQU 11 ; < Used for DQSRcvEnTrain to know we have reached the upper bound.
- SbExtConfig EQU 12 ; < Indicate the default setting for extended PCI configuration support
- SbLrdimms EQU 13 ; < All DIMMs are LRDIMMs
- SbEOL EQU 14 ; < End of list
-LOCAL_STATUS_FIELD TEXTEQU <DWORD>
-
-
-; < CPU MSR Register definitions ------------------------------------------
- SYS_CFG EQU 0C0010010h
- TOP_MEM EQU 0C001001Ah
- TOP_MEM2 EQU 0C001001Dh
- HWCR EQU 0C0010015h
- NB_CFG EQU 0C001001Fh
-
- FS_BASE EQU 0C0000100h
- IORR0_BASE EQU 0C0010016h
- IORR0_MASK EQU 0C0010017h
- BU_CFG EQU 0C0011023h
- BU_CFG2 EQU 0C001102Ah
- COFVID_STAT EQU 0C0010071h
- TSC EQU 10h
-
-; ===============================================================================
- ; SPD Data for each DIMM
-; ===============================================================================
-SPD_DEF_STRUCT STRUCT
- DimmPresent BOOLEAN ? ; < Indicates that the DIMM is present and Data is valid
- Data UINT8 (256) DUP (?) ; < Buffer for 256 Bytes of SPD data from DIMM
-SPD_DEF_STRUCT ENDS
-
-; ===============================================================================
- ; Channel Definition Structure
- ; This data structure defines entries that are specific to the channel initialization
-; ===============================================================================
-CH_DEF_STRUCT STRUCT
- ChannelID UINT8 ? ; < Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
- TechType TECHNOLOGY_TYPE ? ; < Technology type of this channel
- ChDimmPresent UINT8 ? ; < For each bit n 0..7, 1 = DIMM n is present.
- ; < DIMM# Select Signal
- ; < 0 MA0_CS_L[0, 1]
- ; < 1 MB0_CS_L[0, 1]
- ; < 2 MA1_CS_L[0, 1]
- ; < 3 MB1_CS_L[0, 1]
- ; < 4 MA2_CS_L[0, 1]
- ; < 5 MB2_CS_L[0, 1]
- ; < 6 MA3_CS_L[0, 1]
- ; < 7 MB3_CS_L[0, 1]
-
- DCTPtr POINTER ? ; < Pointer to the DCT data of this channel.
- MCTPtr POINTER ? ; < Pointer to the node data of this channel.
- SpdPtr POINTER ? ; < Pointer to the SPD data for this channel. (Setup by NB Constructor)
- DimmSpdPtr POINTER (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Array of pointers to
- ; < SPD Data for each Dimm. (Setup by Tech Block Constructor)
- ChDimmValid UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved.
- RegDimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved.
- LrDimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
- SODimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is a SO-DIMM where 4..7 are reserved.
- Loads UINT8 ? ; < Number of devices loading bus
- Dimms UINT8 ? ; < Number of DIMMs loading Channel
- Ranks UINT8 ? ; < Number of ranks loading Channel DATA
- SlowMode BOOLEAN ? ; < 1T or 2T CMD mode (slow access mode)
- ; < FALSE = 1T
- ; < TRUE = 2T
- ; < The following pointers will be pointed to dynamically allocated buffers.
- ; < Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
- ; < Example: If DIMM and Byte based training, then
- ; < XX is a value in Hex
- ; < BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
- ; < Row1 - Logical DIMM0 XX XX XX XX XX XX XX XX XX
- ; < Row2 - Logical DIMM1 XX XX XX XX XX XX XX XX XX
- RcvEnDlys POINTER ? ; < DQS Receiver Enable Delays
- WrDqsDlys POINTER ? ; < Write DQS delays (only valid for DDR3)
- RdDqsDlys POINTER ? ; < Read Dqs delays
- WrDatDlys POINTER ? ; < Write Data delays
- RdDqsMinDlys POINTER ? ; < Minimum Window for Read DQS
- RdDqsMaxDlys POINTER ? ; < Maximum Window for Read DQS
- WrDatMinDlys POINTER ? ; < Minimum Window for Write data
- WrDatMaxDlys POINTER ? ; < Maximum Window for Write data
- RowCount UINT8 ? ; < Number of rows of the allocated buffer.
- ColumnCount UINT8 ? ; < Number of columns of the allocated buffer.
-
- FailingBitMask POINTER ? ; < Table of masks to Track Failing bits
- DctOdcCtl UINT32 ? ; < Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
- DctAddrTmg UINT32 ? ; < Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
- PhyRODTCSLow UINT32 ? ; < Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h)
- PhyRODTCSHigh UINT32 ? ; < Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h)
- PhyWODTCSLow UINT32 ? ; < Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h)
- PhyWODTCSHigh UINT32 ? ; < Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183)
- PhyWLODT UINT8 (4) DUP (?) ; < Write Levelization ODT Pattern for Dimm 0-3 (see BKDG FN2:Offset 9Ch, index 0x8[11:8])
- DctEccDqsLike UINT16 ? ; < DCT DQS ECC UINT8 like...
- DctEccDqsScale UINT8 ? ; < DCT DQS ECC UINT8 scale
- PtrPatternBufA UINT16 ? ; < Ptr on stack to aligned DQS testing pattern
- PtrPatternBufB UINT16 ? ; < Ptr on stack to aligned DQS testing pattern
- ByteLane UINT8 ? ; < Current UINT8 Lane (0..7)
- Direction UINT8 ? ; < Current DQS-DQ training write direction (0=read, 1=write)
- Pattern UINT8 ? ; < Current pattern
- DqsDelay UINT8 ? ; < Current DQS delay value
- HostBiosSrvc1 UINT16 ? ; < UINT16 sized general purpose field for use by host BIOS. Scratch space.
- HostBiosSrvc2 UINT32 ? ; < UINT32 sized general purpose field for use by host BIOS. Scratch space.
- DctMaxRdLat UINT16 ? ; < Max Read Latency (ns) for the DCT
- DIMMValidCh UINT8 ? ; < DIMM# in CH
- MaxCh UINT8 ? ; < Max number of CH in system
- Dct UINT8 ? ; < Dct pointer
- WrDatGrossH UINT8 ? ; < Write Data Gross delay high value
- DqsRcvEnGrossL UINT8 ? ; < DQS Receive Enable Gross Delay low
-
- TrwtWB UINT8 ? ; < Non-SPD timing value for TrwtWB
- CurrRcvrDctADelay UINT8 ? ; < for keep current RcvrEnDly
- T1000 UINT16 ? ; < get the T1000 figure (cycle time (ns) * 1K)
- DqsRcvEnPass UINT8 ? ; < for TrainRcvrEn UINT8 lane pass flag
- DqsRcvEnSaved UINT8 ? ; < for TrainRcvrEn UINT8 lane saved flag
- SeedPass1Remainder UINT8 ? ; < for Phy assisted DQS receiver enable training
-
- ClToNbFlag UINT8 ? ; < is used to restore ClLinesToNbDis bit after memory
- NodeSysBase UINT32 ? ; < for channel interleave usage
- RefRawCard UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Array of rawcards detected
- CtrlWrd02 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 2 values per DIMM
- CtrlWrd03 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 3 values per DIMM
- CtrlWrd04 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 4 values per DIMM
- CtrlWrd05 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 5 values per DIMM
- CtrlWrd08 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 8 values per DIMM
-
- CsPresentDCT UINT16 ? ; < For each bit n 0..7, 1 = Chip-select n is present
- DimmMirrorPresent UINT8 ? ; < For each bit n 0..7, 1 = DIMM n is OnDimmMirror capable
- DimmSpdCse UINT8 ? ; < For each bit n 0..7, 1 = DIMM n SPD checksum error
- DimmExclude UINT8 ? ; < For each bit n 0..7, 1 = DIMM n gets excluded
- DimmYr06 UINT8 ? ; < Bitmap indicating which Dimms have a manufacturer's year code <= 2006
- DimmWk2406 UINT8 ? ; < Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
- DimmPlPresent UINT8 ? ; < Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
- DimmQrPresent UINT8 ? ; < QuadRank DIMM present?
- DimmDrPresent UINT8 ? ; < Bitmap indicating that Dual Rank Dimms are present
- DimmSRPresent UINT8 ? ; < Bitmap indicating that Single Rank Dimms are present
- Dimmx4Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved.
- Dimmx8Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved.
- Dimmx16Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved.
- LrdimmPhysicalRanks UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Number of Physical Ranks for LRDIMMs
- LrDimmLogicalRanks UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Number of LRDIMM Logical ranks in this configuration
- LrDimmRankMult UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Rank Multipication factor per dimm.
-
- MemClkDisMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
- ; < base on this array to disable unused MemClk to save power.
- ; <
- ; < The array must have 8 entries. Each entry, which associates with
- ; < one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
- ; < Example:
- ; < BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package
- ; < is like below:
- ; < Bit AM3/S1g3 pin name
- ; < 0 M[B,A]_CLK_H/L[0]
- ; < 1 M[B,A]_CLK_H/L[1]
- ; < 2 M[B,A]_CLK_H/L[2]
- ; < 3 M[B,A]_CLK_H/L[3]
- ; < 4 M[B,A]_CLK_H/L[4]
- ; < 5 M[B,A]_CLK_H/L[5]
- ; < 6 M[B,A]_CLK_H/L[6]
- ; < 7 M[B,A]_CLK_H/L[7]
- ; < And platform has the following routing:
- ; < CS0 M[B,A]_CLK_H/L[4]
- ; < CS1 M[B,A]_CLK_H/L[2]
- ; < CS2 M[B,A]_CLK_H/L[3]
- ; < CS3 M[B,A]_CLK_H/L[5]
- ; < Then MemClkDisMap should be pointed to the following array:
- ; < CLK_2 CLK_3 CLK_4 CLK_5
- ; < 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00
- ; < Each entry of the array is the bitmask of 8 chip selects.
-
- CKETriMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of CKE pins to the DIMMs' ranks.
- ; < The array must have 2 entries. Each entry, which associates with
- ; < one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
- ; < AGESA will base on this array to disable unused CKE pins to save power.
-
- ODTTriMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of ODT pins to the DIMMs' ranks.
- ; < The array must have 4 entries. Each entry, which associates with
- ; < one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
- ; < AGESA will base on this array to disable unused ODT pins to save power.
-
- ChipSelTriMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of chip select pins to the DIMMs' ranks.
- ; < The array must have 8 entries. Each entry is a bitmap of 8 CS.
- ; < AGESA will base on this array to disable unused Chip select pins to save power.
-
- ExtendTmp BOOLEAN ? ; < If extended temperature is supported on all dimms on a channel.
-
- Reserved UINT8 (100) DUP (?) ; < Reserved
-CH_DEF_STRUCT ENDS
-
-; ===============================================================================
- ; DCT Channel Timing Parameters
- ; This data structure sets timings that are specific to the channel
-; ===============================================================================
-CH_TIMING_STRUCT STRUCT
- DctDimmValid UINT16 ? ; < For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved.
- DimmMirrorPresent UINT16 ? ; < For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved.
- DimmSpdCse UINT16 ? ; < For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved.
- DimmExclude UINT16 ? ; < For each bit n 0..3, 1 = DIMM n gets excluded because of no common voltage is found
- CsPresent UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is present
- CsEnabled UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is enabled
- CsTestFail UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is present but disabled
- CsTrainFail UINT16 ? ; < Bitmap showing which chipselects failed training
- DIMM1KPage UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved.
- DimmQrPresent UINT16 ? ; < QuadRank DIMM present?
- DimmDrPresent UINT16 ? ; < Bitmap indicating that Dual Rank Dimms are present
- DimmSRPresent UINT8 ? ; < Bitmap indicating that Single Rank Dimms are present
- Dimmx4Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved.
- Dimmx8Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved.
- Dimmx16Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved.
-
- DIMMTrcd UINT16 ? ; < Minimax Trcd*40 (ns) of DIMMs
- DIMMTrp UINT16 ? ; < Minimax Trp*40 (ns) of DIMMs
- DIMMTrtp UINT16 ? ; < Minimax Trtp*40 (ns) of DIMMs
- DIMMTras UINT16 ? ; < Minimax Tras*40 (ns) of DIMMs
- DIMMTrc UINT16 ? ; < Minimax Trc*40 (ns) of DIMMs
- DIMMTwr UINT16 ? ; < Minimax Twr*40 (ns) of DIMMs
- DIMMTrrd UINT16 ? ; < Minimax Trrd*40 (ns) of DIMMs
- DIMMTwtr UINT16 ? ; < Minimax Twtr*40 (ns) of DIMMs
- DIMMTfaw UINT16 ? ; < Minimax Tfaw*40 (ns) of DIMMs
- TargetSpeed UINT16 ? ; < Target DRAM bus speed in MHz
- Speed UINT16 ? ; < DRAM bus speed in MHz
- ; < 400 (MHz)
- ; < 533 (MHz)
- ; < 667 (MHz)
- ; < 800 (MHz)
- ; < and so on...
- CasL UINT8 ? ; < CAS latency DCT setting (busclocks)
- Trcd UINT8 ? ; < DCT Trcd (busclocks)
- Trp UINT8 ? ; < DCT Trp (busclocks)
- Trtp UINT8 ? ; < DCT Trtp (busclocks)
- Tras UINT8 ? ; < DCT Tras (busclocks)
- Trc UINT8 ? ; < DCT Trc (busclocks)
- Twr UINT8 ? ; < DCT Twr (busclocks)
- Trrd UINT8 ? ; < DCT Trrd (busclocks)
- Twtr UINT8 ? ; < DCT Twtr (busclocks)
- Tfaw UINT8 ? ; < DCT Tfaw (busclocks)
- Trfc0 UINT8 ? ; < DCT Logical DIMM0 Trfc
- ; < 0 = 75ns (for 256Mb devs)
- ; < 1 = 105ns (for 512Mb devs)
- ; < 2 = 127.5ns (for 1Gb devs)
- ; < 3 = 195ns (for 2Gb devs)
- ; < 4 = 327.5ns (for 4Gb devs)
- Trfc1 UINT8 ? ; < DCT Logical DIMM1 Trfc (see Trfc0 for format)
- Trfc2 UINT8 ? ; < DCT Logical DIMM2 Trfc (see Trfc0 for format)
- Trfc3 UINT8 ? ; < DCT Logical DIMM3 Trfc (see Trfc0 for format)
- DctMemSize UINT32 ? ; < Base[47:16], total DRAM size controlled by this DCT.
- SlowMode BOOLEAN ? ; < 1T or 2T CMD mode (slow access mode)
- ; < FALSE = 1T
- ; < TRUE = 2T
- TrwtTO UINT8 ? ; < DCT TrwtTO (busclocks)
- Twrrd UINT8 ? ; < DCT Twrrd (busclocks)
- Twrwr UINT8 ? ; < DCT Twrwr (busclocks)
- Trdrd UINT8 ? ; < DCT Trdrd (busclocks)
- TrwtWB UINT8 ? ; < DCT TrwtWB (busclocks)
- TrdrdSD UINT8 ? ; < DCT TrdrdSD (busclocks)
- TwrwrSD UINT8 ? ; < DCT TwrwrSD (busclocks)
- TwrrdSD UINT8 ? ; < DCT TwrrdSD (busclocks)
- MaxRdLat UINT16 ? ; < Max Read Latency
- WrDatGrossH UINT8 ? ; < Temporary variables must be removed
- DqsRcvEnGrossL UINT8 ? ; < Temporary variables must be removed
-CH_TIMING_STRUCT ENDS
-
-; ===============================================================================
- ; Data for each DCT
- ; This data structure defines data used to configure each DRAM controller
-; ===============================================================================
-DCT_STRUCT STRUCT
- Dct UINT8 ? ; < Current Dct
- Timings CH_TIMING_STRUCT {} ; < Channel Timing structure
- ChData POINTER ? ; < Pointed to a dynamically allocated array of Channel structures
- ChannelCount UINT8 ? ; < Number of channel per this DCT
- BkIntDis BOOLEAN ? ; < Bank interleave requested but not enabled on current DCT
-DCT_STRUCT ENDS
-
-
-; ===============================================================================
- ; Data Structure defining each Die
- ; This data structure contains information that is used to configure each Die
-; ===============================================================================
-DIE_STRUCT STRUCT
-
- ; Advanced:
-
- NodeId UINT8 ? ; < Node ID of current controller
- SocketId UINT8 ? ; < Socket ID of this Die
- DieId UINT8 ? ; < ID of this die relative to the socket
- PciAddr PCI_ADDR {} ; < Pci bus and device number of this controller.
- ErrCode AGESA_STATUS ? ; < Current error condition of Node
- ; < 0x0 = AGESA_SUCCESS
- ; < 0x1 = AGESA_UNSUPPORTED
- ; < 0x2 = AGESA_BOUNDS_CHK
- ; < 0x3 = AGESA_ALERT
- ; < 0x4 = AGESA_WARNING
- ; < 0x5 = AGESA_ERROR
- ; < 0x6 = AGESA_CRITICAL
- ; < 0x7 = AGESA_FATAL
- ; <
- ErrStatus BOOLEAN (EsbEOL) DUP (?) ; < Error Status bit Field
- Status BOOLEAN (SbEOL) DUP (?) ; < Status bit Field
- NodeMemSize UINT32 ? ; < Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
- NodeSysBase UINT32 ? ; < Base[47:16] (system address) DRAM base address of this Node.
- NodeHoleBase UINT32 ? ; < If not zero, Base[47:16] (system address) of dram hole for HW remapping. Dram hole exists on this Node
- NodeSysLimit UINT32 ? ; < Base[47:16] (system address) DRAM limit address of this Node.
- DimmPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is present.
- ; < DIMM# Select Signal
- ; < 0 MA0_CS_L[0, 1]
- ; < 1 MB0_CS_L[0, 1]
- ; < 2 MA1_CS_L[0, 1]
- ; < 3 MB1_CS_L[0, 1]
- ; < 4 MA2_CS_L[0, 1]
- ; < 5 MB2_CS_L[0, 1]
- ; < 6 MA3_CS_L[0, 1]
- ; < 7 MB3_CS_L[0, 1]
- DimmValid UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
- RegDimmPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is registered DIMM
- LrDimmPresent UINT32 ? ; < For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
- DimmEccPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is ECC capable.
- DimmParPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
- DimmTrainFail UINT16 ? ; < Bitmap showing which dimms failed training
- ChannelTrainFail UINT16 ? ; < Bitmap showing the channel information about failed Chip Selects
- ; < 0 in any bit field indicates Channel 0
- ; < 1 in any bit field indicates Channel 1
- Dct UINT8 ? ; < Need to be removed
- ; < DCT pointer
- GangedMode BOOLEAN ? ; < Ganged mode
- ; < 0 = disabled
- ; < 1 = enabled
- LogicalCpuid CPU_LOGICAL_ID {} ; < The logical CPUID of the node
- HostBiosSrvc1 UINT16 ? ; < UINT16 sized general purpose field for use by host BIOS. Scratch space.
- HostBiosSrvc2 UINT32 ? ; < UINT32 sized general purpose field for use by host BIOS. Scratch space.
- MLoad UINT8 ? ; < Need to be removed
- ; < Number of devices loading MAA bus
- MaxAsyncLat UINT8 ? ; < Legacy wrapper
- ChbD3Rcvrdly UINT8 ? ; < Legacy wrapper
- ChaMaxRdLat UINT16 ? ; < Max Read Latency (ns) for DCT 0
- ChbD3BcRcvrdly UINT8 ? ; < CHB DIMM 3 Check UINT8 Receiver Enable Delay
-
- DctData POINTER ? ; < Pointed to a dynamically allocated array of DCT_STRUCTs
- DctCount UINT8 ? ; < Number of DCTs per this Die
- Reserved UINT8 (16) DUP (?) ; < Reserved
-DIE_STRUCT ENDS
-
-; *********************************************************************
-; * S3 Support structure
-; *********************************************************************
- ; AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure
-AMD_S3_PARAMS STRUCT
- Signature UINT32 ? ; < "ASTR" for AMD Suspend-To-RAM
- Version UINT16 ? ; < S3 Params version number
- Flags UINT32 ? ; < Indicates operation
- NvStorage POINTER ? ; < Pointer to memory critical save state data
- NvStorageSize UINT32 ? ; < Size in bytes of the NvStorage region
- VolatileStorage POINTER ? ; < Pointer to remaining AMD save state data
- VolatileStorageSize UINT32 ? ; < Size in bytes of the VolatileStorage region
-AMD_S3_PARAMS ENDS
-
-; ===============================================================================
- ; MEM_PARAMETER_STRUCT
- ; This data structure is used to pass wrapper parameters to the memory configuration code
-; ===============================================================================
-MEM_PARAMETER_STRUCT STRUCT
-
- ; Basic (Return parameters)
- ; (This section contains the outbound parameters from the memory init code)
-
- GStatus BOOLEAN (GsbEOL) DUP (?) ; < Global Status bitfield
- HoleBase UINT32 ? ; < If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping.
- Sub4GCacheTop UINT32 ? ; < If not zero, the 32-bit top of cacheable memory.
- Sub1THoleBase UINT32 ? ; < If not zero Base[47:16] (system address) of sub 1TB dram hole.
- SysLimit UINT32 ? ; < Limit[47:16] (system address)
- DDR3Voltage DIMM_VOLTAGE ? ; < Find support voltage and send back to platform BIOS.
-
- MemData POINTER ? ; < Pointer to MEM_DATA_STRUCT
- ; Advanced (Optional parameters)
- ; Optional (all defaults values will be initialized by the
- ; 'AmdMemInitDataStructDef' based on AMD defaults. It is up
- ; to the IBV/OEM to change the defaults after initialization
- ; but prior to the main entry to the memory code):
-
- ; Memory Map/Mgt.
-
- BottomIo UINT16 ? ; < Bottom of 32-bit IO space (8-bits)
- ; < NV_BOTTOM_IO[7:0]=Addr[31:24]
- MemHoleRemapping BOOLEAN ? ; < Memory Hole Remapping (1-bit)
- ; < FALSE = disable
- ; < TRUE = enable
- LimitMemoryToBelow1Tb BOOLEAN ? ; < Limit memory address space to below 1 TB
- ; < FALSE = disable
- ; < TRUE = enable
- ; Dram Timing
-
- UserTimingMode USER_MEMORY_TIMING_MODE ? ; < User Memclock Mode
-
- MemClockValue MEMORY_BUS_SPEED ? ; < Memory Clock Value
-
- ; Dram Configuration
-
- EnableBankIntlv BOOLEAN ? ; < Dram Bank (chip-select) Interleaving (1-bit)
- ; < FALSE =disable (AMD default)
- ; < TRUE =enable
- EnableNodeIntlv BOOLEAN ? ; < Node Memory Interleaving (1-bit)
- ; < FALSE = disable (AMD default)
- ; < TRUE = enable
- EnableChannelIntlv BOOLEAN ? ; < Channel Interleaving (1-bit)
- ; < FALSE = disable (AMD default)
- ; < TRUE = enable
- ; ECC
-
- EnableEccFeature BOOLEAN ? ; < enable ECC error to go into MCE
- ; < FALSE = disable (AMD default)
- ; < TRUE = enable
- ; Dram Power
-
- EnablePowerDown BOOLEAN ? ; < CKE based power down mode (1-bit)
- ; < FALSE =disable (AMD default)
- ; < TRUE =enable
- ; Online Spare
-
- EnableOnLineSpareCtl BOOLEAN ? ; < Chip Select Spare Control bit 0:
- ; < FALSE = disable Spare (AMD default)
- ; < TRUE = enable Spare
- TableBasedAlterations POINTER ? ; < Point to an array of data bytes describing desired modifications to register settings.
-
- PlatformMemoryConfiguration POINTER ?
- ; < Points to a table that contains platform specific settings
- ; < (i.e. MemClk routing, the number of DIMM slots per channel,...)
- ; < AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that
- ; < contains default conservative settings. Platform BIOS can either tweak
- ; < DefaultPlatformMemoryConfiguration or reassign this pointer to its own table.
- ; <
- EnableParity BOOLEAN ? ; < Parity control
- ; < TRUE = enable
- ; < FALSE = disable (AMD default)
- EnableBankSwizzle BOOLEAN ? ; < BankSwizzle control
- ; < FALSE = disable
- ; < TRUE = enable (AMD default)
- EnableMemClr BOOLEAN ? ; < Memory Clear functionality control
- ; < FALSE = disable
- ; < TRUE = enable (AMD default)
- ; Uma Configuration
-
- UmaMode UMA_MODE ? ; < Uma Mode
- ; < 0 = None
- ; < 1 = Specified
- ; < 2 = Auto
- UmaSize UINT32 ? ; < The size of shared graphics dram (16-bits)
- ; < NV_UMA_Size[31:0]=Addr[47:16]
- ; <
- UmaBase UINT32 ? ; < The allocated Uma base address (32-bits)
- ; < NV_UMA_Base[31:0]=Addr[47:16]
- ; <
-
- ; Memory Restore Feature
-
- MemRestoreCtl BOOLEAN ? ; < Memory context restore control
- ; < FALSE = perform memory init as normal (AMD default)
- ; < TRUE = restore memory context and skip training. This requires
- ; < MemContext is valid before AmdInitPost
- SaveMemContextCtl BOOLEAN ? ; < Control switch to save memory context at the end of MemAuto
- ; < TRUE = AGESA will setup MemContext block before exit AmdInitPost
- ; < FALSE = AGESA will not setup MemContext block. Platform is
- ; < expected to call S3Save later in POST if it wants to
- ; < use memory context restore feature.
- MemContext AMD_S3_PARAMS {} ; < Memory context block describes the data that platform needs to
- ; < save and restore for memory context restore feature to work.
- ; < It uses the subset of S3Save block to save/restore. Hence platform
- ; < may save only S3 block and uses it for both S3 resume and
- ; < memory context restore.
- ; < - If MemRestoreCtl is TRUE, platform needs to pass in MemContext
- ; < before AmdInitPost.
- ; < - If SaveMemContextCtl is TRUE, platform needs to save MemContext
- ; < right after AmdInitPost.
-MEM_PARAMETER_STRUCT ENDS
-
-
-; ===============================================================================
- ; Function definition
- ; This data structure passes function pointers to the memory configuration code.
- ; The wrapper can use this structure with customized versions
-; ================================================================================
-MEM_FUNCTION_STRUCT STRUCT
-
- ; PUBLIC required Internal functions
-
- amdMemGetPsCfgU POINTER ? ; < Proc for Unbuffered DIMMs, platform specific
- amdMemGetPsCfgR POINTER ? ; < Proc for Registered DIMMs, platform specific
-
- ; PUBLIC optional functions
-
- amdMemEccInit POINTER ? ; < NB proc for ECC feature
- amdMemChipSelectInterleaveInit POINTER ? ; < NB proc for CS interleave feature
- amdMemDctInterleavingInit POINTER ? ; < NB proc for Channel interleave feature
- amdMemMctInterleavingInit POINTER ? ; < NB proc for Node interleave feature
- amdMemParallelTraining POINTER ? ; < NB proc for parallel training feature
- amdMemEarlySampleSupport POINTER ? ; < NB code for early sample support feature
- amdMemMultiPartInitSupport POINTER ? ; < NB code for 'multi-part'
- amdMemOnlineSpareSupport POINTER ? ; < NB code for On-Line Spare feature
- amdMemUDimmInit POINTER ? ; < NB code for UDIMMs
- amdMemRDimmInit POINTER ? ; < NB code for RDIMMs
- amdMemLrDimmInit POINTER ? ; < NB code for LRDIMMs
-
- Reserved UINT32 (100) DUP (?) ; < Reserved for later function definition
-MEM_FUNCTION_STRUCT ENDS
-
-; ===============================================================================
- ; Socket Structure
-
-; ===============================================================================
-MEM_SOCKET_STRUCT STRUCT
- ChannelPtr POINTER (MAX_CHANNELS_PER_SOCKET) DUP (?) ; < Pointers to each channels training data
-
- TimingsPtr POINTER (MAX_CHANNELS_PER_SOCKET) DUP (?) ; < Pointers to each channels timing data
-
-MEM_SOCKET_STRUCT ENDS
-
-; ===============================================================================
- ; MEM_DATA_STRUCT
-; ===============================================================================
-MEM_DATA_STRUCT STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < AGESA Standard Header
-
- ParameterListPtr POINTER ? ; < List of input Parameters
-
- FunctionList MEM_FUNCTION_STRUCT {} ; < List of function Pointers
-
- GetPlatformCfg POINTER (MAX_PLATFORM_TYPES) DUP (?) ; < look-up platform info
-
- ErrorHandling POINTER ? ; < Error Handling
-
- ; SocketList is a shortcut for IBVs to retrieve training
- ; and timing data for each channel indexed by socket/channel,
- ; eliminating their need to parse die/dct/channel etc.
- ; It contains pointers to the populated data structures for
- ; each channel and skips the channel structures that are
- ; unpopulated. In the case of channels sharing the same DCT,
- ; the pTimings pointers will point to the same DCT Timing data.
-
- SocketList MEM_SOCKET_STRUCT (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Socket list for memory code
-
- DiesPerSystem POINTER ? ; < Pointed to an array of DIE_STRUCTs
- DieCount UINT8 ? ; < Number of MCTs in the system.
-
- SpdDataStructure POINTER ? ; < Pointer to SPD Data structure
-
- PlatFormConfig POINTER ? ; < Pointer to Platform profile/build option config structure
-
- IsFlowControlSupported BOOLEAN ? ; < Indicates if flow control is supported
-
- TscRate UINT32 ? ; < The rate at which the TSC increments in megahertz.
-
-MEM_DATA_STRUCT ENDS
-
-; ===============================================================================
-; UMA_INFO_STRUCT
-; ===============================================================================
-UMA_INFO STRUCT
- UmaBase UINT64 ? ; < UmaBase[63:0] = Addr[63:0]
- UmaSize UINT32 ? ; < UmaSize[31:0] = Addr[31:0]
- UmaAttributes UINT32 ? ; < Indicate the attribute of Uma
- UmaMode UINT8 ? ; < Indicate the mode of Uma
- MemClock UINT16 ? ; < Indicate memory running speed in MHz
- Reserved UINT8 (3) DUP (?) ; < Reserved for future usage
-UMA_INFO ENDS
-
-; ===============================================================================
-; Bitfield for ID
-; ===============================================================================
-ID_FIELD STRUCT
- SocketId UINT16 ?
-; OUT UINT16 SocketId:8; ; < Socket ID
-; OUT UINT16 ModuleId:8; ; < Module ID
-ID_FIELD ENDS
-
-; ===============================================================================
-; Union for ID of socket and module that will be passed out in call out
-; ===============================================================================
-ID_INFO UNION
- IdField ID_FIELD {} ; < Bitfield for ID
- IdInformation UINT16 ? ; < ID information for call out
-ID_INFO ENDS
-
- ; AGESA MEMORY ERRORS
-
- ; AGESA_ALERT Memory Errors
-MEM_ALERT_USER_TMG_MODE_OVERRULED EQU 04010000h ; < TIMING_MODE_SPECIFIC is requested but
- ; < cannot be applied to current configurations.
-MEM_ALERT_ORG_MISMATCH_DIMM EQU 04010100h ; < DIMM organization miss-match
-MEM_ALERT_BK_INT_DIS EQU 04010200h ; < Bank interleaving disable for internal issue
-
- ; AGESA_ERROR Memory Errors
-MEM_ERROR_NO_DQS_POS_RD_WINDOW EQU 04010300h ; < No DQS Position window for RD DQS
-MEM_ERROR_SMALL_DQS_POS_RD_WINDOW EQU 04020300h ; < Small DQS Position window for RD DQS
-MEM_ERROR_NO_DQS_POS_WR_WINDOW EQU 04030300h ; < No DQS Position window for WR DQS
-MEM_ERROR_SMALL_DQS_POS_WR_WINDOW EQU 04040300h ; < Small DQS Position window for WR DQS
-MEM_ERROR_ECC_DIS EQU 04010400h ; < ECC has been disabled as a result of an internal issue
-MEM_ERROR_DIMM_SPARING_NOT_ENABLED EQU 04010500h ; < DIMM sparing has not been enabled for an internal issues
-MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE EQU 04050300h ; < Receive Enable value is too large
-MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW EQU 04060300h ; < There is no DQS receiver enable window
-MEM_ERROR_DRAM_ENABLED_TIME_OUT EQU 04010600h ; < Time out when polling DramEnabled bit
-MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT EQU 04010700h ; < Time out when polling DctAccessDone bit
-MEM_ERROR_SEND_CTRL_WORD_TIME_OUT EQU 04010800h ; < Time out when polling SendCtrlWord bit
-MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT EQU 04010900h ; < Time out when polling PrefDramTrainMode bit
-MEM_ERROR_ENTER_SELF_REF_TIME_OUT EQU 04010A00h ; < Time out when polling EnterSelfRef bit
-MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT EQU 04010B00h ; < Time out when polling FreqChgInProg bit
-MEM_ERROR_EXIT_SELF_REF_TIME_OUT EQU 04020A00h ; < Time out when polling ExitSelfRef bit
-MEM_ERROR_SEND_MRS_CMD_TIME_OUT EQU 04010C00h ; < Time out when polling SendMrsCmd bit
-MEM_ERROR_SEND_ZQ_CMD_TIME_OUT EQU 04010D00h ; < Time out when polling SendZQCmd bit
-MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT EQU 04010E00h ; < Time out when polling DctExtraAccessDone bit
-MEM_ERROR_MEM_CLR_BUSY_TIME_OUT EQU 04010F00h ; < Time out when polling MemClrBusy bit
-MEM_ERROR_MEM_CLEARED_TIME_OUT EQU 04020F00h ; < Time out when polling MemCleared bit
-MEM_ERROR_FLUSH_WR_TIME_OUT EQU 04011000h ; < Time out when polling FlushWr bit
-MEM_ERROR_MAX_LAT_NO_WINDOW EQU 04070300h ; < Fail to find pass during Max Rd Latency training
-MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL EQU 04080300h ; < Fail to launch training code on an AP
-MEM_ERROR_PARALLEL_TRAINING_TIME_OUT EQU 04090300h ; < Fail to finish parallel training
-MEM_ERROR_NO_ADDRESS_MAPPING EQU 04011100h ; < No address mapping found for a dimm
-MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT EQU 040A0300h ; < There is no DQS receiver enable window and the value is equal to the largest value
-MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE EQU 040B0300h ; < Receive Enable value is too large and is 1 less than limit
-MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR EQU 04011200h ; < SPD Checksum error for NV_SPDCHK_RESTRT
-MEM_ERROR_NO_CHIPSELECT EQU 04011300h ; < No chipselects found
-MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM EQU 04011500h ; < Unbuffered dimm is not supported at 333MHz
-MEM_ERROR_WL_PRE_OUT_OF_RANGE EQU 040C0300h ; < Returned PRE value during write levelization was out of range
-
- ; AGESA_WARNING Memory Errors
- MEM_WARNING_UNSUPPORTED_QRDIMM EQU 04011600h ; < QR DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_UDIMM EQU 04021600h ; < U DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_SODIMM EQU 04031600h ; < SO-DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_X4DIMM EQU 04041600h ; < x4 DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_RDIMM EQU 04051600h ; < R DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_LRDIMM EQU 04061600h ; < LR DIMMs detected but not supported
-
- MEM_WARNING_EMP_NOT_SUPPORTED EQU 04011700h ; < Processor is not capable for EMP
- MEM_WARNING_EMP_CONFLICT EQU 04021700h ; < EMP cannot be enabled if channel interleaving,
- ; < bank interleaving, or bank swizzle is enabled.
- MEM_WARNING_EMP_NOT_ENABLED EQU 04031700h ; < Memory size is not power of two.
- MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED EQU 04011800h ; < Performance has been enabled, but battery life is preferred.
- MEM_WARNING_NO_SPDTRC_FOUND EQU 04011900h ; < No Trc timing value found in SPD of a dimm.
- MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED EQU 04012000h ; < Node Interleaveing Requested, but could not be enabled
- MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED EQU 04012100h ; < Channel Interleaveing Requested, but could not be enabled
- MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED EQU 04012200h ; < Bank Interleaveing Requested, but could not be enabled
- MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED EQU 04012300h ; < Voltage 1.35 determined, but could not be supported
- MEM_WARNING_INITIAL_DDR3VOLT_NONZERO EQU 0x04012400 ; < DDR3 voltage initial value is not 0
- MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO EQU 0x04012500 ; < Cannot find a commonly supported VDDIO
-
- ; AGESA_FATAL Memory Errors
- MEM_ERROR_MINIMUM_MODE EQU 04011A00h ; < Running in minimum mode
- MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM EQU 04011B00h ; < DIMM modules are miss-matched
- MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM EQU 04011C00h ; < No DIMMs have been found on system
- MEM_ERROR_MISMATCH_DIMM_CLOCKS EQU 04011D00h ; < DIMM clocks miss-matched
- MEM_ERROR_NO_CYC_TIME EQU 04011E00h ; < No cycle time found
- MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS EQU 04011F00h ; < Heap allocation error with dynamic storing of trained timings
- MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs EQU 04021F00h ; < Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
- MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV EQU 04031F00h ; < Heap allocation error with REMOTE_TRAINING_ENV
- MEM_ERROR_HEAP_ALLOCATE_FOR_SPD EQU 04041F00h ; < Heap allocation error for SPD data
- MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA EQU 04051F00h ; < Heap allocation error for RECEIVED_DATA during parallel training
- MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS EQU 04061F00h ; < Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
- MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA EQU 04071F00h ; < Heap allocation error for Training Data
- MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK EQU 04081F00h ; < Heap allocation error for DIMM Identify "MEM_NB_BLOCK
- MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM EQU 04022300h ; < No Constructor for DIMM Identify
- MEM_ERROR_VDDIO_UNSUPPORTED EQU 04022500h ; < VDDIO of the dimms on the board is not supported
-
-
- ; AGESA_CRITICAL Memory Errors
- MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 EQU 04091F00h ; < Heap allocation error for DMI table for DDR3
- MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 EQU 040A1F00h ; < Heap allocation error for DMI table for DDR2
- MEM_ERROR_UNSUPPORTED_DIMM_CONFIG EQU 04011400h ; < Dimm population is not supported
-
-
-; ----------------------------------------------------------------------------
-; *
-; * END OF MEMORY-SPECIFIC DATA STRUCTURES
-; *
-; *----------------------------------------------------------------------------
-;
-
-
-; ----------------------------------------------------------------------------
-; *
-; * CPU RELATED DEFINITIONS
-; *
-; *----------------------------------------------------------------------------
-;
-
-; CPU Event definitions.
-
-; Defines used to filter CPU events based on functional blocks
-CPU_EVENT_PM_EVENT_MASK EQU 0FF00FF00h
-CPU_EVENT_PM_EVENT_CLASS EQU 008000400h
-
-;================================================================
-; CPU General events
-; Heap allocation (AppFunction = 01h)
-CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT EQU 008000100h
-CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED EQU 008010100h
-CPU_ERROR_HEAP_IS_FULL EQU 008020100h
-CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED EQU 008030100h
-CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT EQU 008040100h
-; BrandId (AppFunction = 02h)
-CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE EQU 008000200h
-; Micro code patch (AppFunction = 03h)
-CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED EQU 008000300h
-; Power management (AppFunction = 04h)
-CPU_EVENT_PM_PSTATE_OVERCURRENT EQU 008000400h
-CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT EQU 008010400h
-CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE EQU 008020400h
-CPU_ERROR_PM_NB_PSTATE_MISMATCH EQU 008030400h
-; Other CPU events (AppFunction = 05h)
-CPU_EVENT_BIST_ERROR EQU 008000500h
-CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY EQU 008010500h
-CPU_EVENT_STACK_REENTRY EQU 008020500h
-CPU_EVENT_CORE_NOT_IDENTIFIED EQU 008030500h
-;=================================================================
-; CPU Feature events
-; Execution cache (AppFunction = 21h)
-; AGESA_CACHE_SIZE_REDUCED 2101
-; AGESA_CACHE_REGIONS_ACROSS_1MB 2102
-; AGESA_CACHE_REGIONS_ACROSS_4GB 2103
-; AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 2104
-; AGESA_CACHE_START_ADDRESS_LESS_D0000 2105
-; AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 2106
-; AGESA_DEALLOCATE_CACHE_REGIONS 2107
-CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR EQU 008002100h
-; Core Leveling (AppFunction = 22h)
-CPU_WARNING_ADJUSTED_LEVELING_MODE EQU 008002200h
-; HT Assist (AppFunction = 23h)
-CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG EQU 008002300h
-
-; CPU Build Configuration structures and definitions
-
-; Build Configuration values for BLDGCFG_AP_MTRR_SETTINGS
-AP_MTRR_SETTINGS STRUCT
- MsrAddr UINT32 ? ; < Fixed-Sized MTRR address
- MsrData UINT64 ? ; < MTRR Settings
-AP_MTRR_SETTINGS ENDS
-
-AMD_AP_MTRR_FIX64k_00000 EQU 000000250h
-AMD_AP_MTRR_FIX16k_80000 EQU 000000258h
-AMD_AP_MTRR_FIX16k_A0000 EQU 000000259h
-AMD_AP_MTRR_FIX4k_C0000 EQU 000000268h
-AMD_AP_MTRR_FIX4k_C8000 EQU 000000269h
-AMD_AP_MTRR_FIX4k_D0000 EQU 00000026Ah
-AMD_AP_MTRR_FIX4k_D8000 EQU 00000026Bh
-AMD_AP_MTRR_FIX4k_E0000 EQU 00000026Ch
-AMD_AP_MTRR_FIX4k_E8000 EQU 00000026Dh
-AMD_AP_MTRR_FIX4k_F0000 EQU 00000026Eh
-AMD_AP_MTRR_FIX4k_F8000 EQU 00000026Fh
-CPU_LIST_TERMINAL EQU 0FFFFFFFFh
-
-; ***********************************************************************
-; *
-; * AGESA interface Call-Out function parameter structures
-; *
-; **********************************************************************
-
- ; Parameters structure for interface call-out AgesaAllocateBuffer
-AGESA_BUFFER_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- BufferLength UINT32 ? ; < Size of buffer to allocate
- BufferHandle UINT32 ? ; < Identifier or name for the buffer
- BufferPointer POINTER ? ; < location of the created buffer
-AGESA_BUFFER_PARAMS ENDS
-
- ; Parameters structure for interface call-out AgesaRunCodeOnAp
-AP_EXE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- FunctionNumber UINT32 ? ; < Index of the procedure to execute
- RelatedDataBlock POINTER ? ; < Location of data structure the procedure will use
- RelatedBlockLength UINT32 ? ; < Size of the related data block
-AP_EXE_PARAMS ENDS
-
- ; Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery
-AGESA_READ_SPD_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < standard header
- SocketId UINT8 ? ; < Address of SPD - socket ID
- MemChannelId UINT8 ? ; < Address of SPD - memory channel ID
- DimmId UINT8 ? ; < Address of SPD - DIMM ID
- Buffer POINTER ? ; < Location where to place the SPD content
- MemData POINTER ? ; < Location of the MemData structure, for reference
-AGESA_READ_SPD_PARAMS ENDS
-
- ; Buffer Handles
- AMD_DMI_INFO_BUFFER_HANDLE EQU 000D000h ; < Assign 0x000D000 buffer handle to DMI function
- AMD_PSTATE_DATA_BUFFER_HANDLE EQU 000D001h ; < Assign 0x000D001 buffer handle to Pstate data
- AMD_PSTATE_ACPI_BUFFER_HANDLE EQU 000D002h ; < Assign 0x000D002 buffer handle to Pstate table
- AMD_BRAND_ID_BUFFER_HANDLE EQU 000D003h ; < Assign 0x000D003 buffer handle to Brand ID
- AMD_ACPI_SLIT_BUFFER_HANDLE EQU 000D004h ; < Assign 0x000D004 buffer handle to SLIT function
- AMD_SRAT_INFO_BUFFER_HANDLE EQU 000D005h ; < Assign 0x000D005 buffer handle to SRAT function
- AMD_WHEA_BUFFER_HANDLE EQU 000D006h ; < Assign 0x000D006 buffer handle to WHEA function
- AMD_S3_INFO_BUFFER_HANDLE EQU 000D007h ; < Assign 0x000D007 buffer handle to S3 function
- AMD_S3_NB_INFO_BUFFER_HANDLE EQU 000D008h ; < Assign 0x000D008 buffer handle to S3 NB device info
- AMD_ACPI_ALIB_BUFFER_HANDLE EQU 000D009h ; < Assign 0x000D009 buffer handle to ALIB SSDT table
- AMD_ACPI_IVRS_BUFFER_HANDLE EQU 000D00Ah ; < Assign 0x000D00A buffer handle to IOMMU IVRS table
-AMD_BUFFER_HANDLE TEXTEQU <DWORD>
-; ***********************************************************************
-; *
-; * AGESA interface Call-Out function prototypes
-; *
-; **********************************************************************
-
-; ***********************************************************************
-; *
-; * AGESA interface structure definition and function prototypes
-; *
-; **********************************************************************
-
-; *********************************************************************
-; * Platform Configuration: The parameters in boot branch function
-; *********************************************************************
-
-; The possible platform control flow settings.
- Nfcm EQU 0 ; < Normal Flow Control Mode.
- UmaDr EQU 1 ; < UMA using Display Refresh flow control.
- UmaIfcm EQU 2 ; < UMA using Isochronous Flow Control.
- Ifcm EQU 3 ; < Isochronous Flow Control Mode (other than for UMA).
- Iommu EQU 4 ; < An IOMMU is in use in the system.
- MaxControlFlow EQU 5 ; < Not a control flow mode, use for limit checking.
-PLATFORM_CONTROL_FLOW TEXTEQU <DWORD>
-
-; Platform Deemphasis Levels.
- DeemphasisLevelNone EQU 0 ; < No Deemphasis.
- DeemphasisLevelMinus3 EQU 1 ; < Minus 3 db deemphasis.
- DeemphasisLevelMinus6 EQU 2 ; < Minus 6 db deemphasis.
- DeemphasisLevelMinus8 EQU 3 ; < Minus 8 db deemphasis.
- DeemphasisLevelMinus11 EQU 4 ; < Minus 11 db deemphasis.
- DeemphasisLevelMinus11pre8 EQU 5 ; < Minus 11, Minus 8 precursor db deemphasis.
- DcvLevelNone EQU 16 ; < No DCV Deemphasis.
- DcvLevelMinus2 EQU 17 ; < Minus 2 db DCV deemphasis.
- DcvLevelMinus3 EQU 18 ; < Minus 3 db DCV deemphasis.
- DcvLevelMinus5 EQU 19 ; < Minus 5 db DCV deemphasis.
- DcvLevelMinus6 EQU 20 ; < Minus 6 db DCV deemphasis.
- DcvLevelMinus7 EQU 21 ; < Minus 7 db DCV deemphasis.
- DcvLevelMinus8 EQU 22 ; < Minus 8 db DCV deemphasis.
- DcvLevelMinus9 EQU 23 ; < Minus 9 db DCV deemphasis.
- DcvLevelMinus11 EQU 24 ; < Minus 11 db DCV deemphasis.
- MaxPlatformDeemphasisLevel EQU 25 ; < Not a deemphasis level, use for limit checking.
-PLATFORM_DEEMPHASIS_LEVEL TEXTEQU <DWORD>
-
-; Provide Deemphasis Levels for HT Links.
-;
-; For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will
-; be checked for a match. The item matches for a Socket, Link if the link frequency is
-; is in the inclusive range HighFreq:LoFreq.
-; AGESA does not set deemphasis in IO devices, only in processors.
-
-CPU_HT_DEEMPHASIS_LEVEL STRUCT
- ; Match fields
- Socket UINT8 ? ; < One Socket on which this Link is located
- Link UINT8 ? ; < The Link on this Processor.
- LoFreq UINT8 ? ; < If the link is set to this frequency or greater, apply these levels, and
- HighFreq UINT8 ? ; < If the link is set to this frequency or less, apply these levels.
- ; Value fields
- ReceiverDeemphasis PLATFORM_DEEMPHASIS_LEVEL ? ; < The deemphasis level for this link
- DcvDeemphasis PLATFORM_DEEMPHASIS_LEVEL ? ; < The DCV, or far transmitter deemphasis level.
-CPU_HT_DEEMPHASIS_LEVEL ENDS
-
-; The possible platform power policy settings.
- Performance EQU 0 ; < Optimize for performance.
- BatteryLife EQU 1 ; < Optimize for battery life.
- MaxPowerPolicy EQU 2 ; < Not a power policy mode, use for limit checking.
-PLATFORM_POWER_POLICY TEXTEQU <DWORD>
-
-; Platform performance settings for optimized settings.
-; Several configuration settings for the processor depend upon other parts and
-; general designer choices for the system. The determination of these data points
-; is not standard for all platforms, so the host environment needs to provide these
-; to specify how the system is to be configured.
-PERFORMANCE_PROFILE STRUCT
- PlatformControlFlowMode PLATFORM_CONTROL_FLOW ? ; < The platform's control flow mode for optimum platform performance.
- UseHtAssist BOOLEAN ? ; < HyperTransport link traffic optimization.
- UseAtmMode BOOLEAN ? ; < HyperTransport link traffic optimization.
- Use32ByteRefresh BOOLEAN ? ; < Display Refresh traffic generates 32 byte requests.
- UseVariableMctIsocPriority BOOLEAN ? ; < The Memory controller will be set to Variable Isoc Priority.
- PlatformPowerPolicy PLATFORM_POWER_POLICY ? ; < The platform's desired power policy
-PERFORMANCE_PROFILE ENDS
-
-; Platform settings that describe the voltage regulator modules of the system.
-; Many power management settings are dependent upon the characteristics of the
-; on-board voltage regulator module (VRM). The host environment needs to provide
-; these to specify how the system is to be configured.
-PLATFORM_VRM_CONFIGURATION STRUCT
- CurrentLimit UINT32 ? ; < Vrm Current Limit.
- LowPowerThreshold UINT32 ? ; < Vrm Low Power Threshold.
- SlewRate UINT32 ? ; < Vrm Slew Rate.
- AdditionalDelay UINT32 ? ; < Vrm Additional Delay.
- HiSpeedEnable BOOLEAN ? ; < Select high speed VRM.
- InrushCurrentLimit UINT32 ? ; < Vrm Inrush Current Limit.
-PLATFORM_VRM_CONFIGURATION ENDS
-
-; The VRM types to characterize.
- CoreVrm EQU 0 ; < VDD plane.
- NbVrm EQU 1 ; < VDDNB plane.
- MaxVrmType EQU 2 ; < Not a valid VRM type, use for limit checking.
-PLATFORM_VRM_TYPE TEXTEQU <DWORD>
-
-; Build Option/Configuration Boolean Structure
-BUILD_OPT_CFG STRUCT
- ; Build Option Area
- VersionString AMD_CODE_HEADER {} ; < AMD embedded code version string
- OptionUDimms BOOLEAN ? ; < UDIMMS
- OptionRDimms BOOLEAN ? ; < RDIMMS
- OptionLrDimms BOOLEAN ? ; < LRDIMMS
- OptionEcc BOOLEAN ? ; < ECC
- OptionBankInterleave BOOLEAN ? ; < BANK_INTERLEAVE
- OptionDctInterleave BOOLEAN ? ; < DCT_INTERLEAVE
- OptionNodeInterleave BOOLEAN ? ; < NODE_INTERLEAVE
- OptionParallelTraining BOOLEAN ? ; < PARALLEL_TRAINING
- OptionOnlineSpare BOOLEAN ? ; < ONLINE_SPARE
- OptionMemRestore BOOLEAN ? ; < MEM CONTEXT RESTORE
- OptionMultisocket BOOLEAN ? ; < MULTISOCKET
- OptionAcpiPstates BOOLEAN ? ; < ACPI_PSTATES
- OptionSrat BOOLEAN ? ; < SRAT
- OptionSlit BOOLEAN ? ; < SLIT
- OptionWhea BOOLEAN ? ; < WHEA
- OptionDmi BOOLEAN ? ; < DMI
- OptionEarlySamples BOOLEAN ? ; < EARLY_SAMPLES
- OptionAddrToCsTranslator BOOLEAN ? ; < ADDR_TO_CS_TRANSLATOR
-
- ; Build Configuration Area
- CfgPciMmioAddress UINT64 ? ; < PciMmioBase
- CfgPciMmioSize UINT32 ? ; < PciMmioSize
- CfgPlatVrmCfg PLATFORM_VRM_CONFIGURATION (MaxVrmType) DUP ({}) ; < Several configuration settings for the voltage regulator modules.
- CfgPlatNumIoApics UINT32 ? ; < PlatformApicIoNumber
- CfgMemInitPstate UINT32 ? ; < MemoryInitPstate
- CfgPlatformC1eMode PLATFORM_C1E_MODES ? ; < PlatformC1eMode
- CfgPlatformC1eOpData UINT32 ? ; < PlatformC1eOpData
- CfgPlatformC1eOpData1 UINT32 ? ; < PlatformC1eOpData1
- CfgPlatformC1eOpData2 UINT32 ? ; < PlatformC1eOpData2
- CfgPlatformC1eOpData3 UINT32 ? ; < PlatformC1eOpData3
- CfgPlatformCStateMode PLATFORM_CSTATE_MODES ? ; < PlatformCStateMode
- CfgPlatformCStateOpData UINT32 ? ; < PlatformCStateOpData
- CfgPlatformCStateIoBaseAddress UINT16 ? ; < PlatformCStateIoBaseAddress
- CfgPlatformCpbMode PLATFORM_CPB_MODES ? ; < PlatformCpbMode
- CfgCoreLevelingMode UINT32 ? ; < CoreLevelingCofig
- CfgPerformanceProfile PERFORMANCE_PROFILE {} ; < The platform's control flow mode and platform performance settings.
- CfgPlatformDeemphasisList POINTER ? ; < HT Deemphasis
- CfgAmdPlatformType UINT32 ? ; < AmdPlatformType
- CfgAmdPstateCapValue UINT32 ? ; < Amd pstate ceiling enabling deck
-
- CfgMemoryBusFrequencyLimit MEMORY_BUS_SPEED ? ; < Memory Bus Frequency Limit
- CfgMemoryModeUnganged BOOLEAN ? ; < Memory Mode Unganged
- CfgMemoryQuadRankCapable BOOLEAN ? ; < Memory Quad Rank Capable
- CfgMemoryQuadrankType QUANDRANK_TYPE ? ; < Memory Quadrank Type
- CfgMemoryRDimmCapable BOOLEAN ? ; < Memory RDIMM Capable
- CfgMemoryLRDimmCapable BOOLEAN ? ; < Memory LRDIMM Capable
- CfgMemoryUDimmCapable BOOLEAN ? ; < Memory UDIMM Capable
- CfgMemorySODimmCapable BOOLEAN ? ; < Memory SODimm Capable
- CfgLimitMemoryToBelow1Tb BOOLEAN ? ; < Limit memory address space to below 1TB
- CfgMemoryEnableBankInterleaving BOOLEAN ? ; < Memory Enable Bank Interleaving
- CfgMemoryEnableNodeInterleaving BOOLEAN ? ; < Memory Enable Node Interleaving
- CfgMemoryChannelInterleaving BOOLEAN ? ; < Memory Channel Interleaving
- CfgMemoryPowerDown BOOLEAN ? ; < Memory Power Down
- CfgPowerDownMode POWER_DOWN_MODE ? ; < Power Down Mode
- CfgOnlineSpare BOOLEAN ? ; < Online Spare
- CfgMemoryParityEnable BOOLEAN ? ; < Memory Parity Enable
- CfgBankSwizzle BOOLEAN ? ; < Bank Swizzle
- CfgTimingModeSelect USER_MEMORY_TIMING_MODE ? ; < Timing Mode Select
- CfgMemoryClockSelect MEMORY_BUS_SPEED ? ; < Memory Clock Select
- CfgDqsTrainingControl BOOLEAN ? ; < Dqs Training Control
- CfgIgnoreSpdChecksum BOOLEAN ? ; < Ignore Spd Checksum
- CfgUseBurstMode BOOLEAN ? ; < Use Burst Mode
- CfgMemoryAllClocksOn BOOLEAN ? ; < Memory All Clocks On
- CfgEnableEccFeature BOOLEAN ? ; < Enable ECC Feature
- CfgEccRedirection BOOLEAN ? ; < ECC Redirection
- CfgScrubDramRate UINT16 ? ; < Scrub Dram Rate
- CfgScrubL2Rate UINT16 ? ; < Scrub L2Rate
- CfgScrubL3Rate UINT16 ? ; < Scrub L3Rate
- CfgScrubIcRate UINT16 ? ; < Scrub Ic Rate
- CfgScrubDcRate UINT16 ? ; < Scrub Dc Rate
- CfgEccSyncFlood BOOLEAN ? ; < ECC Sync Flood
- CfgEccSymbolSize UINT16 ? ; < ECC Symbol Size
- CfgHeapDramAddress UINT64 ? ; < Heap contents will be temporarily stored in this address during the transition
- CfgNodeMem1GBAlign BOOLEAN ? ; < Node Mem 1GB boundary Alignment
- CfgS3LateRestore BOOLEAN ? ; < S3 Late Restore
- CfgAcpiPstateIndependent BOOLEAN ? ; < PSD method dependent/Independent
- CfgApMtrrSettingsList POINTER ? ; < The AP's MTRR settings before final halt
- CfgUmaMode UMA_MODE ? ; < Uma Mode
- CfgUmaSize UINT32 ? ; < Uma Size [31:0]=Addr[47:16]
- CfgUmaAbove4G BOOLEAN ? ; < Uma Above 4G Support
- CfgUmaAlignment UMA_ALIGNMENT ? ; < Uma alignment
- CfgProcessorScopeInSb BOOLEAN ? ; < ACPI Processor Object in \_SB scope
- CfgProcessorScopeName0 CHAR8 ? ; < OEM specific 1st character of processor scope name.
- CfgProcessorScopeName1 CHAR8 ? ; < OEM specific 2nd character of processor scope name.
- CfgGnbHdAudio UINT8 ? ; < Gnb HD Audio Enable
- CfgAbmSupport UINT8 ? ; < ABM support
- CfgDynamicRefreshRate UINT8 ? ; < Dynamic refresh rate
- CfgLcdBackLightControl UINT16 ? ; < Lcd back light control
- CfgGnb3dStereoPinIndex UINT8 ? ; < 3D Stereo Pin ID
- CfgTempPcieMmioBaseAddress UINT32 ? ; < Temp pcie MMIO base address
- CfgGnbIGPUSSID UINT32 ? ; < Gnb internal GPU SSID
- CfgGnbHDAudioSSID UINT32 ? ; < Gnb HD Audio SSID
- CfgGnbPcieSSID UINT32 ? ; < Gnb PCIe SSID
- CfgLvdsSpreadSpectrum UINT16 ? ; < Lvds Spread Spectrum. Build-time customizable only
- CfgLvdsSpreadSpectrumRate UINT16 ? ; < Lvds Spread Spectrum Rate. Build-time customizable only
- CfgSmbus0BaseAddress UINT16 ? ; SMBUS0 Controller Base Address
- CfgSmbus1BaseAddress UINT16 ? ; SMBUS1 Controller Base Address
- CfgSioPmeBaseAddress UINT16 ? ; I/O base address for LPC I/O target range
- CfgAcpiPm1EvtBlkAddr UINT16 ? ; I/O base address of ACPI power management Event Block
- CfgAcpiPm1CntBlkAddr UINT16 ? ; I/O base address of ACPI power management Control Block
- CfgAcpiPmTmrBlkAddr UINT16 ? ; I/O base address of ACPI power management Timer Block
- CfgCpuControlBlkAddr UINT16 ? ; I/O base address of ACPI power management CPU Control Block
- CfgAcpiGpe0BlkAddr UINT16 ? ; I/O base address of ACPI power management General Purpose Event Block
- CfgSmiCmdPortAddr UINT16 ? ; I/O base address of ACPI SMI Command Block
- CfgAcpiPmaCntBlkAddr UINT16 ? ; I/O base address of ACPI power management additional control block
- CfgGecShadowRomBase UINT32 ? ; 32-bit base address to the GEC shadow ROM
- CfgWatchDogTimerBase UINT32 ? ; Watchdog Timer base address
- CfgSpiRomBaseAddress UINT32 ? ; Base address for the SPI ROM controller
- CfgHpetBaseAddress UINT32 ? ; HPET MMIO base address
- CfgAzaliaSsid UINT32 ? ; Subsystem ID of HD Audio controller
- CfgSmbusSsid UINT32 ? ; Subsystem ID of SMBUS controller
- CfgIdeSsid UINT32 ? ; Subsystem ID of IDE controller
- CfgSataAhciSsid UINT32 ? ; Subsystem ID of SATA controller in AHCI mode
- CfgSataIdeSsid UINT32 ? ; Subsystem ID of SATA controller in IDE mode
- CfgSataRaid5Ssid UINT32 ? ; Subsystem ID of SATA controller in RAID5 mode
- CfgSataRaidSsid UINT32 ? ; Subsystem ID of SATA controller in RAID mode
- CfgEhciSsid UINT32 ? ; Subsystem ID of EHCI
- CfgOhciSsid UINT32 ? ; Subsystem ID of OHCI
- CfgLpcSsid UINT32 ? ; Subsystem ID of LPC ISA Bridge
- CfgFchGppLinkConfig GPP_LINKMODE ? ; FCH GPP link configuration
- CfgFchGppPort0Present BOOLEAN ? ; Is FCH GPP port 0 present
- CfgFchGppPort1Present BOOLEAN ? ; Is FCH GPP port 1 present
- CfgFchGppPort2Present BOOLEAN ? ; Is FCH GPP port 2 present
- CfgFchGppPort3Present BOOLEAN ? ; Is FCH GPP port 3 present
- CfgFchGppPort0HotPlug BOOLEAN ? ; Is FCH GPP port 0 hotplug capable
- CfgFchGppPort1HotPlug BOOLEAN ? ; Is FCH GPP port 1 hotplug capable
- CfgFchGppPort2HotPlug BOOLEAN ? ; Is FCH GPP port 2 hotplug capable
- CfgFchGppPort3HotPlug BOOLEAN ? ; Is FCH GPP port 3 hotplug capable
- CfgIommuSupport BOOLEAN ? ; IOMMU support
- CfgLvdsPowerOnSeqDigonToDe UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqDeToVaryBl UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqDeToDigon UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqVaryBlToDe UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqOnToOffDelay UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqVaryBlToBlon UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqBlonToVaryBl UINT8 ? ; Panel initialization timing
- CfgLvdsMaxPixelClockFreq UINT16 ? ; The maximum pixel clock frequency supported
- CfgLcdBitDepthControlValue UINT32 ? ; The LCD bit depth control settings
- CfgLvds24bbpPanelMode UINT8 ? ; The LVDS 24 BBP mode
- CfgPcieRefClkSpreadSpectrum UINT16 ? ; PCIe Reference Clock Spread Spectrum
- Reserved BOOLEAN ? ; < reserved...
-BUILD_OPT_CFG ENDS
-
- ; A structure containing platform specific operational characteristics. This
- ; structure is initially populated by the initializer with a copy of the same
- ; structure that was created at build time using the build configuration controls.
-PLATFORM_CONFIGURATION STRUCT
- PlatformProfile PERFORMANCE_PROFILE {} ; < Several configuration settings for the processor.
- PlatformDeemphasisList POINTER ? ; < Deemphasis levels for the platform's HT links.
- CoreLevelingMode UINT8 ? ; < Indicates how to balance the number of cores per processor.
- C1eMode PLATFORM_C1E_MODES ? ; < Specifies the method of C1e enablement - Disabled, HW, or message based.
- C1ePlatformData UINT32 ? ; < If C1eMode is HW, specifies the P_LVL3 I/O port of the platform.
- C1ePlatformData1 UINT32 ? ; < If C1eMode is SW, specifies the address of chipset's SMI command port.
- C1ePlatformData2 UINT32 ? ; < If C1eMode is SW, specifies the unique number used by the SMI handler to identify SMI source.
- C1ePlatformData3 UINT32 ? ; < If C1eMode is Auto, specifies the P_LVL3 I/O port of the platform for HW C1e
- CStateMode PLATFORM_CSTATE_MODES ? ; < Specifies the method of C-State enablement - Disabled, or C6.
- CStatePlatformData UINT32 ? ; < This element specifies some pertinent data needed for the operation of the Cstate feature
- ; < If CStateMode is CStateModeC6, this item is reserved
- CStateIoBaseAddress UINT16 ? ; < This item specifies a free block of 8 consecutive bytes of I/O ports that
- ; < can be used to allow the CPU to enter Cstates.
- CpbMode PLATFORM_CPB_MODES ? ; < Specifies the method of core performance boost enablement - Disabled, or Auto.
- UserOptionDmi BOOLEAN ? ; < When set to TRUE, the DMI data table is generated.
- UserOptionPState BOOLEAN ? ; < When set to TRUE, the PState data tables are generated.
- UserOptionSrat BOOLEAN ? ; < When set to TRUE, the SRAT data table is generated.
- UserOptionSlit BOOLEAN ? ; < When set to TRUE, the SLIT data table is generated.
- UserOptionWhea BOOLEAN ? ; < When set to TRUE, the WHEA data table is generated.
- PowerCeiling UINT32 ? ; < P-State Ceiling Enabling Deck - Max power milli-watts.
- ForcePstateIndependent BOOLEAN ? ; < P-State _PSD independence or dependence.
- NumberOfIoApics UINT32 ? ; < Number of I/O APICs in the system
- VrmProperties PLATFORM_VRM_CONFIGURATION (MaxVrmType) DUP ({}) ; < Several configuration settings for the voltage regulator modules.
- ProcessorScopeInSb BOOLEAN ? ; < ACPI Processor Object in \_SB scope
- ProcessorScopeName0 CHAR8 ? ; < OEM specific 1st character of processor scope name.
- ProcessorScopeName1 CHAR8 ? ; < OEM specific 2nd character of processor scope name.
- GnbHdAudio UINT8 ? ; < Control GFX HD Audio controller(Used for HDMI and DP display output),
- ; < essentially it enables function 1 of graphics device.
- ; < @li 0 = HD Audio disable
- ; < @li 1 = HD Audio enable
- AbmSupport UINT8 ? ; < Automatic adjust LVDS/eDP Back light level support.It is
- ; < characteristic specific to display panel which used by platform design.
- ; < @li 0 = ABM support disabled
- ; < @li 1 = ABM support enabled
- DynamicRefreshRate UINT8 ? ; < Adjust refresh rate on LVDS/eDP.
- LcdBackLightControl UINT16 ? ; < The PWM frequency to LCD backlight control.
- ; < If equal to 0 backlight not controlled by iGPU.
-PLATFORM_CONFIGURATION ENDS
-
-
-; *********************************************************************
-; * Structures for: AmdInitLate
-; *********************************************************************
- PROC_VERSION_LENGTH EQU 48
- MAX_DIMMS_PER_SOCKET EQU 16
-
-
- ; Interface Parameter Structures
- ; DMI Type4 - Processor ID
-TYPE4_PROC_ID STRUCT
- ProcIdLsd UINT32 ? ; < Lower half of 64b ID
- ProcIdMsd UINT32 ? ; < Upper half of 64b ID
-TYPE4_PROC_ID ENDS
-
- ; DMI Type 4 - Processor information
-TYPE4_DMI_INFO STRUCT
- T4ProcType UINT8 ? ; < CPU Type
- T4ProcFamily UINT8 ? ; < Family 1
- T4ProcId TYPE4_PROC_ID {} ; < Id
- T4Voltage UINT8 ? ; < Voltage
- T4ExternalClock UINT16 ? ; < External clock
- T4MaxSpeed UINT16 ? ; < Max speed
- T4CurrentSpeed UINT16 ? ; < Current speed
- T4Status UINT8 ? ; < Status
- T4ProcUpgrade UINT8 ? ; < Up grade
- T4CoreCount UINT8 ? ; < Core count
- T4CoreEnabled UINT8 ? ; < Core Enable
- T4ThreadCount UINT8 ? ; < Thread count
- T4ProcCharacteristics UINT16 ? ; < Characteristics
- T4ProcFamily2 UINT16 ? ; < Family 2
- T4ProcVersion CHAR8 (PROC_VERSION_LENGTH) DUP (?) ; < Cpu version
-TYPE4_DMI_INFO ENDS
-
- ; DMI Type 7 - Cache information
-TYPE7_DMI_INFO STRUCT
- T7CacheCfg UINT16 ? ; < Cache cfg
- T7MaxCacheSize UINT16 ? ; < Max size
- T7InstallSize UINT16 ? ; < Install size
- T7SupportedSramType UINT16 ? ; < Supported Sram Type
- T7CurrentSramType UINT16 ? ; < Current type
- T7CacheSpeed UINT8 ? ; < Speed
- T7ErrorCorrectionType UINT8 ? ; < ECC type
- T7SystemCacheType UINT8 ? ; < Cache type
- T7Associativity UINT8 ? ; < Associativity
-TYPE7_DMI_INFO ENDS
-
- ; DMI Type 16 offset 04h - Location
-
- OtherLocation EQU 01h ; < Assign 01 to Other
- UnknownLocation EQU 2 ; < Assign 02 to Unknown
- SystemboardOrMotherboard EQU 3 ; < Assign 03 to systemboard or motherboard
- IsaAddonCard EQU 4 ; < Assign 04 to ISA add-on card
- EisaAddonCard EQU 5 ; < Assign 05 to EISA add-on card
- PciAddonCard EQU 6 ; < Assign 06 to PCI add-on card
- McaAddonCard EQU 7 ; < Assign 07 to MCA add-on card
- PcmciaAddonCard EQU 8 ; < Assign 08 to PCMCIA add-on card
- ProprietaryAddonCard EQU 9 ; < Assign 09 to proprietary add-on card
- NuBus EQU 10 ; < Assign 0A to NuBus
- Pc98C20AddonCard EQU 11 ; < Assign 0A0 to PC-98/C20 add-on card
- Pc98C24AddonCard EQU 12 ; < Assign 0A1 to PC-98/C24 add-on card
- Pc98EAddoncard EQU 13 ; < Assign 0A2 to PC-98/E add-on card
- Pc98LocalBusAddonCard EQU 14 ; < Assign 0A3 to PC-98/Local bus add-on card
-DMI_T16_LOCATION TEXTEQU <DWORD> ;} DMI_T16_LOCATION;
-
- ; DMI Type 16 offset 05h - Memory Error Correction
-
- OtherUse EQU 01h ; < Assign 01 to Other
- UnknownUse EQU 2 ; < Assign 02 to Unknown
- SystemMemory EQU 3 ; < Assign 03 to system memory
- VideoMemory EQU 4 ; < Assign 04 to video memory
- FlashMemory EQU 5 ; < Assign 05 to flash memory
- NonvolatileRam EQU 6 ; < Assign 06 to non-volatile RAM
- CacheMemory EQU 7 ; < Assign 07 to cache memory
-DMI_T16_USE TEXTEQU <DWORD> ;} DMI_T16_USE;
-
- ; DMI Type 16 offset 07h - Maximum Capacity
-
- Dmi16OtherErrCorrection EQU 01h ; < Assign 01 to Other
- Dmi16UnknownErrCorrection EQU 2 ; < Assign 02 to Unknown
- Dmi16NoneErrCorrection EQU 3 ; < Assign 03 to None
- Dmi16Parity EQU 4 ; < Assign 04 to parity
- Dmi16SingleBitEcc EQU 5 ; < Assign 05 to Single-bit ECC
- Dmi16MultiBitEcc EQU 6 ; < Assign 06 to Multi-bit ECC
- Dmi16Crc EQU 7 ; < Assign 07 to CRC
-DMI_T16_ERROR_CORRECTION TEXTEQU <DWORD> ;} DMI_T16_ERROR_CORRECTION;
-
- ; DMI Type 16 - Physical Memory Array
-TYPE16_DMI_INFO STRUCT
- Location DMI_T16_LOCATION ? ; < The physical location of the Memory Array,
- ; < whether on the system board or an add-in board.
- Use DMI_T16_USE ? ; < Identifies the function for which the array
- ; < is used.
- MemoryErrorCorrection DMI_T16_ERROR_CORRECTION ? ; < The primary hardware error correction or
- ; < detection method supported by this memory array.
- MaximumCapacity UINT32 ? ; < The maximum memory capacity, in kilobytes,
- ; < for the array.
- NumberOfMemoryDevices UINT16 ? ; < The number of slots or sockets available
- ; < for memory devices in this array.
-TYPE16_DMI_INFO ENDS
-
- ; DMI Type 17 offset 0Eh - Form Factor
- OtherFormFactor EQU 01h ; < Assign 01 to Other
- UnknowFormFactor EQU 2 ; < Assign 02 to Unknown
- SimmFormFactor EQU 3 ; < Assign 03 to SIMM
- SipFormFactor EQU 4 ; < Assign 04 to SIP
- ChipFormFactor EQU 5 ; < Assign 05 to Chip
- DipFormFactor EQU 6 ; < Assign 06 to DIP
- ZipFormFactor EQU 7 ; < Assign 07 to ZIP
- ProprietaryCardFormFactor EQU 8 ; < Assign 08 to Proprietary Card
- DimmFormFactorFormFactor EQU 9 ; < Assign 09 to DIMM
- TsopFormFactor EQU 10 ; < Assign 10 to TSOP
- RowOfChipsFormFactor EQU 11 ; < Assign 11 to Row of chips
- RimmFormFactor EQU 12 ; < Assign 12 to RIMM
- SodimmFormFactor EQU 13 ; < Assign 13 to SODIMM
- SrimmFormFactor EQU 14 ; < Assign 14 to SRIMM
- FbDimmFormFactor EQU 15 ; < Assign 15 to FB-DIMM
-DMI_T17_FORM_FACTOR TEXTEQU <DWORD>
-
- ; DMI Type 17 offset 12h - Memory Type
- OtherMemType EQU 01h ; < Assign 01 to Other
- UnknownMemType EQU 2 ; < Assign 02 to Unknown
- DramMemType EQU 3 ; < Assign 03 to DRAM
- EdramMemType EQU 4 ; < Assign 04 to EDRAM
- VramMemType EQU 5 ; < Assign 05 to VRAM
- SramMemType EQU 6 ; < Assign 06 to SRAM
- RamMemType EQU 7 ; < Assign 07 to RAM
- RomMemType EQU 8 ; < Assign 08 to ROM
- FlashMemType EQU 9 ; < Assign 09 to Flash
- EepromMemType EQU 10 ; < Assign 10 to EEPROM
- FepromMemType EQU 11 ; < Assign 11 to FEPROM
- EpromMemType EQU 12 ; < Assign 12 to EPROM
- CdramMemType EQU 13 ; < Assign 13 to CDRAM
- ThreeDramMemType EQU 14 ; < Assign 14 to 3DRAM
- SdramMemType EQU 15 ; < Assign 15 to SDRAM
- SgramMemType EQU 16 ; < Assign 16 to SGRAM
- RdramMemType EQU 17 ; < Assign 17 to RDRAM
- DdrMemType EQU 18 ; < Assign 18 to DDR
- Ddr2MemType EQU 19 ; < Assign 19 to DDR2
- Ddr2FbdimmMemType EQU 20 ; < Assign 20 to DDR2 FB-DIMM
- Ddr3MemType EQU 24 ; < Assign 24 to DDR3
- Fbd2MemType EQU 25 ; < Assign 25 to FBD2
-DMI_T17_MEMORY_TYPE TEXTEQU <DWORD>
-
- ; DMI Type 17 offset 13h - Type Detail
-DMI_T17_TYPE_DETAIL STRUCT
- Reserved1 UINT16 ?
-; OUT UINT16 Reserved1:1; ; < Reserved
-; OUT UINT16 Other:1; ; < Other
-; OUT UINT16 Unknown:1; ; < Unknown
-; OUT UINT16 FastPaged:1; ; < Fast-Paged
-; OUT UINT16 StaticColumn:1; ; < Static column
-; OUT UINT16 PseudoStatic:1; ; < Pseudo-static
-; OUT UINT16 Rambus:1; ; < RAMBUS
-; OUT UINT16 Synchronous:1; ; < Synchronous
-; OUT UINT16 Cmos:1; ; < CMOS
-; OUT UINT16 Edo:1; ; < EDO
-; OUT UINT16 WindowDram:1; ; < Window DRAM
-; OUT UINT16 CacheDram:1; ; < Cache Dram
-; OUT UINT16 NonVolatile:1; ; < Non-volatile
-; OUT UINT16 Reserved2:3; ; < Reserved
-DMI_T17_TYPE_DETAIL ENDS
-
- ; DMI Type 17 - Memory Device
-TYPE17_DMI_INFO STRUCT
- TotalWidth UINT16 ? ; < Total Width, in bits, of this memory device, including any check or error-correction bits.
- DataWidth UINT16 ? ; < Data Width, in bits, of this memory device.
- MemorySize UINT16 ? ; < The size of the memory device.
- FormFactor DMI_T17_FORM_FACTOR ? ; < The implementation form factor for this memory device.
- DeviceSet UINT8 ? ; < Identifies when the Memory Device is one of a set of
- ; < Memory Devices that must be populated with all devices of
- ; < the same type and size, and the set to which this device belongs.
- DeviceLocator CHAR8 (8) DUP (?) ; < The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
- BankLocator CHAR8 (10) DUP (?) ; < The string number of the string that identifies the physically labeled bank where the memory device is located.
- MemoryType DMI_T17_MEMORY_TYPE ? ; < The type of memory used in this device.
- TypeDetail DMI_T17_TYPE_DETAIL {} ; < Additional detail on the memory device type
- Speed UINT16 ? ; < Identifies the speed of the device, in megahertz (MHz).
- ManufacturerIdCode UINT64 ? ; < Manufacturer ID code.
- SerialNumber CHAR8 (9) DUP (?) ; < Serial Number.
- PartNumber CHAR8 (19) DUP (?) ; < Part Number.
- Attributes UINT8 ? ; < Bits 7-4: Reserved, Bits 3-0: rank.
- ExtSize UINT32 ? ; < Extended Size.
- ConfigSpeed UINT16 ? ; < Configured memory clock speed
-TYPE17_DMI_INFO ENDS
-
- ; Memory DMI Type 17 and 20 - for memory use
-MEM_DMI_INFO STRUCT
- TotalWidth UINT16 ? ; ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
- DataWidth UINT16 ? ; ///< Data Width, in bits, of this memory device.
- MemorySize UINT16 ? ; ///< The size of the memory device.
- FormFactor DMI_T17_FORM_FACTOR ? ; ///< The implementation form factor for this memory device.
- DeviceLocator UINT8 ? ; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
- BankLocator UINT8 ? ; ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
- Speed UINT16 ? ; ///< Identifies the speed of the device, in megahertz (MHz).
- ManufacturerIdCode UINT64 ? ; ///< Manufacturer ID code.
- SerialNumber UINT8 (4) DUP (?) ; ///< Serial Number.
- PartNumber UINT8 (18) DUP (?) ; ///< Part Number.
- Attributes UINT8 ? ; ///< Bits 7-4: Reserved, Bits 3-0: rank.
- ExtSize UINT32 ? ; ///< Extended Size.
- Socket UINT8 ?
-; OUT UINT8 Socket:3 ; ///< Socket ID
-; OUT UINT8 Channel:2 ; ///< Channel ID
-; OUT UINT8 Dimm:2 ; ///< DIMM ID
-; OUT UINT8 DimmPresent:1 ; ///< Dimm Present
- StartingAddr UINT32 ? ; ///< The physical address, in kilobytes, of a range
- ; ///< of memory mapped to the referenced Memory Device.
- EndingAddr UINT32 ? ; ///< The handle, or instance number, associated with
- ; ///< the Memory Device structure to which this address
- ; ///< range is mapped.
- ConfigSpeed UINT16 ? ; ///< Configured memory clock speed
-MEM_DMI_INFO ENDS
-
- ; DMI Type 19 - Memory Array Mapped Address
-TYPE19_DMI_INFO STRUCT
- StartingAddr UINT32 ? ; < The physical address, in kilobytes,
- ; < of a range of memory mapped to the
- ; < specified physical memory array.
- EndingAddr UINT32 ? ; < The physical ending address of the
- ; < last kilobyte of a range of addresses
- ; < mapped to the specified physical memory array.
- MemoryArrayHandle UINT16 ? ; < The handle, or instance number, associated
- ; < with the physical memory array to which this
- ; < address range is mapped.
- PartitionWidth UINT8 ? ; < Identifies the number of memory devices that
- ; < form a single row of memory for the address
- ; < partition defined by this structure.
-TYPE19_DMI_INFO ENDS
-
-; DMI Type 20 - Memory Device Mapped Address
-TYPE20_DMI_INFO STRUCT
- StartingAddr UINT32 ? ; < The physical address, in kilobytes, of a range
- ; < of memory mapped to the referenced Memory Device.
- EndingAddr UINT32 ? ; < The handle, or instance number, associated with
- ; < the Memory Device structure to which this address
- ; < range is mapped.
- MemoryDeviceHandle UINT16 ? ; < The handle, or instance number, associated with
- ; < the Memory Device structure to which this address
- ; < range is mapped.
- MemoryArrayMappedAddressHandle UINT16 ? ; < The handle, or instance number, associated
- ; < with the Memory Array Mapped Address structure to
- ; < which this device address range is mapped.
- PartitionRowPosition UINT8 ? ; < Identifies the position of the referenced Memory
- ; < Device in a row of the address partition.
- InterleavePosition UINT8 ? ; < The position of the referenced Memory Device in
- ; < an interleave.
- InterleavedDataDepth UINT8 ? ; < The maximum number of consecutive rows from the
- ; < referenced Memory Device that are accessed in a
- ; < single interleaved transfer.
-TYPE20_DMI_INFO ENDS
-
- ; Collection of pointers to the DMI records
-DMI_INFO STRUCT
- T4 TYPE4_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 4 struc
- T7L1 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 1
- T7L2 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 2
- T7L3 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 3
- T16 TYPE16_DMI_INFO {} ; < Type 16 struc
- T17 TYPE17_DMI_INFO (MAX_SOCKETS_SUPPORTED * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL) DUP ({}) ; < Type 17 struc
- T19 TYPE19_DMI_INFO {} ; < Type 19 struc
- T20 TYPE20_DMI_INFO (MAX_SOCKETS_SUPPORTED * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL) DUP ({}) ; < Type 20 struc
-DMI_INFO ENDS
-
-
-
-; *********************************************************************
-; * Interface call: AllocateExecutionCache
-; *********************************************************************
- MAX_CACHE_REGIONS EQU 3
-
- ; AllocateExecutionCache sub param structure for cached memory region
-EXECUTION_CACHE_REGION STRUCT
- ExeCacheStartAddr UINT32 ? ; < Start address
- ExeCacheSize UINT32 ? ; < Size
-EXECUTION_CACHE_REGION ENDS
-
-; *********************************************************************
-; * Interface call: AmdGetAvailableExeCacheSize
-; *********************************************************************
- ; Get available Cache remain
-AMD_GET_EXE_SIZE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- AvailableExeCacheSize UINT32 ? ; < Remain size
-AMD_GET_EXE_SIZE_PARAMS ENDS
-
-
-
-
-
-
- ; Selection type for core leveling
- CORE_LEVEL_LOWEST EQU 0 ; < Level to lowest common denominator
- CORE_LEVEL_TWO EQU 1 ; < Level to 2 cores
- CORE_LEVEL_POWER_OF_TWO EQU 2 ; < Level to 1,2,4 or 8
- CORE_LEVEL_NONE EQU 3 ; < Do no leveling
- CORE_LEVEL_COMPUTE_UNIT EQU 4 ; < Level cores to one core per compute unit
- CORE_LEVEL_ONE EQU 5 ; < Level to 1 core
- CORE_LEVEL_THREE EQU 6 ; < Level to 3 cores
- CORE_LEVEL_FOUR EQU 7 ; < Level to 4 cores
- CORE_LEVEL_FIVE EQU 8 ; < Level to 5 cores
- CORE_LEVEL_SIX EQU 9 ; < Level to 6 cores
- CORE_LEVEL_SEVEN EQU 10 ; < Level to 7 cores
- CORE_LEVEL_EIGHT EQU 11 ; < Level to 8 cores
- CORE_LEVEL_NINE EQU 12 ; < Level to 9 cores
- CORE_LEVEL_TEN EQU 13 ; < Level to 10 cores
- CORE_LEVEL_ELEVEN EQU 14 ; < Level to 11 cores
- CORE_LEVEL_TWELVE EQU 15 ; < Level to 12 cores
- CORE_LEVEL_THIRTEEN EQU 16 ; < Level to 13 cores
- CORE_LEVEL_FOURTEEN EQU 17 ; < Level to 14 cores
- CORE_LEVEL_FIFTEEN EQU 18 ; < Level to 15 cores
- CoreLevelModeMax EQU 19 ; < Used for bounds checking
-CORE_LEVELING_TYPE TEXTEQU <DWORD>
-
-
-; ***********************************************************************
-; *
-; * AGESA Basic Level interface structure definition and function prototypes
-; *
-; **********************************************************************
-
-; *********************************************************************
-; * Interface call: AmdCreateStruct
-; *********************************************************************
-
-; *********************************************************************
-; * Interface call: AmdReleaseStruct
-; *********************************************************************
-
-; *********************************************************************
-; * Interface call: AmdInitReset
-; *********************************************************************
- ; AmdInitReset param structure
-AMD_RESET_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < The cached memory region
- HtConfig AMD_HT_RESET_INTERFACE {} ; < The interface for Ht Recovery
- FchInterface FCH_RESET_INTERFACE {} ; Interface for FCH configuration
-AMD_RESET_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitEarly
-; *********************************************************************
- ; InitEarly param structure
-
- ; Provide defaults or customizations to each service performed in AmdInitEarly.
-
-AMD_EARLY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < The standard header
- CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < Execution Map Interface
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- HtConfig AMD_HT_INTERFACE {} ; < HyperTransport Interface
- GnbConfig GNB_CONFIGURATION {} ; < GNB configuration
-AMD_EARLY_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitPost
-; *********************************************************************
- ; AmdInitPost param structure
-AMD_POST_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- MemConfig MEM_PARAMETER_STRUCT {} ; < Memory post param
-AMD_POST_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitEnv
-; *********************************************************************
- ; AmdInitEnv param structure
-AMD_ENV_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- GnbEnvConfiguration GNB_ENV_CONFIGURATION {} ; < platform operational characteristics.
- FchInterface FCH_INTERFACE {} ; FCH configuration
-AMD_ENV_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitMid
-; *********************************************************************
- ; AmdInitMid param structure
-AMD_MID_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- FchInterface FCH_INTERFACE {} ; FCH configuration
-AMD_MID_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitLate
-; *********************************************************************
- ; AmdInitLate param structure
-AMD_LATE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- IvrsExclusionRangeList POINTER ? ; < IVMD exclusion range descriptor
- DmiTable POINTER ? ; < DMI Interface
- AcpiPState POINTER ? ; < Acpi Pstate SSDT Table
- AcpiSrat POINTER ? ; < SRAT Table
- AcpiSlit POINTER ? ; < SLIT Table
- AcpiWheaMce POINTER ? ; < WHEA MCE Table
- AcpiWheaCmc POINTER ? ; < WHEA CMC Table
- AcpiAlib POINTER ? ; < ALIB Table
- AcpiIvrs POINTER ? ; < IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table
-AMD_LATE_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitRecovery
-; *********************************************************************
- ; CPU Recovery Parameters
-AMD_CPU_RECOVERY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard Header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics
-AMD_CPU_RECOVERY_PARAMS ENDS
-
- ; AmdInitRecovery param structure
-AMD_RECOVERY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- MemConfig MEM_PARAMETER_STRUCT {} ; < Memory post param
- CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < The cached memory region. And the max cache region is 3
- CpuRecoveryParams AMD_CPU_RECOVERY_PARAMS {} ; < Params for CPU related recovery init.
-AMD_RECOVERY_PARAMS ENDS
-
-
-; *********************************************************************
-; * Interface call: AmdInitResume
-; *********************************************************************
- ; AmdInitResume param structure
-AMD_RESUME_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < Platform operational characteristics
- S3DataBlock AMD_S3_PARAMS {} ; < Save state data
-AMD_RESUME_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdS3LateRestore
-; *********************************************************************
- ; AmdS3LateRestore param structure
-AMD_S3LATE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- S3DataBlock AMD_S3_PARAMS {} ; < Save state data
-AMD_S3LATE_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdS3Save
-; *********************************************************************
- ; AmdS3Save param structure
-AMD_S3SAVE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- S3DataBlock AMD_S3_PARAMS {} ; < Standard header
- FchInterface FCH_INTERFACE {} ; FCH configuration
-AMD_S3SAVE_PARAMS ENDS
-
- ; General Services API
-
-
-; *********************************************************************
-; * Interface service call: AmdGetApicId
-; *********************************************************************
- ; Request the APIC ID of a particular core.
-
-AMD_APIC_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- Socket UINT8 ? ; < The Core's Socket.
- Core UINT8 ? ; < The Core id.
- IsPresent BOOLEAN ? ; < The Core is present, and ApicAddress is valid.
- ApicAddress UINT8 ? ; < The Core's APIC ID.
-AMD_APIC_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdGetPciAddress
-; *********************************************************************
- ; Request the PCI Address of a Processor Module (that is, its Northbridge)
-
-AMD_GET_PCI_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- Socket UINT8 ? ; < The Processor's socket
- Module UINT8 ? ; < The Module in that Processor
- IsPresent BOOLEAN ? ; < The Core is present, and PciAddress is valid.
- PciAddress PCI_ADDR {} ; < The Processor's PCI Config Space address (Function 0, Register 0)
-AMD_GET_PCI_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdIdentifyCore
-; *********************************************************************
- ; Request the identity (Socket, Module, Core) of the current Processor Core
-
-AMD_IDENTIFY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- Socket UINT8 ? ; < The current Core's Socket
- Module UINT8 ? ; < The current Core's Processor Module
- Core UINT8 ? ; < The current Core's core id.
-AMD_IDENTIFY_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdReadEventLog
-; *********************************************************************
- ; An Event Log Entry.
-EVENT_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- EventClass UINT32 ? ; < The severity of this event, matches AGESA_STATUS.
- EventInfo UINT32 ? ; < The unique event identifier, zero means "no event".
- DataParam1 UINT32 ? ; < Data specific to the Event.
- DataParam2 UINT32 ? ; < Data specific to the Event.
- DataParam3 UINT32 ? ; < Data specific to the Event.
- DataParam4 UINT32 ? ; < Data specific to the Event.
-EVENT_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdIdentifyDimm
-; *********************************************************************
- ; Request the identity of dimm from system address
-
-AMD_IDENTIFY_DIMM STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- MemoryAddress UINT64 ? ; < System Address that needs to be translated to dimm identification.
- SocketId UINT8 ? ; < The socket on which the targeted address locates.
- MemChannelId UINT8 ? ; < The channel on which the targeted address locates.
- DimmId UINT8 ? ; < The dimm on which the targeted address locates.
-AMD_IDENTIFY_DIMM ENDS
-
- ; Data structure for the Mapping Item between Unified ID for IDS Setup Option
- ; and the option value.
-
-IDS_NV_ITEM STRUCT
- IdsNvId UINT16 ? ; < Unified ID for IDS Setup Option.
- IdsNvValue UINT16 ? ; < The value of IDS Setup Option.
-IDS_NV_ITEM ENDS
-
- ; Data Structure for IDS CallOut Function
-IDS_CALLOUT_STRUCT STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < The Standard Header for AGESA Service
- IdsNvPtr POINTER ? ; < Memory Pointer of IDS NV Table
- Reserved UINT32 ? ; < reserved
-IDS_CALLOUT_STRUCT ENDS
-
- AGESA_IDS_DFT_VAL EQU 0FFFFh; < Default value of every uninitlized NV item, the action for it will be ignored
- AGESA_IDS_NV_END EQU 0FFFFh; < Flag specify end of option structure
-; WARNING: Don't change the comment below, it used as signature for script
-; AGESA IDS NV ID Definitions
- AGESA_IDS_EXT_ID_START EQU 0000h; < specify the start of external NV id
-
- AGESA_IDS_NV_UCODE EQU 0001h; < Enable or disable microcode patching
-
- AGESA_IDS_NV_TARGET_PSTATE EQU 0002h; < Set the P-state required to be activated
- AGESA_IDS_NV_POSTPSTATE EQU 0003h; < Set the P-state required to be activated through POST
-
- AGESA_IDS_NV_BANK_INTERLEAVE EQU 0004h; < Enable or disable Bank Interleave
- AGESA_IDS_NV_CHANNEL_INTERLEAVE EQU 0005h; < Enable or disable Channel Interleave
- AGESA_IDS_NV_NODE_INTERLEAVE EQU 0006h; < Enable or disable Node Interleave
- AGESA_IDS_NV_MEMHOLE EQU 0007h; < Enables or disable memory hole
-
- AGESA_IDS_NV_SCRUB_REDIRECTION EQU 0008h; < Enable or disable a write to dram with corrected data
- AGESA_IDS_NV_DRAM_SCRUB EQU 0009h; < Set the rate of background scrubbing for DRAM
- AGESA_IDS_NV_DCACHE_SCRUB EQU 000Ah; < Set the rate of background scrubbing for the DCache.
- AGESA_IDS_NV_L2_SCRUB EQU 000Bh; < Set the rate of background scrubbing for the L2 cache
- AGESA_IDS_NV_L3_SCRUB EQU 000Ch; < Set the rate of background scrubbing for the L3 cache
- AGESA_IDS_NV_ICACHE_SCRUB EQU 000Dh; < Set the rate of background scrubbing for the Icache
- AGESA_IDS_NV_SYNC_ON_ECC_ERROR EQU 000Eh; < Enable or disable the sync flood on un-correctable ECC error
- AGESA_IDS_NV_ECC_SYMBOL_SIZE EQU 000Fh; < Set ECC symbol size
-
- AGESA_IDS_NV_ALL_MEMCLKS EQU 0010h; < Enable or disable all memory clocks enable
- AGESA_IDS_NV_DCT_GANGING_MODE EQU 0011h; < Set the Ganged mode
- AGESA_IDS_NV_DRAM_BURST_LENGTH32 EQU 0012h; < Set the DRAM Burst Length 32
- AGESA_IDS_NV_MEMORY_POWER_DOWN EQU 0013h; < Enable or disable Memory power down mode
- AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE EQU 0014h; < Set the Memory power down mode
- AGESA_IDS_NV_DLL_SHUT_DOWN EQU 0015h; < Enable or disable DLLShutdown
- AGESA_IDS_NV_ONLINE_SPARE EQU 0016h; < Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap
-
- AGESA_IDS_NV_HT_ASSIST EQU 0017h; < Enable or Disable HT Assist
- AGESA_IDS_NV_ATMMODE EQU 0018h; < Enable or Disable ATM mode
-
- AGESA_IDS_NV_HDTOUT EQU 0019h; < Enable or disable HDTOUT feature
-
- AGESA_IDS_NV_HTLINKSOCKET EQU 001Ah; < HT Link Socket
- AGESA_IDS_NV_HTLINKPORT EQU 001Bh; < HT Link Port
- AGESA_IDS_NV_HTLINKFREQ EQU 001Ch; < HT Link Frequency
- AGESA_IDS_NV_HTLINKWIDTHIN EQU 001Dh; < HT Link In Width
- AGESA_IDS_NV_HTLINKWIDTHOUT EQU 001Eh; < HT Link Out Width
-
- AGESA_IDS_NV_GNBHDAUDIOEN EQU 001Fh; < Enable or disable GNB HD Audio
-
- AGESA_IDS_NV_CPB_EN EQU 0020h; < Core Performance Boost
-
- AGESA_IDS_NV_HTC_EN EQU 0021h; < HTC Enable
- AGESA_IDS_NV_HTC_OVERRIDE EQU 0022h; < HTC Override
- AGESA_IDS_NV_HTC_PSTATE_LIMIT EQU 0023h; < HTC P-state limit select
- AGESA_IDS_NV_HTC_TEMP_HYS EQU 0024h; < HTC Temperature Hysteresis
- AGESA_IDS_NV_HTC_ACT_TEMP EQU 0025h; < HTC Activation Temp
-
- AGESA_IDS_NV_POWER_POLICY EQU 0026h; < Select Platform Power Policy
- AGESA_IDS_EXT_ID_END EQU 0027h; < specify the end of external NV ID
-
- IDS_EX_NV_ID TEXTEQU <DWORD>
diff --git a/src/vendorcode/amd/agesa/f12/Legacy/amd.inc b/src/vendorcode/amd/agesa/f12/Legacy/amd.inc
deleted file mode 100644
index 389efba986..0000000000
--- a/src/vendorcode/amd/agesa/f12/Legacy/amd.inc
+++ /dev/null
@@ -1,461 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * Agesa structures and definitions
-; *
-; * Contains AMD AGESA core interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
-;
-; ****************************************************************************
-; *
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; *
-; **************************************************************************
-
-
-UINT64 TEXTEQU <QWORD>
-UINT32 TEXTEQU <DWORD>
-UINT16 TEXTEQU <WORD>
-UINT8 TEXTEQU <BYTE>
-CHAR8 TEXTEQU <BYTE>
-BOOLEAN TEXTEQU <BYTE>
-POINTER TEXTEQU <DWORD>
-
- ; AGESA Types and Definitions
-
- AGESA_REVISION EQU "Arch2008"
- AGESA_ID EQU "AGESA"
-
- LAST_ENTRY EQU 0FFFFFFFFh
- IMAGE_SIGNATURE EQU 'DMA$'
- IOCF8 EQU 0CF8h
- IOCFC EQU 0CFCh
-
- ; The return status for all AGESA public services.
-
- ; Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
- ; will have log entries with more detail.
-
- AGESA_SUCCESS EQU 0 ; < The service completed normally. Info may be logged.
- AGESA_UNSUPPORTED EQU 1 ; < The dispatcher or create struct had an unimplemented function requested.
- ; < Not logged.
- AGESA_BOUNDS_CHK EQU 2 ; < A dynamic parameter was out of range and the service was not provided.
- ; < Example, memory address not installed, heap buffer handle not found.
- ; < Not Logged.
- ; AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
- AGESA_ALERT EQU 3 ; < An observed condition, but no loss of function.
- ; < See log. Example, HT CRC.
- AGESA_WARNING EQU 4 ; < Possible or minor loss of function. See Log.
- AGESA_ERROR EQU 5 ; < Significant loss of function, boot may be possible. See Log.
- AGESA_CRITICAL EQU 6 ; < Continue boot only to notify user. See Log.
- AGESA_FATAL EQU 7 ; < Halt booting. See Log.
- AgesaStatusMax EQU 8 ; < Not a status, use for limit checking.
-AGESA_STATUS TEXTEQU <DWORD>
-
-; For checking whether a status is at or above the mandatory log level.
-AGESA_STATUS_LOG_LEVEL EQU AGESA_ALERT
-
- CALLOUT_ENTRY TEXTEQU <POINTER>
- IMAGE_ENTRY TEXTEQU <POINTER>
- MODULE_ENTRY TEXTEQU <POINTER>
-
-; This allocation type is used by the AmdCreateStruct entry point
- PreMemHeap EQU 0 ; < Create heap in cache.
- PostMemDram EQU 1 ; < Create heap in memory.
- ByHost EQU 2 ; < Create heap by Host.
-ALLOCATION_METHOD TEXTEQU <DWORD>
-
- ; These width descriptors are used by the library function, and others, to specify the data size
- AccessWidth8 EQU 1 ; < Access width is 8 bits.
- AccessWidth16 EQU 2 ; < Access width is 16 bits.
- AccessWidth32 EQU 3 ; < Access width is 32 bits.
- AccessWidth64 EQU 4 ; < Access width is 64 bits.
-
- AccessS3SaveWidth8 EQU 81h ; < Save 8 bits data.
- AccessS3SaveWidth16 EQU 130 ; < Save 16 bits data.
- AccessS3SaveWidth32 EQU 131 ; < Save 32 bits data.
- AccessS3SaveWidth64 EQU 132 ; < Save 64 bits data.
-ACCESS_WIDTH TEXTEQU <DWORD>
-
- ; AGESA struct name
-
- ; AGESA BASIC FUNCTIONS
- AMD_INIT_RECOVERY EQU 00020000h
- AMD_CREATE_STRUCT EQU 00020001h
- AMD_INIT_EARLY EQU 00020002h
- AMD_INIT_ENV EQU 00020003h
- AMD_INIT_LATE EQU 00020004h
- AMD_INIT_MID EQU 00020005h
- AMD_INIT_POST EQU 00020006h
- AMD_INIT_RESET EQU 00020007h
- AMD_INIT_RESUME EQU 00020008h
- AMD_RELEASE_STRUCT EQU 00020009h
- AMD_S3LATE_RESTORE EQU 0002000Ah
- AMD_S3_SAVE EQU 0002000Bh
- AMD_GET_APIC_ID EQU 0002000Ch
- AMD_GET_PCI_ADDRESS EQU 0002000Dh
- AMD_IDENTIFY_CORE EQU 0002000Eh
- AMD_READ_EVENT_LOG EQU 0002000Fh
- AMD_GET_EXECACHE_SIZE EQU 00020010h
- AMD_LATE_RUN_AP_TASK EQU 00020011h
- AMD_IDENTIFY_DIMMS EQU 00020012h
-AGESA_STRUCT_NAME TEXTEQU <DWORD>
-
-
- ; ResetType constant values
- WARM_RESET_WHENEVER EQU 1
- COLD_RESET_WHENEVER EQU 2
- WARM_RESET_IMMEDIATELY EQU 3
- COLD_RESET_IMMEDIATELY EQU 4
-
-
- ; AGESA Structures
-
- ; The standard header for all AGESA services.
-AMD_CONFIG_PARAMS STRUCT
- ImageBasePtr UINT32 ? ; < The AGESA Image base address.
- Func UINT32 ? ; < The service desired, @sa dispatch.h.
- AltImageBasePtr UINT32 ? ; < Alternate Image location
- CalloutPtr CALLOUT_ENTRY ? ; < For Callout from AGESA
- HeapStatus UINT8 ? ; < For heap status from boot time slide.
- HeapBasePtr UINT64 ? ; < Location of the heap
- Reserved UINT8 (7) DUP (?) ; < This space is reserved for future use.
-AMD_CONFIG_PARAMS ENDS
-
-
- ; Create Struct Interface.
-AMD_INTERFACE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Config header
- AgesaFunctionName AGESA_STRUCT_NAME ? ; < The service to init, @sa dispatch.h
- AllocationMethod ALLOCATION_METHOD ? ; < How to handle buffer allocation
- NewStructSize UINT32 ? ; < The size of the allocated data, in for ByHost, else out only.
- NewStructPtr POINTER ? ; < The struct for the service.
- ; < The struct to init for ByHost allocation,
- ; < the initialized struct on return.
-AMD_INTERFACE_PARAMS ENDS
-
- FUNC_0 EQU 0 ; bit-placed for PCI address creation
- FUNC_1 EQU 1
- FUNC_2 EQU 2
- FUNC_3 EQU 3
- FUNC_4 EQU 4
- FUNC_5 EQU 5
- FUNC_6 EQU 6
- FUNC_7 EQU 7
-
- ; AGESA Binary module header structure
-AMD_IMAGE_HEADER STRUCT
- Signature UINT32 ? ; < Binary Signature
- CreatorID CHAR8 (8) DUP (?) ; < 8 characters ID
- Version CHAR8 (12) DUP (?) ; < 12 characters version
- ModuleInfoOffset UINT32 ? ; < Offset of module
- EntryPointAddress UINT32 ? ; < Entry address
- ImageBase UINT32 ? ; < Image base
- RelocTableOffset UINT32 ? ; < Relocate Table offset
- ImageSize UINT32 ? ; < Size
- Checksum UINT16 ? ; < Checksum
- ImageType UINT8 ? ; < Type
- V_Reserved UINT8 ? ; < Reserved
-AMD_IMAGE_HEADER ENDS
- ; AGESA Binary module header structure
-AMD_MODULE_HEADER STRUCT
- ModuleHeaderSignature UINT32 ? ; < Module signature
- ModuleIdentifier CHAR8 (8) DUP (?) ; < 8 characters ID
- ModuleVersion CHAR8 (12) DUP (?) ; < 12 characters version
- ModuleDispatcher POINTER ? ; < A pointer point to dispatcher
- NextBlock POINTER ? ; < Next module header link
-AMD_MODULE_HEADER ENDS
-
-; AMD_CODE_HEADER Signatures.
-AGESA_CODE_SIGNATURE TEXTEQU <'!', '!', 'A', 'G', 'E', 'S', 'A', ' '>
-CIMXNB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'>
-CIMXSB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'>
-
-; AGESA_CODE_SIGNATURE
-AMD_CODE_HEADER STRUCT
- Signature CHAR8 (8) DUP (?) ; < code header Signature
- ComponentName CHAR8 (8) DUP (?) ; < 8 character name of the code module
- Version CHAR8 (12) DUP (?) ; < 12 character version string
- TerminatorNull CHAR8 ? ; < null terminated string
- VerReserved CHAR8 (7) DUP (?) ; < reserved space
-AMD_CODE_HEADER ENDS
-
- ; Extended PCI address format
-EXT_PCI_ADDR STRUCT
- Register UINT32 ?
-; IN OUT UINT32 Register:12; ; < Register offset
-; IN OUT UINT32 Function:3; ; < Function number
-; IN OUT UINT32 Device:5; ; < Device number
-; IN OUT UINT32 Bus:8; ; < Bus number
-; IN OUT UINT32 Segment:4; ; < Segment
-EXT_PCI_ADDR ENDS
-
- ; Union type for PCI address
-PCI_ADDR UNION
- AddressValue UINT32 ? ; < Formal address
- Address EXT_PCI_ADDR {} ; < Extended address
-PCI_ADDR ENDS
-
- ; SBDFO - Segment Bus Device Function Offset
- ; 31:28 Segment (4-bits)
- ; 27:20 Bus (8-bits)
- ; 19:15 Device (5-bits)
- ; 14:12 Function(3-bits)
- ; 11:00 Offset (12-bits)
-
-
-
- ILLEGAL_SBDFO EQU 0FFFFFFFFh
-
- ; CPUID data received registers format
-CPUID_DATA STRUCT
- EAX_Reg UINT32 ? ; < CPUID instruction result in EAX
- EBX_Reg UINT32 ? ; < CPUID instruction result in EBX
- ECX_Reg UINT32 ? ; < CPUID instruction result in ECX
- EDX_Reg UINT32 ? ; < CPUID instruction result in EDX
-CPUID_DATA ENDS
-
- ; HT frequency for external callbacks
-;typedef enum {
- HT_FREQUENCY_200M EQU 0 ; < HT speed 200 for external callbacks
- HT_FREQUENCY_400M EQU 2 ; < HT speed 400 for external callbacks
- HT_FREQUENCY_600M EQU 4 ; < HT speed 600 for external callbacks
- HT_FREQUENCY_800M EQU 5 ; < HT speed 800 for external callbacks
- HT_FREQUENCY_1000M EQU 6 ; < HT speed 1000 for external callbacks
- HT_FREQUENCY_1200M EQU 7 ; < HT speed 1200 for external callbacks
- HT_FREQUENCY_1400M EQU 8 ; < HT speed 1400 for external callbacks
- HT_FREQUENCY_1600M EQU 9 ; < HT speed 1600 for external callbacks
- HT_FREQUENCY_1800M EQU 10 ; < HT speed 1800 for external callbacks
- HT_FREQUENCY_2000M EQU 11 ; < HT speed 2000 for external callbacks
- HT_FREQUENCY_2200M EQU 12 ; < HT speed 2200 for external callbacks
- HT_FREQUENCY_2400M EQU 13 ; < HT speed 2400 for external callbacks
- HT_FREQUENCY_2600M EQU 14 ; < HT speed 2600 for external callbacks
- HT_FREQUENCY_2800M EQU 17 ; < HT speed 2800 for external callbacks
- HT_FREQUENCY_3000M EQU 18 ; < HT speed 3000 for external callbacks
- HT_FREQUENCY_3200M EQU 19 ; < HT speed 3200 for external callbacks
- HT_FREQUENCY_MAX EQU 20 ; < Limit Check.
-HT_FREQUENCIES TEXTEQU <DWORD> ;} HT_FREQUENCIES;
-
-HT3_FREQUENCY_MIN EQU HT_FREQUENCY_1200M
-
-IFNDEF BIT0
- BIT0 EQU 0000000000000001h
-ENDIF
-IFNDEF BIT1
- BIT1 EQU 0000000000000002h
-ENDIF
-IFNDEF BIT2
- BIT2 EQU 0000000000000004h
-ENDIF
-IFNDEF BIT3
- BIT3 EQU 0000000000000008h
-ENDIF
-IFNDEF BIT4
- BIT4 EQU 0000000000000010h
-ENDIF
-IFNDEF BIT5
- BIT5 EQU 0000000000000020h
-ENDIF
-IFNDEF BIT6
- BIT6 EQU 0000000000000040h
-ENDIF
-IFNDEF BIT7
- BIT7 EQU 0000000000000080h
-ENDIF
-IFNDEF BIT8
- BIT8 EQU 0000000000000100h
-ENDIF
-IFNDEF BIT9
- BIT9 EQU 0000000000000200h
-ENDIF
-IFNDEF BIT10
- BIT10 EQU 0000000000000400h
-ENDIF
-IFNDEF BIT11
- BIT11 EQU 0000000000000800h
-ENDIF
-IFNDEF BIT12
- BIT12 EQU 0000000000001000h
-ENDIF
-IFNDEF BIT13
- BIT13 EQU 0000000000002000h
-ENDIF
-IFNDEF BIT14
- BIT14 EQU 0000000000004000h
-ENDIF
-IFNDEF BIT15
- BIT15 EQU 0000000000008000h
-ENDIF
-IFNDEF BIT16
- BIT16 EQU 0000000000010000h
-ENDIF
-IFNDEF BIT17
- BIT17 EQU 0000000000020000h
-ENDIF
-IFNDEF BIT18
- BIT18 EQU 0000000000040000h
-ENDIF
-IFNDEF BIT19
- BIT19 EQU 0000000000080000h
-ENDIF
-IFNDEF BIT20
- BIT20 EQU 0000000000100000h
-ENDIF
-IFNDEF BIT21
- BIT21 EQU 0000000000200000h
-ENDIF
-IFNDEF BIT22
- BIT22 EQU 0000000000400000h
-ENDIF
-IFNDEF BIT23
- BIT23 EQU 0000000000800000h
-ENDIF
-IFNDEF BIT24
- BIT24 EQU 0000000001000000h
-ENDIF
-IFNDEF BIT25
- BIT25 EQU 0000000002000000h
-ENDIF
-IFNDEF BIT26
- BIT26 EQU 0000000004000000h
-ENDIF
-IFNDEF BIT27
- BIT27 EQU 0000000008000000h
-ENDIF
-IFNDEF BIT28
- BIT28 EQU 0000000010000000h
-ENDIF
-IFNDEF BIT29
- BIT29 EQU 0000000020000000h
-ENDIF
-IFNDEF BIT30
- BIT30 EQU 0000000040000000h
-ENDIF
-IFNDEF BIT31
- BIT31 EQU 0000000080000000h
-ENDIF
-IFNDEF BIT32
- BIT32 EQU 0000000100000000h
-ENDIF
-IFNDEF BIT33
- BIT33 EQU 0000000200000000h
-ENDIF
-IFNDEF BIT34
- BIT34 EQU 0000000400000000h
-ENDIF
-IFNDEF BIT35
- BIT35 EQU 0000000800000000h
-ENDIF
-IFNDEF BIT36
- BIT36 EQU 0000001000000000h
-ENDIF
-IFNDEF BIT37
- BIT37 EQU 0000002000000000h
-ENDIF
-IFNDEF BIT38
- BIT38 EQU 0000004000000000h
-ENDIF
-IFNDEF BIT39
- BIT39 EQU 0000008000000000h
-ENDIF
-IFNDEF BIT40
- BIT40 EQU 0000010000000000h
-ENDIF
-IFNDEF BIT41
- BIT41 EQU 0000020000000000h
-ENDIF
-IFNDEF BIT42
- BIT42 EQU 0000040000000000h
-ENDIF
-IFNDEF BIT43
- BIT43 EQU 0000080000000000h
-ENDIF
-IFNDEF BIT44
- BIT44 EQU 0000100000000000h
-ENDIF
-IFNDEF BIT45
- BIT45 EQU 0000200000000000h
-ENDIF
-IFNDEF BIT46
- BIT46 EQU 0000400000000000h
-ENDIF
-IFNDEF BIT47
- BIT47 EQU 0000800000000000h
-ENDIF
-IFNDEF BIT48
- BIT48 EQU 0001000000000000h
-ENDIF
-IFNDEF BIT49
- BIT49 EQU 0002000000000000h
-ENDIF
-IFNDEF BIT50
- BIT50 EQU 0004000000000000h
-ENDIF
-IFNDEF BIT51
- BIT51 EQU 0008000000000000h
-ENDIF
-IFNDEF BIT52
- BIT52 EQU 0010000000000000h
-ENDIF
-IFNDEF BIT53
- BIT53 EQU 0020000000000000h
-ENDIF
-IFNDEF BIT54
- BIT54 EQU 0040000000000000h
-ENDIF
-IFNDEF BIT55
- BIT55 EQU 0080000000000000h
-ENDIF
-IFNDEF BIT56
- BIT56 EQU 0100000000000000h
-ENDIF
-IFNDEF BIT57
- BIT57 EQU 0200000000000000h
-ENDIF
-IFNDEF BIT58
- BIT58 EQU 0400000000000000h
-ENDIF
-IFNDEF BIT59
- BIT59 EQU 0800000000000000h
-ENDIF
-IFNDEF BIT60
- BIT60 EQU 1000000000000000h
-ENDIF
-IFNDEF BIT61
- BIT61 EQU 2000000000000000h
-ENDIF
-IFNDEF BIT62
- BIT62 EQU 4000000000000000h
-ENDIF
-IFNDEF BIT63
- BIT63 EQU 8000000000000000h
-ENDIF
-
diff --git a/src/vendorcode/amd/agesa/f12/Legacy/bridge32.inc b/src/vendorcode/amd/agesa/f12/Legacy/bridge32.inc
deleted file mode 100644
index ca02c3dcc6..0000000000
--- a/src/vendorcode/amd/agesa/f12/Legacy/bridge32.inc
+++ /dev/null
@@ -1,576 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * Agesa structures and definitions
-; *
-; * Contains AMD AGESA core interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
-;
-; ****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*****************************************************************************
-
-PARAM1 textequ <[bp+8]>
-PARAM2 textequ <[bp+12]>
-PARAM3 textequ <[bp+16]>
-RETAddress textequ <[bp+4]>
-
-AMD_PRIVATE_PARAMS STRUCT
- Gate16_CS DW ? ; Segment of AMD_BRIDGE_32 and AMD_CALLOUT_16
- Gate16_SS DW ? ; RM stack segment
- Router_Seg DW ? ; Segment of oem router
- Router_Off DW ? ; Offset of oem router
-AMD_PRIVATE_PARAMS ENDS
-
-; OEM may pre-define the GDT and selector offsets. If they do not, use our defaults.
-IFNDEF AGESA_SELECTOR_GDT
- AGESA_SELECTOR_GDT EQU 00h
-ENDIF
-IFNDEF AGESA_SELECTOR_CODE16
- AGESA_SELECTOR_CODE16 EQU 08h
-ENDIF
-IFNDEF AGESA_SELECTOR_DATA16
- AGESA_SELECTOR_DATA16 EQU 10h
-ENDIF
-IFNDEF AGESA_SELECTOR_CODE32
- AGESA_SELECTOR_CODE32 EQU 18h
-ENDIF
-IFNDEF AGESA_SELECTOR_DATA32
- AGESA_SELECTOR_DATA32 EQU 20h
-ENDIF
-
-
-AMD_BRIDGE_32_GDT MACRO GDT_Name:REQ
-
- GDT_Name LABEL BYTE
- DD 000000000h, 000000000h ; NULL descriptor
- DD 00000ffffh, 000009b00h ; 16-bit code, fixed up
- DD 00000ffffh, 000009300h ; 16-bit data, fixed up
- DD 00000ffffh, 000CF9B00h ; 32-bit protected mode code
- DD 00000ffffh, 000CF9300h ; 32-bit protected mode data
- GDT_Length EQU ($-GDT_Name)
-
-ENDM
-
-;+-------------------------------------------------------------------------
-;
-; AMD_BRIDGE_32 - Execute Agesa through Pushhigh interface
-;
-; Processing:
-; The following steps are taken:
-; 1) Enter 32bit Protected Mode (PM32)
-; 2) Run AGESA code
-; 3) Restore Real Mode (RM)
-;
-; Entry:
-; [big real mode] : ds, es set to base 0 limit 4G segment
-; EDX - if not 0, provides a FAR PTR to oem router (Seg | Offset)
-; ESI - configuration block pointer
-;
-; Exit:
-; EAX - return value
-; ESI - configuration block pointer
-; ds, es, fs, gs - Set to 4GB segment limit for Big Real Mode
-;
-; Modified:
-; None
-;
-
-AMD_BRIDGE_32 MACRO GDT_Name
-
- local copyGDT
- local flushTo16PM
- local agesaReturnAddress
- local leave32bitPM
- local flush2RM
-
- push gs
- push fs
- push ebx
- push ecx
- push edi
- mov eax, esp
- push eax
- movzx esp, sp
-;
-; Do not use any locals here, BP will be changed frequently during RM->PM32->RM
-;
- pushf
- cli ; Disable interrupts during AGESA
- cld ; Need known direction flag during AGESA
-
-;
-; Save the FAR PTR input parameter
-;
- mov gs, dx ; Offset
- shr edx, 16
- mov fs, dx ; Segment
-;
-; Determine where our binary file is and get entry point
-;
- mov edx, (AMD_CONFIG_PARAMS PTR [esi]).ImageBasePtr
- add edx, (AMD_IMAGE_HEADER PTR [edx]).EntryPointAddress
-;
-; Figure out the return address we will use after calling AGESA
-; and store it in ebx until we have our stack set up properly
-;
- mov ebx, cs
- shl ebx, 4
- add ebx, OFFSET agesaReturnAddress
-;
-; Save our current RM stack AND entry EBP
-;
- push ebp
-; push esp
- push ss
-
-;
-; BEGIN --- STACK MUST BE BALANCED AT THIS POINT --- BEGIN
-;
-; Copy the GDT onto the stack for modification
-;
- mov cx, GDT_Length
- sub sp, cx
- mov bp, sp
- lea di, GDT_Name
-copyGDT:
- mov al, cs:[di]
- mov [bp], al
- inc di
- inc bp
- loop copyGDT
-;
-; Patch 16-bit code and data descriptors on stack. We will
-; fix up CS and SS for PM16 during the callout if applicable.
-;
- mov bp, sp
-
- mov eax, cs
- shl eax, 4
- mov [bp+AGESA_SELECTOR_CODE16+2], ax
- shr eax, 16
- mov [bp+AGESA_SELECTOR_CODE16+4], al
-
- mov eax, ss
- shl eax, 4
- mov [bp+AGESA_SELECTOR_DATA16+2], ax
- shr eax, 16
- mov [bp+AGESA_SELECTOR_DATA16+4], al
-;
-; Need to place Length and Address on GDT
-;
- mov eax, ss
- shl eax, 4
- add eax, esp
- push eax
- push WORD PTR (GDT_Length-1)
-;
-; Load the GDT
-;
- mov bp, sp
- lgdt FWORD PTR [bp]
-;
-; TABLE 1
-;
-; Place PRIVATE DATA on stack DIRECTLY following GDT
-; During this routine, stack data is critical. If
-; order is changed or additional added, bad things
-; will happen!
-;
-; HIGHEST PHYSICAL ADDRESS
-;
-; | ... |
-; ------------------------
-; | old RM SP |
-; | old RM SS |
-; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS + (SIZEOF GDT_LENGTH + 6 {size, address})
-; | GDT_DATA32 |
-; | ... |
-; | GDT_NULL |
-; | GDT Addr, Length |
-; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS
-; | Priv.Gate16_SS |
-; | Priv.Gate16_CS |
-; ------------------------ sp
-; ------ THEN PUSH -------
-; | Return to 16-bit CS |
-; | Return to 16-bit Off |
-; | ... |
-;
-; LOWEST PHYSICAL ADDRESS
-;
- mov edi, esp
- sub edi, SIZEOF AMD_PRIVATE_PARAMS
- mov ax, cs
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS, ax
- mov ax, ss
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS, ax
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off, gs
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg, fs
-
- mov esp, edi
-;
-; Save an address for returning to 16 bit real mode on stack,
-; we'll use it in a far ret after turning off CR0.PE so that
-; we can take our address off and force a far jump. Be sure
-; no unexpected data is on the stack after this!
-;
- mov ax, cs
- push cs
- lea ax, flush2RM
- push ax
-;
-; Convert ss:esp to "flat"
-;
-
- mov ax, sp
- push ax
- mov eax, ss
- shl eax, 4
- add eax, esp
- mov esp, eax ; Load the zero based ESP
-
-;
-; Set CR0.PE
-;
- mov eax, CR0 ; Get CPU control word 0
- or al, 01 ; Enable CPU protected mode
- mov CR0, eax ; Write back to CPU control word 0
- jmp flushTo16PM
-
-flushTo16PM:
-;
-; 16-bit protected mode
-;
- mov ax, AGESA_SELECTOR_DATA32
- mov ds, ax
- mov es, ax
- mov fs, ax
- mov gs, ax
- mov ss, ax
-;
-; Push our parameters RIGHT TO LEFT, and then return address
-;
- push esi ; AGESA configuration block pointer (data)
- push ebx ; after AGESA return offset (32PM flat) - consumed by dispatcher ret
- pushd AGESA_SELECTOR_CODE32 ; AGESA entry selector (32PM flat)
- push edx ; AGESA entry point (32PM flat)
-
- DB 066h
- retf ; <><><> Enter AGESA 32-bit code!!! <><><>
-
-agesaReturnAddress:
-;
-; Returns from the Agesa 32-bit code still PM32
-;
- DB 0EAh
- DD OFFSET leave32bitPM
- DW AGESA_SELECTOR_CODE16
-
-leave32bitPM:
-;
-; Now in 16-bit PM
-;
- add esp, 4 ; +4 to remove our config block pointer
-;
-; Eax reserve AGESA_STATUS return code, save it
-;
- mov ebx, eax
-;
-; Turn off CR0.PE, restore 64K stack limit
-;
- pop ax
- mov sp, ax
- mov ax, AGESA_SELECTOR_DATA16
- mov ss, ax
-
- mov eax, CR0
- and al, NOT 1 ; Disable protected mode
- mov CR0, eax ; Write back CR0.PE
-;
-; Jump far to enter RM, we saved this address on the stack
-; already. Hopefully stack is balanced through AGESA
-; nor were any params added by pushing them on the stack and
-; not removing them between BEGIN-END comments.
-;
- retf
-
-flush2RM:
-;
-; Set segments registers for big real mode before returning
-;
- xor ax, ax
- mov ds, ax
- mov es, ax
- mov fs, ax
- mov gs, ax
-;
-; Discard GDT, +6 for GDT pointer/size, privates
-;
- add esp, GDT_Length + 6 + SIZEOF AMD_PRIVATE_PARAMS
-;
-; Restore real mode stack and entry EBP
-;
- pop cx
-; mov esp, [esp]
- mov ss, cx
- pop ebp
-;
-; Restore AGESA_STATUS return code to eax
-;
- mov eax, ebx
-;
-; END --- STACK MUST BE BALANCED TO THIS POINT --- END
-;
-
- popf
- pop ebx
- mov esp, ebx
- pop edi
- pop ecx
- pop ebx
- pop fs
- pop gs
- ; EXIT AMD_BRIDGE_32
-ENDM
-;+-------------------------------------------------------------------------
-;
-; AMD_CALLOUT_16 - Execute Callback from Pushhigh interface
-;
-; Processing:
-; The following steps are taken:
-; 1) Enter PM16
-; 2) Setup stack, get private params
-; 3) Enter RM
-; 4) Get 3 params
-; 5) Call oemCallout OR oem router
-; 6) Enter PM32
-; 7) Return to Agesa PH
-;
-; Entry:
-; [32-bit protected mode]
-; [esp+8] Func
-; [esp+12] Data
-; [esp+16] Configuration Block
-; [esp+4] return address to Agesa
-;
-; Exit:
-; [32-bit protected mode]
-;
-; Modified:
-; None
-;
-AMD_CALLOUT_16 MACRO LocalOemCalloutRouter
-;
-; Note that we are still PM32, so MASM may work strangely
-;
-
- push bp ; Save our original SP to access params
- mov bp, sp
- push bx
- push si
- push di
- push cx
- push dx
- push di
-
- DB 066h, 0EAh
- DW OFFSET PM16Entry
- DW AGESA_SELECTOR_CODE16
-
-PM16Entry:
-;
-; PM16 CS, but still PM32 SS, as we need to access our private params
-; before we enter RM.
-;
-; Note: we are working below the stack temporarily, and and it will
-; not affect our ability to get entry params
-;
- xor ecx, ecx
- xor edx, edx
-;
-; SGDT will give us the original location of the GDT on our CAS stack.
-; We need this value because our private parameters are located just
-; below the GDT.
-;
- mov edi, esp
- sub edi, GDT_Length + 6
- sgdt FWORD PTR [edi] ; [edi] = word size, dword address
- mov edi, DWORD PTR [edi+2] ; Get the PM32 address only
- sub edi, SIZEOF AMD_PRIVATE_PARAMS + 6
-;
-; cx = code segment of this code in RM
-; dx = stack segment of CAS in RM
-; fs = code segment of oem router (save for later)
-; gs = offset of oem router (save for later)
-; fs and gs are loaded after switch to real mode because we can't
-; use them as scratch pad registers in protected mode
-;
- mov cx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS
- mov dx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS
-
- mov eax, edi ; Save edi in eax for after RM switch
- mov edi, esp ; Save our current ESP for RM
-
- movzx ebx, dx
- shl ebx, 4
- sub esp, ebx
-
-;
-; We had been accessing the stack in PM32, we will now change to PM16 so we
-; will make the stack segment 64KB limit so SP needs to be fixed made PM16
-; compatible.
-;
- mov bx, AGESA_SELECTOR_DATA16
- mov ss, bx
-
-;
-; Save the RM segment and RM offset of the jump we will need to make in
-; order to enter RM so that code in this segment is relocatable.
-;
-; BEGIN --- Don't unbalance the stack --- BEGIN
-;
- push cx
- pushw OFFSET RMEntry
-
- mov ebx, CR0
- and bl, NOT 1
- mov CR0, ebx ; CR0.PE cleared
-;
-; Far jump to clear segment descriptor cache and enter RM
-;
- retf
-
-RMEntry:
-;
-; We are in RM, setup RM stack
-;
- movzx ebx, dx ; Get RM SS in ebx
- shl ebx, 4 ; Get our stack top on entry in EBP to
- sub ebp, ebx ; access our entry parameters
- sub eax, ebx ; save copy of parameters address
- mov ss, dx ; Set stack segment
-;
-; We are going to figure out the address to use when we return
-; and have to go back into PM32 while we have access to it
-;
- movzx ebx, cx ; Get original CS in ebx
- shl ebx, 4
- add ebx, OFFSET PM32Entry
-;
-; Now we put our data, func, block params into calling convention
-; for our hook
-;
-; ECX = Func
-; EDX = Data
-; ESI = config pointer
-;
- mov ecx, PARAM1 ; Func
- mov edx, PARAM2 ; Data
- mov esi, PARAM3 ; pointer
-
- push ebx ; Save PM32 mode switch address
- push edi ; Save PM32 stack pointer
- pushf
-;
-; Get Router Function Address
-;
- mov edi, eax
- mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg
- mov fs, ax
- mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off
- mov gs, ax
-
- mov eax, AGESA_UNSUPPORTED ; Default return value
-;
-; If AMD_BRIDGE_32 EDX == 0 call oemCallout
-; otherwise call FAR PTR EDX
-;
-; Critical:
-; sp+2 - EDI aka PM32 stack address
-; sp+4 - address of PM32Entry in PM32
-;
- mov bx, fs
- shl ebx, 16
- mov bx, gs
-
- .if (ebx == 0)
- call LocalOemCalloutRouter
- .else
-;
-; Make far call to Router function
-;
- push cs
- push offset CalloutReturn
- push ebx
- retf
-CalloutReturn:
- .endif
-;
-; Restore PM32 esp from RM stack
-;
- popf
- pop edi ; Our PM32 stack pointer
- pop edx ; Our PM32 mode switch address
-
- mov ebx, CR0
- or bl, 1 ; CR0.PE set
- mov CR0, ebx
-
- mov ebx, AGESA_SELECTOR_DATA32
- pushd AGESA_SELECTOR_CODE32 ; PM32 selector
- push edx ; PM32 entry point
-
- DB 066h
- retf ; Far jump to enter PM32
-
-PM32Entry:
-;
-; END --- Don't unbalance the stack --- END
-; We are now PM32, so remember MASM is assembling in 16-bit again
-;
- mov ss, bx
- mov ds, bx
- mov es, bx
- mov fs, bx
- mov gs, bx
-
- mov sp, di
- pop di
- pop dx
- pop cx
- pop di
- pop si
- pop bx
- pop bp
- ; EXIT AMD_CALLOUT_16
-ENDM
diff --git a/src/vendorcode/amd/agesa/f12/cpcarmac.inc b/src/vendorcode/amd/agesa/f12/cpcarmac.inc
deleted file mode 100644
index ecbdd9c2c1..0000000000
--- a/src/vendorcode/amd/agesa/f12/cpcarmac.inc
+++ /dev/null
@@ -1,452 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; Workfile: cpcarmac.inc $Revision:: 44324 $ $Date:: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
-;
-; Description: Code to setup and break down cache-as-stack
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*****************************************************************************
-
- .XLIST
- INCLUDE cpcar.inc
- .LIST
- .586P
- .mmx
-
-;======================================================================
-; AMD_ENABLE_STACK: Setup a stack
-;
-; In:
-; EBX = Return address (preserved)
-;
-; Out:
-; SS:ESP - Our new private stack location
-;
-; EAX = AGESA_STATUS
-; EDX = Return status code if EAX contains a return code of higher
-; severity than AGESA_SUCCESS
-; ECX = Stack size in bytes
-;
-; Requirements:
-; * This routine presently is limited to a max of 64 processor cores
-; Preserved:
-; ebx ebp
-; Destroyed:
-; eax, ecx, edx, edi, esi, ds, es, ss, esp
-; mmx0, mmx1
-;
-; Description:
-; Fixed MTRR address allocation to cores:
-; The BSP gets 64K of stack, Core0 of each node gets 16K of stack, all other cores get 4K.
-; There is a max of 1 BSP, 7 core0s and 56 other cores.
-; Although each core has it's own cache storage, they share the address space. Each core must
-; be assigned a private and unique address space for its stack. To support legacy systems,
-; the stack needs to be within the legacy address space (1st 1Meg). Room must also be reserved
-; for the other legacy elements (Interrupt vectors, BIOS ROM, video buffer, etc.)
-;
-; 80000h 40000h 00000h
-; +----------+----------+----------+----------+----------+----------+----------+----------+
-; 64K | | | | | | | | | 64K ea
-; ea +----------+----------+----------+----------+----------+----------+----------+----------+
-; | MTRR 0000_0250 MTRRfix64K_00000 |
-; +----------+----------+----------+----------+----------+----------+----------+----------+
-; | 7 , 6 | 5 , 4 | 3 , 2 | 1 , 0 | 0 | | | | <-node
-; |7..1,7..1 |7..1,7..1 |7..1,7..1 |7..1,7..1 | 0 | | | | <-core
-; +----------+----------+----------+----------+----------+----------+----------+----------+
-;
-; C0000h B0000h A0000h 90000h 80000h
-; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
-;16K | | | | | | | | | | | | | | | | |
-; ea +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
-; | MTRR 0259 MTRRfix16K_A0000 | MTRR 0258 MTRRfix16K_80000 |
-; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
-; | > Dis|play B|uffer | < | | | | | 7 | 6 | 5 | 4 | 3 | 2 | 1 | | <-node
-; | > T| e m |p o r |a r y | B u |f f e |r A |r e a<| 0 | 0 | 0 | 0 | 0 | 0 | 0 | | <-core
-; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
-;
-; E0000h D0000h C0000h
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; 4K | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
-; ea +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | 026B MTRRfix4K_D8000 | 026A MTRRfix4K_D0000 | 0269 MTRRfix4K_C8000 | 0268 MTRRfix4K_C0000 |
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | | | | | | | | | | | | | | | | | >| V| I| D| E| O| |B |I |O |S | |A |r |e |a<|
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-;
-; 100000h F0000h E0000h
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | 026F MTRRfix4K_F8000 | 026E MTRRfix4K_F0000 | 026D MTRRfix4K_E8000 | 026C MTRRfix4K_E0000 |
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< |
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-;======================================================================
-AMD_ENABLE_STACK MACRO
- local AmdEnableStackExit
-
-; Note that SS:ESP will be default stack. Note that this stack
-; routine will not be used after memory has been initialized. Because
-; of its limited lifetime, it will not conflict with typical PCI devices.
- movd mm0, ebx ; Put return address in a safe place
- movd mm1, ebp ; Save some other user registers
-
- ; get node id and core id of current executing core
- GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
- ; Note: ESI[31:24] are used for flags: Unrecognized Family, Is_Primary core, Stack already established
-
- ; If we detected an unknown processor family or core combination, return AGESA_FATAL.
- .if (esi & (1 SHL FLAG_UNKNOWN_FAMILY))
- mov edx, CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY
- mov eax, AGESA_FATAL
- jmp AmdEnableStackExit
- .elseif (esi & (1 SHL FLAG_CORE_NOT_IDENTIFIED))
- mov edx, CPU_EVENT_CORE_NOT_IDENTIFIED
- mov eax, AGESA_FATAL
- jmp AmdEnableStackExit
- .endif
-
- ; determine if stack is already enabled. We are using the DefType MSR for this determination.
- ; It is =0 after reset; CAR setup sets it to enable the MTRRs
- mov eax, cr0 ; Is cache enabled? (CD or NW bit set)
- CR0_MASK TEXTEQU %((1 SHL CR0_CD) OR (1 SHL CR0_NW))
- .if (!(eax & CR0_MASK))
- mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF
- _RDMSR ; Are either of the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)
- MSR_MASK TEXTEQU %((1 SHL MTRR_DEF_TYPE_EN)+(1 SHL MTRR_DEF_TYPE_FIX_EN))
- .if (eax & MSR_MASK)
- bts esi, FLAG_STACK_REENTRY ; indicate stack has already been initialized
- .endif
- .endif
-
- ; Set node to map the first 16MB to node 0; 0000_0000 to 00FF_FFFF as DRAM
- mov ebx, esi ; Get my Node/Core info
- xor bl, bl
- shl bh, 3 ; Isolate my node#, match alignment for PCI Dev#
- mov eax, 8000C144h ; D18F1x44:DRAM Base/Limit; N is Base, N+4 is Limit
- add ah, bh
- mov ebx, eax ; Save PCI address for Base/Limit pair
-
- mov dx, 0CF8h
- out dx, eax
- add dx, 4
- xor eax, eax ; Least Significant bit is AD24 so 0 sets mask of 00FF_FFFF (16MB)
- out dx, eax ; DRAM Limit = node0, no interleave
-
- mov eax, ebx
- sub eax, 4 ; Now point to the Base register
- mov dx, 0CF8h
- out dx, eax
- add dx, 4
- mov eax, 00000003h ; Set the read and write enable bits
- out dx, eax ; DRAM Base = 0x0000, R/W
-
- AMD_ENABLE_STACK_FAMILY_HOOK
-
- ; Init CPU MSRs for our init routines
- mov ecx, MTRR_SYS_CFG ; SYS_CFG
- _RDMSR
- bts eax, MTRR_FIX_DRAM_MOD_EN ; Turn on modification enable bit
- _WRMSR
-
- mov eax, esi
- bt eax, FLAG_STACK_REENTRY ; Is this a 2nd entry?
- .if (!carry?) ; On a re-entry, do not clear MTRRs or reset TOM; just reset the stack SS:ESP
- bt eax, FLAG_IS_PRIMARY ; Is this core the primary in a compute unit?
- .if (carry?) ; Families using shared groups do not need to clear the MTRRs since that is done at power-on reset
- ; Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores
- ; Clear all variable and Fixed MTRRs for non-shared cores
- mov ecx, AMD_MTRR_VARIABLE_BASE0
- xor eax, eax
- xor edx, edx
- .while (cl != 10h) ; Variable MTRRphysBase[n] and MTRRphysMask[n]
- _WRMSR
- inc cl
- .endw
- mov cx, AMD_MTRR_FIX64k_00000 ; MSR:0000_0250
- _WRMSR
- mov cx, AMD_MTRR_FIX16k_80000 ; MSR:0000_0258
- _WRMSR
- mov cx, AMD_MTRR_FIX16k_A0000 ; MSR:0000_0259
- _WRMSR
- mov cx, AMD_MTRR_FIX4k_C0000 ; Fixed 4Ks: MTRRfix4K_C0000 to MTRRfix4K_F8000
- .while (cl != 70h)
- _WRMSR
- inc cl
- .endw
-
- ; Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init.
- ; - not strictly needed since the FixedMTRRs take presedence.
- mov eax, (16 * 1024 * 1024)
- mov ecx, TOP_MEM ; MSR:C001_001A
- _WRMSR
- .endif ; End Is_Primary
- .endif ; End Stack_ReEntry
-
- ; Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores
- xor eax, eax
- xor edx, edx
- mov ecx, IORR_BASE ; MSR:C001_0016 - 0019
- .while (cl != 1Ah)
- _WRMSR
- inc cl
- .endw
- mov ecx, TOP_MEM2 ; MSR:C001_001D
- _WRMSR
-
- ; setup MTRRs for stacks
- ; A speculative read can be generated by a speculative fetch mis-aligned in a code zone
- ; or due to a data zone being interpreted as code. When a speculative read occurs outside a
- ; controlled region (intentionally used by software), it could cause an unwanted cache eviction.
- ; To prevent speculative reads from causing an eviction, the unused cache ranges are set
- ; to UC type. Only the actively used regions (stack, heap) are reflected in the MTRRs.
- ; Note: some core stack regions will share an MTRR since the control granularity is much
- ; larger than the allocated stack zone. The allocation algorithm must account for this 'extra'
- ; space covered by the MTRR when parseling out cache space for the various uses. In some cases
- ; this could reduce the amount of EXE cache available to a core. see cpuCacheInit.c
- ;
- ; Outcome of this block is that: (Note the MTRR map at the top of the file)
- ; ebp - start address of stack block
- ; ebx - [31:16] - MTRR MSR address
- ; - [15:8] - slot# in MTRR register
- ; - [7:0] - block size in #4K blocks
- ; review: ESI[31:24]=Flags; SI[15,8]= Node#; SI[7,0]= core# (relative to node)
- ;
-
- mov ax, si ; Load node, core
- .if (al == 0) ; Is a core 0?
- .if (ah == 0) ; Is Node 0? (BSP)
- ; Is BSP, assign a 64K stack
- mov ebx, ((AMD_MTRR_FIX64k_00000 SHL 16) + (3 SHL 8) + (BSP_STACK_SIZE / 1000h))
- mov ebp, BSP_STACK_BASE_ADDR
- .else ; node 1 to 7, core0
- ; Is a Core0 of secondary node, assign 16K stacks
- mov bx, AMD_MTRR_FIX16k_80000
- shl ebx, 16 ;
- mov bh, ah ; Node# is used as slot#
- mov bl, (CORE0_STACK_SIZE / 1000h)
- mov al, ah ; Base = (Node# * Size);
- mul bl ;
- movzx eax, ax ;
- shl eax, 12 ; Expand back to full byte count (* 4K)
- add eax, CORE0_STACK_BASE_ADDR
- mov ebp, eax
- .endif
- .else ;core 1 thru core 7
- ; Is core 1-7 of any node, assign 4K stacks
- mov al, 8 ; CoreIndex = ( (Node# * 8) ...
- mul ah ;
- mov bx, si ;
- add al, bl ; ... + Core#);
-
- mov bx, AMD_MTRR_FIX64k_00000
- shl ebx, 16 ;
- mov bh, al ; Slot# = (CoreIndex / 16) + 4;
- shr bh, 4 ;
- add bh, 4 ;
- mov bl, (CORE1_STACK_SIZE / 1000h)
-
- mul bl ; Base = ( (CoreIndex * Size) ...
- movzx eax, ax ;
- shl eax, 12 ; Expand back to full byte count (* 4K)
- add eax, CORE1_STACK_BASE_ADDR ; ... + Base_Addr);
- mov ebp, eax
- .endif
-
- ; Now set the MTRR. Add this to already existing settings (don't clear any MTRR)
- mov edi, WB_DRAM_TYPE ; Load Cache type in 1st slot
- mov cl, bh ; ShiftCount = ((slot# ...
- and cl, 03h ; ... % 4) ...
- shl cl, 3 ; ... * 8);
- shl edi, cl ; Cache type is now in correct position
- ror ebx, 16 ; Get the MTRR address
- movzx ecx, bx ;
- rol ebx, 16 ; Put slot# & size back in BX
- _RDMSR ; Read-modify-write the MSR
- .if (bh < 4) ; Is value in lower or upper half of MSR?
- or eax, edi ;
- .else ;
- or edx, edi ;
- .endif ;
- _WRMSR ;
-
- ; Enable MTRR defaults as UC type
- mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF
- _RDMSR ; Read-modify-write the MSR
- bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn
- bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn
- _WRMSR
-
- ; Close the modification window on the Fixed MTRRs
- mov ecx, MTRR_SYS_CFG ; MSR:0C001_0010
- _RDMSR
- bts eax, MTRR_FIX_DRAM_EN ; MtrrFixDramEn
- bts eax, MTRR_VAR_DRAM_EN ; variable MTRR enable bit
- btr eax, MTRR_FIX_DRAM_MOD_EN ; Turn off modification enable bit
- _WRMSR
-
- ; Enable caching in CR0
- mov eax, CR0 ; Enable WT/WB cache
- btr eax, CR0_PG ; Make sure paging is disabled
- btr eax, CR0_CD ; Clear CR0 NW and CD
- btr eax, CR0_NW
- mov CR0, eax
-
- ; Use the Stack Base & size to calculate SS and ESP values
- ; review:
- ; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
- ; ebp - start address of stack block
- ; ebx - [31:16] - MTRR MSR address
- ; - [15:8] - slot# in MTRR register
- ; - [7:0] - block size in #4K blocks
- ;
- mov esp, ebp ; Initialize the stack pointer
- mov edi, esp ; Copy the stack start to edi
- movzx bx, bl
- movzx ebx, bx ; Clear upper ebx, don't need MSR addr anymore
- shl ebx, 12 ; Make size full byte count (* 4K)
- add esp, ebx ; Set the Stack Pointer as full linear address
- sub esp, 4
- ;
- ; review:
- ; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
- ; edi - 32b start address of stack block
- ; ebx - size of stack block
- ; esp - 32b linear stack pointer
- ;
-
- ; Determine mode for SS base;
- mov ecx, CR0 ; Check for 32-bit protect mode
- bt ecx, CR0_PE ;
- .if (!carry?) ; PE=0 means real mode
- mov cx, cs ;
- .if (cx >= 0D000h) ; If CS >= D000, it's a real mode segment. PM selector would be 08-> 1000
- ; alter SS:ESP for 16b Real Mode:
- mov eax, edi ;
- shr eax, 4 ; Create a Real Mode segment for ss, ds, es
- mov ss, ax ;
- mov ds, ax ;
- mov es, ax ;
- shl eax, 4 ;
- sub edi, eax ; Adjust the clearing pointer for Seg:Offset mode
- mov esp, ebx ; Make SP an offset from SS
- sub esp, 4 ;
- .endif ; endif
- ; else
- ; Default is to use Protected 32b Mode
- .endif
- ;
- ; Clear The Stack
- ; Now that we have set the location and the MTRRs, initialize the cache by
- ; reading then writing to zero all of the stack area.
- ; review:
- ; ss - Stack base
- ; esp - stack pointer
- ; ebx - size of stack block
- ; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
- ; edi - address of start of stack block
- ;
- shr ebx, 2 ;
- mov cx, bx ; set cx for size count of DWORDS
- ; Check our flags - Don't clear an existing stack
- .if ( !(esi & (1 SHL FLAG_STACK_REENTRY)) )
- cld
- mov esi, edi
- rep lods DWORD PTR [esi] ; Pre-load the range
- xor eax, eax
- mov cx, bx
- mov esi, edi ; Preserve base for push on stack
- rep stos DWORD PTR [edi] ; Clear the range
- mov DWORD PTR [esp], 0ABCDDCBAh ; Put marker in top stack dword
- shl ebx, 2 ; Put stack size and base
- push ebx ; in top of stack
- push esi
-
- mov ecx, ebx ; Return size of stack in bytes
- mov eax, AGESA_SUCCESS ; eax = AGESA_SUCCESS : no error return code
- .else
- movzx ecx, cx
- shl ecx, 2 ; Return size of stack, in bytes
- mov edx, CPU_EVENT_STACK_REENTRY
- mov eax, AGESA_WARNING ; eax = AGESA_WARNING (Stack has already been set up)
- .endif
-
-AmdEnableStackExit:
- movd ebx, mm0 ; Restore return address
- movd ebp, mm1
-ENDM
-
-;======================================================================
-; AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine
-; should only be executed on the BSP
-;
-; In:
-; none
-;
-; Out:
-; EAX = AGESA_SUCCESS
-;
-; Preserved:
-; ebx
-; Destroyed:
-; eax, ecx, edx, esp
-;======================================================================
-AMD_DISABLE_STACK MACRO
-
- mov esp, ebx ; Save return address
-
- ; get node/core/flags of current executing core
- GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
-
- ; Turn on modification enable bit
- mov ecx, MTRR_SYS_CFG ; MSR:C001_0010
- _RDMSR
- bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable modifications
- _WRMSR
-
- ; Set lower 640K MTRRs for Write-Back memory caching
- mov ecx, AMD_MTRR_FIX64k_00000
- mov eax, 1E1E1E1Eh
- mov edx, eax
- _WRMSR ; 0 - 512K = WB Mem
- mov ecx, AMD_MTRR_FIX16k_80000
- _WRMSR ; 512K - 640K = WB Mem
-
- ; Turn off modification enable bit
- mov ecx, MTRR_SYS_CFG ; MSR:C001_0010
- _RDMSR
- btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable modification
- _WRMSR
-
- AMD_DISABLE_STACK_FAMILY_HOOK ; Re-Enable 'normal' cache operations
-
- mov ebx, esp ; restore return address (ebx)
- xor eax, eax
-
-ENDM
diff --git a/src/vendorcode/amd/agesa/f14/Legacy/PlatformMemoryConfiguration.inc b/src/vendorcode/amd/agesa/f14/Legacy/PlatformMemoryConfiguration.inc
deleted file mode 100644
index 86643230ea..0000000000
--- a/src/vendorcode/amd/agesa/f14/Legacy/PlatformMemoryConfiguration.inc
+++ /dev/null
@@ -1,402 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * AMD Platform Specific Memory Configuration
-; *
-; * Contains AMD AGESA Memory Configuration Override Interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 22910 $ @e \$Date: 2009-11-27 04:50:20 -0600 (Fri, 27 Nov 2009) $
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-IFNDEF PSO_ENTRY
- PSO_ENTRY TEXTEQU <UINT8>; < Platform Configuration Table Entry
-ENDIF
-; *****************************************************************************************
-; *
-; * PLATFORM SPECIFIC MEMORY DEFINITIONS
-; *
-; *****************************************************************************************
-; */
-;
-; < Memory Speed and DIMM Population Masks
-;
-; < DDR Speed Masks
-;
-ANY_SPEED EQU 0FFFFFFFFh
-DDR400 EQU ( 1 SHL (DDR400_FREQUENCY / 66))
-DDR533 EQU ( 1 SHL (DDR533_FREQUENCY / 66))
-DDR667 EQU ( 1 SHL (DDR667_FREQUENCY / 66))
-DDR800 EQU ( 1 SHL (DDR800_FREQUENCY / 66))
-DDR1066 EQU ( 1 SHL (DDR1066_FREQUENCY / 66))
-DDR1333 EQU ( 1 SHL (DDR1333_FREQUENCY / 66))
-DDR1600 EQU ( 1 SHL (DDR1600_FREQUENCY / 66))
-DDR1866 EQU ( 1 SHL (DDR1866_FREQUENCY / 66))
-; <
-; < DIMM POPULATION MASKS
-;
-ANY_ EQU 0FFh
-SR_DIMM0 EQU 0001h
-SR_DIMM1 EQU 0010h
-SR_DIMM2 EQU 0100h
-SR_DIMM3 EQU 1000h
-DR_DIMM0 EQU 0002h
-DR_DIMM1 EQU 0020h
-DR_DIMM2 EQU 0200h
-DR_DIMM3 EQU 2000h
-QR_DIMM0 EQU 0004h
-QR_DIMM1 EQU 0040h
-QR_DIMM2 EQU 0400h
-QR_DIMM3 EQU 4000h
-ANY_DIMM0 EQU 000Fh
-ANY_DIMM1 EQU 00F0h
-ANY_DIMM2 EQU 0F00h
-ANY_DIMM3 EQU 0F000h
-;
-; Number of Dimms
-;
-ANY_NUM EQU 0FFh
-NO_DIMM EQU 00h
-ONE_DIMM EQU 01h
-TWO_DIMM EQU 02h
-THREE_DIMM EQU 04h
-FOUR_DIMM EQU 08h
-; *****************************************************************************************
-; *
-; * Platform Specific Override Definitions for Socket, Channel and Dimm
-; * This indicates where a platform override will be applied.
-; *
-; *****************************************************************************************
-;
-; SOCKET MASKS
-;
-ANY_SOCKET EQU 0FFh
-SOCKET0 EQU 01h
-SOCKET1 EQU 02h
-SOCKET2 EQU 04h
-SOCKET3 EQU 08h
-SOCKET4 EQU 10h
-SOCKET5 EQU 20h
-SOCKET6 EQU 40h
-SOCKET7 EQU 80h
-;
-; CHANNEL MASKS
-;
-ANY_CHANNEL EQU 0FFh
-CHANNEL_A EQU 01h
-CHANNEL_B EQU 02h
-CHANNEL_C EQU 04h
-CHANNEL_D EQU 08h
-;
-; DIMM MASKS
-;
-ALL_DIMMS EQU 0FFh
-DIMM0 EQU 01h
-DIMM1 EQU 02h
-DIMM2 EQU 04h
-DIMM3 EQU 08h
-;
-; REGISTER ACCESS MASKS
-;
-ACCESS_NB0 EQU 0h
-ACCESS_NB1 EQU 01h
-ACCESS_NB2 EQU 02h
-ACCESS_NB3 EQU 03h
-ACCESS_NB4 EQU 04h
-ACCESS_PHY EQU 05h
-ACCESS_DCT_XT EQU 06h
-; *****************************************************************************************
-; *
-; * Platform Specific Overriding Table Definitions
-; *
-; *****************************************************************************************
-PSO_END EQU 0 ; < Table End
-PSO_CKE_TRI EQU 1 ; < CKE Tristate Map
-PSO_ODT_TRI EQU 2 ; < ODT Tristate Map
-PSO_CS_TRI EQU 3 ; < CS Tristate Map
-PSO_MAX_DIMMS EQU 4 ; < Max Dimms per channel
-PSO_CLK_SPEED EQU 5 ; < Clock Speed
-PSO_DIMM_TYPE EQU 6 ; < Dimm Type
-PSO_MEMCLK_DIS EQU 7 ; < MEMCLK Disable Map
-PSO_MAX_CHNLS EQU 8 ; < Max Channels per Socket
-PSO_BUS_SPEED EQU 9 ; < Max Memory Bus Speed
-PSO_MAX_CHIPSELS EQU 10 ; < Max Chipsel per Channel
-PSO_MEM_TECH EQU 11 ; < Channel Memory Type
-PSO_WL_SEED EQU 12 ; < DDR3 Write Levelization Seed delay
-PSO_RXEN_SEED EQU 13 ; < Hardwared based RxEn seed
-PSO_NO_LRDIMM_CS67_ROUTING EQU 14 ; < CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
-; **********************************
-; * CONDITIONAL PSO SPECIFIC ENTRIES
-; **********************************
-; Condition Types
-CONDITIONAL_PSO_MIN EQU 100 ; < Start of Conditional Entry Types
-PSO_CONDITION_AND EQU 100 ; < And Block - Start of Conditional block
-PSO_CONDITION_LOC EQU 101 ; < Location - Specify Socket, Channel, Dimms to be affected
-PSO_CONDITION_SPD EQU 102 ; < SPD - Specify a specific SPD value on a Dimm on the channel
-PSO_CONDITION_REG EQU 103 ; Reserved
-PSO_CONDITION_MAX EQU 103 ; < End Of Condition Entry Types
-; Action Types
-PSO_ACTION_MIN EQU 120 ; < Start of Action Entry Types
-PSO_ACTION_ODT EQU 120 ; < ODT values to override
-PSO_ACTION_ADDRTMG EQU 121 ; < Address/Timing values to override
-PSO_ACTION_ODCCONTROL EQU 122 ; < ODC Control values to override
-PSO_ACTION_SLEWRATE EQU 123 ; < Slew Rate value to override
-PSO_ACTION_REG EQU 124 ; Reserved
-PSO_ACTION_SPEEDLIMIT EQU 125 ; < Memory Bus speed Limit based on configuration
-PSO_ACTION_MAX EQU 125 ; < End of Action Entry Types
-CONDITIONAL_PSO_MAX EQU 139 ; < End of Conditional Entry Types
-; *****************************************************************************************
-; *
-; * CONDITIONAL OVERRIDE TABLE MACROS
-; *
-; *****************************************************************************************
-MEMCLK_DIS_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
- DB PSO_MEMCLK_DIS
- DB 10
- DB SocketID
- DB ChannelID
- DB Bit0Map
- DB Bit1Map
- DB Bit2Map
- DB Bit3Map
- DB Bit4Map
- DB Bit5Map
- DB Bit6Map
- DB Bit7Map
-ENDM
-
-CKE_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ
- DB PSO_CKE_TRI
- DB 4
- DB SocketID
- DB ChannelID
- DB Bit0Map
- DB Bit1Map
-ENDM
-
-ODT_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ
- DB PSO_ODT_TRI
- DB 6
- DB SocketID
- DB ChannelID
- DB Bit0Map
- DB Bit1Map
- DB Bit2Map
- DB Bit3Map
-ENDM
-
-CS_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
- DB PSO_CS_TRI
- DB 10
- DB SocketID
- DB ChannelID
- DB Bit0Map
- DB Bit1Map
- DB Bit2Map
- DB Bit3Map
- DB Bit4Map
- DB Bit5Map
- DB Bit6Map
- DB Bit7Map
-ENDM
-
-NUMBER_OF_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfDimmSlotsPerChannel:REQ
- DB PSO_MAX_DIMMS
- DB 3
- DB SocketID
- DB ChannelID
- DB NumberOfDimmSlotsPerChannel
-ENDM
-
-NUMBER_OF_CHIP_SELECTS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfChipSelectsPerChannel:REQ
- DB PSO_MAX_CHIPSELS
- DB 3
- DB SocketID
- DB ChannelID
- DB NumberOfChipSelectsPerChannel
-ENDM
-
-NUMBER_OF_CHANNELS_SUPPORTED MACRO SocketID:REQ, NumberOfChannelsPerSocket:REQ
- DB PSO_MAX_CHNLS
- DB 3
- DB SocketID
- DB ANY_CHANNEL
- DB NumberOfChannelsPerSocket
-ENDM
-
-OVERRIDE_DDR_BUS_SPEED MACRO SocketID:REQ, ChannelID:REQ, TimingMode:REQ, BusSpeed:REQ
- PSO_BUS_SPEED
- DB 10
- DB SocketID
- DB ChannelID
- DD TimingMode
- DD BusSpeed
-ENDM
-
-DRAM_TECHNOLOGY MACRO SocketID:REQ, MemTechType:REQ
- DB PSO_MEM_TECH
- DB 6
- DB SocketID
- DB ANY_CHANNEL
- DD MemTechType
-ENDM
-
-WRITE_LEVELING_SEED MACRO SocketID:REQ, ChannelID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
-Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
- DB PSO_WL_SEED
- DB 11
- DB SocketID
- DB ChannelID
- DB Byte0Seed
- DB Byte1Seed
- DB Byte2Seed
- DB Byte3Seed
- DB Byte4Seed
- DB Byte5Seed
- DB Byte6Seed
- DB Byte7Seed
- DB ByteEccSeed
-ENDM
-
-HW_RXEN_SEED MACRO SocketID:REQ, ChannelID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
-Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
- DB PSO_RXEN_SEED
- DB 20
- DB SocketID
- DB ChannelID
- DW Byte0Seed
- DW Byte1Seed
- DW Byte2Seed
- DW Byte3Seed
- DW Byte4Seed
- DW Byte5Seed
- DW Byte6Seed
- DW Byte7Seed
- DW ByteEccSeed
-ENDM
-
-NO_LRDIMM_CS67_ROUTING MACRO SocketID:REQ, ChannelID:REQ
- DB PSO_NO_LRDIMM_CS67_ROUTING
- DB 3
- DB SocketID
- DB ChannelID
- DB 1
-ENDM
-
-
-; *****************************************************************************************
-; *
-; * CONDITIONAL OVERRIDE TABLE MACROS
-; *
-; *****************************************************************************************
-CONDITION_AND MACRO
- DB PSO_CONDITION_AND
- DB 0
-ENDM
-
-COND_LOC MACRO SocketMsk:REQ, ChannelMsk:REQ, DimmMsk:REQ
- DB PSO_CONDITION_LOC
- DB 3
- DB SocketMsk
- DB ChannelMsk
- DB DimmMsk
-ENDM
-
-COND_SPD MACRO Byte:REQ, Mask:REQ, Value:REQ
- DB PSO_CONDITION_SPD
- DB 3
- DB Byte
- DB Mask
- DB Value
-ENDM
-
-COND_REG MACRO Access:REQ, Offset:REQ, Mask:REQ, Value:REQ
- DB PSO_CONDITION_REG
- DB 11
- DB Access
- DW Offset
- DD Mask
- DD Value
-ENDM
-
-ACTION_ODT MACRO Frequency:REQ, Dimms:REQ, QrDimms:REQ, DramOdt:REQ, QrDramOdt:REQ, DramDynOdt:REQ
- DB PSO_ACTION_ODT
- DB 9
- DD Frequency
- DB Dimms
- DB QrDimms
- DB DramOdt
- DB QrDramOdt
- DB DramDynOdt
-ENDM
-
-ACTION_ADDRTMG MACRO Frequency:REQ, DimmConfig:REQ, AddrTmg:REQ
- DB PSO_ACTION_ADDRTMG
- DB 10
- DD Frequency
- DW DimmConfig
- DD AddrTmg
-ENDM
-
-ACTION_ODCCTRL MACRO Frequency:REQ, DimmConfig:REQ, OdcCtrl:REQ
- DB PSO_ACTION_ODCCONTROL
- DB 10
- DD Frequency
- DW DimmConfig
- DD OdcCtrl
-ENDM
-
-ACTION_SLEWRATE MACRO Frequency:REQ, DimmConfig:REQ, SlewRate:REQ
- DB PSO_ACTION_SLEWRATE
- DB 10
- DD Frequency
- DW DimmConfig
- DD SlewRate
-ENDM
-
-ACTION_SPEEDLIMIT MACRO DimmConfig:REQ, Dimms:REQ, SpeedLimit15:REQ, SpeedLimit135:REQ, SpeedLimit125:REQ
- DB PSO_ACTION_SPEEDLIMIT
- DB 9
- DW DimmConfig
- DB Dimms
- DW SpeedLimit15
- DW SpeedLimit135
- DW SpeedLimit125
-ENDM
-
-; *****************************************************************************************
-; *
-; * END OF CONDITIONAL OVERRIDE TABLE MACROS
-; *
-; *****************************************************************************************
diff --git a/src/vendorcode/amd/agesa/f14/Legacy/Proc/arch2008.asm b/src/vendorcode/amd/agesa/f14/Legacy/Proc/arch2008.asm
deleted file mode 100644
index d30790621c..0000000000
--- a/src/vendorcode/amd/agesa/f14/Legacy/Proc/arch2008.asm
+++ /dev/null
@@ -1,2674 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; Workfile: arch2008.asm $Revision: 37157 $ $Date: 2010-09-01 03:24:07 +0800 (Wed, 01 Sep 2010) $
-;
-; Description: ARCH2008.ASM - AGESA Architecture 2008 Wrapper Template
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- .XLIST
- INCLUDE agesa.inc
- INCLUDE acwrapg.inc ; Necessary support file as part of wrapper, including but not limited to segment start/end macros.
- INCLUDE acwrap.inc ; IBVs may specify host BIOS-specific include files required when building.
- INCLUDE cpcarmac.inc
- INCLUDE bridge32.inc
- .LIST
- .586p
- .mmx
-
-
-;----------------------------------------------------------------------------
-; Local definitions
-;----------------------------------------------------------------------------
-
-sOemCallout STRUCT
- FuncName DD ? ; Call out function name
- FuncPtr DW ? ; Call out function pointer
-sOemCallout ENDS
-
-sOemEventHandler STRUCT
- ClassCode DD ? ; AGESA event log sub-class code
- FuncPtr DW ? ; Event handler function pointer
-sOemEventHandler ENDS
-
-;; A typical legacy BIOS implementation may require the E000 and F000 segments
-;; to be cached.
-EXE_CACHE_REGION_BASE_0 EQU 0E0000h
-EXE_CACHE_REGION_SIZE_0 EQU 20000h
-
-;; In this sample implementation, the B1 and B2 images are placed next to each
-;; other in the BIOS ROM to help with the maximization of cached code.
-EXE_CACHE_REGION_BASE_1 EQU AGESA_B1_ADDRESS
-EXE_CACHE_REGION_SIZE_1 EQU 40000h
-
-;; The third region is not needed in our example.
-EXE_CACHE_REGION_BASE_2 EQU 0
-EXE_CACHE_REGION_SIZE_2 EQU 0
-
-
-;----------------------------------------------------------------------------
-; PERSISTENT SEGMENT
-; This segment is required to be present throughout all BIOS execution.
-;----------------------------------------------------------------------------
-
-AMD_PERSISTENT_START
-
-
-;----------------------------------------------------------------------------
-; Instantiate the global descriptor table
-;----------------------------------------------------------------------------
-
-AMD_BRIDGE_32_GDT AMD_GDT ; Instantiate the global descriptor table
- ; required by the push-high mechanism.
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the persistent segment
-;----------------------------------------------------------------------------
-
-;+-------------------------------------------------------------------------
-;
-; AmdDfltRet
-;
-; Entry:
-; None
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Near stub procedure. Simply perform a retn instruction.
-;
-EXTERN AmdDfltRet:NEAR
-
-
-;+-------------------------------------------------------------------------
-;
-; AmdDfltRetFar
-;
-; Entry:
-; None
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Far stub procedure. Simply perform a retf instruction.
-;
-EXTERN AmdDfltRetFar:FAR
-
-
-;----------------------------------------------------------------------------
-; Declare the optional external routines in the persistent segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myModuleTypeMismatchHandler (Example)
-;
-; Entry:
-; ESI - Pointer to the EVENT_PARAMS structure of the failure.
-; [ESI].DataParam1 - Socket
-; [ESI].DataParam2 - DCT
-; [ESI].DataParam3 - Channel
-; [ESI].DataParam4 - 0x00000000
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure can be used to react to a memory module type
-; mismatch error discovered by the AGESA code. Actions taken
-; may include, but are not limited to:
-; Logging the event to NV for display later
-; Reset, excluding the mismatch on subsequent reboot
-; Do nothing
-;
-; Dependencies:
-; None
-;
-EXTERN myModuleTypeMismatchHandler(AmdDfltRet):NEAR
-
-;+---------------------------------------------------------------------------
-;
-; oemPlatformConfigInit (Optional)
-;
-; Entry:
-; EDI - 32-bit flat pointer to the PLATFORM_CONFIGURATION to be
-; passed in to the next AGESA entry point.
-;
-; typedef struct {
-; IN PERFORMANCE_PROFILE PlatformProfile;
-; IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList;
-; IN UINT8 CoreLevelingMode;
-; IN PLATFORM_C1E_MODES C1eMode;
-; IN UINT32 C1ePlatformData;
-; IN UINT32 C1ePlatformData1;
-; IN UINT32 C1ePlatformData2;
-; IN BOOLEAN UserOptionDmi;
-; IN BOOLEAN UserOptionPState;
-; IN BOOLEAN UserOptionSrat;
-; IN BOOLEAN UserOptionSlit;
-; IN BOOLEAN UserOptionWhea;
-; IN UINT32 PowerCeiling;
-; IN BOOLEAN PstateIndependent;
-; } PLATFORM_CONFIGURATION;
-;
-; typedef struct {
-; IN UINT8 Socket;
-; IN UINT8 Link;
-; IN UINT8 LoFreq;
-; IN UINT8 HighFreq;
-; IN PLATFORM_DEEMPHASIS_LEVEL ReceiverDeemphasis;
-; IN PLATFORM_DEEMPHASIS_LEVEL DcvDeemphasis;
-; } CPU_HT_DEEMPHASIS_LEVEL;
-;
-; typedef struct {
-; IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode;
-; IN BOOLEAN UseHtAssist;
-; IN BOOLEAN UseAtmMode;
-; IN BOOLEAN Use32ByteRefresh;
-; IN BOOLEAN UseVariableMctIsocPriority;
-; } PERFORMANCE_PROFILE;
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Provide a single hook routine to modify the parameters of a
-; PLATFORM_CONFIGURATION structure before any entry point that
-; has such a structure as an input.
-;
-; Dependencies:
-; None
-;
-; Example:
-; If your platform is running in UMA mode, the following code
-; may be added:
-; mov (PLATFORM_CONFIGURATION PTR [edi]).PlatformProfile.PlatformControlFlowMode, UmaDr
-;
-EXTERN oemPlatformConfigInit(AmdDfltRetFar):FAR
-
-;+---------------------------------------------------------------------------
-;
-; oemCallout (Optional)
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The default call out router function which resides in the same
-; segment as the push-high bridge code.
-;
-; Dependencies:
-; None
-;
-EXTERN oemCallout(AmdDfltRet):NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the persistent segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdBridge32
-;
-; Entry:
-; EDX - A Real Mode FAR pointer using seg16:Offset16 format that
-; points to a local host environment call-out router. If
-; this pointer is not equal to zero, then this pointer is
-; used as the call-out router instead of the standard
-; OemCallout. This may be useful when the call-out router
-; is not located in the same segment as the AmdBridge32 and
-; AmdCallout16 routines.
-; ESI - A Flat Mode pointer (32-bit address) that points to the
-; configuration block (AMD_CONFIG_PARAMS) for the AGESA
-; software function.
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; Execute an AGESA software function through the Push-High interface.
-;
-; Dependencies:
-; This procedure requires a stack. The host environment must use the
-; provided service function to establish the stack environment prior
-; to making the call to this procedure.
-;
-AmdBridge32 PROC FAR PUBLIC
- AMD_BRIDGE_32 AMD_GDT ; use the macro for the body
- ret
-AmdBridge32 ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdEnableStack
-;
-; Entry:
-; BX - Return address
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; SS:ESP - Points to the private stack location for this processor core.
-; ECX - Upon success, contains this processor core's stack size in bytes.
-;
-; Modified:
-; EAX, ECX, EDX, EDI, ESI, ESP, DS, ES
-;
-; Purpose:
-; This procedure is used to establish the stack within the host environment.
-;
-; Dependencies:
-; The host environment must use this procedure and not rely on any other
-; sources to create the stack region.
-;
-AmdEnableStack PROC NEAR PUBLIC
- AMD_ENABLE_STACK
- ;; EAX = AGESA_SUCCESS, The stack space has been allocated for this core.
- ;; EAX = AGESA_WARNING, The stack has already been set up. SS:ESP is set
- ;; to stack top, and ECX is the stack size in bytes.
- jmp bx
-AmdEnableStack ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdDisableStack
-;
-; Entry:
-; BX - Return address
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; EAX, ECX, EDX, ESI, ESP
-;
-; Purpose:
-; This procedure is used to remove the pre-memory stack from within the
-; host environment.
-; The exit state for the BSP is described as follows:
-; Memory region 00000-9FFFF MTRRS are set as WB memory.
-; Processor Cache is enabled (CD bit is cleared).
-; MTRRs used for execution cache are kept.
-; Cache content is flushed (invalidated without write-back).
-; Any family-specific clean-up done.
-; The exit state for the APs is described as follows:
-; Memory region 00000-9FFFF MTRRS are set as WB memory.
-; Memory region A0000-DFFFF MTRRS are set as UC IO.
-; Memory region E0000-FFFFF MTRRS are set as UC memory.
-; MTRRs used for execution cache are cleared.
-; Processor Cache is disabled (CD bit is set).
-; Top-of-Memory (TOM) set to the system top of memory as determined
-; by the memory initialization routines.
-; System lock command is enabled.
-; Any family-specific clean-up done.
-;
-; Dependencies:
-; The host environment must use this procedure and not rely on any other
-; sources to break down the stack region.
-; If executing in 16-bit code, the host environment must establish the
-; "Big Real" mode of 32-bit addressing of data.
-;
-AmdDisableStack PROC NEAR PUBLIC
- AMD_DISABLE_STACK
- ;; EAX = AGESA_SUCCESS, The stack space has been disabled for this core.
- jmp bx
-AmdDisableStack ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCallout16
-;
-; Entry:
-; [esp+8] - Func
-; [esp+12] - Data
-; [esp+16] - Configuration Block
-; [esp+4] - Return address to AGESA
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; Execute callback from the push-high interface.
-;
-; Dependencies:
-; None
-;
-AmdCallout16 PROC FAR PUBLIC ; declare the procedure
- AMD_CALLOUT_16 oemCallout ; use the macro for the body
- ret
-AmdCallout16 ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdProcessAgesaErrors (Optional)
-;
-; Entry:
-; AL - Heap status of the AGESA entry point that was just invoked.
-; EBX - AGESA image base address.
-; EDX - Segment / Offset of the appropriate callout router function.
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure is used to handle any errors that may have occurred
-; during an AGESA entry point.
-;
-; Dependencies:
-; None
-;
-AmdProcessAgesaErrors PROC FAR PUBLIC
- LOCAL localCpuInterfaceBlock:EVENT_PARAMS
-
- pushad
- xor edi, edi
- mov di, ss
- shl edi, 4
- lea esi, localCpuInterfaceBlock
- add esi, edi
-
- ; Fill default config block
- mov (EVENT_PARAMS PTR [esi]).StdHeader.Func, AMD_READ_EVENT_LOG
- mov (EVENT_PARAMS PTR [esi]).StdHeader.ImageBasePtr, ebx
- mov (EVENT_PARAMS PTR [esi]).StdHeader.AltImageBasePtr, 0
- mov (EVENT_PARAMS PTR [esi]).StdHeader.HeapStatus, al
- mov edi, SEG AmdCallout16
- shl edi, 4
- add edi, OFFSET AmdCallout16
- mov (EVENT_PARAMS PTR [esi]).StdHeader.CalloutPtr, edi
-
- ; Flush the event log searching for, and handling all monitored events
- xor eax, eax
- .while (eax == 0)
- push edx
- call AmdBridge32
- pop edx
- .if (eax == AGESA_SUCCESS)
- mov eax, (EVENT_PARAMS PTR [esi]).EventInfo
- .if (eax != 0)
- lea di, cs:AgesaEventTable
-
-loopThruTable:
- cmp di, OFFSET cs:AgesaEventTableEnd
- jae unhandledEvent
-
- cmp eax, cs:[di].sOemEventHandler.ClassCode
- je FoundMatch
- add di, SIZEOF sOemEventHandler
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemEventHandler.FuncPtr
- call bx
-
-unhandledEvent:
- xor eax, eax
- .else
- mov al, 1
- .endif
- .endif
- .endw
- popad
- ret
-
-AmdProcessAgesaErrors ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the error handler table
-;----------------------------------------------------------------------------
-
-AgesaEventTable LABEL BYTE
- ;; Add entries as desired
- ;;---------
- ;; EXAMPLE
- ;;---------
- sOemEventHandler <MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, OFFSET myModuleTypeMismatchHandler>
-AgesaEventTableEnd LABEL BYTE
-
-
-AMD_PERSISTENT_END
-
-
-
-
-;----------------------------------------------------------------------------
-; RECOVERY SEGMENT
-; This segment resides in the classic 'boot-block,' and is used
-; for recovery.
-;----------------------------------------------------------------------------
-
-AMD_RECOVERY_START
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the recovery segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myReadSPDRecovery (Required for proper recovery mode operation)
-;
-; Entry:
-; ESI - Pointer to an AGESA_READ_SPD_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT8 SocketId;
-; IN UINT8 MemChannelId;
-; IN UINT8 DimmId;
-; IN OUT UINT8 *Buffer;
-; IN OUT MEM_DATA_STRUCT *MemData;
-; } AGESA_READ_SPD_PARAMS;
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS Indicates the SPD block for the indicated
-; DIMM was read successfully.
-; AGESA_BOUNDS_CHK The specified DIMM is not present.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function and no memory initialized.
-; AGESA_ERROR The DIMM SPD read process has generated
-; communication errors.
-;
-; Modified:
-; None
-;
-; Purpose:
-; This call out reads a block of memory SPD data and places it
-; into the provided buffer.
-;
-; Dependencies:
-; None
-;
-EXTERN myReadSPDRecovery:NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the recovery segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitResetWrapper
-;
-; Entry:
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; A minimal initialization of the processor core is performed. This
-; procedure must be called by all processor cores. The code path
-; separates the BSP from the APs and performs a separate and appropriate
-; list of tasks for each class of core.
-; For the BSP, the following actions are performed:
-; Internal heap sub-system initialization
-; Primary non-coherent HyperTransportT link initialization
-; Return to the host environment to test for Recovery Mode.
-; The AP processor cores do not participate in the recovery process.
-; However, they execute this routine after being released to execute
-; by the BSP during the main boot process. Their actions include the
-; following:
-; Internal heap sub-system initialization
-; Proceed to a wait loop waiting for commands from the BSP
-;
-; For the cache regions, up to three regions of execution cache can be
-; allocated following the following rules:
-; 1. Once a region is allocated, it cannot be de-allocated. However, it
-; can be expanded.
-; 2. At most, two of the three regions can be located above 1 MByte. A
-; region failing this rule is ignored.
-; 3. All region addresses must be at or above the 0x000D0000 linear
-; address. A region failing this rule is ignored.
-; 4. The address is aligned on a 32-KByte boundary. Starting addresses
-; is rounded down to the nearest 32-Kbyte boundary.
-; 5. The execution cache size must be a multiple of 32 KByte. Size is
-; rounded up to the next multiple of 32 KByte.
-; 6. A region must not span either the 1-MByte boundary or the 4-GByte
-; boundary. Allocated size is truncated to not span the boundary.
-; 7. The granted cached execution regions, address, and size are calculated
-; based on the available cache resources of the processor core.
-; Allocations are made up to the limit of cache available on the
-; installed processor.
-; Warning: Enabling instruction cache outside of this interface can cause
-; data corruption.
-;
-; Dependencies:
-; This procedure is expected to be executed soon after a system reset
-; for the main boot path or resume path of execution.
-;
-; This procedure requires a stack.
-;
-; Because the heap system is not yet operational at the point of the
-; interface call, the host environment must allocate the storage for
-; the AMD_RESET_PARAMS structure before making the first call to
-; AmdCreateStruct. This is the ByHost method of allocation.
-;
-AmdInitResetWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
- local localResetParams:AMD_RESET_PARAMS
-
- pushad
-
- ; Prepare for the call to initialize the input parameters for AmdInitReset
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B1_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- ; Use the 'ByHost' allocation method because the heap has not been initialized as of yet.
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RESET
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, ByHost
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, sizeof AMD_RESET_PARAMS
- lea edx, localResetParams
- add edx, eax
- push edx
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr, edx
- mov dx, SEG AmdCalloutRouterRecovery
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterRecovery
- push edx
- call AmdBridge32
- pop edx
- pop esi
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- ; Allocate the execution cache to maximize the amount of code in ROM that is cached.
- ; Placing the B1 and B2 images near one another is a good way to ensure the AGESA code
- ; is cached.
- mov (AMD_RESET_PARAMS ptr [esi]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_0
- mov (AMD_RESET_PARAMS ptr [esi]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_0
- mov (AMD_RESET_PARAMS ptr [esi + sizeof EXECUTION_CACHE_REGION]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_1
- mov (AMD_RESET_PARAMS ptr [esi + sizeof EXECUTION_CACHE_REGION]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_1
- mov (AMD_RESET_PARAMS ptr [esi + (2 * sizeof EXECUTION_CACHE_REGION)]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_2
- mov (AMD_RESET_PARAMS ptr [esi + (2 * sizeof EXECUTION_CACHE_REGION)]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_2
-
- ; Call in to the AmdInitReset entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS Early initialization completed successfully.
- ;; AGESA_WARNING One or more of the execution cache allocation
- ;; rules were violated, but an adjustment was made
- ;; and space was allocated.
- ;; AGESA_ERROR One or more of the execution cache allocation rules
- ;; were violated, which resulted in a requested cache
- ;; region to not be allocated.
- ;; The storage space allocated for the AMD_RESET_PARAMS
- ;; structure is insufficient.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_RESET_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B1_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
-
- ;; Here are what the MTRRs should look like based off of the CacheRegions specified above:
-
- ;; Fixed-Range MTRRs
- ;; Name Address Value
- ;; ---------------- -------- ----------------
- ;; MTRRfix4k_E0000 0000026C 0505050505050505
- ;; MTRRfix4k_E8000 0000026D 0505050505050505
- ;; MTRRfix4k_F0000 0000026E 0505050505050505
- ;; MTRRfix4k_F8000 0000026F 0505050505050505
- ;; MTRRdefType 000002FF 0000000000000C00
- ;;
- ;; Variable-Range MTRRs and IO Range
- ;; MTRRphysBase(n) MTRRphysMask(n)
- ;; ----------------- -----------------
- ;; n=0 0000000000000000 0000000000000000
- ;; n=1 0000000000000000 0000000000000000
- ;; n=2 0000000000000000 0000000000000000
- ;; n=3 0000000000000000 0000000000000000
- ;; n=4 0000000000000000 0000000000000000
- ;; n=5 Heap Base (Varies by core) 0000FFFFFFFF0800
- ;; n=6 AGESA_B1_ADDRESS | 6 0000FFFFFFFC0800
- ;; n=7 0000000000000000 0000000000000000
-
-
- ;; Because the allocation method is 'ByHost,' the call to AMD_RELEASE_STRUCT is
- ;; not necessary. Stack space reclamation is left up to the host BIOS.
-
- popad
- ret
-
-
-AmdInitResetWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitRecoveryWrapper
-;
-; Entry:
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Perform a minimum initialization of the processor and memory to
-; support a recovery mode flash ROM update.
-; For the BSP, the following actions are performed:
-; Configuration of CPU core for recovery process
-; Minimal initialization of some memory
-; The AP processor cores do not participate in the recovery process.
-; No actions or tasks are performed by the AP cores for this time point.
-;
-; Dependencies:
-; This procedure requires a stack. The host environment must use one of
-; the provided service functions to establish the stack environment prior
-; to making the call to this procedure.
-;
-AmdInitRecoveryWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitRecovery
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B1_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RECOVERY
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterRecovery
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterRecovery
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
-
- ; Call in to the AmdInitRecovery entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_WARNING One or more of the allocation rules were violated,
- ;; but an adjustment was made and space was allocated.
- ;; AGESA_ERROR One or more of the allocation rules were violated,
- ;; which resulted in a requested cache region to not be
- ;; allocated.
- ;; AGESA_FATAL No memory was found in the system.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_RECOVERY_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B1_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitRecovery
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-AmdInitRecoveryWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCalloutRouterRecovery
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The call out router function for AmdInitReset and
-; AmdInitRecovery.
-;
-; Dependencies:
-; None
-;
-AmdCalloutRouterRecovery PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
- xor ax, ax
- mov ds, ax
- mov es, ax
- lea di, cs:CalloutRouterTableRecovery
- mov eax, AGESA_UNSUPPORTED
-
-loopThruTable:
- cmp di, OFFSET cs:CalloutRouterTableRecoveryEnd
- jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
- cmp ecx, cs:[di].sOemCallout.FuncName
- je FoundMatch
- add di, SIZEOF sOemCallout
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemCallout.FuncPtr
- call bx
-
-amdCpuCalloutExit:
- ret
-AmdCalloutRouterRecovery ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the callout dispatch table for the recovery segment
-;----------------------------------------------------------------------------
-
-CalloutRouterTableRecovery LABEL BYTE
- ;; Standard B1 implementations only need the SPD reader call out function to be implemented.
- sOemCallout <AGESA_READ_SPD, OFFSET myReadSPDRecovery>
-CalloutRouterTableRecoveryEnd LABEL BYTE
-
-
-AMD_RECOVERY_END
-
-
-
-;----------------------------------------------------------------------------
-; PRE-MEMORY SEGMENT
-; This segment must be uncompressed in the ROM image.
-;----------------------------------------------------------------------------
-
-AMD_PREMEM_START
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the recovery segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myReadSPDPremem (Required)
-;
-; Entry:
-; ESI - Pointer to an AGESA_READ_SPD_PARAMS structure
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT8 SocketId;
-; IN UINT8 MemChannelId;
-; IN UINT8 DimmId;
-; IN OUT UINT8 *Buffer;
-; IN OUT MEM_DATA_STRUCT *MemData;
-; } AGESA_READ_SPD_PARAMS;
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS Indicates the SPD block for the indicated
-; DIMM was read successfully.
-; AGESA_BOUNDS_CHK The specified DIMM is not present.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function and no memory initialized.
-; AGESA_ERROR The DIMM SPD read process has generated
-; communication errors.
-;
-; Modified:
-; None
-;
-; Purpose:
-; This call out reads a block of memory SPD data and places it
-; into the provided buffer.
-;
-; Dependencies:
-; None
-;
-EXTERN myReadSPDPremem:NEAR
-
-;+-------------------------------------------------------------------------
-;
-; AmdDfltRetPremem
-;
-; Entry:
-; None
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Near stub procedure in the prememory segment. Simply perform a
-; retn instruction.
-;
-EXTERN AmdDfltRetPremem:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myDoReset (Required)
-;
-; Entry:
-; EDX - Reset type
-; 1 - Warm reset whenever
-; 2 - Cold reset whenever
-; 3 - Warm reset immediately
-; 4 - Cold reset immediately
-; ESI - Pointer to an AMD_CONFIG_PARAMS structure.
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function.
-;
-; Modified:
-; None
-;
-; Purpose:
-; This host environment function must initiate the specified type
-; of system reset.
-;
-; Implementation of this function by the host environment is
-; REQUIRED. Some host environments may record this as a request
-; allowing other elements in the system to perform some additional
-; tasks before the actual reset is issued.
-;
-; Dependencies:
-; The AMD processor contains 3 bits (BiosRstDet[2:0]) in a PCI
-; register (F0x6C Link Initialization Control Register) that
-; indicate the reset status. These bits are reserved for use by
-; the AGESA software and should not be modified by the host
-; environment.
-;
-EXTERN myDoReset:NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myGetNonVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; None
-;
-; Exit:
-; EBX - Pointer to the non-volatile S3 context block
-; ECX - Size in bytes of the non-volatile S3 context block
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must return the pointer to the data
-; saved during the mySaveNonVolatileS3Context routine.
-;
-; Dependencies:
-; None
-;
-EXTERN myGetNonVolatileS3Context:NEAR
-
-
-;----------------------------------------------------------------------------
-; Declare the optional external routines in the prememory segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myAgesaHookBeforeExitSelfRefresh (Optional)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 44h
-; ESI - Pointer to a data structure containing the memory information
-;
-; Exit:
-; After returning control to AGESA, AGESA will display: - AGESA_TESTPOINT - 45h
-; EAX - Contains the AGESA_STATUS return code
-; AGESA_SUCCESS The function has completed successfully
-; AGESA_UNSUPPORTED This function is not implemented by the host environment
-; AGESA_WARNING A non-critical issue has occued in the host environment
-;
-; Modified:
-; None
-;
-; Purpose:
-; General purpose hook called before the exiting self refresh
-; This procedure is called once per channel
-;
-; Implementation of this function is optional for the host environment
-; This call-out is an opportunity for the host environment to make dynamic
-; modifications to the memory timing settings specific to the board or host
-; environment before exiting self refresh on S3 resume
-;
-; Dependencies:
-; This procedure is called before the exit self refresh bit is set in the resume
-; sequence. The host environment must initiate the OS restart process. This procedure
-; requires a stack. The host environment must establish the stack environment prior
-; to making the call to this procedure
-;
-EXTERN myAgesaHookBeforeExitSelfRefresh(AmdDfltRetPremem):NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myHookBeforeDramInit (Optional)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 40h
-; ESI - Pointer to a data structure containing the memory information
-;
-; Exit:
-; After returning control to AGESA, AGESA will display - AGESA_TESTPOINT - 41h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This function is not implemented by the host environment
-;
-; Modified:
-; None
-;
-; Purpose:
-; General-purpose hook called before the DRAM_Init bit is set. Called
-; once per MCT
-;
-; Implementation of this function is optional for the host environment
-; This call-out is an opportunity for the host environment to make
-; dynamic modifications to the memory timing settings specific to the
-; board or host environment
-;
-; Dependencies:
-; None
-;
-EXTERN myHookBeforeDramInit(AmdDfltRetPremem):NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myHookBeforeDQSTraining (Optional)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 42h
-; ESI - Pointer to a data structure containing the memory information.
-;
-; Exit:
-; After returning control to AGESA, AGESA will display - AGESA_TESTPOINT - 43h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This function is not implemented by the
-; host environment.
-;
-; Modified:
-; None
-;
-; Purpose:
-; General-purpose hook called just before the memory training processes
-; begin. Called once per MCT.
-;
-; Implementation of this function is optional for the host environment.
-; This call-out is an opportunity for the host environment to make
-; dynamic modifications to the memory timing settings specific to the
-; board or host environment.
-;
-; The host environment may also use this call-out for some board-
-; specific features that should be activated at this time point,
-; such as:
-; Low voltage DIMMs-the host environment should set the recommended
-; voltages found in the memory data structure for each memory
-; channel. This needs to occur before training begins.
-;
-; Dependencies:
-; None
-;
-EXTERN myHookBeforeDQSTraining(AmdDfltRetPremem):NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the prememory segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitEarlyWrapper
-;
-; Entry:
-; On Entry to "AmdInitEarly" AGESA will display AGESA_TESTPOINT - C4h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitEarly" AGESA will display AGESA_TESTPOINT - C5h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; A full initialization of the processor is performed. Action details
-; differ for the BSP and AP processor cores.
-; For the BSP, the following actions are performed:
-; Full HyperTransportT link initialization, coherent and non-coherent
-; Processor register loading
-; Microcode patch load
-; Errata workaround processing
-; Launch all processor cores
-; Configure the processor power management capabilities
-; Request a warm reset if needed
-; For the AP, the following actions are performed:
-; Processor register loading
-; Microcode patch load
-; Errata workaround processing
-; Configure the processor power management capabilities
-;
-; Dependencies:
-; This procedure is expected to be called before main memory initialization
-; and before the system warm reset. Prior to this, the basic configuration
-; done by the AmdInitReset routine must be completed.
-;
-; This procedure requires a stack. The host environment must use one of the
-; provided service functions to establish the stack environment prior to
-; making the call to this procedure.
-;
-; The processes performed at this time point require communication between
-; processor cores.
-;
-; The host environment must recognize that all processor cores are running
-; in parallel and avoid activities that might interfere with the core-to-core
-; communication, such as modifying the MTRR settings or writing to the APIC
-; registers.
-;
-AmdInitEarlyWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitEarly
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_EARLY
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPremem
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPremem
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + (3 * (SIZEOF EXECUTION_CACHE_REGION)))
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitEarly entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ALERT An HyperTransportT link CRC error was observed.
- ;; AGESA_WARNING One of more of the allocation rules were violated,
- ;; but an adjustment was made and space was allocated.
- ;; Or a HyperTransport device does not have the expected
- ;; capabilities, or unusable redundant HyperTransport
- ;; links were found.
- ;; AGESA_ERROR One or more of the allocation rules were violated, which
- ;; resulted in a requested cache region to not be allocated.
- ;; Or, a HyperTransport device failed to initialize.
- ;; AGESA_CRITICAL An illegal or unsupported mixture of processor types was
- ;; found, or the processors installed were found to have an
- ;; insufficient MP capability rating for this platform.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_EARLY_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitEarly
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitEarlyWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitPostWrapper
-;
-; Entry:
-; On Entry to "AmdInitPost" AGESA will display AGESA_TESTPOINT - C6h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitPost" AGESA will display AGESA_TESTPOINT - C7h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The main system memory is located, initialized, and brought on-line.
-; The processor(s) are prepared for full operation and control by the
-; host environment. Action details differ for the BSP and AP processor
-; cores.
-; For the BSP, the following actions are performed:
-; Full memory initialization and configuration. BSP is the master for
-; this process and may delegate some tasks to APs.
-; AP collection of data for use later.
-; Transfer the HOBs including the artifact data out of the pre-memory
-; cache storage into a temporary holding buffer in the main memory.
-; Check the BIST status of the BSP
-; Shut down the APs.
-; Prepare for the host environment to begin main boot activity.
-; Disable the pre-memory stack.
-; For the APs, the following actions are performed:
-; Report core identity information.
-; Execute indicated memory initialization processes as directed.
-; Check the BIST status of the AP
-; Disable the pre-memory stack.
-; Prepare to halt, giving control to host environment.
-; The entire range of system memory is enabled for Write-Back cache.
-; The fixed MTRRs and the variable MTRRs[7:6] are not changed in order
-; to leave in place any flash ROM region currently set for Write-Protect
-; execution cache.
-;
-; Dependencies:
-; This procedure is called after the host environment has determined that
-; a normal boot to operating system should be performed after any system
-; warm reset is completed and after the configuration done by AmdInitEarly
-; has completed.
-;
-; This procedure requires a stack. The host environment must use one of the
-; provided service functions to establish the stack environment prior to
-; making the call to this procedure.
-;
-; The processes performed at this time point require communication between
-; processor cores. The host environment must recognize that all processor
-; cores are running in parallel and avoid activities that might interfere
-; with the core-to-core communication, such as modifying the MTRR settings
-; or writing to the APIC registers.
-;
-AmdInitPostWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitPost
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_POST
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPremem
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPremem
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitPost entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ALERT A BIST error was found on one of the cores.
- ;; AGESA_WARNING HT Assist feature is running sub-optimally.
- ;; AGESA_FATAL Memory initialization failed.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_POST_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitPost
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitPostWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitResumeWrapper
-;
-; Entry:
-; On Entry to "AmdInitResume" AGESA will display AGESA_TESTPOINT - D0h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitResume" AGESA will display AGESA_TESTPOINT - D1h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure initializes or re-initializes the silicon components
-; for the resume boot path. For the processor, main memory is brought
-; out of self-refresh mode. This procedure will use the context data
-; in the NvStorage area of the input structure to re-start the main
-; memory. The host environment must fill the AMD_S3_PARAMS NvStorage
-; and VolatileStorage pointers and related size elements to describe
-; the location of the context data. Note that for this procedure, the
-; two data areas do not need to be contained in one buffer zone, they
-; can be anywhere in the accessible memory address space. If the host
-; environment uses a non-volatile storage device accessed on the system
-; address bus such as flashROM, then the context data does not need to
-; be moved prior to this call. If the host environment uses a non-
-; volatile storage device not located on the system address bus (e.g.
-; CMOS or SSEPROM) then the host environment must transfer the context
-; data to a buffer in main memory prior to calling this procedure.
-;
-; Dependencies:
-; The host environment must have determined that the system should take
-; the resume path prior to calling this procedure. The configuration
-; done by AmdInitEarly and any necessary warm reset must be complete.
-; After this procedure, execution proceeds to general system restoration.
-;
-; This procedure requires a stack. The host environment must use one of
-; the provided service functions to establish the stack environment prior
-; to making the call to this procedure.
-;
-AmdInitResumeWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitResume
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RESUME
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPremem
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPremem
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
- call oemPlatformConfigInit
-
- call myGetNonVolatileS3Context
- mov (AMD_RESUME_PARAMS ptr [esi]).S3DataBlock.NvStorage, ebx
- mov (AMD_RESUME_PARAMS ptr [esi]).S3DataBlock.NvStorageSize, ecx
-
- ; Call in to the AmdInitResume entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS Re-initialization has been completed successfully.
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_RESUME_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
-
- ; Allow AGESA to free the space used by AmdInitResume
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitResumeWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCalloutRouterPremem
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The call out router function for AmdInitEarly,
-; AmdInitPost, and AmdInitResume.
-;
-; Dependencies:
-; None
-;
-AmdCalloutRouterPremem PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
- xor ax, ax
- mov ds, ax
- mov es, ax
- lea di, cs:CalloutRouterTablePremem
- mov eax, AGESA_UNSUPPORTED
-
-loopThruTable:
- cmp di, OFFSET cs:CalloutRouterTablePrememEnd
- jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
- cmp ecx, cs:[di].sOemCallout.FuncName
- je FoundMatch
- add di, SIZEOF sOemCallout
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemCallout.FuncPtr
- call bx
-
-amdCpuCalloutExit:
- ret
-AmdCalloutRouterPremem ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the callout dispatch table for the prememory segment
-;----------------------------------------------------------------------------
-
-CalloutRouterTablePremem LABEL BYTE
- ;; Add entries as desired.
- sOemCallout <AGESA_READ_SPD, OFFSET myReadSPDPremem>
- sOemCallout <AGESA_HOOKBEFORE_DRAM_INIT, OFFSET myHookBeforeDramInit>
- sOemCallout <AGESA_HOOKBEFORE_DQS_TRAINING, OFFSET myHookBeforeDQSTraining>
- sOemCallout <AGESA_HOOKBEFORE_EXIT_SELF_REF, OFFSET myAgesaHookBeforeExitSelfRefresh>
- sOemCallout <AGESA_DO_RESET, OFFSET myDoReset>
-CalloutRouterTablePrememEnd LABEL BYTE
-
-
-
-AMD_PREMEM_END
-
-
-;----------------------------------------------------------------------------
-; POST SEGMENT
-; This segment may be decompressed and run from system RAM.
-;----------------------------------------------------------------------------
-
-AMD_POST_START
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the POST segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myAllocateBuffer (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E2h
-; ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 BufferLength;
-; IN UINT32 BufferHandle;
-; OUT VOID *BufferPointer;
-; } AGESA_BUFFER_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E3h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The requested size of memory has been
-; successfully allocated.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function.
-; AGESA_ERROR Less than the requested amount of memory
-; was allocated.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of memory allocation.
-; This function must allocate a buffer of the requested size or
-; larger. This function is required to be implemented by the host
-; environment.
-;
-; Dependencies:
-; The following call-outs must work together in the host system.
-; Parameters of the same name have the same function and must be
-; treated the same in each function:
-; AgesaAllocateBuffer
-; AgesaDeallocateBuffer
-; AgesaLocateBuffer
-; AgesaRunFcnOnAp
-; The host environment may need to reserve a location in the buffer
-; to store any host environment specific value(s). The returned
-; pointer must not include this reserved space. The host environment
-; on the AgesaDeallocateBuffer call needs to account for the reserved
-; space. This reserved space may be an identifier or the "handle"
-; used to identify the specific memory block.
-;
-EXTERN myAllocateBuffer:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myDeallocateBuffer (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E4h
-; ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 BufferLength;
-; IN UINT32 BufferHandle;
-; OUT VOID *BufferPointer;
-; } AGESA_BUFFER_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E5h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_BOUNDS_CHK The BufferHandle is invalid. The AGESA
-; software continues with its function.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of memory allocation.
-; This function releases a valid working buffer. This function is
-; required for the host environment to implement.
-;
-; Dependencies:
-; The following call-outs must work together in the host system.
-; Parameters of the same name have the same function and must be
-; treated the same in each function:
-; AgesaAllocateBuffer
-; AgesaDeallocateBuffer
-; AgesaLocateBuffer
-; AgesaRunFcnOnAp
-;
-EXTERN myDeallocateBuffer:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myLocateBuffer (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E6h
-; ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 BufferLength;
-; IN UINT32 BufferHandle;
-; OUT VOID *BufferPointer;
-; } AGESA_BUFFER_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E7h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_BOUNDS_CHK The presented handle is invalid or the
-; buffer could not be located.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of memory allocation.
-; This function must locate the buffer related to the indicated
-; handle and return the address of the buffer and its length.
-; This function is required to be implemented in the host
-; environment.
-;
-; Dependencies:
-; The following call-outs must work together in the host system.
-; Parameters of the same name have the same function and must be
-; treated the same in each function:
-; AgesaAllocateBuffer
-; AgesaDeallocateBuffer
-; AgesaLocateBuffer
-; AgesaRunFcnOnAp
-;
-EXTERN myLocateBuffer:NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myRunFuncOnAp (Required)
-;
-; Entry:
-; EDX - Local APIC ID of the target core.
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must route execution to the target AP and
-; have that AP call the AmdLateRunApTaskWrapper routine defined
-; above.
-;
-; Dependencies:
-; None
-;
-EXTERN myRunFuncOnAp:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; mySaveNonVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; EBX - Pointer to the non-volatile S3 context block
-; ECX - Size in bytes of the non-volatile S3 context block
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must save the non-volatile data to an area
-; that will not lose context while in the ACPI S3 sleep state, but
-; cannot be placed in system RAM. This data will need to be
-; available during the call to AmdInitResume.
-;
-; Dependencies:
-; None
-;
-EXTERN mySaveNonVolatileS3Context:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; mySaveVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; EBX - Pointer to the volatile S3 context block
-; ECX - Size in bytes of the volatile S3 context block
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must save the volatile data to an area
-; that will not lose context while in the ACPI S3 sleep state.
-; This data will need to be available during the call to
-; AmdS3LateRestore.
-;
-; Dependencies:
-; None
-;
-EXTERN mySaveVolatileS3Context:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myGetVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; None
-;
-; Exit:
-; EBX - Pointer to the volatile S3 context block
-; ECX - Size in bytes of the volatile S3 context block
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must return the pointer to the data
-; saved during the mySaveVolatileS3Context routine.
-;
-; Dependencies:
-; None
-;
-EXTERN myGetVolatileS3Context:NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the POST segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitEnvWrapper
-;
-; Entry:
-; On Entry to "AmdInitEnv" AGESA will display AGESA_TESTPOINT - C8h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitEnv" AGESA will display AGESA_TESTPOINT - C9h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure uses the AgesaAllocateBuffer call-out to acquire
-; permanent buffer space for the UEFI Hand-Off Blocks (HOBs). This
-; is also known as, or includes, artifact data being used by the
-; AGESA software. Upon entry to this procedure, the data is being
-; held in a temporary memory location and it must be moved to a
-; location controlled and protected by the host environment.
-;
-; These actions are performed by the BSP. The APs are not assigned
-; any tasks at this time point.
-;
-; Dependencies:
-; This procedure must be called after full memory is initialized and
-; the host environment has taken control of main memory allocation.
-; This procedure should be called before the PCI enumeration takes
-; place and as soon as possible after the host environment memory
-; allocation sub-system has started.
-;
-; This procedure requires a stack. The host environment must use one
-; of the provided service functions to establish the stack environment
-; prior to making the call to this procedure.
-;
-AmdInitEnvWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitEnv
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_ENV
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitEnv entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ERROR The artifact data could not be found or the host
- ;; environment failed to allocate sufficient buffer space.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_ENV_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitEnv
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitEnvWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitMidWrapper
-;
-; Entry:
-; On Entry to "AmdInitMid" AGESA will display AGESA_TESTPOINT - CAh
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitMid" AGESA will display AGESA_TESTPOINT - CBh
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure call performs special configuration requirements for
-; the graphics display hardware.
-;
-; These actions are performed by the BSP. The APs are not assigned any
-; tasks at this time point.
-;
-; Dependencies:
-; This procedure must be called after PCI enumeration has allocated
-; resources, but before the video BIOS call is performed.
-;
-; This procedure requires a stack. The host environment must use one
-; of the provided service functions to establish the stack environment
-; prior to making the call to this procedure.
-;
-AmdInitMidWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitMid
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_MID
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitMid entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_MID_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitMid
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-
-AmdInitMidWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitLateWrapper
-;
-; Entry:
-; On Entry to "AmdInitLate" AGESA will display AGESA_TESTPOINT - CCh
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitLate" AGESA will display AGESA_TESTPOINT - CDh
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The main purpose of this function is to generate informational
-; data tables used by the operating system. The individual tables
-; can be selected for generation through the user selection entries
-; on the input parameters.
-;
-; This routine uses the Call-Out AgesaAllocateBuffer to allocate a
-; buffer of the proper size to contain the data.
-;
-; The code path separates the BSP from the APs and perform a separate
-; and appropriate list of tasks for each class of core.
-; For the BSP, the following actions are performed:
-; Allocate buffer space for the tables.
-; Generate the table contents.
-; Make sure that the CPU is in a known good power state before
-; proceeding to boot the OS.
-; For the APs, the following actions are performed:
-; Final register settings preparing for entry to OS.
-; Establish the final PState for entry to OS.
-;
-; Dependencies:
-; This routine is expected to be executed late in the boot sequence
-; after main memory has been initialized, after PCI enumeration has
-; completed, after the host environment ACPI sub-system has started,
-; after the host environment has taken control of the APs, but just
-; before the start of OS boot.
-;
-; The host environment must provide the required call-outs listed in
-; the "Required Call-Out Procedures" section of the AGESA interface
-; specification to provide the buffer space in main memory and execute
-; code on the APs. The host environment must register the created ACPI
-; table in the main ACPI pointer tables. This may require moving the
-; generated tables to another location in memory.
-;
-; This procedure requires a stack. The host environment must establish
-; the stack environment prior to making the call to this procedure.
-; Some functions depend upon the preservation of the heap data across
-; the shift from pre-memory environment to a post-memory environment.
-; If that data was not preserved, then those functions cannot complete
-; and an error is returned.
-;
-AmdInitLateWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitLate
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_LATE
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitLate entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ALERT
- ;; AGESA_ERROR The system could not allocate the needed amount of
- ;; buffer space; or could not locate the artifact data block in
- ;; memory. Likely cause: the host environment may not have preserved
- ;; the data properly.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_LATE_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- push es
- mov ax, SEG AmdAcpiSratPointer
- mov es, ax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiSrat
- mov es:AmdAcpiSratPointer, ebx
- mov eax, DWORD PTR [ebx + 4]
- mov es:AmdAcpiSratSize, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiSlit
- mov es:AmdAcpiSlitPointer, ebx
- mov eax, DWORD PTR [ebx + 4]
- mov es:AmdAcpiSlitSize, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiPState
- mov es:AmdAcpiSsdtPointer, ebx
- mov eax, DWORD PTR [ebx + 4]
- mov es:AmdAcpiSsdtSize, eax
-
- xor eax, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiWheaMce
- mov es:AmdAcpiWheaMcePointer, ebx
- mov ax, WORD PTR [ebx]
- mov es:AmdAcpiWheaMceSize, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiWheaMce
- mov es:AmdAcpiWheaCmcPointer, ebx
- mov ax, WORD PTR [ebx]
- mov es:AmdAcpiWheaCmcSize, eax
-
- mov eax, (AMD_LATE_PARAMS ptr [esi]).DmiTable
- mov es:AmdDmiInfoPointer, eax
- pop es
-
-
- ; Allow AGESA to free the space used by AmdInitLate
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-
-AmdInitLateWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdS3SaveWrapper
-;
-; Entry:
-; On Entry to "AmdS3Save" AGESA will display AGESA_TESTPOINT - CEh
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Entry to "AmdS3Save" AGESA will display AGESA_TESTPOINT - CFh
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure saves critical registers and/or configuration
-; information for preservation across a system suspend mode. All
-; actions needed to prepare the processor for suspend mode is
-; performed, however this procedure does NOT initiate the suspend
-; process. The host environment is expected to perform that duty.
-;
-; These actions are performed by the BSP. The APs are not assigned
-; any tasks at this time point.
-;
-; The initializer routine will NULL out the save area pointers and
-; sizes. This procedure will determine the size of storage needed
-; for all the processor context, and make a call out to the environment
-; for allocation of one buffer to store all of the data. Upon exit, the
-; pointers and sizes within the AMD_S3_PARAMS structure will be updated
-; with the appropriate addresses within the buffer that was allocated.
-; The host environment is expected to then transfer the data pointed to
-; by NvStorage to a non-volatile storage area, and the data pointed to
-; by VolatileStorage to either a non-volatile storage area or system
-; RAM that retains its content across suspend.
-;
-; Dependencies:
-; The host environment must initiate the suspend process.
-;
-; This procedure requires a stack. The host environment must establish
-; the stack environment prior to making the call to this procedure.
-;
-AmdS3SaveWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdS3Save
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_S3_SAVE
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
- call oemPlatformConfigInit
-
- ; Call in to the AmdS3Save entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS All suspend duties have been completed successfully.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_S3SAVE_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- mov ecx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.NvStorageSize
- .if (ecx != 0)
- mov ebx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.NvStorage
- call mySaveNonVolatileS3Context
- .endif
-
- mov ecx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.VolatileStorageSize
- .if (ecx != 0)
- mov ebx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.VolatileStorage
- call mySaveVolatileS3Context
- .endif
-
- ; Allow AGESA to free the space used by AmdS3Save
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-
-AmdS3SaveWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdS3LateRestoreWrapper
-;
-; Entry:
-; On Entry to "AmdS3LateRestore" AGESA will display AGESA_TESTPOINT - D2h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdS3LateRestore" AGESA will display AGESA_TESTPOINT - D3h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure restores the processor state, reloads critical
-; silicon component registers, and performs any re-initialization
-; required by the silicon. This procedure will use the context data
-; in the VolatileStorage area of the input structure to restore the
-; processor registers.
-;
-; The host environment must fill the AMD_S3_PARAMS NvStorage and
-; VolatileStorage pointers and related size elements to describe
-; the location of the context data. Note that for this procedure,
-; the two data areas do not need to be contained in one buffer zone,
-; they can be anywhere in the accessible memory address space. If
-; the host environment uses a non-volatile storage device accessed
-; on the system address bus such as flashROM, then the context data
-; does not need to be moved prior to this call. If the host
-; environment uses a non-volatile storage device not located on the
-; system address bus (e.g. CMOS or SSEPROM) then the host environment
-; must transfer the context data to a buffer in main memory prior to
-; calling this procedure.
-;
-; These actions are performed by the BSP. The APs are not assigned
-; any tasks at this time point.
-;
-; Dependencies:
-; This procedure is called late in the resume sequence, after the
-; PCI control space is restored and just before resuming operating
-; system execution.
-;
-; The host environment must initiate the OS restart process.
-;
-; This procedure requires a stack. The host environment must establish
-; the stack environment prior to making the call to this procedure.
-;
-AmdS3LateRestoreWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdS3LateRestore
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_S3LATE_RESTORE
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
- call oemPlatformConfigInit
-
- call myGetVolatileS3Context
- mov (AMD_S3LATE_PARAMS ptr [esi]).S3DataBlock.VolatileStorage, ebx
- mov (AMD_S3LATE_PARAMS ptr [esi]).S3DataBlock.VolatileStorageSize, ecx
-
- ; Call in to the AmdS3LateRestore entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS All resume processes have been completed successfully.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_S3LATE_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdS3LateRestore
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-AmdS3LateRestoreWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdLateRunApTaskWrapper
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - D4h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - D5h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This entry point is tightly connected with the "AgesaRunFcnOnAp"
-; call out. The AGESA software will call the call-out "AgesaRunFcnOnAp";
-; the host environment will then call this entry point to have the AP
-; execute the requested function. This is needed late in the Post and
-; Resume branches for running an AP task since the AGESA software has
-; relinquished control of the APs to the host environment.
-;
-; Dependencies:
-; The host environment must implement the"AgesaRunFcnOnAp" call-out
-; and route execution to the target AP.
-;
-AmdLateRunApTaskWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdLateRunApTask
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_LATE_RUN_AP_TASK
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- push es
- mov ax, SEG AmdRunCodeOnApDataPointer
- mov es, ax
- mov eax, es:AmdRunCodeOnApDataPointer
- mov (AP_EXE_PARAMS PTR [esi]).RelatedDataBlock, eax
- mov eax, es:AmdRunCodeOnApDataSize
- mov (AP_EXE_PARAMS PTR [esi]).RelatedBlockLength, eax
- mov eax, es:AmdRunCodeOnApFunction
- mov (AP_EXE_PARAMS PTR [esi]).FunctionNumber, eax
- pop es
-
- ; Call in to the AmdLateRunApTask dispatcher
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- push es
- mov bx, SEG AmdRunCodeOnApStatus
- mov es, bx
- mov es:AmdRunCodeOnApStatus, eax
- pop es
-
- ; Allow AGESA to free the space used by AmdLateRunApTask
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-
-AmdLateRunApTaskWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdRunFuncOnAp (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E8h
-; EDX - Local APIC ID of the target core.
-; ESI - Pointer to an AP_EXE_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 FunctionNumber;
-; IN VOID *RelatedDataBlock;
-; IN UINT32 RelatedDataBlockLength;
-; } AP_EXE_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E9h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This is a required function, so this value
-; being returned causes a critical error
-; response value from the AGESAT software
-; function and no memory initialized.
-; AGESA_WARNING The AP did not respond.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of AP task dispatching.
-; This function must cause the indicated function code to be executed
-; upon the specified Application Processor. This procedure must be
-; executed in 32-bit mode. This function is required to be implemented
-; in the host environment.
-;
-; Dependencies:
-; The host environment must route execution to the target AP and
-; have that AP call the"AmdLateRunApTask" entry point.
-;
-AmdRunFuncOnAp PROC NEAR PUBLIC
-
- push es
- mov ax, SEG AmdRunCodeOnApDataPointer
- mov es, ax
- mov eax, (AP_EXE_PARAMS PTR [esi]).RelatedDataBlock
- mov es:AmdRunCodeOnApDataPointer, eax
- mov eax, (AP_EXE_PARAMS PTR [esi]).RelatedBlockLength
- mov es:AmdRunCodeOnApDataSize, eax
- mov eax, (AP_EXE_PARAMS PTR [esi]).FunctionNumber
- mov es:AmdRunCodeOnApFunction, eax
- mov eax, AGESA_UNSUPPORTED
- mov es:AmdRunCodeOnApStatus, eax
- pop es
-
- call myRunFuncOnAp
-
- push es
- mov ax, SEG AmdRunCodeOnApStatus
- mov es, ax
- mov eax, es:AmdRunCodeOnApStatus
- pop es
- ret
-AmdRunFuncOnAp ENDP
-
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCalloutRouterPost
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The call out router function for AmdInitEnv,
-; AmdInitMid, AmdInitLate, AmdS3Save, and
-; AmdS3LateRestore.
-;
-; Dependencies:
-; None
-;
-AmdCalloutRouterPost PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
- xor ax, ax
- mov ds, ax
- mov es, ax
- lea di, cs:CalloutRouterTablePost
- mov eax, AGESA_UNSUPPORTED
-
-loopThruTable:
- cmp di, OFFSET cs:CalloutRouterTablePostEnd
- jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
- cmp ecx, cs:[di].sOemCallout.FuncName
- je FoundMatch
- add di, SIZEOF sOemCallout
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemCallout.FuncPtr
- call bx
-
-amdCpuCalloutExit:
- ret
-AmdCalloutRouterPost ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the callout dispatch table for the POST segment
-;----------------------------------------------------------------------------
-
-CalloutRouterTablePost LABEL BYTE
- ;; Add entries as desired.
- sOemCallout <AGESA_ALLOCATE_BUFFER, OFFSET myAllocateBuffer>
- sOemCallout <AGESA_DEALLOCATE_BUFFER, OFFSET myDeallocateBuffer>
- sOemCallout <AGESA_LOCATE_BUFFER, OFFSET myLocateBuffer>
- sOemCallout <AGESA_RUNFUNC_ONAP, OFFSET AmdRunFuncOnAp>
-CalloutRouterTablePostEnd LABEL BYTE
-
-AMD_POST_END
-
-
-;----------------------------------------------------------------------------
-; CPU DATA SEGMENT
-; This segment must be writable, and present at the time that
-; AmdInitLate is run.
-;----------------------------------------------------------------------------
-
-CPU_DATASEG_START
-
- ;; Data used to store pointers for later use by the host environment.
- PUBLIC AmdAcpiSratPointer
- PUBLIC AmdAcpiSratSize
- PUBLIC AmdAcpiSlitPointer
- PUBLIC AmdAcpiSlitSize
- PUBLIC AmdAcpiSsdtPointer
- PUBLIC AmdAcpiSsdtSize
- PUBLIC AmdAcpiWheaMcePointer
- PUBLIC AmdAcpiWheaMceSize
- PUBLIC AmdAcpiWheaCmcPointer
- PUBLIC AmdAcpiWheaCmcSize
- PUBLIC AmdDmiInfoPointer
- AmdAcpiSratPointer DWORD ?
- AmdAcpiSratSize DWORD ?
- AmdAcpiSlitPointer DWORD ?
- AmdAcpiSlitSize DWORD ?
- AmdAcpiSsdtPointer DWORD ?
- AmdAcpiSsdtSize DWORD ?
- AmdAcpiWheaMcePointer DWORD ?
- AmdAcpiWheaMceSize DWORD ?
- AmdAcpiWheaCmcPointer DWORD ?
- AmdAcpiWheaCmcSize DWORD ?
- AmdDmiInfoPointer DWORD ?
-
- ;; Data used for communication between the AP and the BSP.
- PUBLIC AmdRunCodeOnApDataPointer
- PUBLIC AmdRunCodeOnApDataSize
- PUBLIC AmdRunCodeOnApFunction
- PUBLIC AmdRunCodeOnApStatus
- AmdRunCodeOnApDataPointer DWORD ?
- AmdRunCodeOnApDataSize DWORD ?
- AmdRunCodeOnApFunction DWORD ?
- AmdRunCodeOnApStatus DWORD ?
-
-CPU_DATASEG_END
-
-
-END
diff --git a/src/vendorcode/amd/agesa/f14/Legacy/agesa.inc b/src/vendorcode/amd/agesa/f14/Legacy/agesa.inc
deleted file mode 100644
index 84f9ec7bf1..0000000000
--- a/src/vendorcode/amd/agesa/f14/Legacy/agesa.inc
+++ /dev/null
@@ -1,2570 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * Agesa structures and definitions
-; *
-; * Contains AMD AGESA core interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 47417 $ @e \$Date: 2011-02-18 12:48:20 -0700 (Fri, 18 Feb 2011) $
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-INCLUDE amd.inc
-UINT64 TEXTEQU <QWORD>
-UINT32 TEXTEQU <DWORD>
-UINT16 TEXTEQU <WORD>
-UINT8 TEXTEQU <BYTE>
-CHAR8 TEXTEQU <BYTE>
-BOOLEAN TEXTEQU <BYTE>
-POINTER TEXTEQU <DWORD>
-
- ; AGESA Types and Definitions
-
-
-
- ; AGESA BASIC CALLOUTS
- AGESA_MEM_RELEASE EQU 00028000h
-
- ; AGESA ADVANCED CALLOUTS, Processor
- AGESA_CHECK_UMA EQU 00028100h
- AGESA_DO_RESET EQU 00028101h
- AGESA_ALLOCATE_BUFFER EQU 00028102h
- AGESA_DEALLOCATE_BUFFER EQU 00028103h
- AGESA_LOCATE_BUFFER EQU 00028104h
- AGESA_RUNFUNC_ONAP EQU 00028105h
-
- ; AGESA ADVANCED CALLOUTS, HyperTransport
-
- ; AGESA ADVANCED CALLOUTS, Memory
- AGESA_READ_SPD EQU 00028140h
- AGESA_HOOKBEFORE_DRAM_INIT EQU 00028141h
- AGESA_HOOKBEFORE_DQS_TRAINING EQU 00028142h
- AGESA_READ_SPD_RECOVERY EQU 00028143h
- AGESA_HOOKBEFORE_EXIT_SELF_REF EQU 00028144h
- AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY EQU 00028145h
-
- ; AGESA IDS CALLOUTS
- AGESA_GET_IDS_INIT_DATA EQU 00028200h
-
- ; AGESA GNB CALLOUTS
- AGESA_GNB_PCIE_SLOT_RESET EQU 00028301h
-; ------------------------------------------------------------------------
-
- ; HyperTransport Interface
-
-
-
-; -----------------------------------------------------------------------------
- ; HT DEFINITIONS AND MACROS
-
-; -----------------------------------------------------------------------------
-
-
- ; Width equates for call backs
- HT_WIDTH_8_BITS EQU 8
- HT_WIDTH_16_BITS EQU 16
- HT_WIDTH_4_BITS EQU 4
- HT_WIDTH_2_BITS EQU 2
- HT_WIDTH_NO_LIMIT EQU HT_WIDTH_16_BITS
-
- ; Frequency Limit equates for call backs which take a frequency supported mask.
- HT_FREQUENCY_LIMIT_200M EQU 1
- HT_FREQUENCY_LIMIT_400M EQU 7
- HT_FREQUENCY_LIMIT_600M EQU 1Fh
- HT_FREQUENCY_LIMIT_800M EQU 3Fh
- HT_FREQUENCY_LIMIT_1000M EQU 7Fh
- HT_FREQUENCY_LIMIT_HT1_ONLY EQU 7Fh
- HT_FREQUENCY_LIMIT_1200M EQU 0FFh
- HT_FREQUENCY_LIMIT_1400M EQU 1FFh
- HT_FREQUENCY_LIMIT_1600M EQU 3FFh
- HT_FREQUENCY_LIMIT_1800M EQU 7FFh
- HT_FREQUENCY_LIMIT_2000M EQU 0FFFh
- HT_FREQUENCY_LIMIT_2200M EQU 1FFFh
- HT_FREQUENCY_LIMIT_2400M EQU 3FFFh
- HT_FREQUENCY_LIMIT_2600M EQU 7FFFh
- HT_FREQUENCY_LIMIT_2800M EQU 27FFFh
- HT_FREQUENCY_LIMIT_3000M EQU 67FFFh
- HT_FREQUENCY_LIMIT_3200M EQU 0E7FFFh
- HT_FREQUENCY_LIMIT_3600M EQU 1E7FFFh
- HT_FREQUENCY_LIMIT_MAX EQU HT_FREQUENCY_LIMIT_3600M
- HT_FREQUENCY_NO_LIMIT EQU 0FFFFFFFFh
-
- ; Unit ID Clumping special values
- HT_CLUMPING_DISABLE EQU 00000000h
- HT_CLUMPING_NO_LIMIT EQU 0FFFFFFFFh
-
- HT_LIST_TERMINAL EQU 0FFh
- HT_LIST_MATCH_ANY EQU 0FEh
- HT_LIST_MATCH_INTERNAL_LINK EQU 0FDh
-
- ; Event Notify definitions
-
- ; Event definitions.
-
- ; Coherent subfunction events
- HT_EVENT_COH_EVENTS EQU 10001000h
- HT_EVENT_COH_NO_TOPOLOGY EQU 10011000h
- HT_EVENT_COH_OBSOLETE000 EQU 10021000h
- HT_EVENT_COH_PROCESSOR_TYPE_MIX EQU 10031000h
- HT_EVENT_COH_NODE_DISCOVERED EQU 10041000h
- HT_EVENT_COH_MPCAP_MISMATCH EQU 10051000h
-
- ; Non-coherent subfunction events
- HT_EVENT_NCOH_EVENTS EQU 10002000h
- HT_EVENT_NCOH_BUID_EXCEED EQU 10012000h
- HT_EVENT_NCOH_OBSOLETE000 EQU 10022000h
- HT_EVENT_NCOH_BUS_MAX_EXCEED EQU 10032000h
- HT_EVENT_NCOH_CFG_MAP_EXCEED EQU 10042000h
- HT_EVENT_NCOH_DEVICE_FAILED EQU 10052000h
- HT_EVENT_NCOH_AUTO_DEPTH EQU 10062000h
-
- ; Optimization subfunction events
- HT_EVENT_OPT_EVENTS EQU 10003000h
- HT_EVENT_OPT_REQUIRED_CAP_RETRY EQU 10013000h
- HT_EVENT_OPT_REQUIRED_CAP_GEN3 EQU 10023000h
- HT_EVENT_OPT_UNUSED_LINKS EQU 10033000h
- HT_EVENT_OPT_LINK_PAIR_EXCEED EQU 10043000h
-
- ; HW Fault events
- HT_EVENT_HW_EVENTS EQU 10004000h
- HT_EVENT_HW_SYNCFLOOD EQU 10014000h
- HT_EVENT_HW_HTCRC EQU 10024000h
-
- ; The Recovery HT component uses 0x10005000 for events.
- ; For consistency, we avoid that range here.
-
- HT_MAX_NC_BUIDS EQU 32
-; ----------------------------------------------------------------------------
- ; HT TYPEDEFS, STRUCTURES, ENUMS
-
-; ----------------------------------------------------------------------------
-MATCHED EQU 0 ; < The link matches the requested customization.
-POWERED_OFF EQU 1 ; < Power the link off.
-UNMATCHED EQU 2 ; < The link should be processed according to normal defaults.
-MaxFinalLinkState EQU 3 ; < Not a final link state, use for limit checking.
-FINAL_LINK_STATE TEXTEQU <DWORD>
-
- ; Swap a device from its current id to a new one.
-
-BUID_SWAP_ITEM STRUCT
- FromId UINT8 ? ; < The device responding to FromId,
- ToId UINT8 ? ; < will be moved to ToId.
-BUID_SWAP_ITEM ENDS
-
-
- ; Each Non-coherent chain may have a list of device swaps. After performing the swaps,
- ; the final in order list of device ids is provided. (There can be more swaps than devices.)
- ; The unused entries in both are filled with 0xFF.
-
-BUID_SWAP_LIST STRUCT
- Swaps BUID_SWAP_ITEM (HT_MAX_NC_BUIDS) DUP ({}) ; < The BUID Swaps to perform
- FinalIds UINT8 (HT_MAX_NC_BUIDS) DUP (?) ; < The ordered final BUIDs, resulting from the swaps
-BUID_SWAP_LIST ENDS
-
-
- ; Control Manual Initialization of Non-Coherent Chains
-
- ; This interface is checked every time a non-coherent chain is
- ; processed. BUID assignment may be controlled explicitly on a
- ; non-coherent chain. Provide a swap list. Swaps controls the
- ; BUID assignment and FinalIds provides the device to device
- ; Linking. Device orientation can be detected automatically, or
- ; explicitly. See interface documentation for more details.
-
- ; If a manual swap list is not supplied,
- ; automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
- ; based on each device's unit count.
-
-MANUAL_BUID_SWAP_LIST STRUCT
- ; Match fields
- Socket UINT8 ? ; < The Socket on which this chain is located
- Link UINT8 ? ; < The Link on the host for this chain
- ; Override fields
- SwapList BUID_SWAP_LIST {} ; < The swap list
-MANUAL_BUID_SWAP_LIST ENDS
-
-
- ; Override options for DEVICE_CAP_OVERRIDE.
-
- ; Specify which override actions should be performed. For Checks, 1 means to check the item
- ; and 0 means to skip the check. For the override options, 1 means to apply the override and
- ; 0 means to ignore the override.
-
-DEVICE_CAP_OVERRIDE_OPTIONS STRUCT
- IsCheckDevVenId UINT32 ?
-; IN UINT32 IsCheckDevVenId:1; ; < Check Match on Device/Vendor id
-; IN UINT32 IsCheckRevision:1; ; < Check Match on device Revision
-; IN UINT32 IsOverrideWidthIn:1; ; < Override Width In
-; IN UINT32 IsOverrideWidthOut:1; ; < Override Width Out
-; IN UINT32 IsOverrideFreq:1; ; < Override Frequency
-; IN UINT32 IsOverrideClumping:1; ; < Override Clumping
-; IN UINT32 IsDoCallout:1; ; < Make the optional callout
-DEVICE_CAP_OVERRIDE_OPTIONS ENDS
-
- ; Override capabilities of a device.
-
- ; This interface is checked once for every Link on every IO device.
- ; Provide the width and frequency capability if needed for this device.
- ; This is used along with device capabilities, the limit interfaces, and northbridge
- ; limits to compute the default settings. The components of the device's PCI config
- ; address are provided, so its settings can be consulted if need be.
- ; The optional callout is a catch all.
-
-DEVICE_CAP_OVERRIDE STRUCT
- ; Match fields
- HostSocket UINT8 ? ; < The Socket on which this chain is located.
- HostLink UINT8 ? ; < The Link on the host for this chain.
- Depth UINT8 ? ; < The Depth in the I/O chain from the Host.
- DevVenId UINT32 ? ; < The Device's PCI Vendor + Device ID (offset 0x00).
- Revision UINT8 ? ; < The Device's PCI Revision field (offset 0x08).
- Link UINT8 ? ; < The Device's Link number (0 or 1).
- Options DEVICE_CAP_OVERRIDE_OPTIONS {} ; < The options for this device override.
- ; Override fields
- LinkWidthIn UINT8 ? ; < modify to change the Link Width In.
- LinkWidthOut UINT8 ? ; < modify to change the Link Width Out.
- FreqCap UINT32 ? ; < modify to change the Link's frequency capability.
- Clumping UINT32 ? ; < modify to change Unit ID clumping support.
- Callout CALLOUT_ENTRY ? ; < optional call for really complex cases, or NULL.
-DEVICE_CAP_OVERRIDE ENDS
-
- ; Callout param struct for override capabilities of a device.
-
- ; If the optional callout is implemented this param struct is passed to it.
-
-DEVICE_CAP_CALLOUT_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < The header
- ; Match fields
- HostSocket UINT8 ? ; < The Socket on which this chain is located.
- HostLink UINT8 ? ; < The Link on the host for this chain.
- Depth UINT8 ? ; < The Depth in the I/O chain from the Host.
- DevVenId UINT32 ? ; < The Device's PCI Vendor + Device ID (offset 0x00).
- Revision UINT8 ? ; < The Device's PCI Revision field (offset 0x08).
- Link UINT8 ? ; < The Device's Link number (0 or 1).
- PciAddress PCI_ADDR {} ; < The Device's PCI Address.
- ; Override fields
- LinkWidthIn POINTER ? ; < modify to change the Link Width In.
- LinkWidthOut POINTER ? ; < modify to change the Link Width Out.
- FreqCap POINTER ? ; < modify to change the Link's frequency capability.
- Clumping POINTER ? ; < modify to change Unit ID clumping support.
-DEVICE_CAP_CALLOUT_PARAMS ENDS
-
- ; Limits for CPU to CPU Links.
-
- ; For each coherent connection this interface is checked once.
- ; Provide the frequency and width if needed for this Link (usually based on board
- ; restriction). This is used with CPU device capabilities and northbridge limits
- ; to compute the default settings.
-
-CPU_TO_CPU_PCB_LIMITS STRUCT
- ; Match fields
- SocketA UINT8 ? ; < One Socket on which this Link is located
- LinkA UINT8 ? ; < The Link on this Node
- SocketB UINT8 ? ; < The other Socket on which this Link is located
- LinkB UINT8 ? ; < The Link on that Node
- ; Limit fields
- ABLinkWidthLimit UINT8 ? ; < modify to change the Link Width A->B
- BALinkWidthLimit UINT8 ? ; < modify to change the Link Width B-<A
- PcbFreqCap UINT32 ? ; < modify to change the Link's frequency capability
-CPU_TO_CPU_PCB_LIMITS ENDS
-
- ; Get limits for non-coherent Links.
-
- ; For each non-coherent connection this interface is checked once.
- ; Provide the frequency and width if needed for this Link (usually based on board
- ; restriction). This is used with device capabilities, device overrides, and northbridge limits
- ; to compute the default settings.
-
-IO_PCB_LIMITS STRUCT
- ; Match fields
- HostSocket UINT8 ? ; < The Socket on which this Link is located
- HostLink UINT8 ? ; < The Link about to be initialized
- Depth UINT8 ? ; < The Depth in the I/O chain from the Host
- ; Limit fields
- DownstreamLinkWidthLimit UINT8 ? ; < modify to change the Link Width going away from processor
- UpstreamLinkWidthLimit UINT8 ? ; < modify to change the Link Width moving toward processor
- PcbFreqCap UINT32 ? ; < modify to change the Link's frequency capability
-IO_PCB_LIMITS ENDS
-
- ; Manually control bus number assignment.
-
- ; This interface is checked every time a non-coherent chain is processed.
- ; If a system can not use the auto Bus numbering feature for non-coherent chain bus
- ; assignments, this interface can provide explicit control. For each chain, provide
- ; the bus number range to use.
-
-OVERRIDE_BUS_NUMBERS STRUCT
- ; Match fields
- Socket UINT8 ? ; < The Socket on which this chain is located
- Link UINT8 ? ; < The Link on the host for this chain
- ; Override fields
- SecBus UINT8 ? ; < Secondary Bus number for this non-coherent chain
- SubBus UINT8 ? ; < Subordinate Bus number
-OVERRIDE_BUS_NUMBERS ENDS
-
-
- ; Ignore a Link.
-
- ; This interface is checked every time a coherent Link is found and then every
- ; time a non-coherent Link from a CPU is found.
- ; Any coherent or non-coherent Link from a CPU can be ignored and not used
- ; for discovery or initialization. Useful for connection based systems.
- ; (Note: not checked for IO device to IO Device Links.)
-
-IGNORE_LINK STRUCT
- ; Match fields
- Socket UINT8 ? ; < The Socket on which this Link is located
- Link UINT8 ? ; < The Link about to be initialized
- ; Customization fields
- LinkState FINAL_LINK_STATE ? ; < The link may be left unitialized, or powered off.
-IGNORE_LINK ENDS
-
-
- ; Skip reganging of subLinks.
-
- ; This interface is checked whenever two subLinks are both connected to the same CPUs.
- ; Normally, unganged sublinks between the same two CPUs are reganged.
- ; Provide a matching structure to leave the Links unganged.
-
-SKIP_REGANG STRUCT
- ; Match fields
- SocketA UINT8 ? ; < One Socket on which this Link is located
- LinkA UINT8 ? ; < The Link on this Node
- SocketB UINT8 ? ; < The other Socket on which this Link is located
- LinkB UINT8 ? ; < The Link on that Node
- ; Customization fields
- LinkState FINAL_LINK_STATE ? ; < The paired sublink may be active, or powered off.
-SKIP_REGANG ENDS
-
- ; The System Socket layout, which sockets are physically connected.
-
- ; The hardware method for Socket naming is preferred. Use this software method only
- ; if required.
-
-SYSTEM_PHYSICAL_SOCKET_MAP STRUCT
- CurrentSocket UINT8 ? ; < The socket from which this connection originates.
- CurrentLink UINT8 ? ; < The Link from the source socket connects to another socket.
- TargetSocket UINT8 ? ; < The target socket which is connected on that link.
-SYSTEM_PHYSICAL_SOCKET_MAP ENDS
-
-; ----------------------------------------------------------------------------
-
- ; This is the input structure for AmdHtInitialize.
-
-AMD_HT_INTERFACE STRUCT
- ; Basic level customization
- AutoBusStart UINT8 ? ; < For automatic bus number assignment, starting bus number usually zero.
- AutoBusMax UINT8 ? ; < For automatic bus number assignment, do not assign above max.
- AutoBusIncrement UINT8 ? ; < For automatic bus number assignment, each chain gets this many busses.
-
- ; Advanced Level Customization
- ManualBuidSwapList POINTER ? ; < Provide Manual Swap List, if any.
- DeviceCapOverrideList POINTER ? ; < Provide Device Overrides, if any.
- CpuToCpuPcbLimitsList POINTER ? ; < Provide CPU PCB Limits, if any.
- IoPcbLimitsList POINTER ? ; < Provide IO PCB Limits, if any.
- OverrideBusNumbersList POINTER ? ; < Provide manual Bus Number assignment, if any.
- ; < Use either auto bus numbering or override bus
- ; < numbers, not both.
-
- IgnoreLinkList POINTER ? ; < Provide links to ignore, if any.
- SkipRegangList POINTER ? ; < Provide links to remain unganged, if any.
-
- ; Expert Level Customization
- Topolist POINTER ? ; < Use this topology list in addition to the built in, if not NULL.
- SystemPhysicalSocketMap POINTER ?
- ; < The hardware socket naming method is preferred,
- ; < If it can't be used, this provides a software method.
-AMD_HT_INTERFACE ENDS
-
-; -----------------------------------------------------------------------------
-
- ; HT Recovery Interface
-
-
-
-; -----------------------------------------------------------------------------
-; * HT Recovery DEFINITIONS AND MACROS
-; *
-; *-----------------------------------------------------------------------------
-;
-
- ; BBHT subfunction events
- HT_EVENT_BB_EVENTS EQU 10005000h
- HT_EVENT_BB_BUID_EXCEED EQU 10015000h
- HT_EVENT_BB_DEVICE_FAILED EQU 10055000h
- HT_EVENT_BB_AUTO_DEPTH EQU 10065000h
-
-; ----------------------------------------------------------------------------
-; * HT Recovery TYPEDEFS, STRUCTURES, ENUMS
-; *
-; *----------------------------------------------------------------------------
-;
-
-
- ; The Interface structure to Recovery HT.
-
-AMD_HT_RESET_INTERFACE STRUCT
- ManualBuidSwapList POINTER ? ; < Option to manually control SB link init
- Depth UINT32 ? ; < If auto init was used this is set to the depth of the chain,
- ; < else, for manual init unmodified.
-AMD_HT_RESET_INTERFACE ENDS
-
-; ---------------------------------------------------------------------------
-; CPU Feature related info
-; ---------------------------------------------------------------------------
- ; Build Configuration values for BLDCFG_PLATFORM_C1E_MODE
- C1eModeDisabled EQU 0 ; < Disabled
- C1eModeHardware EQU 1 ; < Hardware method
- C1eModeMsgBased EQU 2 ; < Message-based method
- C1eModeSoftwareDeprecated EQU 3 ; < Deprecated software SMI method
- C1eModeHardwareSoftwareDeprecated EQU 4 ; < Hardware or Deprecated software SMI method
- MaxC1eMode EQU 5 ; < Not a valid value, used for verifying input
-PLATFORM_C1E_MODES TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
- CStateModeDisabled EQU 0 ; < Disabled
- CStateModeC6 EQU 1 ; < C6 State
- MaxCStateMode EQU 2 ; < Not a valid value, used for verifying input
-PLATFORM_CSTATE_MODES TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_PLATFORM_CPB_MODE
- CpbModeAuto EQU 0 ; < Auto
- CpbModeDisabled EQU 1 ; < Disabled
- MaxCpbMode EQU 2 ; < Not a valid value, used for verifying input
-PLATFORM_CPB_MODES TEXTEQU <DWORD>
-
-
-;----------------------------------------------------------------------------
-; GNB PCIe configuration info
-;----------------------------------------------------------------------------
-
-GNB_EVENT_INVALID_CONFIGURATION EQU 20010000h ; User configuration invalid
-GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION EQU 20010001h ; Requested lane allocation for PCIe port can not be supported
-GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION EQU 20010002h ; Requested incorrect PCIe port device address
-GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION EQU 20010003h ; Incorrect parameter in DDI link configuration
-GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION EQU 20010004h ; Invalid with for PCIe port or DDI link
-GNB_EVENT_INVALID_LANES_CONFIGURATION EQU 20010005h ; Lane double subscribe lanes
-GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION EQU 20010006h ; Requested lane allocation for DDI link(s) can not be supported
-GNB_EVENT_LINK_TRAINING_FAIL EQU 20020000h ; PCIe Link training fail
-GNB_EVENT_BROKEN_LANE_RECOVERY EQU 20030000h ; Broken lane workaround applied to recover link training
-GNB_EVENT_GEN2_SUPPORT_RECOVERY EQU 20040000h ; Scale back to GEN1 to recover link training
-
-DESCRIPTOR_TERMINATE_LIST EQU 80000000h
-
-PCIe_PORT_MISC_CONTROL STRUCT
- LinkComplianceMode UINT8 ?
- ;IN UINT8 LinkComplianceMode :1; ;< Force port into compliance mode (device will not be trained, port output compliance pattern)
-PCIe_PORT_MISC_CONTROL ENDS
-
-PCIe_PORT_DATA STRUCT
- PortPresent UINT8 ? ; < Enable PCIe port for initialization.
- ChannelType UINT8 ? ; < Channel type.
- ; 0 - "lowLoss",
- ; 1 - "highLoss",
- ; 2 - "mob0db",
- ; 3 - "mob3db",
- ; 4 - "extnd6db"
- ; 5 - "extnd8db"
- ;
- DeviceNumber UINT8 ? ; < Device number for port. Available device numbers may very on different CPUs.
- FunctionNumber UINT8 ? ; < Reserved for future use
- LinkSpeedCapability UINT8 ? ; < Advertised Gen Capability
- ; 0 - Maximum supported by silicon
- ; 1 - Gen1
- ; 2 - Gen2
- ; 3 - Gen3
- ;
- LinkAspm UINT8 ? ; < ASPM control. (see OemPcieLinkAspm for additional option to control ASPM)
- ; 0 - Disabled
- ; 1 - L0s only
- ; 2 - L1 only
- ; 2 - L0s and L1
- ;
- LinkHotplug UINT8 ? ; < Hotplug control.
- ; 0 - Disabled
- ; 1 - Basic
- ; 2 - Server
- ; 3 - Enhanced
- ;
- ResetId UINT8 ? ; < Arbitrary number greater than 0 assigned by platform firmware for GPIO
- ; identification which control reset for given port.
- ; Each port with unique GPIO should have unique ResetId assigned.
- ; All ports use same GPIO to control reset should have same ResetId assigned.
- ; see AgesaPcieSlotResetControl
- ;
- MiscControls PCIe_PORT_MISC_CONTROL {} ; < Misc extended controls
-PCIe_PORT_DATA ENDS
-
-;DDI channel lane mapping
-
-CHANNEL_MAPPING STRUCT ;
- Lane0 UINT8 ? ;
- ;IN UINT8 Lane0 :2; ;
- ;IN UINT8 Lane1 :2; ///< Lane 1 mapping (see "Lane 0 mapping")
- ;IN UINT8 Lane2 :2; ///< Lane 2 mapping (see "Lane 0 mapping")
- ;IN UINT8 Lane3 :2; ///< Lane 3 mapping (see "Lane 0 mapping")
-CHANNEL_MAPPING ENDS ;
-
-CONN_CHANNEL_MAPPING UNION
- ChannelMappingValue UINT8 ? ; < Raw lane mapping
- ChannelMapping CHANNEL_MAPPING {} ;
-CONN_CHANNEL_MAPPING ENDS ;
-
-; DDI Configuration
-PCIe_DDI_DATA STRUCT
- ConnectorType UINT8 ? ; < Display Connector Type
- ; 0 - DP
- ; 1 - eDP
- ; 2 - Single Link DVI
- ; 3 - Dual Link DVI
- ; 4 - HDMI
- ; 5 - Travis DP-to-VGA
- ; 6 - Travis DP-to-LVDS
- ; 7 - Hudson-2 NutMeg DP-to-VGA
- ; 8 - Single Link DVI-I
- ; 9 - CRT (VGA)
- ; 10 - LVDS
- ; 11 - VBIOS auto detect connector type
- AuxIndex UINT8 ? ; < Indicates which AUX or DDC Line is used
- ; 0 - AUX1
- ; 1 - AUX2
- ; 2 - AUX3
- ; 3 - AUX4
- ; 4 - AUX5
- ; 5 - AUX6
- ;
- HdpIndex UINT8 ? ; < Indicates which HDP pin is used
- ; 0 - HDP1
- ; 1 - HDP2
- ; 2 - HDP3
- ; 3 - HDP4
- ; 4 - HDP5
- ; 5 - HDP6
- Mapping CONN_CHANNEL_MAPPING (2) DUP ({}) ;< Set specific mapping of lanes to connector pins
- ;Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane
- ;Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only
- ;applicable for Dual DDI link)
- ;if Mapping[x] set to 0 than default mapping assumed
-
-PCIe_DDI_DATA ENDS
-
-
-; Engine Configuration
-PCIe_ENGINE_DATA STRUCT
- EngineType UINT8 ? ; < Engine type
- ; 0 - Ignore engine configuration
- ; 1 - PCIe port
- ; 2 - DDI
- StartLane UINT16 ? ; < Start lane number (in reversed configuration StartLane > EndLane).
- EndLane UINT16 ? ; < End lane number (in reversed configuration StartLane > EndLane).
-PCIe_ENGINE_DATA ENDS
-
-; PCIe port descriptor
-PCIe_PORT_DESCRIPTOR STRUCT
- Flags UINT32 ? ; < Descriptor flags
- ; Bit31 - last descriptor in complex
- EngineData PCIe_ENGINE_DATA {} ; < Engine data
- Port PCIe_PORT_DATA {} ; < PCIe port specific configuration info
-PCIe_PORT_DESCRIPTOR ENDS
-
-; DDI descriptor
-PCIe_DDI_DESCRIPTOR STRUCT
- Flags UINT32 ? ; < Descriptor flags
- EngineData PCIe_ENGINE_DATA {} ; < Engine data
- Ddi PCIe_DDI_DATA {} ; < DDI port specific configuration info
-PCIe_DDI_DESCRIPTOR ENDS
-
-; Slot Reset Info
-PCIe_SLOT_RESET_INFO STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < AGESA Standard Header
- ResetId UINT8 ? ; < Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
- ResetControl UINT8 ? ; < Reset control as defined by PCIE_RESET_CONTROL
-PCIe_SLOT_RESET_INFO ENDS
-
-
-; PCIe Complex descriptor
-PCIe_COMPLEX_DESCRIPTOR STRUCT
- Flags UINT32 ? ; < Descriptor flags
- ; Bit31 - last descriptor in topology
- ;
- ;
- SocketId UINT32 ? ; < Socket Id
- PciePortList POINTER ? ;< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
- DdiLinkList POINTER ? ;< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
- Reserved POINTER ? ;< Reserved for future use
-PCIe_COMPLEX_DESCRIPTOR ENDS
-
- AssertSlotReset EQU 0
- DeassertSlotReset EQU 1
-PCIE_RESET_CONTROL TEXTEQU <DWORD>
-
- PcieUnusedEngine EQU 0
- PciePortEngine EQU 1
- PcieDdiEngine EQU 2
- MaxPcieEngine EQU 3 ; < Not a valid value, used for verifying input
-PCIE_ENGINE_TYPE TEXTEQU <DWORD>
-
- PcieGenMaxSupported EQU 0
- PcieGen1 EQU 1
- PcieGen2 EQU 2
- MaxPcieGen EQU 3 ; < Not a valid value, used for verifying input
-PCIE_LINK_SPEED_CAP TEXTEQU <DWORD>
-
- PsppDisabled EQU 0
- PsppPerformance EQU 1
- PsppBalanceHigh EQU 2
- PsppBalanceLow EQU 3
- PsppPowerSaving EQU 4
- MaxPspp EQU 5 ; < Not a valid value, used for verifying input
-PCIE_PSPP_POLICY TEXTEQU <DWORD>
-
- ConnectorTypeDP EQU 0
- ConnectorTypeEDP EQU 1
- ConnectorTypeSingleLinkDVI EQU 2
- ConnectorTypeDualLinkDVI EQU 3
- ConnectorTypeHDMI EQU 4
- ConnectorTypeTravisDpToVga EQU 5
- ConnectorTypeTravisDpToLvds EQU 6
- ConnectorTypeNutmegDpToVga EQU 7
- ConnectorTypeSingleLinkDviI EQU 8
- ConnectorTypeCrt EQU 9
- ConnectorTypeLvds EQU 10
- ConnectorTypeAutoDetect EQU 11
- MaxConnectorType EQU 12 ; < Not a valid value, used for verifying input
-PCIE_CONNECTOR_TYPE TEXTEQU <DWORD>
-
- ChannelTypeLowLoss EQU 0
- ChannelTypeHighLoss EQU 1
- ChannelTypeMob0db EQU 2
- ChannelTypeMob3db EQU 3
- ChannelTypeExt6db EQU 4
- ChannelTypeExt8db EQU 5
- MaxChannelType EQU 6 ; < Not a valid value, used for verifying input
-PCIE_CHANNEL_TYPE TEXTEQU <DWORD>
-
- AspmDisabled EQU 0
- AspmL0s EQU 1
- AspmL1 EQU 2
- AspmL0sL1 EQU 3
- MaxAspm EQU 4 ; < Not a valid value, used for verifying input
-PCIE_ASPM_TYPE TEXTEQU <DWORD>
-
- HotplugDisabled EQU 0
- HotplugBasic EQU 1
- HotplugServer EQU 2
- HotplugEnhanced EQU 3
- HotplugInboard EQU 4
- MaxHotplug EQU 5 ; < Not a valid value, used for verifying input
-PCIE_HOTPLUG_TYPE TEXTEQU <DWORD>
-
- PortDisabled EQU 0
- PortEnabled EQU 1
-PCIE_PORT_ENABLE TEXTEQU <DWORD>
-
- Aux1 EQU 0
- Aux2 EQU 1
- Aux3 EQU 2
- Aux4 EQU 3
- Aux5 EQU 4
- Aux6 EQU 5
- MaxAux EQU 6 ; < Not a valid value, used for verifying input
-PCIE_AUX_TYPE TEXTEQU <DWORD>
-
- Hdp1 EQU 0
- Hdp2 EQU 1
- Hdp3 EQU 2
- Hdp4 EQU 3
- Hdp5 EQU 4
- Hdp6 EQU 5
- MaxHdp EQU 6 ; < Not a valid value, used for verifying input
-PCIE_HDP_TYPE TEXTEQU <DWORD>
-
-;----------------------------------------------------------------------------
-; GNB configuration info
-;----------------------------------------------------------------------------
-;
-
-; LVDS Misc Control Field
-LVDS_MISC_CONTROL_FIELD STRUCT
- FpdiMode UINT8 ?
- ;IN UINT8 FpdiMode:1;
- ;IN UINT8 DlChSwap:1;
- ;IN UINT8 VsyncActiveLow:1;
- ;IN UINT8 HsyncActiveLow:1;
- ;IN UINT8 BLONActiveLow:1;
- ;IN UINT8 Reserved:3;
-LVDS_MISC_CONTROL_FIELD ENDS
-
-; LVDS Misc Control
-LVDS_MISC_CONTROL UNION
- Field LVDS_MISC_CONTROL_FIELD {}
- Value UINT8 ?
-LVDS_MISC_CONTROL ENDS
-
-; Configuration settings for GNB.
-GNB_ENV_CONFIGURATION STRUCT
- Gnb3dStereoPinIndex UINT8 ? ;< 3D Stereo Pin ID.
- ; @li 0 = Stereo 3D is disabled (default).
- ; @li 1 = Use processor pin HPD1.
- ; @li 2 = Use processor pin HPD2
- ; @li 3 = Use processor pin HPD3
- ; @li 4 = Use processor pin HPD4
- ; @li 5 = Use processor pin HPD5
- ; @li 6 = Use processor pin HPD6
- LvdsSpreadSpectrum UINT16 ? ; Spread spectrum value in 0.01 %
- LvdsSpreadSpectrumRate UINT16 ? ; Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
- LvdsMiscControl LVDS_MISC_CONTROL {} ; This item configures LVDS swap/Hsync/Vsync/BLON
- PcieRefClkSpreadSpectrum UINT16 ? ; Spread spectrum value in 0.01 %
-GNB_ENV_CONFIGURATION ENDS
-
-; GNB configuration info
-GNB_CONFIGURATION STRUCT
- PcieComplexList POINTER ? ; Pointer to array of PCIe_COMPLEX_DESCRIPTOR structures describe PCIe topology on each processor package or NULL.
- ; Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST
- ;
- ;
- ;
- ; Topology organization definition assume PCIe_COMPLEX_DESCRIPTOR defined first following
- ; PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR for given PCIe_COMPLEX_DESCRIPTOR
- ; defined in arbitrary sequence:
- ; Example of topology definition for single socket system:
- ; PlatfromTopology LABEL DWORD
- ;
- ; Port0_2 PCIe_PORT_DESCRIPTOR <>;
- ; Port0_3 PCIe_PORT_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST> ;
- ; ...
- ; Ddi0_A PCIe_DDI_DESCRIPTOR <>;
- ; Ddi0_B PCIe_DDI_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST,>;
- ; ...
- ; Cpu0 PCIe_COMPLEX_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST, 0, Port0_2, Ddi0_A>
- ;
- ;
- PsppPolicy UINT8 ? ;< PSPP (PCIe Speed Power Policy)
- ; @li @b 0 - Disabled
- ; @li @b 1 - Performance
- ; @li @b 2 - Balance-High
- ; @li @b 3 - Balance-Low
- ; @li @b 4 - Power Saving
- ;
-GNB_CONFIGURATION ENDS
-
-
-; ---------------------------------------------------------------------------
-
-; MEMORY-SPECIFIC DATA STRUCTURES
-
-; ---------------------------------------------------------------------------
-
-
- ; AGESA MAXIMIUM VALUES
-
- ; These Max values are used to define array sizes and associated loop
- ; counts in the code. They reflect the maximum values that AGESA
- ; currently supports and does not necessarily reflect the hardware
- ; capabilities of configuration.
-
-
- MAX_SOCKETS_SUPPORTED EQU 8 ; < Max number of sockets in system
- MAX_CHANNELS_PER_SOCKET EQU 4 ; < Max Channels per sockets
- MAX_DIMMS_PER_CHANNEL EQU 4 ; < Max DIMMs on a memory channel (independent of platform)
- NUMBER_OF_DELAY_TABLES EQU 9 ; < Number of tables defined in CH_DEF_STRUCT.
- ; < Eg: UINT16 *RcvEnDlys;
- ; < UINT8 *WrDqsDlys;
- ; < UINT8 *RdDqsDlys;
- ; < UINT8 *WrDatDlys;
- ; < UINT8 *RdDqsMinDlys;
- ; < UINT8 *RdDqsMaxDlys;
- ; < UINT8 *WrDatMinDlys;
- ; < UINT8 *WrDatMaxDlys;
- NUMBER_OF_FAILURE_MASK_TABLES EQU 1 ; < Number of failure mask tables
- MAX_PLATFORM_TYPES EQU 16 ; < Platform types per system
-
- MCT_TRNG_KEEPOUT_START EQU 00004000h ; < base [39:8]
- MCT_TRNG_KEEPOUT_END EQU 00007FFFh ; < base [39:8]
-
- UMA_ATTRIBUTE_INTERLEAVE EQU 80000000h ; < Uma Region is interleaved
- UMA_ATTRIBUTE_ON_DCT0 EQU 40000000h ; < UMA resides on memory that belongs to DCT0
- UMA_ATTRIBUTE_ON_DCT1 EQU 20000000h ; < UMA resides on memory that belongs to DCT1
-
- PSO_TABLE TEXTEQU <UINT8>; < Platform Configuration Table
-
- ; AGESA DEFINITIONS
-
- ; Many of these are derived from the platform and hardware specific definitions
-
- ; EccSymbolSize override value
- ECCSYMBOLSIZE_USE_BKDG EQU 0 ; < Use BKDG Recommended Value
- ECCSYMBOLSIZE_FORCE_X4 EQU 4 ; < Force to x4
- ECCSYMBOLSIZE_FORCE_X8 EQU 8 ; < Force to x8
- ; CPU Package Type
- PT_L1 EQU 0 ; < L1 Package type
- PT_M2 EQU 1 ; < AM Package type
- PT_S1 EQU 2 ; < S1 Package type
-
- ; Structures use to pass system Logical CPU-ID
-CPU_LOGICAL_ID STRUCT
- Family UINT64 ? ; < Indicates logical ID Family
- Revision UINT64 ? ; < Indicates logical ID Family
-CPU_LOGICAL_ID ENDS
-
- ; Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
-
- AMD_PLATFORM_SERVER EQU 8000h ; < Server
- AMD_PLATFORM_DESKTOP EQU 10000h ; < Desktop
- AMD_PLATFORM_MOBILE EQU 20000h ; < Mobile
-AMD_PLATFORM_TYPE TEXTEQU <DWORD>
-
- ; Dram technology type
-
- DDR2_TECHNOLOGY EQU 0 ; < DDR2 technology
- DDR3_TECHNOLOGY EQU 1 ; < DDR3 technology
-TECHNOLOGY_TYPE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
-
- DDR400_FREQUENCY EQU 200 ; < DDR 400
- DDR533_FREQUENCY EQU 266 ; < DDR 533
- DDR667_FREQUENCY EQU 333 ; < DDR 667
- DDR800_FREQUENCY EQU 400 ; < DDR 800
- DDR1066_FREQUENCY EQU 533 ; < DDR 1066
- DDR1333_FREQUENCY EQU 667 ; < DDR 1333
- DDR1600_FREQUENCY EQU 800 ; < DDR 1600
- DDR1866_FREQUENCY EQU 933 ; < DDR 1866
- UNSUPPORTED_DDR_FREQUENCY EQU 934 ; < Highest limit of DDR frequency
-MEMORY_BUS_SPEED TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
-
- QUADRANK_REGISTERED EQU 0
- QUADRANK_UNBUFFERED EQU 1
-QUANDRANK_TYPE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_TIMING_MODE_SELECT
-
- TIMING_MODE_AUTO EQU 0 ; < Use best rate possible
- TIMING_MODE_LIMITED EQU 1 ; < Set user top limit
- TIMING_MODE_SPECIFIC EQU 2 ; < Set user specified speed
-USER_MEMORY_TIMING_MODE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_POWER_DOWN_MODE
-
- POWER_DOWN_BY_CHANNEL EQU 0
- POWER_DOWN_BY_CHIP_SELECT EQU 1
- POWER_DOWN_AUTO EQU 2
-POWER_DOWN_MODE TEXTEQU <DWORD>
-
- ; Low voltage support
-
- VOLT1_5 EQU 0 ; < 1.5 Volt
- VOLT1_35 EQU 1 ; < 1.35 Volt
- VOLT1_25 EQU 2 ; < 1.25 Volt
- VOLT_UNSUPPORTED EQU 0xFF ; < No common voltage found
-DIMM_VOLTAGE TEXTEQU <DWORD>
-
- ; UMA Mode
-
- UMA_NONE EQU 0 ; < UMA None
- UMA_SPECIFIED EQU 1 ; < UMA Specified
- UMA_AUTO EQU 2 ; < UMA Auto
-UMA_MODE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_UMA_ALIGNMENT
-
- NO_UMA_ALIGNED EQU 00FFFFFFh
- UMA_128MB_ALIGNED EQU 00FFF800h
- UMA_256MB_ALIGNED EQU 00FFF000h
- UMA_512MB_ALIGNED EQU 00FFE000h
-UMA_ALIGNMENT TEXTEQU <DWORD>
- ; ===============================================================================
- ; Global MCT Configuration Status Word (GStatus)
- ; ===============================================================================
-
- GsbMTRRshort EQU 0 ; < Ran out of MTRRs while mapping memory
- GsbAllECCDimms EQU 1 ; < All banks of all Nodes are ECC capable
- GsbDramECCDis EQU 2 ; < Dram ECC requested but not enabled.
- GsbSoftHole EQU 3 ; < A Node Base gap was created
- GsbHWHole EQU 4 ; < A HW dram remap was created
- GsbNodeIntlv EQU 5 ; < Node Memory interleaving was enabled
- GsbSpIntRemapHole EQU 6 ; < Special condition for Node Interleave and HW remapping
- GsbEnDIMMSpareNW EQU 7 ; < Indicates that DIMM Spare can be used without a warm reset
-
- GsbEOL EQU 8 ; < End of list
-GLOBAL_STATUS_FIELD TEXTEQU <DWORD>
-
-; ===============================================================================
- ; Local Error Status (DIE_STRUCT.ErrStatus[31:0])
-; ===============================================================================
-
- EsbNoDimms EQU 0 ; < No DIMMs
- EsbSpdChkSum EQU 1 ; < SPD Checksum fail
- EsbDimmMismatchM EQU 2 ; < dimm module type(buffer) mismatch
- EsbDimmMismatchT EQU 3 ; < dimm CL/T mismatch
- EsbDimmMismatchO EQU 4 ; < dimm organization mismatch (128-bit)
- EsbNoTrcTrfc EQU 5 ; < SPD missing Trc or Trfc info
- EsbNoCycTime EQU 6 ; < SPD missing byte 23 or 25
- EsbBkIntDis EQU 7 ; < Bank interleave requested but not enabled
- EsbDramECCDis EQU 8 ; < Dram ECC requested but not enabled
- EsbSpareDis EQU 9 ; < Online spare requested but not enabled
- EsbMinimumMode EQU 10 ; < Running in Minimum Mode
- EsbNoRcvrEn EQU 11 ; < No DQS Receiver Enable pass window found
- EsbSmallRcvr EQU 12 ; < DQS Rcvr En pass window too small (far right of dynamic range)
- EsbNoDqsPos EQU 13 ; < No DQS-DQ passing positions
- EsbSmallDqs EQU 14 ; < DQS-DQ passing window too small
- EsbDCBKScrubDis EQU 15 ; < DCache scrub requested but not enabled
-
- EsbEMPNotSupported EQU 16 ; < Processor is not capable for EMP.
- EsbEMPConflict EQU 17 ; < EMP requested but cannot be enabled since
- ; < channel interleaving, bank interleaving, or bank swizzle is enabled.
- EsbEMPDis EQU 18 ; < EMP requested but cannot be enabled since
- ; < memory size of each DCT is not a power of two.
-
- EsbEOL EQU 19 ; < End of list
-ERROR_STATUS_FIELD TEXTEQU <DWORD>
-
-; ===============================================================================
- ; Local Configuration Status (DIE_STRUCT.Status[31:0])
-; ===============================================================================
-
- SbRegistered EQU 0 ; < All DIMMs are Registered
- SbEccDimms EQU 1 ; < All banks ECC capable
- SbParDimms EQU 2 ; < All banks Addr/CMD Parity capable
- SbDiagClks EQU 3 ; < Jedec ALL slots clock enable diag mode
- Sb128bitmode EQU 4 ; < DCT in 128-bit mode operation
- Sb64MuxedMode EQU 5 ; < DCT in 64-bit mux'ed mode.
- Sb2TMode EQU 6 ; < 2T CMD timing mode is enabled.
- SbSWNodeHole EQU 7 ; < Remapping of Node Base on this Node to create a gap.
- SbHWHole EQU 8 ; < Memory Hole created on this Node using HW remapping.
- SbOver400Mhz EQU 9 ; < DCT freq greater than or equal to 400MHz flag
- SbDQSPosPass2 EQU 10 ; < Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
- SbDQSRcvLimit EQU 11 ; < Used for DQSRcvEnTrain to know we have reached the upper bound.
- SbExtConfig EQU 12 ; < Indicate the default setting for extended PCI configuration support
- SbLrdimms EQU 13 ; < All DIMMs are LRDIMMs
- SbEOL EQU 14 ; < End of list
-LOCAL_STATUS_FIELD TEXTEQU <DWORD>
-
-
-; < CPU MSR Register definitions ------------------------------------------
- SYS_CFG EQU 0C0010010h
- TOP_MEM EQU 0C001001Ah
- TOP_MEM2 EQU 0C001001Dh
- HWCR EQU 0C0010015h
- NB_CFG EQU 0C001001Fh
-
- FS_BASE EQU 0C0000100h
- IORR0_BASE EQU 0C0010016h
- IORR0_MASK EQU 0C0010017h
- BU_CFG EQU 0C0011023h
- BU_CFG2 EQU 0C001102Ah
- COFVID_STAT EQU 0C0010071h
- TSC EQU 10h
-
-; ===============================================================================
- ; SPD Data for each DIMM
-; ===============================================================================
-SPD_DEF_STRUCT STRUCT
- DimmPresent BOOLEAN ? ; < Indicates that the DIMM is present and Data is valid
- Data UINT8 (256) DUP (?) ; < Buffer for 256 Bytes of SPD data from DIMM
-SPD_DEF_STRUCT ENDS
-
-; ===============================================================================
- ; Channel Definition Structure
- ; This data structure defines entries that are specific to the channel initialization
-; ===============================================================================
-CH_DEF_STRUCT STRUCT
- ChannelID UINT8 ? ; < Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
- TechType TECHNOLOGY_TYPE ? ; < Technology type of this channel
- ChDimmPresent UINT8 ? ; < For each bit n 0..7, 1 = DIMM n is present.
- ; < DIMM# Select Signal
- ; < 0 MA0_CS_L[0, 1]
- ; < 1 MB0_CS_L[0, 1]
- ; < 2 MA1_CS_L[0, 1]
- ; < 3 MB1_CS_L[0, 1]
- ; < 4 MA2_CS_L[0, 1]
- ; < 5 MB2_CS_L[0, 1]
- ; < 6 MA3_CS_L[0, 1]
- ; < 7 MB3_CS_L[0, 1]
-
- DCTPtr POINTER ? ; < Pointer to the DCT data of this channel.
- MCTPtr POINTER ? ; < Pointer to the node data of this channel.
- SpdPtr POINTER ? ; < Pointer to the SPD data for this channel. (Setup by NB Constructor)
- DimmSpdPtr POINTER (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Array of pointers to
- ; < SPD Data for each Dimm. (Setup by Tech Block Constructor)
- ChDimmValid UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved.
- RegDimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved.
- LrDimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
- SODimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is a SO-DIMM where 4..7 are reserved.
- Loads UINT8 ? ; < Number of devices loading bus
- Dimms UINT8 ? ; < Number of DIMMs loading Channel
- Ranks UINT8 ? ; < Number of ranks loading Channel DATA
- SlowMode BOOLEAN ? ; < 1T or 2T CMD mode (slow access mode)
- ; < FALSE = 1T
- ; < TRUE = 2T
- ; < The following pointers will be pointed to dynamically allocated buffers.
- ; < Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
- ; < Example: If DIMM and Byte based training, then
- ; < XX is a value in Hex
- ; < BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
- ; < Row1 - Logical DIMM0 XX XX XX XX XX XX XX XX XX
- ; < Row2 - Logical DIMM1 XX XX XX XX XX XX XX XX XX
- RcvEnDlys POINTER ? ; < DQS Receiver Enable Delays
- WrDqsDlys POINTER ? ; < Write DQS delays (only valid for DDR3)
- RdDqsDlys POINTER ? ; < Read Dqs delays
- WrDatDlys POINTER ? ; < Write Data delays
- RdDqsMinDlys POINTER ? ; < Minimum Window for Read DQS
- RdDqsMaxDlys POINTER ? ; < Maximum Window for Read DQS
- WrDatMinDlys POINTER ? ; < Minimum Window for Write data
- WrDatMaxDlys POINTER ? ; < Maximum Window for Write data
- RowCount UINT8 ? ; < Number of rows of the allocated buffer.
- ColumnCount UINT8 ? ; < Number of columns of the allocated buffer.
-
- FailingBitMask POINTER ? ; < Table of masks to Track Failing bits
- DctOdcCtl UINT32 ? ; < Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
- DctAddrTmg UINT32 ? ; < Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
- PhyRODTCSLow UINT32 ? ; < Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h)
- PhyRODTCSHigh UINT32 ? ; < Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h)
- PhyWODTCSLow UINT32 ? ; < Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h)
- PhyWODTCSHigh UINT32 ? ; < Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183)
- PhyWLODT UINT8 (4) DUP (?) ; < Write Levelization ODT Pattern for Dimm 0-3 (see BKDG FN2:Offset 9Ch, index 0x8[11:8])
- DctEccDqsLike UINT16 ? ; < DCT DQS ECC UINT8 like...
- DctEccDqsScale UINT8 ? ; < DCT DQS ECC UINT8 scale
- PtrPatternBufA UINT16 ? ; < Ptr on stack to aligned DQS testing pattern
- PtrPatternBufB UINT16 ? ; < Ptr on stack to aligned DQS testing pattern
- ByteLane UINT8 ? ; < Current UINT8 Lane (0..7)
- Direction UINT8 ? ; < Current DQS-DQ training write direction (0=read, 1=write)
- Pattern UINT8 ? ; < Current pattern
- DqsDelay UINT8 ? ; < Current DQS delay value
- HostBiosSrvc1 UINT16 ? ; < UINT16 sized general purpose field for use by host BIOS. Scratch space.
- HostBiosSrvc2 UINT32 ? ; < UINT32 sized general purpose field for use by host BIOS. Scratch space.
- DctMaxRdLat UINT16 ? ; < Max Read Latency (ns) for the DCT
- DIMMValidCh UINT8 ? ; < DIMM# in CH
- MaxCh UINT8 ? ; < Max number of CH in system
- Dct UINT8 ? ; < Dct pointer
- WrDatGrossH UINT8 ? ; < Write Data Gross delay high value
- DqsRcvEnGrossL UINT8 ? ; < DQS Receive Enable Gross Delay low
-
- TrwtWB UINT8 ? ; < Non-SPD timing value for TrwtWB
- CurrRcvrDctADelay UINT8 ? ; < for keep current RcvrEnDly
- T1000 UINT16 ? ; < get the T1000 figure (cycle time (ns) * 1K)
- DqsRcvEnPass UINT8 ? ; < for TrainRcvrEn UINT8 lane pass flag
- DqsRcvEnSaved UINT8 ? ; < for TrainRcvrEn UINT8 lane saved flag
- SeedPass1Remainder UINT8 ? ; < for Phy assisted DQS receiver enable training
-
- ClToNbFlag UINT8 ? ; < is used to restore ClLinesToNbDis bit after memory
- NodeSysBase UINT32 ? ; < for channel interleave usage
- RefRawCard UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Array of rawcards detected
- CtrlWrd02 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 2 values per DIMM
- CtrlWrd03 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 3 values per DIMM
- CtrlWrd04 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 4 values per DIMM
- CtrlWrd05 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 5 values per DIMM
- CtrlWrd08 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 8 values per DIMM
-
- CsPresentDCT UINT16 ? ; < For each bit n 0..7, 1 = Chip-select n is present
- DimmMirrorPresent UINT8 ? ; < For each bit n 0..7, 1 = DIMM n is OnDimmMirror capable
- DimmSpdCse UINT8 ? ; < For each bit n 0..7, 1 = DIMM n SPD checksum error
- DimmExclude UINT8 ? ; < For each bit n 0..7, 1 = DIMM n gets excluded
- DimmYr06 UINT8 ? ; < Bitmap indicating which Dimms have a manufacturer's year code <= 2006
- DimmWk2406 UINT8 ? ; < Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
- DimmPlPresent UINT8 ? ; < Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
- DimmQrPresent UINT8 ? ; < QuadRank DIMM present?
- DimmDrPresent UINT8 ? ; < Bitmap indicating that Dual Rank Dimms are present
- DimmSRPresent UINT8 ? ; < Bitmap indicating that Single Rank Dimms are present
- Dimmx4Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved.
- Dimmx8Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved.
- Dimmx16Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved.
- LrdimmPhysicalRanks UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Number of Physical Ranks for LRDIMMs
- LrDimmLogicalRanks UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Number of LRDIMM Logical ranks in this configuration
- LrDimmRankMult UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Rank Multipication factor per dimm.
-
- MemClkDisMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
- ; < base on this array to disable unused MemClk to save power.
- ; <
- ; < The array must have 8 entries. Each entry, which associates with
- ; < one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
- ; < Example:
- ; < BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package
- ; < is like below:
- ; < Bit AM3/S1g3 pin name
- ; < 0 M[B,A]_CLK_H/L[0]
- ; < 1 M[B,A]_CLK_H/L[1]
- ; < 2 M[B,A]_CLK_H/L[2]
- ; < 3 M[B,A]_CLK_H/L[3]
- ; < 4 M[B,A]_CLK_H/L[4]
- ; < 5 M[B,A]_CLK_H/L[5]
- ; < 6 M[B,A]_CLK_H/L[6]
- ; < 7 M[B,A]_CLK_H/L[7]
- ; < And platform has the following routing:
- ; < CS0 M[B,A]_CLK_H/L[4]
- ; < CS1 M[B,A]_CLK_H/L[2]
- ; < CS2 M[B,A]_CLK_H/L[3]
- ; < CS3 M[B,A]_CLK_H/L[5]
- ; < Then MemClkDisMap should be pointed to the following array:
- ; < CLK_2 CLK_3 CLK_4 CLK_5
- ; < 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00
- ; < Each entry of the array is the bitmask of 8 chip selects.
-
- CKETriMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of CKE pins to the DIMMs' ranks.
- ; < The array must have 2 entries. Each entry, which associates with
- ; < one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
- ; < AGESA will base on this array to disable unused CKE pins to save power.
-
- ODTTriMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of ODT pins to the DIMMs' ranks.
- ; < The array must have 4 entries. Each entry, which associates with
- ; < one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
- ; < AGESA will base on this array to disable unused ODT pins to save power.
-
- ChipSelTriMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of chip select pins to the DIMMs' ranks.
- ; < The array must have 8 entries. Each entry is a bitmap of 8 CS.
- ; < AGESA will base on this array to disable unused Chip select pins to save power.
-
- ExtendTmp BOOLEAN ? ; < If extended temperature is supported on all dimms on a channel.
-
- Reserved UINT8 (100) DUP (?) ; < Reserved
-CH_DEF_STRUCT ENDS
-
-; ===============================================================================
- ; DCT Channel Timing Parameters
- ; This data structure sets timings that are specific to the channel
-; ===============================================================================
-CH_TIMING_STRUCT STRUCT
- DctDimmValid UINT16 ? ; < For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved.
- DimmMirrorPresent UINT16 ? ; < For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved.
- DimmSpdCse UINT16 ? ; < For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved.
- DimmExclude UINT16 ? ; < For each bit n 0..3, 1 = DIMM n gets excluded because of no common voltage is found
- CsPresent UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is present
- CsEnabled UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is enabled
- CsTestFail UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is present but disabled
- CsTrainFail UINT16 ? ; < Bitmap showing which chipselects failed training
- DIMM1KPage UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved.
- DimmQrPresent UINT16 ? ; < QuadRank DIMM present?
- DimmDrPresent UINT16 ? ; < Bitmap indicating that Dual Rank Dimms are present
- DimmSRPresent UINT8 ? ; < Bitmap indicating that Single Rank Dimms are present
- Dimmx4Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved.
- Dimmx8Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved.
- Dimmx16Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved.
-
- DIMMTrcd UINT16 ? ; < Minimax Trcd*40 (ns) of DIMMs
- DIMMTrp UINT16 ? ; < Minimax Trp*40 (ns) of DIMMs
- DIMMTrtp UINT16 ? ; < Minimax Trtp*40 (ns) of DIMMs
- DIMMTras UINT16 ? ; < Minimax Tras*40 (ns) of DIMMs
- DIMMTrc UINT16 ? ; < Minimax Trc*40 (ns) of DIMMs
- DIMMTwr UINT16 ? ; < Minimax Twr*40 (ns) of DIMMs
- DIMMTrrd UINT16 ? ; < Minimax Trrd*40 (ns) of DIMMs
- DIMMTwtr UINT16 ? ; < Minimax Twtr*40 (ns) of DIMMs
- DIMMTfaw UINT16 ? ; < Minimax Tfaw*40 (ns) of DIMMs
- TargetSpeed UINT16 ? ; < Target DRAM bus speed in MHz
- Speed UINT16 ? ; < DRAM bus speed in MHz
- ; < 400 (MHz)
- ; < 533 (MHz)
- ; < 667 (MHz)
- ; < 800 (MHz)
- ; < and so on...
- CasL UINT8 ? ; < CAS latency DCT setting (busclocks)
- Trcd UINT8 ? ; < DCT Trcd (busclocks)
- Trp UINT8 ? ; < DCT Trp (busclocks)
- Trtp UINT8 ? ; < DCT Trtp (busclocks)
- Tras UINT8 ? ; < DCT Tras (busclocks)
- Trc UINT8 ? ; < DCT Trc (busclocks)
- Twr UINT8 ? ; < DCT Twr (busclocks)
- Trrd UINT8 ? ; < DCT Trrd (busclocks)
- Twtr UINT8 ? ; < DCT Twtr (busclocks)
- Tfaw UINT8 ? ; < DCT Tfaw (busclocks)
- Trfc0 UINT8 ? ; < DCT Logical DIMM0 Trfc
- ; < 0 = 75ns (for 256Mb devs)
- ; < 1 = 105ns (for 512Mb devs)
- ; < 2 = 127.5ns (for 1Gb devs)
- ; < 3 = 195ns (for 2Gb devs)
- ; < 4 = 327.5ns (for 4Gb devs)
- Trfc1 UINT8 ? ; < DCT Logical DIMM1 Trfc (see Trfc0 for format)
- Trfc2 UINT8 ? ; < DCT Logical DIMM2 Trfc (see Trfc0 for format)
- Trfc3 UINT8 ? ; < DCT Logical DIMM3 Trfc (see Trfc0 for format)
- DctMemSize UINT32 ? ; < Base[47:16], total DRAM size controlled by this DCT.
- SlowMode BOOLEAN ? ; < 1T or 2T CMD mode (slow access mode)
- ; < FALSE = 1T
- ; < TRUE = 2T
- TrwtTO UINT8 ? ; < DCT TrwtTO (busclocks)
- Twrrd UINT8 ? ; < DCT Twrrd (busclocks)
- Twrwr UINT8 ? ; < DCT Twrwr (busclocks)
- Trdrd UINT8 ? ; < DCT Trdrd (busclocks)
- TrwtWB UINT8 ? ; < DCT TrwtWB (busclocks)
- TrdrdSD UINT8 ? ; < DCT TrdrdSD (busclocks)
- TwrwrSD UINT8 ? ; < DCT TwrwrSD (busclocks)
- TwrrdSD UINT8 ? ; < DCT TwrrdSD (busclocks)
- MaxRdLat UINT16 ? ; < Max Read Latency
- WrDatGrossH UINT8 ? ; < Temporary variables must be removed
- DqsRcvEnGrossL UINT8 ? ; < Temporary variables must be removed
-CH_TIMING_STRUCT ENDS
-
-; ===============================================================================
- ; Data for each DCT
- ; This data structure defines data used to configure each DRAM controller
-; ===============================================================================
-DCT_STRUCT STRUCT
- Dct UINT8 ? ; < Current Dct
- Timings CH_TIMING_STRUCT {} ; < Channel Timing structure
- ChData POINTER ? ; < Pointed to a dynamically allocated array of Channel structures
- ChannelCount UINT8 ? ; < Number of channel per this DCT
-DCT_STRUCT ENDS
-
-
-; ===============================================================================
- ; Data Structure defining each Die
- ; This data structure contains information that is used to configure each Die
-; ===============================================================================
-DIE_STRUCT STRUCT
-
- ; Advanced:
-
- NodeId UINT8 ? ; < Node ID of current controller
- SocketId UINT8 ? ; < Socket ID of this Die
- DieId UINT8 ? ; < ID of this die relative to the socket
- PciAddr PCI_ADDR {} ; < Pci bus and device number of this controller.
- ErrCode AGESA_STATUS ? ; < Current error condition of Node
- ; < 0x0 = AGESA_SUCCESS
- ; < 0x1 = AGESA_UNSUPPORTED
- ; < 0x2 = AGESA_BOUNDS_CHK
- ; < 0x3 = AGESA_ALERT
- ; < 0x4 = AGESA_WARNING
- ; < 0x5 = AGESA_ERROR
- ; < 0x6 = AGESA_CRITICAL
- ; < 0x7 = AGESA_FATAL
- ; <
- ErrStatus BOOLEAN (EsbEOL) DUP (?) ; < Error Status bit Field
- Status BOOLEAN (SbEOL) DUP (?) ; < Status bit Field
- NodeMemSize UINT32 ? ; < Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
- NodeSysBase UINT32 ? ; < Base[47:16] (system address) DRAM base address of this Node.
- NodeHoleBase UINT32 ? ; < If not zero, Base[47:16] (system address) of dram hole for HW remapping. Dram hole exists on this Node
- NodeSysLimit UINT32 ? ; < Base[47:16] (system address) DRAM limit address of this Node.
- DimmPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is present.
- ; < DIMM# Select Signal
- ; < 0 MA0_CS_L[0, 1]
- ; < 1 MB0_CS_L[0, 1]
- ; < 2 MA1_CS_L[0, 1]
- ; < 3 MB1_CS_L[0, 1]
- ; < 4 MA2_CS_L[0, 1]
- ; < 5 MB2_CS_L[0, 1]
- ; < 6 MA3_CS_L[0, 1]
- ; < 7 MB3_CS_L[0, 1]
- DimmValid UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
- RegDimmPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is registered DIMM
- LrDimmPresent UINT32 ? ; < For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
- DimmEccPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is ECC capable.
- DimmParPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
- DimmTrainFail UINT16 ? ; < Bitmap showing which dimms failed training
- ChannelTrainFail UINT16 ? ; < Bitmap showing the channel information about failed Chip Selects
- ; < 0 in any bit field indicates Channel 0
- ; < 1 in any bit field indicates Channel 1
- Dct UINT8 ? ; < Need to be removed
- ; < DCT pointer
- GangedMode BOOLEAN ? ; < Ganged mode
- ; < 0 = disabled
- ; < 1 = enabled
- LogicalCpuid CPU_LOGICAL_ID {} ; < The logical CPUID of the node
- HostBiosSrvc1 UINT16 ? ; < UINT16 sized general purpose field for use by host BIOS. Scratch space.
- HostBiosSrvc2 UINT32 ? ; < UINT32 sized general purpose field for use by host BIOS. Scratch space.
- MLoad UINT8 ? ; < Need to be removed
- ; < Number of devices loading MAA bus
- MaxAsyncLat UINT8 ? ; < Legacy wrapper
- ChbD3Rcvrdly UINT8 ? ; < Legacy wrapper
- ChaMaxRdLat UINT16 ? ; < Max Read Latency (ns) for DCT 0
- ChbD3BcRcvrdly UINT8 ? ; < CHB DIMM 3 Check UINT8 Receiver Enable Delay
-
- DctData POINTER ? ; < Pointed to a dynamically allocated array of DCT_STRUCTs
- DctCount UINT8 ? ; < Number of DCTs per this Die
- Reserved UINT8 (16) DUP (?) ; < Reserved
-DIE_STRUCT ENDS
-
-; *********************************************************************
-; * S3 Support structure
-; *********************************************************************
- ; AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure
-AMD_S3_PARAMS STRUCT
- Signature UINT32 ? ; < "ASTR" for AMD Suspend-To-RAM
- Version UINT16 ? ; < S3 Params version number
- Flags UINT32 ? ; < Indicates operation
- NvStorage POINTER ? ; < Pointer to memory critical save state data
- NvStorageSize UINT32 ? ; < Size in bytes of the NvStorage region
- VolatileStorage POINTER ? ; < Pointer to remaining AMD save state data
- VolatileStorageSize UINT32 ? ; < Size in bytes of the VolatileStorage region
-AMD_S3_PARAMS ENDS
-
-; ===============================================================================
- ; MEM_PARAMETER_STRUCT
- ; This data structure is used to pass wrapper parameters to the memory configuration code
-; ===============================================================================
-MEM_PARAMETER_STRUCT STRUCT
-
- ; Basic (Return parameters)
- ; (This section contains the outbound parameters from the memory init code)
-
- GStatus BOOLEAN (GsbEOL) DUP (?) ; < Global Status bitfield
- HoleBase UINT32 ? ; < If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping.
- Sub4GCacheTop UINT32 ? ; < If not zero, the 32-bit top of cacheable memory.
- SysLimit UINT32 ? ; < Limit[47:16] (system address)
- DDR3Voltage DIMM_VOLTAGE ? ; < Find support voltage and send back to platform BIOS.
- ; < 0 = 1.5v
- ; < 1 = 1.35v
- ; < 2 = 1.2v
- ; < 0xFF = Mixed 1.5V and 1.2V in the system. 1.5V dimms get excluded
- ; < from the system.
- ; <
-
- MemData POINTER ? ; < Pointer to MEM_DATA_STRUCT
- ; Advanced (Optional parameters)
- ; Optional (all defaults values will be initialized by the
- ; 'AmdMemInitDataStructDef' based on AMD defaults. It is up
- ; to the IBV/OEM to change the defaults after initialization
- ; but prior to the main entry to the memory code):
-
- ; Memory Map/Mgt.
-
- BottomIo UINT16 ? ; < Bottom of 32-bit IO space (8-bits)
- ; < NV_BOTTOM_IO[7:0]=Addr[31:24]
- MemHoleRemapping BOOLEAN ? ; < Memory Hole Remapping (1-bit)
- ; < FALSE = disable
- ; < TRUE = enable
-
-
- ; Dram Timing
-
- UserTimingMode USER_MEMORY_TIMING_MODE ? ; < User Memclock Mode
-
- MemClockValue MEMORY_BUS_SPEED ? ; < Memory Clock Value
-
- ; Dram Configuration
-
- EnableBankIntlv BOOLEAN ? ; < Dram Bank (chip-select) Interleaving (1-bit)
- ; < FALSE =disable (AMD default)
- ; < TRUE =enable
- EnableNodeIntlv BOOLEAN ? ; < Node Memory Interleaving (1-bit)
- ; < FALSE = disable (AMD default)
- ; < TRUE = enable
- EnableChannelIntlv BOOLEAN ? ; < Channel Interleaving (1-bit)
- ; < FALSE = disable (AMD default)
- ; < TRUE = enable
- ; ECC
-
- EnableEccFeature BOOLEAN ? ; < enable ECC error to go into MCE
- ; < FALSE = disable (AMD default)
- ; < TRUE = enable
- ; Dram Power
-
- EnablePowerDown BOOLEAN ? ; < CKE based power down mode (1-bit)
- ; < FALSE =disable (AMD default)
- ; < TRUE =enable
- ; Online Spare
-
- EnableOnLineSpareCtl BOOLEAN ? ; < Chip Select Spare Control bit 0:
- ; < FALSE = disable Spare (AMD default)
- ; < TRUE = enable Spare
- TableBasedAlterations POINTER ? ; < Point to an array of data bytes describing desired modifications to register settings.
-
- PlatformMemoryConfiguration POINTER ?
- ; < Points to a table that contains platform specific settings
- ; < (i.e. MemClk routing, the number of DIMM slots per channel,...)
- ; < AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that
- ; < contains default conservative settings. Platform BIOS can either tweak
- ; < DefaultPlatformMemoryConfiguration or reassign this pointer to its own table.
- ; <
- EnableParity BOOLEAN ? ; < Parity control
- ; < TRUE = enable
- ; < FALSE = disable (AMD default)
- EnableBankSwizzle BOOLEAN ? ; < BankSwizzle control
- ; < FALSE = disable
- ; < TRUE = enable (AMD default)
- EnableMemClr BOOLEAN ? ; < Memory Clear functionality control
- ; < FALSE = disable
- ; < TRUE = enable (AMD default)
- ; Uma Configuration
-
- UmaMode UMA_MODE ? ; < Uma Mode
- ; < 0 = None
- ; < 1 = Specified
- ; < 2 = Auto
- UmaSize UINT32 ? ; < The size of shared graphics dram (16-bits)
- ; < NV_UMA_Size[31:0]=Addr[47:16]
- ; <
- UmaBase UINT32 ? ; < The allocated Uma base address (32-bits)
- ; < NV_UMA_Base[31:0]=Addr[47:16]
- ; <
-
- ; Memory Restore Feature
-
- MemRestoreCtl BOOLEAN ? ; < Memory context restore control
- ; < FALSE = perform memory init as normal (AMD default)
- ; < TRUE = restore memory context and skip training. This requires
- ; < MemContext is valid before AmdInitPost
- SaveMemContextCtl BOOLEAN ? ; < Control switch to save memory context at the end of MemAuto
- ; < TRUE = AGESA will setup MemContext block before exit AmdInitPost
- ; < FALSE = AGESA will not setup MemContext block. Platform is
- ; < expected to call S3Save later in POST if it wants to
- ; < use memory context restore feature.
- MemContext AMD_S3_PARAMS {} ; < Memory context block describes the data that platform needs to
- ; < save and restore for memory context restore feature to work.
- ; < It uses the subset of S3Save block to save/restore. Hence platform
- ; < may save only S3 block and uses it for both S3 resume and
- ; < memory context restore.
- ; < - If MemRestoreCtl is TRUE, platform needs to pass in MemContext
- ; < before AmdInitPost.
- ; < - If SaveMemContextCtl is TRUE, platform needs to save MemContext
- ; < right after AmdInitPost.
-MEM_PARAMETER_STRUCT ENDS
-
-
-; ===============================================================================
- ; Function definition
- ; This data structure passes function pointers to the memory configuration code.
- ; The wrapper can use this structure with customized versions
-; ================================================================================
-MEM_FUNCTION_STRUCT STRUCT
-
- ; PUBLIC required Internal functions
-
- amdMemGetPsCfgU POINTER ? ; < Proc for Unbuffered DIMMs, platform specific
- amdMemGetPsCfgR POINTER ? ; < Proc for Registered DIMMs, platform specific
-
- ; PUBLIC optional functions
-
- amdMemEccInit POINTER ? ; < NB proc for ECC feature
- amdMemChipSelectInterleaveInit POINTER ? ; < NB proc for CS interleave feature
- amdMemDctInterleavingInit POINTER ? ; < NB proc for Channel interleave feature
- amdMemMctInterleavingInit POINTER ? ; < NB proc for Node interleave feature
- amdMemParallelTraining POINTER ? ; < NB proc for parallel training feature
- amdMemEarlySampleSupport POINTER ? ; < NB code for early sample support feature
- amdMemMultiPartInitSupport POINTER ? ; < NB code for 'multi-part'
- amdMemOnlineSpareSupport POINTER ? ; < NB code for On-Line Spare feature
- amdMemUDimmInit POINTER ? ; < NB code for UDIMMs
- amdMemRDimmInit POINTER ? ; < NB code for RDIMMs
- amdMemLrDimmInit POINTER ? ; < NB code for LRDIMMs
-
- Reserved UINT32 (100) DUP (?) ; < Reserved for later function definition
-MEM_FUNCTION_STRUCT ENDS
-
-; ===============================================================================
- ; Socket Structure
-
-; ===============================================================================
-MEM_SOCKET_STRUCT STRUCT
- ChannelPtr POINTER (MAX_CHANNELS_PER_SOCKET) DUP (?) ; < Pointers to each channels training data
-
- TimingsPtr POINTER (MAX_CHANNELS_PER_SOCKET) DUP (?) ; < Pointers to each channels timing data
-
-MEM_SOCKET_STRUCT ENDS
-
-; ===============================================================================
- ; MEM_DATA_STRUCT
-; ===============================================================================
-MEM_DATA_STRUCT STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < AGESA Standard Header
-
- ParameterListPtr POINTER ? ; < List of input Parameters
-
- FunctionList MEM_FUNCTION_STRUCT {} ; < List of function Pointers
-
- GetPlatformCfg POINTER (MAX_PLATFORM_TYPES) DUP (?) ; < look-up platform info
-
- ErrorHandling POINTER ? ; < Error Handling
-
- ; SocketList is a shortcut for IBVs to retrieve training
- ; and timing data for each channel indexed by socket/channel,
- ; eliminating their need to parse die/dct/channel etc.
- ; It contains pointers to the populated data structures for
- ; each channel and skips the channel structures that are
- ; unpopulated. In the case of channels sharing the same DCT,
- ; the pTimings pointers will point to the same DCT Timing data.
-
- SocketList MEM_SOCKET_STRUCT (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Socket list for memory code
-
- DiesPerSystem POINTER ? ; < Pointed to an array of DIE_STRUCTs
- DieCount UINT8 ? ; < Number of MCTs in the system.
-
- SpdDataStructure POINTER ? ; < Pointer to SPD Data structure
-
- PlatFormConfig POINTER ? ; < Pointer to Platform profile/build option config structure
-
- IsFlowControlSupported BOOLEAN ? ; < Indicates if flow control is supported
-
- TscRate UINT32 ? ; < The rate at which the TSC increments in megahertz.
-
-MEM_DATA_STRUCT ENDS
-
-; ===============================================================================
-; UMA_INFO_STRUCT
-; ===============================================================================
-UMA_INFO STRUCT
- UmaBase UINT64 ? ; < UmaBase[63:0] = Addr[63:0]
- UmaSize UINT32 ? ; < UmaSize[31:0] = Addr[31:0]
- UmaAttributes UINT32 ? ; < Indicate the attribute of Uma
- UmaMode UINT8 ? ; < Indicate the mode of Uma
- MemClock UINT16 ? ; < Indicate memory running speed in MHz
- Reserved UINT8 (3) DUP (?) ; < Reserved for future usage
-UMA_INFO ENDS
-
- ; AGESA MEMORY ERRORS
-
- ; AGESA_ALERT Memory Errors
-MEM_ALERT_USER_TMG_MODE_OVERRULED EQU 04010000h ; < TIMING_MODE_SPECIFIC is requested but
- ; < cannot be applied to current configurations.
-MEM_ALERT_ORG_MISMATCH_DIMM EQU 04010100h ; < DIMM organization miss-match
-MEM_ALERT_BK_INT_DIS EQU 04010200h ; < Bank interleaving disable for internal issue
-
- ; AGESA_ERROR Memory Errors
-MEM_ERROR_NO_DQS_POS_RD_WINDOW EQU 04010300h ; < No DQS Position window for RD DQS
-MEM_ERROR_SMALL_DQS_POS_RD_WINDOW EQU 04020300h ; < Small DQS Position window for RD DQS
-MEM_ERROR_NO_DQS_POS_WR_WINDOW EQU 04030300h ; < No DQS Position window for WR DQS
-MEM_ERROR_SMALL_DQS_POS_WR_WINDOW EQU 04040300h ; < Small DQS Position window for WR DQS
-MEM_ERROR_ECC_DIS EQU 04010400h ; < ECC has been disabled as a result of an internal issue
-MEM_ERROR_DIMM_SPARING_NOT_ENABLED EQU 04010500h ; < DIMM sparing has not been enabled for an internal issues
-MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE EQU 04050300h ; < Receive Enable value is too large
-MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW EQU 04060300h ; < There is no DQS receiver enable window
-MEM_ERROR_DRAM_ENABLED_TIME_OUT EQU 04010600h ; < Time out when polling DramEnabled bit
-MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT EQU 04010700h ; < Time out when polling DctAccessDone bit
-MEM_ERROR_SEND_CTRL_WORD_TIME_OUT EQU 04010800h ; < Time out when polling SendCtrlWord bit
-MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT EQU 04010900h ; < Time out when polling PrefDramTrainMode bit
-MEM_ERROR_ENTER_SELF_REF_TIME_OUT EQU 04010A00h ; < Time out when polling EnterSelfRef bit
-MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT EQU 04010B00h ; < Time out when polling FreqChgInProg bit
-MEM_ERROR_EXIT_SELF_REF_TIME_OUT EQU 04020A00h ; < Time out when polling ExitSelfRef bit
-MEM_ERROR_SEND_MRS_CMD_TIME_OUT EQU 04010C00h ; < Time out when polling SendMrsCmd bit
-MEM_ERROR_SEND_ZQ_CMD_TIME_OUT EQU 04010D00h ; < Time out when polling SendZQCmd bit
-MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT EQU 04010E00h ; < Time out when polling DctExtraAccessDone bit
-MEM_ERROR_MEM_CLR_BUSY_TIME_OUT EQU 04010F00h ; < Time out when polling MemClrBusy bit
-MEM_ERROR_MEM_CLEARED_TIME_OUT EQU 04020F00h ; < Time out when polling MemCleared bit
-MEM_ERROR_FLUSH_WR_TIME_OUT EQU 04011000h ; < Time out when polling FlushWr bit
-MEM_ERROR_MAX_LAT_NO_WINDOW EQU 04070300h ; < Fail to find pass during Max Rd Latency training
-MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL EQU 04080300h ; < Fail to launch training code on an AP
-MEM_ERROR_PARALLEL_TRAINING_TIME_OUT EQU 04090300h ; < Fail to finish parallel training
-MEM_ERROR_NO_ADDRESS_MAPPING EQU 04011100h ; < No address mapping found for a dimm
-MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT EQU 040A0300h ; < There is no DQS receiver enable window and the value is equal to the largest value
-MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE EQU 040B0300h ; < Receive Enable value is too large and is 1 less than limit
-MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR EQU 04011200h ; < SPD Checksum error for NV_SPDCHK_RESTRT
-MEM_ERROR_NO_CHIPSELECT EQU 04011300h ; < No chipselects found
-MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM EQU 04011500h ; < Unbuffered dimm is not supported at 333MHz
-MEM_ERROR_WL_PRE_OUT_OF_RANGE EQU 040C0300h ; < Returned PRE value during write levelization was out of range
-
- ; AGESA_WARNING Memory Errors
- MEM_WARNING_UNSUPPORTED_QRDIMM EQU 04011600h ; < QR DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_UDIMM EQU 04021600h ; < U DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_SODIMM EQU 04031600h ; < SO-DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_X4DIMM EQU 04041600h ; < x4 DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_RDIMM EQU 04051600h ; < R DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_LRDIMM EQU 04061600h ; < LR DIMMs detected but not supported
-
- MEM_WARNING_EMP_NOT_SUPPORTED EQU 04011700h ; < Processor is not capable for EMP
- MEM_WARNING_EMP_CONFLICT EQU 04021700h ; < EMP cannot be enabled if channel interleaving,
- ; < bank interleaving, or bank swizzle is enabled.
- MEM_WARNING_EMP_NOT_ENABLED EQU 04031700h ; < Memory size is not power of two.
- MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED EQU 04011800h ; < Performance has been enabled, but battery life is preferred.
- MEM_WARNING_NO_SPDTRC_FOUND EQU 04011900h ; < No Trc timing value found in SPD of a dimm.
- MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED EQU 04012000h ; < Node Interleaveing Requested, but could not be enabled
- MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED EQU 04012100h ; < Channel Interleaveing Requested, but could not be enabled
- MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED EQU 04012200h ; < Bank Interleaveing Requested, but could not be enabled
- MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED EQU 04012300h ; < Voltage 1.35 determined, but could not be supported
-
- ; AGESA_FATAL Memory Errors
- MEM_ERROR_MINIMUM_MODE EQU 04011A00h ; < Running in minimum mode
- MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM EQU 04011B00h ; < DIMM modules are miss-matched
- MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM EQU 04011C00h ; < No DIMMs have been found on system
- MEM_ERROR_MISMATCH_DIMM_CLOCKS EQU 04011D00h ; < DIMM clocks miss-matched
- MEM_ERROR_NO_CYC_TIME EQU 04011E00h ; < No cycle time found
- MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS EQU 04011F00h ; < Heap allocation error with dynamic storing of trained timings
- MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs EQU 04021F00h ; < Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
- MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV EQU 04031F00h ; < Heap allocation error with REMOTE_TRAINING_ENV
- MEM_ERROR_HEAP_ALLOCATE_FOR_SPD EQU 04041F00h ; < Heap allocation error for SPD data
- MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA EQU 04051F00h ; < Heap allocation error for RECEIVED_DATA during parallel training
- MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS EQU 04061F00h ; < Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
- MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA EQU 04071F00h ; < Heap allocation error for Training Data
- MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK EQU 04081F00h ; < Heap allocation error for DIMM Identify "MEM_NB_BLOCK
- MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM EQU 04022300h ; < No Constructor for DIMM Identify
-
-
- ; AGESA_CRITICAL Memory Errors
- MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 EQU 04091F00h ; < Heap allocation error for DMI table for DDR3
- MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 EQU 040A1F00h ; < Heap allocation error for DMI table for DDR2
- MEM_ERROR_UNSUPPORTED_DIMM_CONFIG EQU 04011400h ; < Dimm population is not supported
-
-
-; ----------------------------------------------------------------------------
-; *
-; * END OF MEMORY-SPECIFIC DATA STRUCTURES
-; *
-; *----------------------------------------------------------------------------
-;
-
-
-; ----------------------------------------------------------------------------
-; *
-; * CPU RELATED DEFINITIONS
-; *
-; *----------------------------------------------------------------------------
-;
-
-; CPU Event definitions.
-
-; Defines used to filter CPU events based on functional blocks
-CPU_EVENT_PM_EVENT_MASK EQU 0FF00FF00h
-CPU_EVENT_PM_EVENT_CLASS EQU 008000400h
-
-;================================================================
-; CPU General events
-; Heap allocation (AppFunction = 01h)
-CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT EQU 008000100h
-CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED EQU 008010100h
-CPU_ERROR_HEAP_IS_FULL EQU 008020100h
-CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED EQU 008030100h
-CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT EQU 008040100h
-; BrandId (AppFunction = 02h)
-CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE EQU 008000200h
-; Micro code patch (AppFunction = 03h)
-CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED EQU 008000300h
-; Power management (AppFunction = 04h)
-CPU_EVENT_PM_PSTATE_OVERCURRENT EQU 008000400h
-CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT EQU 008010400h
-CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE EQU 008020400h
-CPU_ERROR_PM_NB_PSTATE_MISMATCH EQU 008030400h
-; BIST (AppFunction = 05h)
-CPU_EVENT_BIST_ERROR EQU 008000500h
-;=================================================================
-; CPU Feature events
-; Execution cache (AppFunction = 21h)
-; AGESA_CACHE_SIZE_REDUCED 2101
-; AGESA_CACHE_REGIONS_ACROSS_1MB 2102
-; AGESA_CACHE_REGIONS_ACROSS_4GB 2103
-; AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 2104
-; AGESA_CACHE_START_ADDRESS_LESS_D0000 2105
-; AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 2106
-; AGESA_DEALLOCATE_CACHE_REGIONS 2107
-CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR EQU 008002100h
-; Core Leveling (AppFunction = 22h)
-CPU_WARNING_ADJUSTED_LEVELING_MODE EQU 008002200h
-; HT Assist (AppFunction = 23h)
-CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG EQU 008002300h
-
-; CPU Build Configuration structures and definitions
-
-; Build Configuration values for BLDGCFG_AP_MTRR_SETTINGS
-AP_MTRR_SETTINGS STRUCT
- MsrAddr UINT32 ? ; < Fixed-Sized MTRR address
- MsrData UINT64 ? ; < MTRR Settings
-AP_MTRR_SETTINGS ENDS
-
-AMD_AP_MTRR_FIX64k_00000 EQU 000000250h
-AMD_AP_MTRR_FIX16k_80000 EQU 000000258h
-AMD_AP_MTRR_FIX16k_A0000 EQU 000000259h
-AMD_AP_MTRR_FIX4k_C0000 EQU 000000268h
-AMD_AP_MTRR_FIX4k_C8000 EQU 000000269h
-AMD_AP_MTRR_FIX4k_D0000 EQU 00000026Ah
-AMD_AP_MTRR_FIX4k_D8000 EQU 00000026Bh
-AMD_AP_MTRR_FIX4k_E0000 EQU 00000026Ch
-AMD_AP_MTRR_FIX4k_E8000 EQU 00000026Dh
-AMD_AP_MTRR_FIX4k_F0000 EQU 00000026Eh
-AMD_AP_MTRR_FIX4k_F8000 EQU 00000026Fh
-CPU_LIST_TERMINAL EQU 0FFFFFFFFh
-
-; ***********************************************************************
-; *
-; * AGESA interface Call-Out function parameter structures
-; *
-; **********************************************************************
-
- ; Parameters structure for interface call-out AgesaAllocateBuffer
-AGESA_BUFFER_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- BufferLength UINT32 ? ; < Size of buffer to allocate
- BufferHandle UINT32 ? ; < Identifier or name for the buffer
- BufferPointer POINTER ? ; < location of the created buffer
-AGESA_BUFFER_PARAMS ENDS
-
- ; Parameters structure for interface call-out AgesaRunCodeOnAp
-AP_EXE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- FunctionNumber UINT32 ? ; < Index of the procedure to execute
- RelatedDataBlock POINTER ? ; < Location of data structure the procedure will use
- RelatedBlockLength UINT32 ? ; < Size of the related data block
-AP_EXE_PARAMS ENDS
-
- ; Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery
-AGESA_READ_SPD_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < standard header
- SocketId UINT8 ? ; < Address of SPD - socket ID
- MemChannelId UINT8 ? ; < Address of SPD - memory channel ID
- DimmId UINT8 ? ; < Address of SPD - DIMM ID
- Buffer POINTER ? ; < Location where to place the SPD content
- MemData POINTER ? ; < Location of the MemData structure, for reference
-AGESA_READ_SPD_PARAMS ENDS
-
- ; Buffer Handles
- AMD_DMI_INFO_BUFFER_HANDLE EQU 000D000h ; < Assign 0x000D000 buffer handle to DMI function
- AMD_PSTATE_DATA_BUFFER_HANDLE EQU 000D001h ; < Assign 0x000D001 buffer handle to Pstate data
- AMD_PSTATE_ACPI_BUFFER_HANDLE EQU 000D002h ; < Assign 0x000D002 buffer handle to Pstate table
- AMD_BRAND_ID_BUFFER_HANDLE EQU 000D003h ; < Assign 0x000D003 buffer handle to Brand ID
- AMD_ACPI_SLIT_BUFFER_HANDLE EQU 000D004h ; < Assign 0x000D004 buffer handle to SLIT function
- AMD_SRAT_INFO_BUFFER_HANDLE EQU 000D005h ; < Assign 0x000D005 buffer handle to SRAT function
- AMD_WHEA_BUFFER_HANDLE EQU 000D006h ; < Assign 0x000D006 buffer handle to WHEA function
- AMD_S3_INFO_BUFFER_HANDLE EQU 000D007h ; < Assign 0x000D007 buffer handle to S3 function
- AMD_S3_NB_INFO_BUFFER_HANDLE EQU 000D008h ; < Assign 0x000D008 buffer handle to S3 NB device info
- AMD_ACPI_ALIB_BUFFER_HANDLE EQU 000D009h ; < Assign 0x000D009 buffer handle to ALIB SSDT table
-AMD_BUFFER_HANDLE TEXTEQU <DWORD>
-; ***********************************************************************
-; *
-; * AGESA interface Call-Out function prototypes
-; *
-; **********************************************************************
-
-; ***********************************************************************
-; *
-; * AGESA interface structure definition and function prototypes
-; *
-; **********************************************************************
-
-; *********************************************************************
-; * Platform Configuration: The parameters in boot branch function
-; *********************************************************************
-
-; The possible platform control flow settings.
- Nfcm EQU 0 ; < Normal Flow Control Mode.
- UmaDr EQU 1 ; < UMA using Display Refresh flow control.
- UmaIfcm EQU 2 ; < UMA using Isochronous Flow Control.
- Ifcm EQU 3 ; < Isochronous Flow Control Mode (other than for UMA).
- Iommu EQU 4 ; < An IOMMU is in use in the system.
- MaxControlFlow EQU 5 ; < Not a control flow mode, use for limit checking.
-PLATFORM_CONTROL_FLOW TEXTEQU <DWORD>
-
-; Platform Deemphasis Levels.
- DeemphasisLevelNone EQU 0 ; < No Deemphasis.
- DeemphasisLevelMinus3 EQU 1 ; < Minus 3 db deemphasis.
- DeemphasisLevelMinus6 EQU 2 ; < Minus 6 db deemphasis.
- DeemphasisLevelMinus8 EQU 3 ; < Minus 8 db deemphasis.
- DeemphasisLevelMinus11 EQU 4 ; < Minus 11 db deemphasis.
- DeemphasisLevelMinus11pre8 EQU 5 ; < Minus 11, Minus 8 precursor db deemphasis.
- DcvLevelNone EQU 16 ; < No DCV Deemphasis.
- DcvLevelMinus2 EQU 17 ; < Minus 2 db DCV deemphasis.
- DcvLevelMinus3 EQU 18 ; < Minus 3 db DCV deemphasis.
- DcvLevelMinus5 EQU 19 ; < Minus 5 db DCV deemphasis.
- DcvLevelMinus6 EQU 20 ; < Minus 6 db DCV deemphasis.
- DcvLevelMinus7 EQU 21 ; < Minus 7 db DCV deemphasis.
- DcvLevelMinus8 EQU 22 ; < Minus 8 db DCV deemphasis.
- DcvLevelMinus9 EQU 23 ; < Minus 9 db DCV deemphasis.
- DcvLevelMinus11 EQU 24 ; < Minus 11 db DCV deemphasis.
- MaxPlatformDeemphasisLevel EQU 25 ; < Not a deemphasis level, use for limit checking.
-PLATFORM_DEEMPHASIS_LEVEL TEXTEQU <DWORD>
-
-; Provide Deemphasis Levels for HT Links.
-;
-; For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will
-; be checked for a match. The item matches for a Socket, Link if the link frequency is
-; is in the inclusive range HighFreq:LoFreq.
-; AGESA does not set deemphasis in IO devices, only in processors.
-
-CPU_HT_DEEMPHASIS_LEVEL STRUCT
- ; Match fields
- Socket UINT8 ? ; < One Socket on which this Link is located
- Link UINT8 ? ; < The Link on this Processor.
- LoFreq UINT8 ? ; < If the link is set to this frequency or greater, apply these levels, and
- HighFreq UINT8 ? ; < If the link is set to this frequency or less, apply these levels.
- ; Value fields
- ReceiverDeemphasis PLATFORM_DEEMPHASIS_LEVEL ? ; < The deemphasis level for this link
- DcvDeemphasis PLATFORM_DEEMPHASIS_LEVEL ? ; < The DCV, or far transmitter deemphasis level.
-CPU_HT_DEEMPHASIS_LEVEL ENDS
-
-; The possible platform power policy settings.
- Performance EQU 0 ; < Optimize for performance.
- BatteryLife EQU 1 ; < Optimize for battery life.
- MaxPowerPolicy EQU 2 ; < Not a power policy mode, use for limit checking.
-PLATFORM_POWER_POLICY TEXTEQU <DWORD>
-
-; Platform performance settings for optimized settings.
-; Several configuration settings for the processor depend upon other parts and
-; general designer choices for the system. The determination of these data points
-; is not standard for all platforms, so the host environment needs to provide these
-; to specify how the system is to be configured.
-PERFORMANCE_PROFILE STRUCT
- PlatformControlFlowMode PLATFORM_CONTROL_FLOW ? ; < The platform's control flow mode for optimum platform performance.
- UseHtAssist BOOLEAN ? ; < HyperTransport link traffic optimization.
- UseAtmMode BOOLEAN ? ; < HyperTransport link traffic optimization.
- Use32ByteRefresh BOOLEAN ? ; < Display Refresh traffic generates 32 byte requests.
- UseVariableMctIsocPriority BOOLEAN ? ; < The Memory controller will be set to Variable Isoc Priority.
- PlatformPowerPolicy PLATFORM_POWER_POLICY ? ; < The platform's desired power policy
-PERFORMANCE_PROFILE ENDS
-
-; Platform settings that describe the voltage regulator modules of the system.
-; Many power management settings are dependent upon the characteristics of the
-; on-board voltage regulator module (VRM). The host environment needs to provide
-; these to specify how the system is to be configured.
-PLATFORM_VRM_CONFIGURATION STRUCT
- CurrentLimit UINT32 ? ; < Vrm Current Limit.
- LowPowerThreshold UINT32 ? ; < Vrm Low Power Threshold.
- SlewRate UINT32 ? ; < Vrm Slew Rate.
- AdditionalDelay UINT32 ? ; < Vrm Additional Delay.
- HiSpeedEnable BOOLEAN ? ; < Select high speed VRM.
- InrushCurrentLimit UINT32 ? ; < Vrm Inrush Current Limit.
-PLATFORM_VRM_CONFIGURATION ENDS
-
-; The VRM types to characterize.
- CoreVrm EQU 0 ; < VDD plane.
- NbVrm EQU 1 ; < VDDNB plane.
- MaxVrmType EQU 2 ; < Not a valid VRM type, use for limit checking.
-PLATFORM_VRM_TYPE TEXTEQU <DWORD>
-
-; Build Option/Configuration Boolean Structure
-BUILD_OPT_CFG STRUCT
- ; Build Option Area
- VersionString AMD_CODE_HEADER {} ; < AMD embedded code version string
- OptionUDimms BOOLEAN ? ; < UDIMMS
- OptionRDimms BOOLEAN ? ; < RDIMMS
- OptionLrDimms BOOLEAN ? ; < LRDIMMS
- OptionEcc BOOLEAN ? ; < ECC
- OptionBankInterleave BOOLEAN ? ; < BANK_INTERLEAVE
- OptionDctInterleave BOOLEAN ? ; < DCT_INTERLEAVE
- OptionNodeInterleave BOOLEAN ? ; < NODE_INTERLEAVE
- OptionParallelTraining BOOLEAN ? ; < PARALLEL_TRAINING
- OptionOnlineSpare BOOLEAN ? ; < ONLINE_SPARE
- OptionMemRestore BOOLEAN ? ; < MEM CONTEXT RESTORE
- OptionMultisocket BOOLEAN ? ; < MULTISOCKET
- OptionAcpiPstates BOOLEAN ? ; < ACPI_PSTATES
- OptionSrat BOOLEAN ? ; < SRAT
- OptionSlit BOOLEAN ? ; < SLIT
- OptionWhea BOOLEAN ? ; < WHEA
- OptionDmi BOOLEAN ? ; < DMI
- OptionEarlySamples BOOLEAN ? ; < EARLY_SAMPLES
- OptionAddrToCsTranslator BOOLEAN ? ; < ADDR_TO_CS_TRANSLATOR
-
- ; Build Configuration Area
- CfgPciMmioAddress UINT64 ? ; < PciMmioBase
- CfgPciMmioSize UINT32 ? ; < PciMmioSize
- CfgPlatVrmCfg PLATFORM_VRM_CONFIGURATION (MaxVrmType) DUP ({}) ; < Several configuration settings for the voltage regulator modules.
- CfgPlatNumIoApics UINT32 ? ; < PlatformApicIoNumber
- CfgMemInitPstate UINT32 ? ; < MemoryInitPstate
- CfgPlatformC1eMode PLATFORM_C1E_MODES ? ; < PlatformC1eMode
- CfgPlatformC1eOpData UINT32 ? ; < PlatformC1eOpData
- CfgPlatformC1eOpData1 UINT32 ? ; < PlatformC1eOpData1
- CfgPlatformC1eOpData2 UINT32 ? ; < PlatformC1eOpData2
- CfgPlatformCStateMode PLATFORM_CSTATE_MODES ? ; < PlatformCStateMode
- CfgPlatformCStateOpData UINT32 ? ; < PlatformCStateOpData
- CfgPlatformCStateIoBaseAddress UINT16 ? ; < PlatformCStateIoBaseAddress
- CfgPlatformCpbMode PLATFORM_CPB_MODES ? ; < PlatformCpbMode
- CfgCoreLevelingMode UINT32 ? ; < CoreLevelingCofig
- CfgPerformanceProfile PERFORMANCE_PROFILE {} ; < The platform's control flow mode and platform performance settings.
- CfgPlatformDeemphasisList POINTER ? ; < HT Deemphasis
- CfgAmdPlatformType UINT32 ? ; < AmdPlatformType
- CfgAmdPstateCapValue UINT32 ? ; < Amd pstate ceiling enabling deck
-
- CfgMemoryBusFrequencyLimit MEMORY_BUS_SPEED ? ; < Memory Bus Frequency Limit
- CfgMemoryModeUnganged BOOLEAN ? ; < Memory Mode Unganged
- CfgMemoryQuadRankCapable BOOLEAN ? ; < Memory Quad Rank Capable
- CfgMemoryQuadrankType QUANDRANK_TYPE ? ; < Memory Quadrank Type
- CfgMemoryRDimmCapable BOOLEAN ? ; < Memory RDIMM Capable
- CfgMemoryLRDimmCapable BOOLEAN ? ; < Memory LRDIMM Capable
- CfgMemoryUDimmCapable BOOLEAN ? ; < Memory UDIMM Capable
- CfgMemorySODimmCapable BOOLEAN ? ; < Memory SODimm Capable
- CfgMemoryEnableBankInterleaving BOOLEAN ? ; < Memory Enable Bank Interleaving
- CfgMemoryEnableNodeInterleaving BOOLEAN ? ; < Memory Enable Node Interleaving
- CfgMemoryChannelInterleaving BOOLEAN ? ; < Memory Channel Interleaving
- CfgMemoryPowerDown BOOLEAN ? ; < Memory Power Down
- CfgPowerDownMode POWER_DOWN_MODE ? ; < Power Down Mode
- CfgOnlineSpare BOOLEAN ? ; < Online Spare
- CfgMemoryParityEnable BOOLEAN ? ; < Memory Parity Enable
- CfgBankSwizzle BOOLEAN ? ; < Bank Swizzle
- CfgTimingModeSelect USER_MEMORY_TIMING_MODE ? ; < Timing Mode Select
- CfgMemoryClockSelect MEMORY_BUS_SPEED ? ; < Memory Clock Select
- CfgDqsTrainingControl BOOLEAN ? ; < Dqs Training Control
- CfgIgnoreSpdChecksum BOOLEAN ? ; < Ignore Spd Checksum
- CfgUseBurstMode BOOLEAN ? ; < Use Burst Mode
- CfgMemoryAllClocksOn BOOLEAN ? ; < Memory All Clocks On
- CfgEnableEccFeature BOOLEAN ? ; < Enable ECC Feature
- CfgEccRedirection BOOLEAN ? ; < ECC Redirection
- CfgScrubDramRate UINT16 ? ; < Scrub Dram Rate
- CfgScrubL2Rate UINT16 ? ; < Scrub L2Rate
- CfgScrubL3Rate UINT16 ? ; < Scrub L3Rate
- CfgScrubIcRate UINT16 ? ; < Scrub Ic Rate
- CfgScrubDcRate UINT16 ? ; < Scrub Dc Rate
- CfgEccSyncFlood BOOLEAN ? ; < ECC Sync Flood
- CfgEccSymbolSize UINT16 ? ; < ECC Symbol Size
- CfgHeapDramAddress UINT64 ? ; < Heap contents will be temporarily stored in this address during the transition
- CfgNodeMem1GBAlign BOOLEAN ? ; < Node Mem 1GB boundary Alignment
- CfgS3LateRestore BOOLEAN ? ; < S3 Late Restore
- CfgAcpiPstateIndependent BOOLEAN ? ; < PSD method dependent/Independent
- CfgApMtrrSettingsList POINTER ? ; < The AP's MTRR settings before final halt
- CfgUmaMode UMA_MODE ? ; < Uma Mode
- CfgUmaSize UINT32 ? ; < Uma Size [31:0]=Addr[47:16]
- CfgUmaAbove4G BOOLEAN ? ; < Uma Above 4G Support
- CfgUmaAlignment UMA_ALIGNMENT ? ; < Uma alignment
- CfgProcessorScopeInSb BOOLEAN ? ; < ACPI Processor Object in \_SB scope
- CfgProcessorScopeName0 CHAR8 ? ; < OEM specific 1st character of processor scope name.
- CfgProcessorScopeName1 CHAR8 ? ; < OEM specific 2nd character of processor scope name.
- CfgGnbHdAudio UINT8 ? ; < Gnb HD Audio Enable
- CfgAbmSupport UINT8 ? ; < ABM support
- CfgDynamicRefreshRate UINT8 ? ; < Dynamic refresh rate
- CfgLcdBackLightControl UINT16 ? ; < Lcd back light control
- CfgGnb3dStereoPinIndex UINT8 ? ; < 3D Stereo Pin ID
- CfgTempPcieMmioBaseAddress UINT32 ? ; < Temp pcie MMIO base address
- CfgGnbIGPUSSID UINT32 ? ; < Gnb internal GPU SSID
- CfgGnbHDAudioSSID UINT32 ? ; < Gnb HD Audio SSID
- CfgGnbPcieSSID UINT32 ? ; < Gnb PCIe SSID
- CfgLvdsSpreadSpectrum UINT16 ? ; < Lvds Spread Spectrum. Build-time customizable only
- CfgLvdsSpreadSpectrumRate UINT16 ? ; < Lvds Spread Spectrum Rate. Build-time customizable only
- CfgLvdsMiscControl LVDS_MISC_CONTROL {}; THe LVDS Misc control
- CfgPcieRefClkSpreadSpectrum UINT16 ? ; PCIe Reference Clock Spread Spectrum
- Reserved BOOLEAN ? ; < reserved...
-BUILD_OPT_CFG ENDS
-
- ; A structure containing platform specific operational characteristics. This
- ; structure is initially populated by the initializer with a copy of the same
- ; structure that was created at build time using the build configuration controls.
-PLATFORM_CONFIGURATION STRUCT
- PlatformProfile PERFORMANCE_PROFILE {} ; < Several configuration settings for the processor.
- PlatformDeemphasisList POINTER ? ; < Deemphasis levels for the platform's HT links.
- CoreLevelingMode UINT8 ? ; < Indicates how to balance the number of cores per processor.
- C1eMode PLATFORM_C1E_MODES ? ; < Specifies the method of C1e enablement - Disabled, HW, or message based.
- C1ePlatformData UINT32 ? ; < If C1eMode is HW, specifies the P_LVL3 I/O port of the platform.
- C1ePlatformData1 UINT32 ? ; < If C1eMode is SW, specifies the address of chipset's SMI command port.
- C1ePlatformData2 UINT32 ? ; < If C1eMode is SW, specifies the unique number used by the SMI handler to identify SMI source.
- CStateMode PLATFORM_CSTATE_MODES ? ; < Specifies the method of C-State enablement - Disabled, or C6.
- CStatePlatformData UINT32 ? ; < This element specifies some pertinent data needed for the operation of the Cstate feature
- ; < If CStateMode is CStateModeC6, this item is reserved
- CStateIoBaseAddress UINT16 ? ; < This item specifies a free block of 8 consecutive bytes of I/O ports that
- ; < can be used to allow the CPU to enter Cstates.
- CpbMode PLATFORM_CPB_MODES ? ; < Specifies the method of core performance boost enablement - Disabled, or Auto.
- UserOptionDmi BOOLEAN ? ; < When set to TRUE, the DMI data table is generated.
- UserOptionPState BOOLEAN ? ; < When set to TRUE, the PState data tables are generated.
- UserOptionSrat BOOLEAN ? ; < When set to TRUE, the SRAT data table is generated.
- UserOptionSlit BOOLEAN ? ; < When set to TRUE, the SLIT data table is generated.
- UserOptionWhea BOOLEAN ? ; < When set to TRUE, the WHEA data table is generated.
- PowerCeiling UINT32 ? ; < P-State Ceiling Enabling Deck - Max power milli-watts.
- ForcePstateIndependent BOOLEAN ? ; < P-State _PSD independence or dependence.
- NumberOfIoApics UINT32 ? ; < Number of I/O APICs in the system
- VrmProperties PLATFORM_VRM_CONFIGURATION (MaxVrmType) DUP ({}) ; < Several configuration settings for the voltage regulator modules.
- ProcessorScopeInSb BOOLEAN ? ; < ACPI Processor Object in \_SB scope
- ProcessorScopeName0 CHAR8 ? ; < OEM specific 1st character of processor scope name.
- ProcessorScopeName1 CHAR8 ? ; < OEM specific 2nd character of processor scope name.
- GnbHdAudio UINT8 ? ; < Control GFX HD Audio controller(Used for HDMI and DP display output),
- ; < essentially it enables function 1 of graphics device.
- ; < @li 0 = HD Audio disable
- ; < @li 1 = HD Audio enable
- AbmSupport UINT8 ? ; < Automatic adjust LVDS/eDP Back light level support.It is
- ; < characteristic specific to display panel which used by platform design.
- ; < @li 0 = ABM support disabled
- ; < @li 1 = ABM support enabled
- DynamicRefreshRate UINT8 ? ; < Adjust refresh rate on LVDS/eDP.
- LcdBackLightControl UINT16 ? ; < The PWM frequency to LCD backlight control.
- ; < If equal to 0 backlight not controlled by iGPU.
-PLATFORM_CONFIGURATION ENDS
-
-
-; *********************************************************************
-; * Structures for: AmdInitLate
-; *********************************************************************
- PROC_VERSION_LENGTH EQU 48
- MAX_DIMMS_PER_SOCKET EQU 16
-
-
- ; Interface Parameter Structures
- ; DMI Type4 - Processor ID
-TYPE4_PROC_ID STRUCT
- ProcIdLsd UINT32 ? ; < Lower half of 64b ID
- ProcIdMsd UINT32 ? ; < Upper half of 64b ID
-TYPE4_PROC_ID ENDS
-
- ; DMI Type 4 - Processor information
-TYPE4_DMI_INFO STRUCT
- T4ProcType UINT8 ? ; < CPU Type
- T4ProcFamily UINT8 ? ; < Family 1
- T4ProcId TYPE4_PROC_ID {} ; < Id
- T4Voltage UINT8 ? ; < Voltage
- T4ExternalClock UINT16 ? ; < External clock
- T4MaxSpeed UINT16 ? ; < Max speed
- T4CurrentSpeed UINT16 ? ; < Current speed
- T4Status UINT8 ? ; < Status
- T4ProcUpgrade UINT8 ? ; < Up grade
- T4CoreCount UINT8 ? ; < Core count
- T4CoreEnabled UINT8 ? ; < Core Enable
- T4ThreadCount UINT8 ? ; < Thread count
- T4ProcCharacteristics UINT16 ? ; < Characteristics
- T4ProcFamily2 UINT16 ? ; < Family 2
- T4ProcVersion CHAR8 (PROC_VERSION_LENGTH) DUP (?) ; < Cpu version
-TYPE4_DMI_INFO ENDS
-
- ; DMI Type 7 - Cache information
-TYPE7_DMI_INFO STRUCT
- T7CacheCfg UINT16 ? ; < Cache cfg
- T7MaxCacheSize UINT16 ? ; < Max size
- T7InstallSize UINT16 ? ; < Install size
- T7SupportedSramType UINT16 ? ; < Supported Sram Type
- T7CurrentSramType UINT16 ? ; < Current type
- T7CacheSpeed UINT8 ? ; < Speed
- T7ErrorCorrectionType UINT8 ? ; < ECC type
- T7SystemCacheType UINT8 ? ; < Cache type
- T7Associativity UINT8 ? ; < Associativity
-TYPE7_DMI_INFO ENDS
-
- ; DMI Type 16 offset 04h - Location
-
- OtherLocation EQU 01h ; < Assign 01 to Other
- UnknownLocation EQU 2 ; < Assign 02 to Unknown
- SystemboardOrMotherboard EQU 3 ; < Assign 03 to systemboard or motherboard
- IsaAddonCard EQU 4 ; < Assign 04 to ISA add-on card
- EisaAddonCard EQU 5 ; < Assign 05 to EISA add-on card
- PciAddonCard EQU 6 ; < Assign 06 to PCI add-on card
- McaAddonCard EQU 7 ; < Assign 07 to MCA add-on card
- PcmciaAddonCard EQU 8 ; < Assign 08 to PCMCIA add-on card
- ProprietaryAddonCard EQU 9 ; < Assign 09 to proprietary add-on card
- NuBus EQU 10 ; < Assign 0A to NuBus
- Pc98C20AddonCard EQU 11 ; < Assign 0A0 to PC-98/C20 add-on card
- Pc98C24AddonCard EQU 12 ; < Assign 0A1 to PC-98/C24 add-on card
- Pc98EAddoncard EQU 13 ; < Assign 0A2 to PC-98/E add-on card
- Pc98LocalBusAddonCard EQU 14 ; < Assign 0A3 to PC-98/Local bus add-on card
-DMI_T16_LOCATION TEXTEQU <DWORD> ;} DMI_T16_LOCATION;
-
- ; DMI Type 16 offset 05h - Memory Error Correction
-
- OtherUse EQU 01h ; < Assign 01 to Other
- UnknownUse EQU 2 ; < Assign 02 to Unknown
- SystemMemory EQU 3 ; < Assign 03 to system memory
- VideoMemory EQU 4 ; < Assign 04 to video memory
- FlashMemory EQU 5 ; < Assign 05 to flash memory
- NonvolatileRam EQU 6 ; < Assign 06 to non-volatile RAM
- CacheMemory EQU 7 ; < Assign 07 to cache memory
-DMI_T16_USE TEXTEQU <DWORD> ;} DMI_T16_USE;
-
- ; DMI Type 16 offset 07h - Maximum Capacity
-
- Dmi16OtherErrCorrection EQU 01h ; < Assign 01 to Other
- Dmi16UnknownErrCorrection EQU 2 ; < Assign 02 to Unknown
- Dmi16NoneErrCorrection EQU 3 ; < Assign 03 to None
- Dmi16Parity EQU 4 ; < Assign 04 to parity
- Dmi16SingleBitEcc EQU 5 ; < Assign 05 to Single-bit ECC
- Dmi16MultiBitEcc EQU 6 ; < Assign 06 to Multi-bit ECC
- Dmi16Crc EQU 7 ; < Assign 07 to CRC
-DMI_T16_ERROR_CORRECTION TEXTEQU <DWORD> ;} DMI_T16_ERROR_CORRECTION;
-
- ; DMI Type 16 - Physical Memory Array
-TYPE16_DMI_INFO STRUCT
- Location DMI_T16_LOCATION ? ; < The physical location of the Memory Array,
- ; < whether on the system board or an add-in board.
- Use DMI_T16_USE ? ; < Identifies the function for which the array
- ; < is used.
- MemoryErrorCorrection DMI_T16_ERROR_CORRECTION ? ; < The primary hardware error correction or
- ; < detection method supported by this memory array.
- MaximumCapacity UINT32 ? ; < The maximum memory capacity, in kilobytes,
- ; < for the array.
- NumberOfMemoryDevices UINT16 ? ; < The number of slots or sockets available
- ; < for memory devices in this array.
-TYPE16_DMI_INFO ENDS
-
- ; DMI Type 17 offset 0Eh - Form Factor
- OtherFormFactor EQU 01h ; < Assign 01 to Other
- UnknowFormFactor EQU 2 ; < Assign 02 to Unknown
- SimmFormFactor EQU 3 ; < Assign 03 to SIMM
- SipFormFactor EQU 4 ; < Assign 04 to SIP
- ChipFormFactor EQU 5 ; < Assign 05 to Chip
- DipFormFactor EQU 6 ; < Assign 06 to DIP
- ZipFormFactor EQU 7 ; < Assign 07 to ZIP
- ProprietaryCardFormFactor EQU 8 ; < Assign 08 to Proprietary Card
- DimmFormFactorFormFactor EQU 9 ; < Assign 09 to DIMM
- TsopFormFactor EQU 10 ; < Assign 10 to TSOP
- RowOfChipsFormFactor EQU 11 ; < Assign 11 to Row of chips
- RimmFormFactor EQU 12 ; < Assign 12 to RIMM
- SodimmFormFactor EQU 13 ; < Assign 13 to SODIMM
- SrimmFormFactor EQU 14 ; < Assign 14 to SRIMM
- FbDimmFormFactor EQU 15 ; < Assign 15 to FB-DIMM
-DMI_T17_FORM_FACTOR TEXTEQU <DWORD>
-
- ; DMI Type 17 offset 12h - Memory Type
- OtherMemType EQU 01h ; < Assign 01 to Other
- UnknownMemType EQU 2 ; < Assign 02 to Unknown
- DramMemType EQU 3 ; < Assign 03 to DRAM
- EdramMemType EQU 4 ; < Assign 04 to EDRAM
- VramMemType EQU 5 ; < Assign 05 to VRAM
- SramMemType EQU 6 ; < Assign 06 to SRAM
- RamMemType EQU 7 ; < Assign 07 to RAM
- RomMemType EQU 8 ; < Assign 08 to ROM
- FlashMemType EQU 9 ; < Assign 09 to Flash
- EepromMemType EQU 10 ; < Assign 10 to EEPROM
- FepromMemType EQU 11 ; < Assign 11 to FEPROM
- EpromMemType EQU 12 ; < Assign 12 to EPROM
- CdramMemType EQU 13 ; < Assign 13 to CDRAM
- ThreeDramMemType EQU 14 ; < Assign 14 to 3DRAM
- SdramMemType EQU 15 ; < Assign 15 to SDRAM
- SgramMemType EQU 16 ; < Assign 16 to SGRAM
- RdramMemType EQU 17 ; < Assign 17 to RDRAM
- DdrMemType EQU 18 ; < Assign 18 to DDR
- Ddr2MemType EQU 19 ; < Assign 19 to DDR2
- Ddr2FbdimmMemType EQU 20 ; < Assign 20 to DDR2 FB-DIMM
- Ddr3MemType EQU 24 ; < Assign 24 to DDR3
- Fbd2MemType EQU 25 ; < Assign 25 to FBD2
-DMI_T17_MEMORY_TYPE TEXTEQU <DWORD>
-
- ; DMI Type 17 offset 13h - Type Detail
-DMI_T17_TYPE_DETAIL STRUCT
- Reserved1 UINT16 ?
-; OUT UINT16 Reserved1:1; ; < Reserved
-; OUT UINT16 Other:1; ; < Other
-; OUT UINT16 Unknown:1; ; < Unknown
-; OUT UINT16 FastPaged:1; ; < Fast-Paged
-; OUT UINT16 StaticColumn:1; ; < Static column
-; OUT UINT16 PseudoStatic:1; ; < Pseudo-static
-; OUT UINT16 Rambus:1; ; < RAMBUS
-; OUT UINT16 Synchronous:1; ; < Synchronous
-; OUT UINT16 Cmos:1; ; < CMOS
-; OUT UINT16 Edo:1; ; < EDO
-; OUT UINT16 WindowDram:1; ; < Window DRAM
-; OUT UINT16 CacheDram:1; ; < Cache Dram
-; OUT UINT16 NonVolatile:1; ; < Non-volatile
-; OUT UINT16 Reserved2:3; ; < Reserved
-DMI_T17_TYPE_DETAIL ENDS
-
- ; DMI Type 17 - Memory Device
-TYPE17_DMI_INFO STRUCT
- TotalWidth UINT16 ? ; < Total Width, in bits, of this memory device, including any check or error-correction bits.
- DataWidth UINT16 ? ; < Data Width, in bits, of this memory device.
- MemorySize UINT16 ? ; < The size of the memory device.
- FormFactor DMI_T17_FORM_FACTOR ? ; < The implementation form factor for this memory device.
- DeviceSet UINT8 ? ; < Identifies when the Memory Device is one of a set of
- ; < Memory Devices that must be populated with all devices of
- ; < the same type and size, and the set to which this device belongs.
- DeviceLocator CHAR8 (8) DUP (?) ; < The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
- BankLocator CHAR8 (10) DUP (?) ; < The string number of the string that identifies the physically labeled bank where the memory device is located.
- MemoryType DMI_T17_MEMORY_TYPE ? ; < The type of memory used in this device.
- TypeDetail DMI_T17_TYPE_DETAIL {} ; < Additional detail on the memory device type
- Speed UINT16 ? ; < Identifies the speed of the device, in megahertz (MHz).
- ManufacturerIdCode UINT64 ? ; < Manufacturer ID code.
- SerialNumber CHAR8 (9) DUP (?) ; < Serial Number.
- PartNumber CHAR8 (19) DUP (?) ; < Part Number.
- Attributes UINT8 ? ; < Bits 7-4: Reserved, Bits 3-0: rank.
- ExtSize UINT32 ? ; < Extended Size.
- ConfigSpeed UINT16 ? ; < Configured memory clock speed
-TYPE17_DMI_INFO ENDS
-
- ; Memory DMI Type 17 and 20 - for memory use
-MEM_DMI_INFO STRUCT
- TotalWidth UINT16 ? ; ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
- DataWidth UINT16 ? ; ///< Data Width, in bits, of this memory device.
- MemorySize UINT16 ? ; ///< The size of the memory device.
- FormFactor DMI_T17_FORM_FACTOR ? ; ///< The implementation form factor for this memory device.
- DeviceLocator UINT8 ? ; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
- BankLocator UINT8 ? ; ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
- Speed UINT16 ? ; ///< Identifies the speed of the device, in megahertz (MHz).
- ManufacturerIdCode UINT64 ? ; ///< Manufacturer ID code.
- SerialNumber UINT8 (4) DUP (?) ; ///< Serial Number.
- PartNumber UINT8 (18) DUP (?) ; ///< Part Number.
- Attributes UINT8 ? ; ///< Bits 7-4: Reserved, Bits 3-0: rank.
- ExtSize UINT32 ? ; ///< Extended Size.
- Socket UINT8 ?
-; OUT UINT8 Socket:3 ; ///< Socket ID
-; OUT UINT8 Channel:2 ; ///< Channel ID
-; OUT UINT8 Dimm:2 ; ///< DIMM ID
-; OUT UINT8 DimmPresent:1 ; ///< Dimm Present
- StartingAddr UINT32 ? ; ///< The physical address, in kilobytes, of a range
- ; ///< of memory mapped to the referenced Memory Device.
- EndingAddr UINT32 ? ; ///< The handle, or instance number, associated with
- ; ///< the Memory Device structure to which this address
- ; ///< range is mapped.
- ConfigSpeed UINT16 ? ; ///< Configured memory clock speed
-MEM_DMI_INFO ENDS
-
- ; DMI Type 19 - Memory Array Mapped Address
-TYPE19_DMI_INFO STRUCT
- StartingAddr UINT32 ? ; < The physical address, in kilobytes,
- ; < of a range of memory mapped to the
- ; < specified physical memory array.
- EndingAddr UINT32 ? ; < The physical ending address of the
- ; < last kilobyte of a range of addresses
- ; < mapped to the specified physical memory array.
- MemoryArrayHandle UINT16 ? ; < The handle, or instance number, associated
- ; < with the physical memory array to which this
- ; < address range is mapped.
- PartitionWidth UINT8 ? ; < Identifies the number of memory devices that
- ; < form a single row of memory for the address
- ; < partition defined by this structure.
-TYPE19_DMI_INFO ENDS
-
-; DMI Type 20 - Memory Device Mapped Address
-TYPE20_DMI_INFO STRUCT
- StartingAddr UINT32 ? ; < The physical address, in kilobytes, of a range
- ; < of memory mapped to the referenced Memory Device.
- EndingAddr UINT32 ? ; < The handle, or instance number, associated with
- ; < the Memory Device structure to which this address
- ; < range is mapped.
- MemoryDeviceHandle UINT16 ? ; < The handle, or instance number, associated with
- ; < the Memory Device structure to which this address
- ; < range is mapped.
- MemoryArrayMappedAddressHandle UINT16 ? ; < The handle, or instance number, associated
- ; < with the Memory Array Mapped Address structure to
- ; < which this device address range is mapped.
- PartitionRowPosition UINT8 ? ; < Identifies the position of the referenced Memory
- ; < Device in a row of the address partition.
- InterleavePosition UINT8 ? ; < The position of the referenced Memory Device in
- ; < an interleave.
- InterleavedDataDepth UINT8 ? ; < The maximum number of consecutive rows from the
- ; < referenced Memory Device that are accessed in a
- ; < single interleaved transfer.
-TYPE20_DMI_INFO ENDS
-
- ; Collection of pointers to the DMI records
-DMI_INFO STRUCT
- T4 TYPE4_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 4 struc
- T7L1 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 1
- T7L2 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 2
- T7L3 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 3
- T16 TYPE16_DMI_INFO {} ; < Type 16 struc
- T17 TYPE17_DMI_INFO (MAX_SOCKETS_SUPPORTED * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL) DUP ({}) ; < Type 17 struc
- T19 TYPE19_DMI_INFO {} ; < Type 19 struc
- T20 TYPE20_DMI_INFO (MAX_SOCKETS_SUPPORTED * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL) DUP ({}) ; < Type 20 struc
-DMI_INFO ENDS
-
-
-
-; *********************************************************************
-; * Interface call: AllocateExecutionCache
-; *********************************************************************
- MAX_CACHE_REGIONS EQU 3
-
- ; AllocateExecutionCache sub param structure for cached memory region
-EXECUTION_CACHE_REGION STRUCT
- ExeCacheStartAddr UINT32 ? ; < Start address
- ExeCacheSize UINT32 ? ; < Size
-EXECUTION_CACHE_REGION ENDS
-
-; *********************************************************************
-; * Interface call: AmdGetAvailableExeCacheSize
-; *********************************************************************
- ; Get available Cache remain
-AMD_GET_EXE_SIZE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- AvailableExeCacheSize UINT32 ? ; < Remain size
-AMD_GET_EXE_SIZE_PARAMS ENDS
-
-
-
-
-
-
- ; Selection type for core leveling
- CORE_LEVEL_LOWEST EQU 0 ; < Level to lowest common denominator
- CORE_LEVEL_TWO EQU 1 ; < Level to 2 cores
- CORE_LEVEL_POWER_OF_TWO EQU 2 ; < Level to 1,2,4 or 8
- CORE_LEVEL_NONE EQU 3 ; < Do no leveling
- CORE_LEVEL_COMPUTE_UNIT EQU 4 ; < Level cores to one core per compute unit
- CORE_LEVEL_ONE EQU 5 ; < Level to 1 core
- CORE_LEVEL_THREE EQU 6 ; < Level to 3 cores
- CORE_LEVEL_FOUR EQU 7 ; < Level to 4 cores
- CORE_LEVEL_FIVE EQU 8 ; < Level to 5 cores
- CORE_LEVEL_SIX EQU 9 ; < Level to 6 cores
- CORE_LEVEL_SEVEN EQU 10 ; < Level to 7 cores
- CORE_LEVEL_EIGHT EQU 11 ; < Level to 8 cores
- CORE_LEVEL_NINE EQU 12 ; < Level to 9 cores
- CORE_LEVEL_TEN EQU 13 ; < Level to 10 cores
- CORE_LEVEL_ELEVEN EQU 14 ; < Level to 11 cores
- CORE_LEVEL_TWELVE EQU 15 ; < Level to 12 cores
- CORE_LEVEL_THIRTEEN EQU 16 ; < Level to 13 cores
- CORE_LEVEL_FOURTEEN EQU 17 ; < Level to 14 cores
- CORE_LEVEL_FIFTEEN EQU 18 ; < Level to 15 cores
- CoreLevelModeMax EQU 19 ; < Used for bounds checking
-CORE_LEVELING_TYPE TEXTEQU <DWORD>
-
-
-; ***********************************************************************
-; *
-; * AGESA Basic Level interface structure definition and function prototypes
-; *
-; **********************************************************************
-
-; *********************************************************************
-; * Interface call: AmdCreateStruct
-; *********************************************************************
-
-; *********************************************************************
-; * Interface call: AmdReleaseStruct
-; *********************************************************************
-
-; *********************************************************************
-; * Interface call: AmdInitReset
-; *********************************************************************
- ; AmdInitReset param structure
-AMD_RESET_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < The cached memory region
- HtConfig AMD_HT_RESET_INTERFACE {} ; < The interface for Ht Recovery
-AMD_RESET_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitEarly
-; *********************************************************************
- ; InitEarly param structure
-
- ; Provide defaults or customizations to each service performed in AmdInitEarly.
-
-AMD_EARLY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < The standard header
- CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < Execution Map Interface
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- HtConfig AMD_HT_INTERFACE {} ; < HyperTransport Interface
- GnbConfig GNB_CONFIGURATION {} ; < GNB configuration
-AMD_EARLY_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitPost
-; *********************************************************************
- ; AmdInitPost param structure
-AMD_POST_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- MemConfig MEM_PARAMETER_STRUCT {} ; < Memory post param
-AMD_POST_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitEnv
-; *********************************************************************
- ; AmdInitEnv param structure
-AMD_ENV_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- GnbEnvConfiguration GNB_ENV_CONFIGURATION {} ; < platform operational characteristics.
-AMD_ENV_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitMid
-; *********************************************************************
- ; AmdInitMid param structure
-AMD_MID_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
-AMD_MID_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitLate
-; *********************************************************************
- ; AmdInitLate param structure
-AMD_LATE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- DmiTable POINTER ? ; < DMI Interface
- AcpiPState POINTER ? ; < Acpi Pstate SSDT Table
- AcpiSrat POINTER ? ; < SRAT Table
- AcpiSlit POINTER ? ; < SLIT Table
- AcpiWheaMce POINTER ? ; < WHEA MCE Table
- AcpiWheaCmc POINTER ? ; < WHEA CMC Table
- AcpiAlib POINTER ? ; < ALIB Table
-AMD_LATE_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitRecovery
-; *********************************************************************
- ; CPU Recovery Parameters
-AMD_CPU_RECOVERY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard Header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics
-AMD_CPU_RECOVERY_PARAMS ENDS
-
- ; AmdInitRecovery param structure
-AMD_RECOVERY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- MemConfig MEM_PARAMETER_STRUCT {} ; < Memory post param
- CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < The cached memory region. And the max cache region is 3
- CpuRecoveryParams AMD_CPU_RECOVERY_PARAMS {} ; < Params for CPU related recovery init.
-AMD_RECOVERY_PARAMS ENDS
-
-
-; *********************************************************************
-; * Interface call: AmdInitResume
-; *********************************************************************
- ; AmdInitResume param structure
-AMD_RESUME_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < Platform operational characteristics
- S3DataBlock AMD_S3_PARAMS {} ; < Save state data
-AMD_RESUME_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdS3LateRestore
-; *********************************************************************
- ; AmdS3LateRestore param structure
-AMD_S3LATE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- S3DataBlock AMD_S3_PARAMS {} ; < Save state data
-AMD_S3LATE_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdS3Save
-; *********************************************************************
- ; AmdS3Save param structure
-AMD_S3SAVE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- S3DataBlock AMD_S3_PARAMS {} ; < Standard header
-AMD_S3SAVE_PARAMS ENDS
-
- ; General Services API
-
-
-; *********************************************************************
-; * Interface service call: AmdGetApicId
-; *********************************************************************
- ; Request the APIC ID of a particular core.
-
-AMD_APIC_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- Socket UINT8 ? ; < The Core's Socket.
- Core UINT8 ? ; < The Core id.
- IsPresent BOOLEAN ? ; < The Core is present, and ApicAddress is valid.
- ApicAddress UINT8 ? ; < The Core's APIC ID.
-AMD_APIC_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdGetPciAddress
-; *********************************************************************
- ; Request the PCI Address of a Processor Module (that is, its Northbridge)
-
-AMD_GET_PCI_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- Socket UINT8 ? ; < The Processor's socket
- Module UINT8 ? ; < The Module in that Processor
- IsPresent BOOLEAN ? ; < The Core is present, and PciAddress is valid.
- PciAddress PCI_ADDR {} ; < The Processor's PCI Config Space address (Function 0, Register 0)
-AMD_GET_PCI_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdIdentifyCore
-; *********************************************************************
- ; Request the identity (Socket, Module, Core) of the current Processor Core
-
-AMD_IDENTIFY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- Socket UINT8 ? ; < The current Core's Socket
- Module UINT8 ? ; < The current Core's Processor Module
- Core UINT8 ? ; < The current Core's core id.
-AMD_IDENTIFY_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdReadEventLog
-; *********************************************************************
- ; An Event Log Entry.
-EVENT_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- EventClass UINT32 ? ; < The severity of this event, matches AGESA_STATUS.
- EventInfo UINT32 ? ; < The unique event identifier, zero means "no event".
- DataParam1 UINT32 ? ; < Data specific to the Event.
- DataParam2 UINT32 ? ; < Data specific to the Event.
- DataParam3 UINT32 ? ; < Data specific to the Event.
- DataParam4 UINT32 ? ; < Data specific to the Event.
-EVENT_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdIdentifyDimm
-; *********************************************************************
- ; Request the identity of dimm from system address
-
-AMD_IDENTIFY_DIMM STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- MemoryAddress UINT64 ? ; < System Address that needs to be translated to dimm identification.
- SocketId UINT8 ? ; < The socket on which the targeted address locates.
- MemChannelId UINT8 ? ; < The channel on which the targeted address locates.
- DimmId UINT8 ? ; < The dimm on which the targeted address locates.
-AMD_IDENTIFY_DIMM ENDS
-
- ; Data structure for the Mapping Item between Unified ID for IDS Setup Option
- ; and the option value.
-
-IDS_NV_ITEM STRUCT
- IdsNvId UINT16 ? ; < Unified ID for IDS Setup Option.
- IdsNvValue UINT16 ? ; < The value of IDS Setup Option.
-IDS_NV_ITEM ENDS
-
- ; Data Structure for IDS CallOut Function
-IDS_CALLOUT_STRUCT STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < The Standard Header for AGESA Service
- IdsNvPtr POINTER ? ; < Memory Pointer of IDS NV Table
- Reserved UINT32 ? ; < reserved
-IDS_CALLOUT_STRUCT ENDS
-
- AGESA_IDS_DFT_VAL EQU 0FFFFh; < Default value of every uninitlized NV item, the action for it will be ignored
- AGESA_IDS_NV_END EQU 0FFFFh; < Flag specify end of option structure
-; WARNING: Don't change the comment below, it used as signature for script
-; AGESA IDS NV ID Definitions
- AGESA_IDS_EXT_ID_START EQU 0000h; < specify the start of external NV id
-
- AGESA_IDS_NV_UCODE EQU 0001h; < Enable or disable microcode patching
-
- AGESA_IDS_NV_TARGET_PSTATE EQU 0002h; < Set the P-state required to be activated
- AGESA_IDS_NV_POSTPSTATE EQU 0003h; < Set the P-state required to be activated through POST
-
- AGESA_IDS_NV_BANK_INTERLEAVE EQU 0004h; < Enable or disable Bank Interleave
- AGESA_IDS_NV_CHANNEL_INTERLEAVE EQU 0005h; < Enable or disable Channel Interleave
- AGESA_IDS_NV_NODE_INTERLEAVE EQU 0006h; < Enable or disable Node Interleave
- AGESA_IDS_NV_MEMHOLE EQU 0007h; < Enables or disable memory hole
-
- AGESA_IDS_NV_SCRUB_REDIRECTION EQU 0008h; < Enable or disable a write to dram with corrected data
- AGESA_IDS_NV_DRAM_SCRUB EQU 0009h; < Set the rate of background scrubbing for DRAM
- AGESA_IDS_NV_DCACHE_SCRUB EQU 000Ah; < Set the rate of background scrubbing for the DCache.
- AGESA_IDS_NV_L2_SCRUB EQU 000Bh; < Set the rate of background scrubbing for the L2 cache
- AGESA_IDS_NV_L3_SCRUB EQU 000Ch; < Set the rate of background scrubbing for the L3 cache
- AGESA_IDS_NV_ICACHE_SCRUB EQU 000Dh; < Set the rate of background scrubbing for the Icache
- AGESA_IDS_NV_SYNC_ON_ECC_ERROR EQU 000Eh; < Enable or disable the sync flood on un-correctable ECC error
- AGESA_IDS_NV_ECC_SYMBOL_SIZE EQU 000Fh; < Set ECC symbol size
-
- AGESA_IDS_NV_ALL_MEMCLKS EQU 0010h; < Enable or disable all memory clocks enable
- AGESA_IDS_NV_DCT_GANGING_MODE EQU 0011h; < Set the Ganged mode
- AGESA_IDS_NV_DRAM_BURST_LENGTH32 EQU 0012h; < Set the DRAM Burst Length 32
- AGESA_IDS_NV_MEMORY_POWER_DOWN EQU 0013h; < Enable or disable Memory power down mode
- AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE EQU 0014h; < Set the Memory power down mode
- AGESA_IDS_NV_DLL_SHUT_DOWN EQU 0015h; < Enable or disable DLLShutdown
- AGESA_IDS_NV_ONLINE_SPARE EQU 0016h; < Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap
-
- AGESA_IDS_NV_HT_ASSIST EQU 0017h; < Enable or Disable HT Assist
- AGESA_IDS_NV_ATMMODE EQU 0018h; < Enable or Disable ATM mode
-
- AGESA_IDS_NV_HDTOUT EQU 0019h; < Enable or disable HDTOUT feature
-
- AGESA_IDS_NV_HTLINKSOCKET EQU 001Ah; < HT Link Socket
- AGESA_IDS_NV_HTLINKPORT EQU 001Bh; < HT Link Port
- AGESA_IDS_NV_HTLINKFREQ EQU 001Ch; < HT Link Frequency
- AGESA_IDS_NV_HTLINKWIDTHIN EQU 001Dh; < HT Link In Width
- AGESA_IDS_NV_HTLINKWIDTHOUT EQU 001Eh; < HT Link Out Width
-
- AGESA_IDS_NV_GNBHDAUDIOEN EQU 001Fh; < Enable or disable GNB HD Audio
-
- AGESA_IDS_NV_CPB_EN EQU 0020h; < Core Performance Boost
-
- AGESA_IDS_NV_HTC_EN EQU 0021h; < HTC Enable
- AGESA_IDS_NV_HTC_OVERRIDE EQU 0022h; < HTC Override
- AGESA_IDS_NV_HTC_PSTATE_LIMIT EQU 0023h; < HTC P-state limit select
- AGESA_IDS_NV_HTC_TEMP_HYS EQU 0024h; < HTC Temperature Hysteresis
- AGESA_IDS_NV_HTC_ACT_TEMP EQU 0025h; < HTC Activation Temp
-
- AGESA_IDS_NV_POWER_POLICY EQU 0026h; < Select Platform Power Policy
- AGESA_IDS_EXT_ID_END EQU 0027h; < specify the end of external NV ID
-
- IDS_EX_NV_ID TEXTEQU <DWORD>
diff --git a/src/vendorcode/amd/agesa/f14/Legacy/amd.inc b/src/vendorcode/amd/agesa/f14/Legacy/amd.inc
deleted file mode 100644
index b7162024e4..0000000000
--- a/src/vendorcode/amd/agesa/f14/Legacy/amd.inc
+++ /dev/null
@@ -1,461 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * Agesa structures and definitions
-; *
-; * Contains AMD AGESA core interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 33891 $ @e \$Date: 2010-06-26 00:22:54 +0800 (Sat, 26 Jun 2010) $
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-
-UINT64 TEXTEQU <QWORD>
-UINT32 TEXTEQU <DWORD>
-UINT16 TEXTEQU <WORD>
-UINT8 TEXTEQU <BYTE>
-CHAR8 TEXTEQU <BYTE>
-BOOLEAN TEXTEQU <BYTE>
-POINTER TEXTEQU <DWORD>
-
- ; AGESA Types and Definitions
-
- AGESA_REVISION EQU "Arch2008"
- AGESA_ID EQU "AGESA"
-
- LAST_ENTRY EQU 0FFFFFFFFh
- IMAGE_SIGNATURE EQU 'DMA$'
- IOCF8 EQU 0CF8h
- IOCFC EQU 0CFCh
-
- ; The return status for all AGESA public services.
-
- ; Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
- ; will have log entries with more detail.
-
- AGESA_SUCCESS EQU 0 ; < The service completed normally. Info may be logged.
- AGESA_UNSUPPORTED EQU 1 ; < The dispatcher or create struct had an unimplemented function requested.
- ; < Not logged.
- AGESA_BOUNDS_CHK EQU 2 ; < A dynamic parameter was out of range and the service was not provided.
- ; < Example, memory address not installed, heap buffer handle not found.
- ; < Not Logged.
- ; AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
- AGESA_ALERT EQU 3 ; < An observed condition, but no loss of function.
- ; < See log. Example, HT CRC.
- AGESA_WARNING EQU 4 ; < Possible or minor loss of function. See Log.
- AGESA_ERROR EQU 5 ; < Significant loss of function, boot may be possible. See Log.
- AGESA_CRITICAL EQU 6 ; < Continue boot only to notify user. See Log.
- AGESA_FATAL EQU 7 ; < Halt booting. See Log.
- AgesaStatusMax EQU 8 ; < Not a status, use for limit checking.
-AGESA_STATUS TEXTEQU <DWORD>
-
-; For checking whether a status is at or above the mandatory log level.
-AGESA_STATUS_LOG_LEVEL EQU AGESA_ALERT
-
- CALLOUT_ENTRY TEXTEQU <POINTER>
- IMAGE_ENTRY TEXTEQU <POINTER>
- MODULE_ENTRY TEXTEQU <POINTER>
-
-; This allocation type is used by the AmdCreateStruct entry point
- PreMemHeap EQU 0 ; < Create heap in cache.
- PostMemDram EQU 1 ; < Create heap in memory.
- ByHost EQU 2 ; < Create heap by Host.
-ALLOCATION_METHOD TEXTEQU <DWORD>
-
- ; These width descriptors are used by the library function, and others, to specify the data size
- AccessWidth8 EQU 1 ; < Access width is 8 bits.
- AccessWidth16 EQU 2 ; < Access width is 16 bits.
- AccessWidth32 EQU 3 ; < Access width is 32 bits.
- AccessWidth64 EQU 4 ; < Access width is 64 bits.
-
- AccessS3SaveWidth8 EQU 81h ; < Save 8 bits data.
- AccessS3SaveWidth16 EQU 130 ; < Save 16 bits data.
- AccessS3SaveWidth32 EQU 131 ; < Save 32 bits data.
- AccessS3SaveWidth64 EQU 132 ; < Save 64 bits data.
-ACCESS_WIDTH TEXTEQU <DWORD>
-
- ; AGESA struct name
-
- ; AGESA BASIC FUNCTIONS
- AMD_INIT_RECOVERY EQU 00020000h
- AMD_CREATE_STRUCT EQU 00020001h
- AMD_INIT_EARLY EQU 00020002h
- AMD_INIT_ENV EQU 00020003h
- AMD_INIT_LATE EQU 00020004h
- AMD_INIT_MID EQU 00020005h
- AMD_INIT_POST EQU 00020006h
- AMD_INIT_RESET EQU 00020007h
- AMD_INIT_RESUME EQU 00020008h
- AMD_RELEASE_STRUCT EQU 00020009h
- AMD_S3LATE_RESTORE EQU 0002000Ah
- AMD_S3_SAVE EQU 0002000Bh
- AMD_GET_APIC_ID EQU 0002000Ch
- AMD_GET_PCI_ADDRESS EQU 0002000Dh
- AMD_IDENTIFY_CORE EQU 0002000Eh
- AMD_READ_EVENT_LOG EQU 0002000Fh
- AMD_GET_EXECACHE_SIZE EQU 00020010h
- AMD_LATE_RUN_AP_TASK EQU 00020011h
- AMD_IDENTIFY_DIMMS EQU 00020012h
-AGESA_STRUCT_NAME TEXTEQU <DWORD>
-
-
- ; ResetType constant values
- WARM_RESET_WHENEVER EQU 1
- COLD_RESET_WHENEVER EQU 2
- WARM_RESET_IMMEDIATELY EQU 3
- COLD_RESET_IMMEDIATELY EQU 4
-
-
- ; AGESA Structures
-
- ; The standard header for all AGESA services.
-AMD_CONFIG_PARAMS STRUCT
- ImageBasePtr UINT32 ? ; < The AGESA Image base address.
- Func UINT32 ? ; < The service desired, @sa dispatch.h.
- AltImageBasePtr UINT32 ? ; < Alternate Image location
- CalloutPtr CALLOUT_ENTRY ? ; < For Callout from AGESA
- HeapStatus UINT8 ? ; < For heap status from boot time slide.
- HeapBasePtr UINT64 ? ; < Location of the heap
- Reserved UINT8 (7) DUP (?) ; < This space is reserved for future use.
-AMD_CONFIG_PARAMS ENDS
-
-
- ; Create Struct Interface.
-AMD_INTERFACE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Config header
- AgesaFunctionName AGESA_STRUCT_NAME ? ; < The service to init, @sa dispatch.h
- AllocationMethod ALLOCATION_METHOD ? ; < How to handle buffer allocation
- NewStructSize UINT32 ? ; < The size of the allocated data, in for ByHost, else out only.
- NewStructPtr POINTER ? ; < The struct for the service.
- ; < The struct to init for ByHost allocation,
- ; < the initialized struct on return.
-AMD_INTERFACE_PARAMS ENDS
-
- FUNC_0 EQU 0 ; bit-placed for PCI address creation
- FUNC_1 EQU 1
- FUNC_2 EQU 2
- FUNC_3 EQU 3
- FUNC_4 EQU 4
- FUNC_5 EQU 5
- FUNC_6 EQU 6
- FUNC_7 EQU 7
-
- ; AGESA Binary module header structure
-AMD_IMAGE_HEADER STRUCT
- Signature UINT32 ? ; < Binary Signature
- CreatorID CHAR8 (8) DUP (?) ; < 8 characters ID
- Version CHAR8 (12) DUP (?) ; < 12 characters version
- ModuleInfoOffset UINT32 ? ; < Offset of module
- EntryPointAddress UINT32 ? ; < Entry address
- ImageBase UINT32 ? ; < Image base
- RelocTableOffset UINT32 ? ; < Relocate Table offset
- ImageSize UINT32 ? ; < Size
- Checksum UINT16 ? ; < Checksum
- ImageType UINT8 ? ; < Type
- V_Reserved UINT8 ? ; < Reserved
-AMD_IMAGE_HEADER ENDS
- ; AGESA Binary module header structure
-AMD_MODULE_HEADER STRUCT
- ModuleHeaderSignature UINT32 ? ; < Module signature
- ModuleIdentifier CHAR8 (8) DUP (?) ; < 8 characters ID
- ModuleVersion CHAR8 (12) DUP (?) ; < 12 characters version
- ModuleDispatcher POINTER ? ; < A pointer point to dispatcher
- NextBlock POINTER ? ; < Next module header link
-AMD_MODULE_HEADER ENDS
-
-; AMD_CODE_HEADER Signatures.
-AGESA_CODE_SIGNATURE TEXTEQU <'!', '!', 'A', 'G', 'E', 'S', 'A', ' '>
-CIMXNB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'>
-CIMXSB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'>
-
-; AGESA_CODE_SIGNATURE
-AMD_CODE_HEADER STRUCT
- Signature CHAR8 (8) DUP (?) ; < code header Signature
- ComponentName CHAR8 (8) DUP (?) ; < 8 character name of the code module
- Version CHAR8 (12) DUP (?) ; < 12 character version string
- TerminatorNull CHAR8 ? ; < null terminated string
- VerReserved CHAR8 (7) DUP (?) ; < reserved space
-AMD_CODE_HEADER ENDS
-
- ; Extended PCI address format
-EXT_PCI_ADDR STRUCT
- Register UINT32 ?
-; IN OUT UINT32 Register:12; ; < Register offset
-; IN OUT UINT32 Function:3; ; < Function number
-; IN OUT UINT32 Device:5; ; < Device number
-; IN OUT UINT32 Bus:8; ; < Bus number
-; IN OUT UINT32 Segment:4; ; < Segment
-EXT_PCI_ADDR ENDS
-
- ; Union type for PCI address
-PCI_ADDR UNION
- AddressValue UINT32 ? ; < Formal address
- Address EXT_PCI_ADDR {} ; < Extended address
-PCI_ADDR ENDS
-
- ; SBDFO - Segment Bus Device Function Offset
- ; 31:28 Segment (4-bits)
- ; 27:20 Bus (8-bits)
- ; 19:15 Device (5-bits)
- ; 14:12 Function(3-bits)
- ; 11:00 Offset (12-bits)
-
-
-
- ILLEGAL_SBDFO EQU 0FFFFFFFFh
-
- ; CPUID data received registers format
-CPUID_DATA STRUCT
- EAX_Reg UINT32 ? ; < CPUID instruction result in EAX
- EBX_Reg UINT32 ? ; < CPUID instruction result in EBX
- ECX_Reg UINT32 ? ; < CPUID instruction result in ECX
- EDX_Reg UINT32 ? ; < CPUID instruction result in EDX
-CPUID_DATA ENDS
-
- ; HT frequency for external callbacks
-;typedef enum {
- HT_FREQUENCY_200M EQU 0 ; < HT speed 200 for external callbacks
- HT_FREQUENCY_400M EQU 2 ; < HT speed 400 for external callbacks
- HT_FREQUENCY_600M EQU 4 ; < HT speed 600 for external callbacks
- HT_FREQUENCY_800M EQU 5 ; < HT speed 800 for external callbacks
- HT_FREQUENCY_1000M EQU 6 ; < HT speed 1000 for external callbacks
- HT_FREQUENCY_1200M EQU 7 ; < HT speed 1200 for external callbacks
- HT_FREQUENCY_1400M EQU 8 ; < HT speed 1400 for external callbacks
- HT_FREQUENCY_1600M EQU 9 ; < HT speed 1600 for external callbacks
- HT_FREQUENCY_1800M EQU 10 ; < HT speed 1800 for external callbacks
- HT_FREQUENCY_2000M EQU 11 ; < HT speed 2000 for external callbacks
- HT_FREQUENCY_2200M EQU 12 ; < HT speed 2200 for external callbacks
- HT_FREQUENCY_2400M EQU 13 ; < HT speed 2400 for external callbacks
- HT_FREQUENCY_2600M EQU 14 ; < HT speed 2600 for external callbacks
- HT_FREQUENCY_2800M EQU 17 ; < HT speed 2800 for external callbacks
- HT_FREQUENCY_3000M EQU 18 ; < HT speed 3000 for external callbacks
- HT_FREQUENCY_3200M EQU 19 ; < HT speed 3200 for external callbacks
- HT_FREQUENCY_MAX EQU 20 ; < Limit Check.
-HT_FREQUENCIES TEXTEQU <DWORD> ;} HT_FREQUENCIES;
-
-HT3_FREQUENCY_MIN EQU HT_FREQUENCY_1200M
-
-IFNDEF BIT0
- BIT0 EQU 0000000000000001h
-ENDIF
-IFNDEF BIT1
- BIT1 EQU 0000000000000002h
-ENDIF
-IFNDEF BIT2
- BIT2 EQU 0000000000000004h
-ENDIF
-IFNDEF BIT3
- BIT3 EQU 0000000000000008h
-ENDIF
-IFNDEF BIT4
- BIT4 EQU 0000000000000010h
-ENDIF
-IFNDEF BIT5
- BIT5 EQU 0000000000000020h
-ENDIF
-IFNDEF BIT6
- BIT6 EQU 0000000000000040h
-ENDIF
-IFNDEF BIT7
- BIT7 EQU 0000000000000080h
-ENDIF
-IFNDEF BIT8
- BIT8 EQU 0000000000000100h
-ENDIF
-IFNDEF BIT9
- BIT9 EQU 0000000000000200h
-ENDIF
-IFNDEF BIT10
- BIT10 EQU 0000000000000400h
-ENDIF
-IFNDEF BIT11
- BIT11 EQU 0000000000000800h
-ENDIF
-IFNDEF BIT12
- BIT12 EQU 0000000000001000h
-ENDIF
-IFNDEF BIT13
- BIT13 EQU 0000000000002000h
-ENDIF
-IFNDEF BIT14
- BIT14 EQU 0000000000004000h
-ENDIF
-IFNDEF BIT15
- BIT15 EQU 0000000000008000h
-ENDIF
-IFNDEF BIT16
- BIT16 EQU 0000000000010000h
-ENDIF
-IFNDEF BIT17
- BIT17 EQU 0000000000020000h
-ENDIF
-IFNDEF BIT18
- BIT18 EQU 0000000000040000h
-ENDIF
-IFNDEF BIT19
- BIT19 EQU 0000000000080000h
-ENDIF
-IFNDEF BIT20
- BIT20 EQU 0000000000100000h
-ENDIF
-IFNDEF BIT21
- BIT21 EQU 0000000000200000h
-ENDIF
-IFNDEF BIT22
- BIT22 EQU 0000000000400000h
-ENDIF
-IFNDEF BIT23
- BIT23 EQU 0000000000800000h
-ENDIF
-IFNDEF BIT24
- BIT24 EQU 0000000001000000h
-ENDIF
-IFNDEF BIT25
- BIT25 EQU 0000000002000000h
-ENDIF
-IFNDEF BIT26
- BIT26 EQU 0000000004000000h
-ENDIF
-IFNDEF BIT27
- BIT27 EQU 0000000008000000h
-ENDIF
-IFNDEF BIT28
- BIT28 EQU 0000000010000000h
-ENDIF
-IFNDEF BIT29
- BIT29 EQU 0000000020000000h
-ENDIF
-IFNDEF BIT30
- BIT30 EQU 0000000040000000h
-ENDIF
-IFNDEF BIT31
- BIT31 EQU 0000000080000000h
-ENDIF
-IFNDEF BIT32
- BIT32 EQU 0000000100000000h
-ENDIF
-IFNDEF BIT33
- BIT33 EQU 0000000200000000h
-ENDIF
-IFNDEF BIT34
- BIT34 EQU 0000000400000000h
-ENDIF
-IFNDEF BIT35
- BIT35 EQU 0000000800000000h
-ENDIF
-IFNDEF BIT36
- BIT36 EQU 0000001000000000h
-ENDIF
-IFNDEF BIT37
- BIT37 EQU 0000002000000000h
-ENDIF
-IFNDEF BIT38
- BIT38 EQU 0000004000000000h
-ENDIF
-IFNDEF BIT39
- BIT39 EQU 0000008000000000h
-ENDIF
-IFNDEF BIT40
- BIT40 EQU 0000010000000000h
-ENDIF
-IFNDEF BIT41
- BIT41 EQU 0000020000000000h
-ENDIF
-IFNDEF BIT42
- BIT42 EQU 0000040000000000h
-ENDIF
-IFNDEF BIT43
- BIT43 EQU 0000080000000000h
-ENDIF
-IFNDEF BIT44
- BIT44 EQU 0000100000000000h
-ENDIF
-IFNDEF BIT45
- BIT45 EQU 0000200000000000h
-ENDIF
-IFNDEF BIT46
- BIT46 EQU 0000400000000000h
-ENDIF
-IFNDEF BIT47
- BIT47 EQU 0000800000000000h
-ENDIF
-IFNDEF BIT48
- BIT48 EQU 0001000000000000h
-ENDIF
-IFNDEF BIT49
- BIT49 EQU 0002000000000000h
-ENDIF
-IFNDEF BIT50
- BIT50 EQU 0004000000000000h
-ENDIF
-IFNDEF BIT51
- BIT51 EQU 0008000000000000h
-ENDIF
-IFNDEF BIT52
- BIT52 EQU 0010000000000000h
-ENDIF
-IFNDEF BIT53
- BIT53 EQU 0020000000000000h
-ENDIF
-IFNDEF BIT54
- BIT54 EQU 0040000000000000h
-ENDIF
-IFNDEF BIT55
- BIT55 EQU 0080000000000000h
-ENDIF
-IFNDEF BIT56
- BIT56 EQU 0100000000000000h
-ENDIF
-IFNDEF BIT57
- BIT57 EQU 0200000000000000h
-ENDIF
-IFNDEF BIT58
- BIT58 EQU 0400000000000000h
-ENDIF
-IFNDEF BIT59
- BIT59 EQU 0800000000000000h
-ENDIF
-IFNDEF BIT60
- BIT60 EQU 1000000000000000h
-ENDIF
-IFNDEF BIT61
- BIT61 EQU 2000000000000000h
-ENDIF
-IFNDEF BIT62
- BIT62 EQU 4000000000000000h
-ENDIF
-IFNDEF BIT63
- BIT63 EQU 8000000000000000h
-ENDIF
-
diff --git a/src/vendorcode/amd/agesa/f14/Legacy/bridge32.inc b/src/vendorcode/amd/agesa/f14/Legacy/bridge32.inc
deleted file mode 100644
index 8685c6c077..0000000000
--- a/src/vendorcode/amd/agesa/f14/Legacy/bridge32.inc
+++ /dev/null
@@ -1,577 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * Agesa structures and definitions
-; *
-; * Contains AMD AGESA core interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 23714 $ @e \$Date: 2009-12-10 07:28:37 +0800 (Thu, 10 Dec 2009) $
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-PARAM1 textequ <[bp+8]>
-PARAM2 textequ <[bp+12]>
-PARAM3 textequ <[bp+16]>
-RETAddress textequ <[bp+4]>
-
-AMD_PRIVATE_PARAMS STRUCT
- Gate16_CS DW ? ; Segment of AMD_BRIDGE_32 and AMD_CALLOUT_16
- Gate16_SS DW ? ; RM stack segment
- Router_Seg DW ? ; Segment of oem router
- Router_Off DW ? ; Offset of oem router
-AMD_PRIVATE_PARAMS ENDS
-
-; OEM may pre-define the GDT and selector offsets. If they do not, use our defaults.
-IFNDEF AGESA_SELECTOR_GDT
- AGESA_SELECTOR_GDT EQU 00h
-ENDIF
-IFNDEF AGESA_SELECTOR_CODE16
- AGESA_SELECTOR_CODE16 EQU 08h
-ENDIF
-IFNDEF AGESA_SELECTOR_DATA16
- AGESA_SELECTOR_DATA16 EQU 10h
-ENDIF
-IFNDEF AGESA_SELECTOR_CODE32
- AGESA_SELECTOR_CODE32 EQU 18h
-ENDIF
-IFNDEF AGESA_SELECTOR_DATA32
- AGESA_SELECTOR_DATA32 EQU 20h
-ENDIF
-
-
-AMD_BRIDGE_32_GDT MACRO GDT_Name:REQ
-
- GDT_Name LABEL BYTE
- DD 000000000h, 000000000h ; NULL descriptor
- DD 00000ffffh, 000009b00h ; 16-bit code, fixed up
- DD 00000ffffh, 000009300h ; 16-bit data, fixed up
- DD 00000ffffh, 000CF9B00h ; 32-bit protected mode code
- DD 00000ffffh, 000CF9300h ; 32-bit protected mode data
- GDT_Length EQU ($-GDT_Name)
-
-ENDM
-
-;+-------------------------------------------------------------------------
-;
-; AMD_BRIDGE_32 - Execute Agesa through Pushhigh interface
-;
-; Processing:
-; The following steps are taken:
-; 1) Enter 32bit Protected Mode (PM32)
-; 2) Run AGESA code
-; 3) Restore Real Mode (RM)
-;
-; Entry:
-; [big real mode] : ds, es set to base 0 limit 4G segment
-; EDX - if not 0, provides a FAR PTR to oem router (Seg | Offset)
-; ESI - configuration block pointer
-;
-; Exit:
-; EAX - return value
-; ESI - configuration block pointer
-; ds, es, fs, gs - Set to 4GB segment limit for Big Real Mode
-;
-; Modified:
-; None
-;
-
-AMD_BRIDGE_32 MACRO GDT_Name
-
- local copyGDT
- local flushTo16PM
- local agesaReturnAddress
- local leave32bitPM
- local flush2RM
-
- push gs
- push fs
- push ebx
- push ecx
- push edi
- mov eax, esp
- push eax
- movzx esp, sp
-;
-; Do not use any locals here, BP will be changed frequently during RM->PM32->RM
-;
- pushf
- cli ; Disable interrupts during AGESA
- cld ; Need known direction flag during AGESA
-
-;
-; Save the FAR PTR input parameter
-;
- mov gs, dx ; Offset
- shr edx, 16
- mov fs, dx ; Segment
-;
-; Determine where our binary file is and get entry point
-;
- mov edx, (AMD_CONFIG_PARAMS PTR [esi]).ImageBasePtr
- add edx, (AMD_IMAGE_HEADER PTR [edx]).EntryPointAddress
-;
-; Figure out the return address we will use after calling AGESA
-; and store it in ebx until we have our stack set up properly
-;
- mov ebx, cs
- shl ebx, 4
- add ebx, OFFSET agesaReturnAddress
-;
-; Save our current RM stack AND entry EBP
-;
- push ebp
-; push esp
- push ss
-
-;
-; BEGIN --- STACK MUST BE BALANCED AT THIS POINT --- BEGIN
-;
-; Copy the GDT onto the stack for modification
-;
- mov cx, GDT_Length
- sub sp, cx
- mov bp, sp
- lea di, GDT_Name
-copyGDT:
- mov al, cs:[di]
- mov [bp], al
- inc di
- inc bp
- loop copyGDT
-;
-; Patch 16-bit code and data descriptors on stack. We will
-; fix up CS and SS for PM16 during the callout if applicable.
-;
- mov bp, sp
-
- mov eax, cs
- shl eax, 4
- mov [bp+AGESA_SELECTOR_CODE16+2], ax
- shr eax, 16
- mov [bp+AGESA_SELECTOR_CODE16+4], al
-
- mov eax, ss
- shl eax, 4
- mov [bp+AGESA_SELECTOR_DATA16+2], ax
- shr eax, 16
- mov [bp+AGESA_SELECTOR_DATA16+4], al
-;
-; Need to place Length and Address on GDT
-;
- mov eax, ss
- shl eax, 4
- add eax, esp
- push eax
- push WORD PTR (GDT_Length-1)
-;
-; Load the GDT
-;
- mov bp, sp
- lgdt FWORD PTR [bp]
-;
-; TABLE 1
-;
-; Place PRIVATE DATA on stack DIRECTLY following GDT
-; During this routine, stack data is critical. If
-; order is changed or additional added, bad things
-; will happen!
-;
-; HIGHEST PHYSICAL ADDRESS
-;
-; | ... |
-; ------------------------
-; | old RM SP |
-; | old RM SS |
-; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS + (SIZEOF GDT_LENGTH + 6 {size, address})
-; | GDT_DATA32 |
-; | ... |
-; | GDT_NULL |
-; | GDT Addr, Length |
-; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS
-; | Priv.Gate16_SS |
-; | Priv.Gate16_CS |
-; ------------------------ sp
-; ------ THEN PUSH -------
-; | Return to 16-bit CS |
-; | Return to 16-bit Off |
-; | ... |
-;
-; LOWEST PHYSICAL ADDRESS
-;
- mov edi, esp
- sub edi, SIZEOF AMD_PRIVATE_PARAMS
- mov ax, cs
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS, ax
- mov ax, ss
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS, ax
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off, gs
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg, fs
-
- mov esp, edi
-;
-; Save an address for returning to 16 bit real mode on stack,
-; we'll use it in a far ret after turning off CR0.PE so that
-; we can take our address off and force a far jump. Be sure
-; no unexpected data is on the stack after this!
-;
- mov ax, cs
- push cs
- lea ax, flush2RM
- push ax
-;
-; Convert ss:esp to "flat"
-;
-
- mov ax, sp
- push ax
- mov eax, ss
- shl eax, 4
- add eax, esp
- mov esp, eax ; Load the zero based ESP
-
-;
-; Set CR0.PE
-;
- mov eax, CR0 ; Get CPU control word 0
- or al, 01 ; Enable CPU protected mode
- mov CR0, eax ; Write back to CPU control word 0
- jmp flushTo16PM
-
-flushTo16PM:
-;
-; 16-bit protected mode
-;
- mov ax, AGESA_SELECTOR_DATA32
- mov ds, ax
- mov es, ax
- mov fs, ax
- mov gs, ax
- mov ss, ax
-;
-; Push our parameters RIGHT TO LEFT, and then return address
-;
- push esi ; AGESA configuration block pointer (data)
- push ebx ; after AGESA return offset (32PM flat) - consumed by dispatcher ret
- pushd AGESA_SELECTOR_CODE32 ; AGESA entry selector (32PM flat)
- push edx ; AGESA entry point (32PM flat)
-
- DB 066h
- retf ; <><><> Enter AGESA 32-bit code!!! <><><>
-
-agesaReturnAddress:
-;
-; Returns from the Agesa 32-bit code still PM32
-;
- DB 0EAh
- DD OFFSET leave32bitPM
- DW AGESA_SELECTOR_CODE16
-
-leave32bitPM:
-;
-; Now in 16-bit PM
-;
- add esp, 4 ; +4 to remove our config block pointer
-;
-; Eax reserve AGESA_STATUS return code, save it
-;
- mov ebx, eax
-;
-; Turn off CR0.PE, restore 64K stack limit
-;
- pop ax
- mov sp, ax
- mov ax, AGESA_SELECTOR_DATA16
- mov ss, ax
-
- mov eax, CR0
- and al, NOT 1 ; Disable protected mode
- mov CR0, eax ; Write back CR0.PE
-;
-; Jump far to enter RM, we saved this address on the stack
-; already. Hopefully stack is balanced through AGESA
-; nor were any params added by pushing them on the stack and
-; not removing them between BEGIN-END comments.
-;
- retf
-
-flush2RM:
-;
-; Set segments registers for big real mode before returning
-;
- xor ax, ax
- mov ds, ax
- mov es, ax
- mov fs, ax
- mov gs, ax
-;
-; Discard GDT, +6 for GDT pointer/size, privates
-;
- add esp, GDT_Length + 6 + SIZEOF AMD_PRIVATE_PARAMS
-;
-; Restore real mode stack and entry EBP
-;
- pop cx
-; mov esp, [esp]
- mov ss, cx
- pop ebp
-;
-; Restore AGESA_STATUS return code to eax
-;
- mov eax, ebx
-;
-; END --- STACK MUST BE BALANCED TO THIS POINT --- END
-;
-
- popf
- pop ebx
- mov esp, ebx
- pop edi
- pop ecx
- pop ebx
- pop fs
- pop gs
- ; EXIT AMD_BRIDGE_32
-ENDM
-;+-------------------------------------------------------------------------
-;
-; AMD_CALLOUT_16 - Execute Callback from Pushhigh interface
-;
-; Processing:
-; The following steps are taken:
-; 1) Enter PM16
-; 2) Setup stack, get private params
-; 3) Enter RM
-; 4) Get 3 params
-; 5) Call oemCallout OR oem router
-; 6) Enter PM32
-; 7) Return to Agesa PH
-;
-; Entry:
-; [32-bit protected mode]
-; [esp+8] Func
-; [esp+12] Data
-; [esp+16] Configuration Block
-; [esp+4] return address to Agesa
-;
-; Exit:
-; [32-bit protected mode]
-;
-; Modified:
-; None
-;
-AMD_CALLOUT_16 MACRO LocalOemCalloutRouter
-;
-; Note that we are still PM32, so MASM may work strangely
-;
-
- push bp ; Save our original SP to access params
- mov bp, sp
- push bx
- push si
- push di
- push cx
- push dx
- push di
-
- DB 066h, 0EAh
- DW OFFSET PM16Entry
- DW AGESA_SELECTOR_CODE16
-
-PM16Entry:
-;
-; PM16 CS, but still PM32 SS, as we need to access our private params
-; before we enter RM.
-;
-; Note: we are working below the stack temporarily, and and it will
-; not affect our ability to get entry params
-;
- xor ecx, ecx
- xor edx, edx
-;
-; SGDT will give us the original location of the GDT on our CAS stack.
-; We need this value because our private parameters are located just
-; below the GDT.
-;
- mov edi, esp
- sub edi, GDT_Length + 6
- sgdt FWORD PTR [edi] ; [edi] = word size, dword address
- mov edi, DWORD PTR [edi+2] ; Get the PM32 address only
- sub edi, SIZEOF AMD_PRIVATE_PARAMS + 6
-;
-; cx = code segment of this code in RM
-; dx = stack segment of CAS in RM
-; fs = code segment of oem router (save for later)
-; gs = offset of oem router (save for later)
-; fs and gs are loaded after switch to real mode because we can't
-; use them as scratch pad registers in protected mode
-;
- mov cx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS
- mov dx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS
-
- mov eax, edi ; Save edi in eax for after RM switch
- mov edi, esp ; Save our current ESP for RM
-
- movzx ebx, dx
- shl ebx, 4
- sub esp, ebx
-
-;
-; We had been accessing the stack in PM32, we will now change to PM16 so we
-; will make the stack segment 64KB limit so SP needs to be fixed made PM16
-; compatible.
-;
- mov bx, AGESA_SELECTOR_DATA16
- mov ss, bx
-
-;
-; Save the RM segment and RM offset of the jump we will need to make in
-; order to enter RM so that code in this segment is relocatable.
-;
-; BEGIN --- Don't unbalance the stack --- BEGIN
-;
- push cx
- pushw OFFSET RMEntry
-
- mov ebx, CR0
- and bl, NOT 1
- mov CR0, ebx ; CR0.PE cleared
-;
-; Far jump to clear segment descriptor cache and enter RM
-;
- retf
-
-RMEntry:
-;
-; We are in RM, setup RM stack
-;
- movzx ebx, dx ; Get RM SS in ebx
- shl ebx, 4 ; Get our stack top on entry in EBP to
- sub ebp, ebx ; access our entry parameters
- sub eax, ebx ; save copy of parameters address
- mov ss, dx ; Set stack segment
-;
-; We are going to figure out the address to use when we return
-; and have to go back into PM32 while we have access to it
-;
- movzx ebx, cx ; Get original CS in ebx
- shl ebx, 4
- add ebx, OFFSET PM32Entry
-;
-; Now we put our data, func, block params into calling convention
-; for our hook
-;
-; ECX = Func
-; EDX = Data
-; ESI = config pointer
-;
- mov ecx, PARAM1 ; Func
- mov edx, PARAM2 ; Data
- mov esi, PARAM3 ; pointer
-
- push ebx ; Save PM32 mode switch address
- push edi ; Save PM32 stack pointer
- pushf
-;
-; Get Router Function Address
-;
- mov edi, eax
- mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg
- mov fs, ax
- mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off
- mov gs, ax
-
- mov eax, AGESA_UNSUPPORTED ; Default return value
-;
-; If AMD_BRIDGE_32 EDX == 0 call oemCallout
-; otherwise call FAR PTR EDX
-;
-; Critical:
-; sp+2 - EDI aka PM32 stack address
-; sp+4 - address of PM32Entry in PM32
-;
- mov bx, fs
- shl ebx, 16
- mov bx, gs
-
- .if (ebx == 0)
- call LocalOemCalloutRouter
- .else
-;
-; Make far call to Router function
-;
- push cs
- push offset CalloutReturn
- push ebx
- retf
-CalloutReturn:
- .endif
-;
-; Restore PM32 esp from RM stack
-;
- popf
- pop edi ; Our PM32 stack pointer
- pop edx ; Our PM32 mode switch address
-
- mov ebx, CR0
- or bl, 1 ; CR0.PE set
- mov CR0, ebx
-
- mov ebx, AGESA_SELECTOR_DATA32
- pushd AGESA_SELECTOR_CODE32 ; PM32 selector
- push edx ; PM32 entry point
-
- DB 066h
- retf ; Far jump to enter PM32
-
-PM32Entry:
-;
-; END --- Don't unbalance the stack --- END
-; We are now PM32, so remember MASM is assembling in 16-bit again
-;
- mov ss, bx
- mov ds, bx
- mov es, bx
- mov fs, bx
- mov gs, bx
-
- mov sp, di
- pop di
- pop dx
- pop cx
- pop di
- pop si
- pop bx
- pop bp
- ; EXIT AMD_CALLOUT_16
-ENDM
diff --git a/src/vendorcode/amd/agesa/f14/Lib/IA32/amdlib32.asm b/src/vendorcode/amd/agesa/f14/Lib/IA32/amdlib32.asm
deleted file mode 100644
index ff0f85b0ba..0000000000
--- a/src/vendorcode/amd/agesa/f14/Lib/IA32/amdlib32.asm
+++ /dev/null
@@ -1,151 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa library 32bit
-; *
-; * Contains AMD AGESA Library
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Lib
-; * @e \$Revision: 17071 $ @e \$Date: 2009-07-30 10:13:11 -0700 (Thu, 30 Jul 2009) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-.586p
-.xmm
-.model flat,C
-ASSUME FS:NOTHING
-.code
-
-;---------------------------------------------------------------------------
-;
-; _mm_clflush_fs - execute clflush instruction for address fs:address32
-; this lets clflush operate beyond 4GB in 32-bit mode
-;
-; void _mm_clflush_fs (void *address32);
-;
-
-_mm_clflush_fs proc public
-
-
-
-
-
-
- mov eax, [esp+8]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- clflush fs:[eax]
-
-
-
- ret
-_mm_clflush_fs ENDP
-
-
-;---------------------------------------------------------------------------
-;
-; _mm_stream_si128_fs - execute movntdq instruction for address fs:address32
-; this lets movntdq operate beyond 4GB in 32-bit mode
-;
-; void _mm_stream_si128_fs (void *dest, void *data)
-;
-_mm_stream_si128_fs proc public
- push esi
- mov esi, [esp+12]
- movdqa xmm0, [esi]
- mov esi, [esp+8]
- movntdq fs:[esi], xmm0
-
-
-
-
-
-
-
- pop esi
- ret
-
-
-
-
-_mm_stream_si128_fs ENDP
-
-
-
-
-;---------------------------------------------------------------------------
-
-
-END
diff --git a/src/vendorcode/amd/agesa/f14/Lib/IA32/ms_shift.asm b/src/vendorcode/amd/agesa/f14/Lib/IA32/ms_shift.asm
deleted file mode 100644
index 3eb51134d5..0000000000
--- a/src/vendorcode/amd/agesa/f14/Lib/IA32/ms_shift.asm
+++ /dev/null
@@ -1,110 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa library 32bit
-; *
-; * Contains AMD AGESA Library
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Lib
-; * @e \$Revision: 9201 $ @e \$Date: 2008-10-31 03:36:20 -0500 (Fri, 31 Oct 2008) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-.586p
-.model flat
-ASSUME FS:NOTHING
-.code
-;/*++
-;
-;Routine Description:
-;
-; Shifts a UINT64 to the right.
-;
-;Arguments:
-;
-; EDX:EAX - UINT64 value to be shifted
-; CL - Shift count
-;
-;Returns:
-;
-; EDX:EAX - shifted value
-;
-;--*/
-_aullshr PROC NEAR C PUBLIC
- .if (cl < 64)
- .if (cl >= 32)
- sub cl, 32
- mov eax, edx
- xor edx, edx
- .endif
- shrd eax, edx, cl
- shr edx, cl
- .else
- xor eax, eax
- xor edx, edx
- .endif
- ret
-_aullshr ENDP
-
-;/*++
-;
-;Routine Description:
-;
-; Shifts a UINT64 to the left.
-;
-;Arguments:
-;
-; EDX:EAX - UINT64 value to be shifted
-; CL - Shift count
-;
-;Returns:
-;
-; EDX:EAX - shifted value
-;
-;--*/
-_allshl PROC NEAR C PUBLIC USES CX
- .if (cl < 64)
- .if (cl >= 32)
- sub cl, 32
- mov edx, eax
- xor eax, eax
- .endif
- shld edx, eax, cl
- shl eax, cl
- .else
- xor eax, eax
- xor edx, edx
- .endif
- ret
-_allshl ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f14/Lib/IA32/msmemcpy.asm b/src/vendorcode/amd/agesa/f14/Lib/IA32/msmemcpy.asm
deleted file mode 100644
index b74818c3d0..0000000000
--- a/src/vendorcode/amd/agesa/f14/Lib/IA32/msmemcpy.asm
+++ /dev/null
@@ -1,84 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa library 32bit
-; *
-; * Contains AMD AGESA Library
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Lib
-; * @e \$Revision: 9201 $ @e \$Date: 2008-10-31 03:36:20 -0500 (Fri, 31 Oct 2008) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-.586p
-.model flat
-ASSUME FS:NOTHING
-.code
-; void *memcpy( void *dest, void *src, size_t count );
-;
-; Copy count bytes from src to dest, returning dest.
-; ("c" is not legal as an assembly parameter name, replaced with value.)
-; Assume ES is set appropriately, 32 bit flat.
-;
-public memcpy
-memcpy PROC NEAR C PUBLIC USES ECX EDI ESI dest:DWORD, src:DWORD, count:DWORD
- pushf
- cld ; We will increment through *dest
- mov edi, dest
- mov esi, src
- mov ecx, count
- rep movsb
- mov eax, dest
- popf
- ret
-memcpy ENDP
-
-; void *memset( void *dest, int c, size_t count );
-;
-; At dest, set count bytes to byte value, returning dest.
-; ("c" is not legal as an assembly parameter name, replaced with value.)
-; Assume ES is set appropriately, 32 bit flat.
-;
-public memset
-memset PROC NEAR C PUBLIC USES ECX EDI dest:DWORD, value:DWORD, count:DWORD
- pushf
- cld ; We will increment through *dest
- mov edi, dest
- mov eax, value
- mov ecx, count
- rep stosb
- mov eax, edi
- popf
- ret
-memset ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f14/Lib/x64/amdlib64.asm b/src/vendorcode/amd/agesa/f14/Lib/x64/amdlib64.asm
deleted file mode 100644
index abc1179903..0000000000
--- a/src/vendorcode/amd/agesa/f14/Lib/x64/amdlib64.asm
+++ /dev/null
@@ -1,591 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa library 64bit
-; *
-; * Contains AMD AGESA Library
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Lib
-; * @e \$Revision: 17071 $ @e \$Date: 2009-07-30 10:13:11 -0700 (Thu, 30 Jul 2009) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-.code
-;/*++
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write IO byte
-; *
-; * @param[in] CX IO port address
-; * @param[in] DL IO port Value
-; */
-
-PUBLIC WriteIo8
-WriteIo8 PROC
- mov al, dl
- mov dx, cx
- out dx, al
- ret
-WriteIo8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write IO word
-; *
-; * @param[in] CX IO port address
-; * @param[in] DX IO port Value
-; */
-PUBLIC WriteIo16
-WriteIo16 PROC
- mov ax, dx
- mov dx, cx
- out dx, ax
- ret
-WriteIo16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write IO dword
-; *
-; * @param[in] CX IO port address
-; * @param[in] EDX IO port Value
-; */
-
-PUBLIC WriteIo32
-WriteIo32 PROC
- mov eax, edx
- mov dx, cx
- out dx, eax
- ret
-WriteIo32 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read IO byte
-; *
-; * @param[in] CX IO port address
-; * @retval AL IO port Value
-; */
-PUBLIC ReadIo8
-ReadIo8 PROC
- mov dx, cx
- in al, dx
- ret
-ReadIo8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read IO word
-; *
-; * @param[in] CX IO port address
-; * @retval AX IO port Value
-; */
-PUBLIC ReadIo16
-ReadIo16 PROC
- mov dx, cx
- in ax, dx
- ret
-ReadIo16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read IO dword
-; *
-; * @param[in] CX IO port address
-; * @retval EAX IO port Value
-; */
-PUBLIC ReadIo32
-ReadIo32 PROC
- mov dx, cx
- in eax, dx
- ret
-ReadIo32 ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read MSR
-; *
-; * @param[in] RCX MSR Address
-; * @param[in] RDX Pointer to data
-; * @param[in] R8D ConfigPtr (Optional)
-; */
-PUBLIC LibAmdMsrRead
-LibAmdMsrRead PROC
- push rsi
- mov rsi, rdx
- rdmsr
- mov [rsi], eax
- mov [rsi+4], edx
- pop rsi
- ret
-LibAmdMsrRead ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write MSR
-; *
-; * @param[in] RCX MSR Address
-; * @param[in] RDX Pointer to data
-; * @param[in] R8D ConfigPtr (Optional)
-; */
-PUBLIC LibAmdMsrWrite
-LibAmdMsrWrite PROC
- push rsi
- mov rsi, rdx
- mov eax, [rsi]
- and rax, 0ffffffffh
- mov edx, [rsi+4]
- and rdx, 0ffffffffh
- wrmsr
- pop rsi
- ret
-LibAmdMsrWrite ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read CPUID
-; *
-; * @param[in] RCX CPUID function
-; * @param[in] RDX Pointer to CPUID_DATA to save cpuid data
-; * @param[in] R8D ConfigPtr (Optional)
-; */
-PUBLIC LibAmdCpuidRead
-LibAmdCpuidRead PROC
-
- push rbx
- push rsi
- mov rsi, rdx
- mov rax, rcx
- cpuid
- mov [rsi], eax
- mov [rsi+4], ebx
- mov [rsi+8], ecx
- mov [rsi+12],edx
- pop rsi
- pop rbx
- ret
-
-LibAmdCpuidRead ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read TSC
-; *
-; *
-; * @retval RAX Time stamp counter value
-; */
-
-PUBLIC ReadTSC
-ReadTSC PROC
- rdtsc
- and rax, 0ffffffffh
- shl rdx, 32
- or rax, rdx
- ret
-ReadTSC ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read memory/MMIO byte
-; *
-; * @param[in] RCX - Memory Address
-; * @retval Memory byte at given address
-; */
-PUBLIC Read64Mem8
-Read64Mem8 PROC
-
- xor rax, rax
- mov al, [rcx]
- ret
-
-Read64Mem8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read memory/MMIO word
-; *
-; * @param[in] RCX - Memory Address
-; * @retval Memory word at given address
-; */
-PUBLIC Read64Mem16
-Read64Mem16 PROC
-
- xor rax, rax
- mov ax, [rcx]
- ret
-
-Read64Mem16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read memory/MMIO dword
-; *
-; * @param[in] RCX - Memory Address
-; * @retval Memory dword at given address
-; */
-PUBLIC Read64Mem32
-Read64Mem32 PROC
-
- xor rax, rax
- mov eax, [rcx]
- ret
-
-Read64Mem32 ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write memory/MMIO byte
-; *
-; * @param[in] RCX Memory Address
-; * @param[in] DL Value to write
-; */
-
-PUBLIC Write64Mem8
-Write64Mem8 PROC
-
- xor rax, rax
- mov rax, rdx
- mov [rcx], al
- ret
-
-Write64Mem8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write memory/MMIO word
-; *
-; * @param[in] RCX Memory Address
-; * @param[in] DX Value to write
-; */
-PUBLIC Write64Mem16
-Write64Mem16 PROC
-
- xor rax, rax
- mov rax, rdx
- mov [rcx], ax
- ret
-
-Write64Mem16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write memory/MMIO dword
-; *
-; * @param[in] RCX Memory Address
-; * @param[in] EDX Value to write
-; */
-PUBLIC Write64Mem32
-Write64Mem32 PROC
-
- xor rax, rax
- mov rax, rdx
- mov [rcx], eax
- ret
-
-Write64Mem32 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read various CPU registers
-; *
-; * @param[in] CL Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
-; * @param[in] RDX Pointer to value
-; */
-
-PUBLIC LibAmdReadCpuReg
-LibAmdReadCpuReg PROC
-
- push rax
- xor rax, rax
-Reg00h:
- cmp cl, 00h
- jne Reg04h
- mov rax, cr0
- jmp RegRead
-Reg04h:
- cmp cl, 04h
- jne Reg10h
- mov rax, cr4
- jmp RegRead
-Reg10h:
- cmp cl, 10h
- jne Reg11h
- mov rax, dr0
- jmp RegRead
-Reg11h:
- cmp cl, 11h
- jne Reg12h
- mov rax, dr1
- jmp RegRead
-Reg12h:
- cmp cl, 12h
- jne Reg13h
- mov rax, dr2
- jmp RegRead
-Reg13h:
- cmp cl, 13h
- jne Reg17h
- mov rax, dr3
- jmp RegRead
-Reg17h:
- cmp cl, 17h
- jne RegRead
- mov rax, dr7
-RegRead:
- mov [rdx], eax
- pop rax
- ret
-LibAmdReadCpuReg ENDP
-
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write various CPU registers
-; *
-; * @param[in] CL Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
-; * @param[in] RDX Value to write
-; */
-
-PUBLIC LibAmdWriteCpuReg
-LibAmdWriteCpuReg PROC
-
- push rax
-Reg00h:
- cmp cl, 00h
- jne Reg04h
- mov rax, cr0
- mov eax, edx
- mov cr0, rax
- jmp Done
-Reg04h:
- cmp cl, 04h
- jne Reg10h
- mov rax, cr4
- mov eax, edx
- mov cr4, rax
- jmp Done
-Reg10h:
- cmp cl, 10h
- jne Reg11h
- mov rax, dr0
- mov eax, edx
- mov dr0, rax
- jmp Done
-Reg11h:
- cmp cl, 11h
- jne Reg12h
- mov rax, dr1
- mov eax, edx
- mov dr1, rax
- jmp Done
-Reg12h:
- cmp cl, 12h
- jne Reg13h
- mov rax, dr2
- mov eax, edx
- mov dr2, rax
- jmp Done
-Reg13h:
- cmp cl, 13h
- jne Reg17h
- mov rax, dr3
- mov eax, edx
- mov dr3, rax
- jmp Done
-Reg17h:
- cmp cl, 17h
- jne Done
- mov rax, dr7
- mov eax, edx
- mov dr7, rax
-Done:
- pop rax
- ret
-LibAmdWriteCpuReg ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write back invalidate caches using wbinvd.
-; *
-; *
-; *
-; */
-
-PUBLIC LibAmdWriteBackInvalidateCache
-LibAmdWriteBackInvalidateCache PROC
- wbinvd
- ret
-LibAmdWriteBackInvalidateCache ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Stop CPU
-; *
-; *
-; *
-; */
-
-PUBLIC StopHere
-StopHere PROC
-@@:
- jmp short @b
-StopHere ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Enter debugger on SimNow
-; *
-; *
-; *
-; */
-PUBLIC LibAmdSimNowEnterDebugger
-LibAmdSimNowEnterDebugger PROC
- pushfq
- mov rax, 0BACCD00Bh ; Backdoor in SimNow
- mov rbx, 2 ; Select breakpoint feature
- cpuid
-@@:
- jmp short @b
- popfq
- ret
-LibAmdSimNowEnterDebugger ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * IDS IO port write
-; *
-; * @param[in] ECX IO Port Address
-; * @param[in] EDX Value to write
-; * @param[in] R8D IDS flags
-; *
-; */
-
-PUBLIC IdsOutPort
-IdsOutPort PROC
- push rbx
- push rax
-
- mov ebx, r8d
- mov eax, edx
- mov edx, ecx
- out dx, eax
-
- pop rax
- pop rbx
- ret
-IdsOutPort ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Force breakpoint on HDT
-; *
-; *
-; */
-PUBLIC LibAmdHDTBreakPoint
-LibAmdHDTBreakPoint PROC
-
- push rbx
-
- mov rcx, 0C001100Ah ;bit 0 = HDT redirect
- mov rdi, 09C5A203Ah ;Password
- rdmsr
- and rax, 0ffffffffh
- or rax, 1
-
- wrmsr
-
- mov rax, 0B2h ;Marker = B2
- db 0F1h ;ICEBP
-
- pop rbx
- ret
-
-LibAmdHDTBreakPoint ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Find the most right hand side non-zero bit with
-; *
-; * @param[in] ECX Value
-; */
-PUBLIC LibAmdBitScanForward
-LibAmdBitScanForward PROC
- bsf eax, ecx
- jnz nonZeroSource
- mov al,32
-nonZeroSource:
- ret
-LibAmdBitScanForward ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Find the most left hand side non-zero bit.
-; *
-; * @param[in] ECX Value
-; */
-PUBLIC LibAmdBitScanReverse
-LibAmdBitScanReverse PROC
- bsr eax, ecx
- jnz nonZeroSource
- mov al,0FFh
-nonZeroSource:
- ret
-LibAmdBitScanReverse ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Flush specified number of cache line
-; *
-; * @param[in] RCX Physical address to be flushed
-; * @param[in] DL number of cachelines to be flushed
-; */
-PUBLIC LibAmdCLFlush
-LibAmdCLFlush PROC
- push rax
- mov rax, rcx
- movzx rcx, dl
- @@:
- mfence
- clflush [rax]
- mfence
- add rax,64
- loop @B
- pop rax
- ret
-LibAmdCLFlush ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevD32.asm b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevD32.asm
deleted file mode 100644
index 4112659226..0000000000
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevD32.asm
+++ /dev/null
@@ -1,113 +0,0 @@
-;/**
-; * @file
-; *
-; * AGESA Family 10h Revision D support routines.
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: CPU/F10
-; * @e \$Revision: 23714 $ @e \$Date: 2009-12-10 07:28:37 +0800 (Thu, 10 Dec 2009) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- .XLIST
- .LIST
-
- .586P
-
-;===============================================
-;===============================================
-;==
-;== M E M O R Y P R E S E N T S E G M E N T
-;==
-;===============================================
-;===============================================
- .MODEL flat
- .CODE
-
-;======================================================================
-; F10RevDProbeFilterCritical: Performs critical sequence for probe
-; filter initialization.
-;
-; In:
-; PciAddress Full PCI address of the node to init
-; PciRegister Current value of F3x1D4
-;
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-F10RevDProbeFilterCritical PROC NEAR C PUBLIC USES EAX ECX EDX, PciAddress:DWORD, PciRegister:DWORD
-
- mov ecx, 0C001001Fh
- rdmsr
- push eax
- push ecx
- push edx
- or dh, 40h
- wrmsr
-
- mov eax, 810003D4h
-
- mov ecx, PciRegister
- mov edx, PciAddress
- shr edx, 4
- and dh, 0F8h
- or ah, dh
-
- or cl, 2
- db 0Fh, 0AEh, 0F0h ; MFENCE
-
- mov dx, 0CF8h ; Set Reg Config Space
- db 0Fh, 0AEh, 0F0h ; MFENCE
-
- out dx, eax
- db 0Fh, 0AEh, 0F0h ; MFENCE
-
- mov dl, 0FCh ; Set DX to Pci Config Data
- mov eax, ecx ;Set config Reg data
- db 0Fh, 0AEh, 0F0h ; MFENCE
-
- out dx, eax ; move data to return position
- db 0Fh, 0AEh, 0F0h ; MFENCE
-
- pop edx
- pop ecx
- pop eax
- wrmsr
- ret
-
-F10RevDProbeFilterCritical ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevD64.asm b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevD64.asm
deleted file mode 100644
index 4353190451..0000000000
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevD64.asm
+++ /dev/null
@@ -1,127 +0,0 @@
-;/**
-; * @file
-; *
-; * AGESA Family 10h Revision D support routines.
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: CPU/F10
-; * @e \$Revision: 23714 $ @e \$Date: 2009-12-10 07:28:37 +0800 (Thu, 10 Dec 2009) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- .XLIST
- .LIST
-
-;===============================================
-;===============================================
-;==
-;== M E M O R Y P R E S E N T S E G M E N T
-;==
-;===============================================
-;===============================================
- .CODE
-
-;======================================================================
-; F10RevDProbeFilterCritical: Performs critical sequence for probe
-; filter initialization.
-;
-; In:
-; PciAddress Full PCI address of the node to init
-; PciRegister Current value of F3x1D4
-;
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-PUBLIC F10RevDProbeFilterCritical
-F10RevDProbeFilterCritical PROC
-
- push rax
- push rcx
- push rdx
- push rsi
- push rdi
-
- mov esi, ecx
- mov edi, edx
-
- mov ecx, 0C001001Fh
- rdmsr
- push rax
- push rcx
- push rdx
- or dh, 40h
- wrmsr
-
- mov eax, 810003D4h
-
- mov ecx, edi
- mov edx, esi
-
- shr edx, 4
- and dh, 0F8h
- or ah, dh
-
- or cl, 2
- mfence
-
- mov dx, 0CF8h ; Set Reg Config Space
- mfence
-
- out dx, eax
- mfence
-
- mov dl, 0FCh ; Set DX to Pci Config Data
- mov eax, ecx ;Set config Reg data
- mfence
-
- out dx, eax ; move data to return position
- mfence
-
- pop rdx
- pop rcx
- pop rax
- wrmsr
-
- pop rdi
- pop rsi
- pop rdx
- pop rcx
- pop rax
- ret
-
-F10RevDProbeFilterCritical ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm
deleted file mode 100644
index de5201d1b1..0000000000
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm
+++ /dev/null
@@ -1,345 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa pre-memory miscellaneous support, including ap halt loop.
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: CPU
-; * @e \$Revision: 35270 $ @e \$Date: 2010-07-20 00:02:41 +0800 (Tue, 20 Jul 2010) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- .XLIST
- INCLUDE agesa.inc
- INCLUDE cpcarmac.inc
- .LIST
-
- .586P
-
-;===============================================
-;===============================================
-;==
-;== M E M O R Y A B S E N T S E G M E N T
-;==
-;===============================================
-;===============================================
- .MODEL flat
- .CODE
-;======================================================================
-; ExecuteFinalHltInstruction: Disables the stack and performs
-; a hlt instruction on an AP.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; eax, ebx, ecx, edx, esp
-;
-;======================================================================
-PUBLIC ExecuteFinalHltInstruction
-ExecuteFinalHltInstruction PROC NEAR C USES ESI EDI HaltFlags:DWORD, ApMtrrSettingList:PTR, StandardHeader:PTR
-
- mov esi, StandardHeader ; The code must reference all parameters to avoid a build warning
- mov esi, HaltFlags
- mov edi, ApMtrrSettingList
- ; Do these special steps in case if the core is part of a compute unit
- ; Note: The following bits are family specific flags, that gets set during build time,
- ; and indicates things like "family cache control methodology", etc.
- ; esi bit0 = 0 -> not a Primary core
- ; esi bit0 = 1 -> Primary core
- ; esi bit1 = 0 -> Cache disable
- ; esi bit1 = 1 -> Cache enable
- .if (esi & 2h)
- ; Set CombineCr0Cd bit
- mov ecx, CU_CFG3
- _RDMSR
- bts edx, (COMBINE_CR0_CD - 32)
- _WRMSR
- ; Clear the CR0.CD bit
- mov eax, CR0 ; Make sure cache is enabled for all APs
- btr eax, CR0_CD
- btr eax, CR0_NW
- mov CR0, eax ; Write back to CR0
- .else
- mov eax, CR0 ; Make sure cache is disabled for all APs
- bts eax, CR0_CD ; Disable cache
- bts eax, CR0_NW
- mov CR0, eax ; Write back to CR0
- .endif
-
- .if (esi & 1h)
- ; This core is a primary core and needs to do all the MTRRs, including shared MTRRs.
- mov esi, edi ; Get ApMtrrSettingList
-
- ; Configure the MTRRs on the AP so
- ; when it runs remote code it will execute
- ; out of RAM instead of ROM.
-
- ; Disable MTRRs and turn on modification enable bit
- mov ecx, MTRR_SYS_CFG
- _RDMSR
- btr eax, MTRR_VAR_DRAM_EN ; Disable
- bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable
- btr eax, MTRR_FIX_DRAM_EN ; Disable
- bts eax, SYS_UC_LOCK_EN
- _WRMSR
-
- ; Setup default values for Fixed-Sized MTRRs
- ; Set 7FFFh-00000h as WB
- mov ecx, AMD_AP_MTRR_FIX64k_00000
- mov eax, 1E1E1E1Eh
- mov edx, eax
- _WRMSR
-
- ; Set 9FFFFh-80000h also as WB
- mov ecx, AMD_AP_MTRR_FIX16k_80000
- _WRMSR
-
- ; Set BFFFFh-A0000h as Uncacheable Memory-mapped IO
- mov ecx, AMD_AP_MTRR_FIX16k_A0000
- xor eax, eax
- xor edx, edx
- _WRMSR
-
- ; Set DFFFFh-C0000h as Uncacheable Memory-mapped IO
- xor eax, eax
- xor edx, edx
- mov ecx, AMD_AP_MTRR_FIX4k_C0000
-
-CDLoop:
- _WRMSR
- inc ecx
- cmp ecx, AMD_AP_MTRR_FIX4k_D8000
- jbe CDLoop
-
- ; Set FFFFFh-E0000h as Uncacheable Memory
- mov eax, 18181818h
- mov edx, eax
-
- mov ecx, AMD_AP_MTRR_FIX4k_E0000
-
-EFLoop:
- _WRMSR
- inc ecx
- cmp ecx, AMD_AP_MTRR_FIX4k_F8000
- jbe EFLoop
-
- ; If IBV provided settings for Fixed-Sized MTRRs,
- ; overwrite the default settings.
- .if ((esi != 0) && (esi != 0FFFFFFFFh))
- mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
- ; While we are not at the end of the list
- .while (ecx != CPU_LIST_TERMINAL)
- ; Ensure that the MSR address is valid for Fixed-Sized MTRRs
- .if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \
- (ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || (ecx == AMD_AP_MTRR_FIX16k_A0000))
- mov eax, dword ptr (AP_MTRR_SETTINGS ptr [esi]).MsrData
- mov edx, dword ptr (AP_MTRR_SETTINGS ptr [esi+4]).MsrData
- _WRMSR
- .endif
- add esi, sizeof (AP_MTRR_SETTINGS)
- mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
- .endw
- .endif
-
- ; restore variable MTRR6 and MTRR7 to default states
- mov ecx, AMD_MTRR_VARIABLE_BASE6 ; clear MTRRPhysBase6 MTRRPhysMask6
- xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7
- xor edx, edx
- .while (cl < 010h)
- _WRMSR
- inc cl
- .endw
-
- ; Enable fixed-range and variable-range MTRRs
- mov ecx, AMD_MTRR_DEFTYPE
- _RDMSR
- bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn
- bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn
- _WRMSR
-
- ; Enable Top-of-Memory setting
- ; Enable use of RdMem/WrMem bits attributes
- mov ecx, MTRR_SYS_CFG
- _RDMSR
- bts eax, MTRR_VAR_DRAM_EN ; Enable
- btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable
- bts eax, MTRR_FIX_DRAM_EN ; Enable
- _WRMSR
-
- mov esi, (1 SHL FLAG_IS_PRIMARY)
- .else ; end if primary core
- xor esi, esi
- .endif
- ; Make sure not to touch any Shared MSR from this point on
-
- AMD_DISABLE_STACK_FAMILY_HOOK
-
- xor eax, eax
-
-@@:
- cli
- hlt
- jmp @B ;ExecuteHltInstruction
- ret
-ExecuteFinalHltInstruction ENDP
-
-;======================================================================
-; ExecuteHltInstruction: Performs a hlt instruction.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; eax, ebx, ecx, edx, esp
-;
-;======================================================================
-PUBLIC ExecuteHltInstruction
-ExecuteHltInstruction PROC NEAR C
- cli
- hlt
- ret
-ExecuteHltInstruction ENDP
-
-;======================================================================
-; NmiHandler: Simply performs an IRET.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-PUBLIC NmiHandler
-NmiHandler PROC NEAR C
- iretd
-NmiHandler ENDP
-
-;======================================================================
-; GetCsSelector: Returns the current protected mode CS selector.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-PUBLIC GetCsSelector
-GetCsSelector PROC NEAR C, CsSelector:PTR
- push ax
- push ebx
-
- call FarCallGetCs
- mov ebx, CsSelector
- mov [ebx], ax
- pop ebx
- pop ax
- ret
-GetCsSelector ENDP
-
-;======================================================================
-; FarCallGetCs:
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; none
-;
-; WARNING: This routine has a mirror routine in the PREMEM segment.
-; These two routines MUST be sync'd for content.
-;======================================================================
-FarCallGetCs PROC FAR PRIVATE
-
- mov ax, ss:[esp + 4]
- retf
-
-FarCallGetCs ENDP
-
-;======================================================================
-; SetIdtr:
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; none
-;
-; WARNING: This routine has a mirror routine in the PREMEM segment.
-; These two routines MUST be sync'd for content.
-;======================================================================
-PUBLIC SetIdtr
-SetIdtr PROC NEAR C USES EBX, IdtPtr:PTR
- mov ebx, IdtPtr
- lidt fword ptr ss:[ebx]
- ret
-SetIdtr ENDP
-
-;======================================================================
-; ExecuteWbinvdInstruction: Performs a wbinvd instruction.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-PUBLIC ExecuteWbinvdInstruction
-ExecuteWbinvdInstruction PROC NEAR C
- wbinvd ; Write back the cache tag RAMs
- ret
-ExecuteWbinvdInstruction ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt64.asm b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt64.asm
deleted file mode 100644
index f1411fa21b..0000000000
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt64.asm
+++ /dev/null
@@ -1,157 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa pre-memory miscellaneous support, including ap halt loop.
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: CPU
-; * @e \$Revision: 10071 $ @e \$Date: 2008-12-16 18:03:04 -0600 (Tue, 16 Dec 2008) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- text SEGMENT
-
-
-;======================================================================
-; ExecuteFinalHltInstruction: Performs a hlt instruction.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; eax, ebx, ecx, edx, esp
-;
-;======================================================================
-ExecuteFinalHltInstruction PROC PUBLIC
-@@:
- cli
- hlt
- jmp @B ;ExecuteHltInstruction
-ExecuteFinalHltInstruction ENDP
-
-;======================================================================
-; ExecuteHltInstruction: Performs a hlt instruction.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; eax, ebx, ecx, edx, esp
-;
-;======================================================================
-ExecuteHltInstruction PROC PUBLIC
- cli
- hlt
- ret
-ExecuteHltInstruction ENDP
-
-;======================================================================
-; NmiHandler: Simply performs an IRET.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-NmiHandler PROC PUBLIC
- iretq
-NmiHandler ENDP
-
-;======================================================================
-; GetCsSelector: Returns the current protected mode CS selector.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-GetCsSelector PROC PUBLIC
- ; This stub function is here to avoid compilation errors.
- ; At this time, there is no need to provide a 64 bit function.
- ret
-GetCsSelector ENDP
-
-;======================================================================
-; SetIdtr:
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; none
-;
-; WARNING: This routine has a mirror routine in the PREMEM segment.
-; These two routines MUST be sync'd for content.
-;======================================================================
-SetIdtr PROC PUBLIC
- ; This stub function is here to avoid compilation errors.
- ; At this time, there is no need to provide a 64 bit function.
- ret
-SetIdtr ENDP
-
-;======================================================================
-; ExecuteWbinvdInstruction: Performs a wbinvd instruction.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-ExecuteWbinvdInstruction PROC PUBLIC
- wbinvd ; Write back the cache tag RAMs
- ret
-ExecuteWbinvdInstruction ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.asm b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.asm
deleted file mode 100644
index 63c85b94aa..0000000000
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.asm
+++ /dev/null
@@ -1,497 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; $Workfile:: mu.asm $ $Revision:: 274#$ $Date: 2010-03-04 06:16:56 +0800 (Thu, 04 Mar 2010) $
-; Description: Main memory controller system configuration for AGESA
-;
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-;============================================================================
-
-
- .XLIST
- .LIST
-
- .686p
- .MODEL FLAT
- .CODE
- ASSUME FS: NOTHING
-
-; Define the calling convention used for the C library modules
-;@attention - This should be in a central include file
-CALLCONV EQU NEAR C
-
-
-;===============================================================================
-;memUOutPort:
-;
-; Do a 32 Bit IO Out operation using edx.
-; NOTE: This function will be obsolete in the future.
-;
-; In: Port - port number
-; Value - value to be written
-;
-; Out:
-;
-; All registers preserved.
-;===============================================================================
-MemUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD
- pushad
- mov edx,Port
- mov eax,Value
- out dx,al
- popad
- ret
-MemUOutPort ENDP
-
-
-;----------------------------------------------------------------------------
-; _SFENCE();
-;
-_SFENCE macro
- db 0Fh,0AEh,0F8h
- endm
-
-;----------------------------------------------------------------------------
-; _MFENCE();
-;
-_MFENCE macro
- db 0Fh,0AEh,0F0h
- endm
-
-;----------------------------------------------------------------------------
-; _EXECFENCE();
-;
-_EXECFENCE macro
- out 0EDh,al ;prevent speculative execution of following instructions
- endm
-
-;===============================================================================
-;MemUWriteCachelines:
-; Write a test pattern to DRAM
-;
-; In: Pattern - pointer to the write pattern
-; Address - Physical address to be read
-; ClCount - number of cachelines to be read
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUWriteCachelines PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD, ClCount:WORD
- pushad
- push ds
-
- mov eax,Address
- push ss
- pop ds
- xor edx,edx
- mov edx, DWORD PTR Pattern
- mov esi,edx
- mov edx,16
- _EXECFENCE
- xor ecx, ecx
- mov cx,ClCount
- shl ecx,2
- @@:
- db 66h, 0Fh,6Fh,06 ;MOVDQA xmm0,[esi]
- db 64h, 66h, 0Fh,0E7h,00 ;MOVNTDQ fs:[eax],xmm0 (xmm0 is 128 bits)
- add eax,edx
- add esi,edx
- loop @B
-
- pop ds
- popad
- ret
-MemUWriteCachelines ENDP
-
-;===============================================================================
-;MemUReadCachelines:
-;
-; Read a pattern of 72 bit times (per DQ), to test dram functionality. The
-;pattern is a stress pattern which exercises both ISI and crosstalk. The number
-;of cache lines to fill is dependent on DCT width mode and burstlength.
-;
-; In: Buffer - pointer to a buffer where read data will be stored
-; Address - Physical address to be read
-; ClCount - number of cachelines to be read
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUReadCachelines PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
-LOCAL Count:BYTE
- pushad
- ; First, issue continuous dummy reads to fill up the cache
- mov eax,Address
- .if (ClCount > 18)
- mov cx,ClCount
- shr cx,4
- mov Count,cl
- .while (Count != 0)
- push eax
- mov edi,eax
- add edi,128 ;bias value (to account for signed displacement)
- ;clflush opcode=0F AE /7
- mov esi,edi
- mov ebx,esi
- mov ecx,esi
- mov edx,esi
- add edi,4*64 ;TestAddr+4 cache lines
- add ebx,8*64 ;TestAddr+8 cache lines
- add ecx,12*64 ;TestAddr+12 cache lines
- add edx,16*64 ;TestAddr+16 cache lines
- sub edx,128
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- mov eax,fs:[edi] ;TestAddr+6 cache lines
- _MFENCE
- mov eax,fs:[edi+64] ;TestAddr+7 cache lines
- _MFENCE
- mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
- _MFENCE
- mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
- _MFENCE
- mov eax,fs:[ebx] ;TestAddr+10 cache lines
- _MFENCE
- mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
- _MFENCE
- mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
- _MFENCE
- mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
- _MFENCE
- mov eax,fs:[ecx] ;TestAddr+14 cache lines
- _MFENCE
- mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
- _MFENCE
- pop eax
- add eax,(16*64) ;Next 16CL
- dec Count
- .endw
- .else
- mov edi,eax
- add edi,128 ;bias value (to account for signed displacement)
- ;clflush opcode=0F AE /7
- mov esi,edi
- mov ebx,esi
- mov ecx,esi
- mov edx,esi
- add edi,4*64 ;TestAddr+4 cache lines
- add ebx,8*64 ;TestAddr+8 cache lines
- add ecx,12*64 ;TestAddr+12 cache lines
- add edx,16*64 ;TestAddr+16 cache lines
- sub edx,128
- .if(ClCount == 1)
- _MFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- .elseif(ClCount == 3)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- .elseif(ClCount == 6)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- .elseif(ClCount == 9)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- mov eax,fs:[edi] ;TestAddr+6 cache lines
- _MFENCE
- mov eax,fs:[edi+64] ;TestAddr+7 cache lines
- _MFENCE
- mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
- _MFENCE
- .elseif(ClCount == 18)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- mov eax,fs:[edi] ;TestAddr+6 cache lines
- _MFENCE
- mov eax,fs:[edi+64] ;TestAddr+7 cache lines
- _MFENCE
- mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
- _MFENCE
- mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
- _MFENCE
- mov eax,fs:[ebx] ;TestAddr+10 cache lines
- _MFENCE
- mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
- _MFENCE
- mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
- _MFENCE
- mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
- _MFENCE
- mov eax,fs:[ecx] ;TestAddr+14 cache lines
- _MFENCE
- mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
- _MFENCE
- mov eax,fs:[edx] ;TestAddr+16 cache lines
- _MFENCE
- mov eax,fs:[edx+64] ;TestAddr+17 cache lines
- _MFENCE
- .endif
- .endif
- _MFENCE
-
- ; Then, copy data to buffer
- mov esi,Address
- xor edx,edx
- mov edx,DWORD PTR Buffer
- mov edi,edx
- xor ecx, ecx
- mov cx,ClCount
- shl ecx,6
- @@:
- mov al,fs:[esi]
- mov ss:[edi],al
- inc esi
- inc edi
- loop @B
-
- popad
- ret
-MemUReadCachelines ENDP
-
-;===============================================================================
-;MemUDummyCLRead:
-;
-; Perform a single cache line read from a given physical address.
-;
-; In: Address - Physical address to be read
-; ClCount - number of cachelines to be read
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUDummyCLRead PROC CALLCONV PUBLIC Address:DWORD
- _SFENCE
- pushad
- mov eax,Address
- mov dl,fs:[eax]
- popad
- ret
-MemUDummyCLRead ENDP
-
-;===============================================================================
-;MemUFlushPattern:
-;
-; Flush a pattern of 72 bit times (per DQ) from cache. This procedure is used
-;to ensure cache miss on the next read training.
-;
-; In: Address - Physical address to be flushed
-; ClCount - number of cachelines to be flushed
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUFlushPattern PROC CALLCONV PUBLIC Address:DWORD, ClCount:WORD
- pushad
- mov edi,Address
- movzx ecx,ClCount
- @@:
- _MFENCE ; Force strong ordering of clflush
- db 64h,0Fh,0AEh,3Fh ; MemUClFlush fs:[edi]
- _MFENCE
- add edi,64
- loop @B
- popad
- ret
-MemUFlushPattern ENDP
-
-
-;===============================================================================
-;MemUGetWrLvNblErr:
-; Read ClCount number of cachelines then return the bitmap that indicates
-; the write leveling result of each byte lane.
-;
-; IN: ErrBitmap - pointer to a DWORD that will be assigned with WL result
-; Address - Physical address to be sampled
-; ClCount - number of cachelines to be read
-;
-; OUT: ErrBitmap - WL result
-;
-;All registers preserved
-;===============================================================================
-MemUGetWrLvNblErr PROC CALLCONV PUBLIC ErrBitmap:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
-LOCAL ZeroCount[32]:WORD
-
- pushad
- mov esi,Address
- _EXECFENCE
- ;Cache fill
- movzx ecx,ClCount
- @@:
- mov eax,fs:[esi]
- add esi,64
- loop @B
- _MFENCE
-
- ; Then, count the number of 0's
- ;push es
- ;push ss
- ;pop es
- lea edi,ZeroCount
- mov cx,SIZEOF ZeroCount
- mov al,0
- rep stosb
- ;pop es
-
- mov esi,Address
- lea edi,ZeroCount
- mov cx,ClCount
- shl cx,6
- .while(cx > 0)
- mov al,fs:[esi]
- test al,00Fh ;check lower nibble
- .if(ZERO?)
- inc WORD PTR [edi]
- .endif
- add edi,2
- test al,0F0h ;check upper nibble
- .if(ZERO?)
- inc WORD PTR [edi]
- .endif
- add edi,2
- inc esi
- dec cx
- test cx,07h
- .if(ZERO?)
- sub edi,(16*2)
- sub cx,8
- add esi,8
- .endif
- .endw
-
- ; Then, average and compress data to error bits
- lea esi,ZeroCount
- mov dx,ClCount
- shl dx,1
- xor eax,eax
- xor ecx,ecx
- mov cl,0
- .while(cl<16)
- .if(WORD PTR [esi] < dx)
- bts eax,ecx
- .endif
- add esi,2
- inc cl
- .endw
- xor edx,edx
- mov dx,WORD PTR ErrBitmap
- mov [edx], ax
-
- popad
- ret
-MemUGetWrLvNblErr ENDP
-
-;===============================================================================
-;AlignPointerTo16Byte:
-; Modifies BufferPtr to be 16 byte aligned
-;
-; In: BufferPtrPtr - Pointer to buffer pointer
-; Out: BufferPtrPtr - Pointer to buffer pointer that has been 16 byte aligned
-;
-;All registers preserved.
-;===============================================================================
-AlignPointerTo16Byte PROC CALLCONV PUBLIC BufferPtrPtr:NEAR PTR DWORD
- push edx
- push eax
- mov edx, BufferPtrPtr
- mov eax, [edx]
- add eax, 16
- and ax, 0FFF0h
- mov [edx], eax
- pop eax
- pop edx
- ret
-AlignPointerTo16Byte ENDP
-
-;===============================================================================
-;MemUMFenceInstr:
-; Serialize instruction
-;
-; In:
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUMFenceInstr PROC CALLCONV PUBLIC
- _MFENCE
- ret
-MemUMFenceInstr ENDP
-
- END
-
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mru.asm b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mru.asm
deleted file mode 100644
index 56db233be6..0000000000
--- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mru.asm
+++ /dev/null
@@ -1,187 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; $Workfile:: mu.asm $ $Revision:: 237#$ $Date: 2009-12-10 07:28:37 +0800 (Thu, 10 Dec 2009) $
-; Description: Main memory controller system configuration for AGESA DDR 2
-;
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-;============================================================================
-
-
- .XLIST
- .LIST
- .686p
- .MODEL FLAT
- .CODE
- ASSUME FS: NOTHING
-
-
-; Define the calling convention used for the C library modules
-;@attention - This should be in a central include file
-CALLCONV EQU NEAR C
-
-
-;===============================================================================
-;MemRecUOutPort:
-;
-; Do a 32 Bit IO Out operation using edx.
-; NOTE: This function will be obsolete in the future.
-;
-; In: Port - port number
-; Value - value to be written to port
-;
-; Out:
-;
-;All registers preserved except for "Out:"
-;===============================================================================
-MemRecUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD
- pushad
- mov edx,Port
- mov eax,Value
- out dx,al
- popad
- ret
-MemRecUOutPort ENDP
-
-
-
-;----------------------------------------------------------------------------
-; _MFENCE();
-;
-_MFENCE macro
- db 0Fh,0AEh,0F0h
- endm
-
-;----------------------------------------------------------------------------
-; _EXECFENCE();
-;
-_EXECFENCE macro
- out 0EDh,al ;prevent speculative execution of following instructions
- endm
-
-;===============================================================================
-;MemRecUWrite1CL:
-;
-; Write data from buffer to a system address
-;
-; In: Address - System address to read from
-; Pattern - pointer pattern.
-;
-; Out:
-;
-;All registers preserved except for "Out:"
-;===============================================================================
-MemRecUWrite1CL PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD
- pushad
- push ds
-
- mov eax,Address
- push ss
- pop ds
- xor edx,edx
- mov edx, DWORD PTR Pattern
- mov esi,edx
- mov edx,16
- _EXECFENCE
- mov ecx,4
- @@:
- db 66h,0Fh,6Fh,06 ;MOVDQA xmm0,[esi]
- db 64h,66h,0Fh,0E7h,00 ;MOVNTDQ fs:[eax],xmm0 (xmm0 is 128 bits)
- add eax,edx
- add esi,edx
- loop @B
-
- pop ds
- popad
- ret
-MemRecUWrite1CL ENDP
-
-;===============================================================================
-;MemRecURead1CL:
-;
-; Read one cacheline to buffer
-;
-; In: Buffer - pointer buffer.
-; : Address - System address to read from
-;
-; Out:
-;
-;All registers preserved except for "Out:"
-;===============================================================================
-MemRecURead1CL PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD
-
- pushad
-
- mov esi,Address
- xor edx,edx
- mov edx,DWORD PTR Buffer
- mov edi,edx
- mov ecx,64
- @@:
- mov al,fs:[esi]
- mov ss:[edi],al
- inc esi
- inc edi
- loop @B
-
- popad
- ret
-MemRecURead1CL ENDP
-
-
-;===============================================================================
-;MemRecUFlushPattern:
-;
-; Flush one cache line
-;
-; In: Address - System address [31:0]
-; Out:
-;
-;All registers preserved except for "Out:"
-;===============================================================================
-MemRecUFlushPattern PROC CALLCONV PUBLIC Address:DWORD
- pushad
- mov eax,Address
- _EXECFENCE
- ;clflush fs:[eax]
- db 064h ;access relative to FS BASE prefix
- db 00Fh ;opcode
- db 0AEh ;opcode
- db 038h ;eax indirect addressing
- _MFENCE
- popad
- ret
-MemRecUFlushPattern ENDP
-
-
-
- END
-
diff --git a/src/vendorcode/amd/agesa/f14/cpcarmac.inc b/src/vendorcode/amd/agesa/f14/cpcarmac.inc
deleted file mode 100644
index 54e7f95bb6..0000000000
--- a/src/vendorcode/amd/agesa/f14/cpcarmac.inc
+++ /dev/null
@@ -1,447 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; Workfile: cpcarmac.inc $Revision:: 38483 $ $Date:: 2010-09-25 02:13:03 +0800 (Sat, 25 Sep 2010) $
-;
-; Description: Code to setup and break down cache-as-stack
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- .XLIST
- INCLUDE cpcar.inc
- .LIST
- .586P
- .mmx
-
-;======================================================================
-; AMD_ENABLE_STACK: Setup a stack
-;
-; In:
-; EBX = Return address (preserved)
-;
-; Out:
-; SS:ESP - Our new private stack location
-;
-; EAX = AGESA_STATUS
-;
-; ECX = Stack size in bytes
-;
-; Requirements:
-; * This routine presently is limited to a max of 64 processor cores
-; Preserved:
-; ebx ebp
-; Destroyed:
-; eax, ecx, edx, edi, esi, ds, es, ss, esp
-; mmx0, mmx1
-;
-; Description:
-; Fixed MTRR address allocation to cores:
-; The BSP gets 64K of stack, Core0 of each node gets 16K of stack, all other cores get 4K.
-; There is a max of 1 BSP, 7 core0s and 56 other cores.
-; Although each core has it's own cache storage, they share the address space. Each core must
-; be assigned a private and unique address space for its stack. To support legacy systems,
-; the stack needs to be within the legacy address space (1st 1Meg). Room must also be reserved
-; for the other legacy elements (Interrupt vectors, BIOS ROM, video buffer, etc.)
-;
-; 80000h 40000h 00000h
-; +----------+----------+----------+----------+----------+----------+----------+----------+
-; 64K | | | | | | | | | 64K ea
-; ea +----------+----------+----------+----------+----------+----------+----------+----------+
-; | MTRR 0000_0250 MTRRfix64K_00000 |
-; +----------+----------+----------+----------+----------+----------+----------+----------+
-; | 7 , 6 | 5 , 4 | 3 , 2 | 1 , 0 | 0 | | | | <-node
-; |7..1,7..1 |7..1,7..1 |7..1,7..1 |7..1,7..1 | 0 | | | | <-core
-; +----------+----------+----------+----------+----------+----------+----------+----------+
-;
-; C0000h B0000h A0000h 90000h 80000h
-; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
-;16K | | | | | | | | | | | | | | | | |
-; ea +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
-; | MTRR 0259 MTRRfix16K_A0000 | MTRR 0258 MTRRfix16K_80000 |
-; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
-; | > Dis|play B|uffer | < | | | | | 7 | 6 | 5 | 4 | 3 | 2 | 1 | | <-node
-; | > T| e m |p o r |a r y | B u |f f e |r A |r e a<| 0 | 0 | 0 | 0 | 0 | 0 | 0 | | <-core
-; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
-;
-; E0000h D0000h C0000h
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; 4K | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
-; ea +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | 026B MTRRfix4K_D8000 | 026A MTRRfix4K_D0000 | 0269 MTRRfix4K_C8000 | 0268 MTRRfix4K_C0000 |
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | | | | | | | | | | | | | | | | | >| V| I| D| E| O| |B |I |O |S | |A |r |e |a<|
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-;
-; 100000h F0000h E0000h
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | 026F MTRRfix4K_F8000 | 026E MTRRfix4K_F0000 | 026D MTRRfix4K_E8000 | 026C MTRRfix4K_E0000 |
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< |
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-;======================================================================
-AMD_ENABLE_STACK MACRO
- local AmdEnableStackExit
-
-; Note that SS:ESP will be default stack. Note that this stack
-; routine will not be used after memory has been initialized. Because
-; of its limited lifetime, it will not conflict with typical PCI devices.
- movd mm0, ebx ; Put return address in a safe place
- movd mm1, ebp ; Save some other user registers
-
- ; get node id and core id of current executing core
- GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
- ; Note: ESI[31:24] are used for flags: Unrecognized Family, Is_Primary core, Stack already established
-
- ; If we detected an unknown processor family, return AGESA_FATAL.
- .if (esi & (1 SHL FLAG_UNKNOWN_FAMILY))
- mov eax, AGESA_FATAL
- jmp AmdEnableStackExit
- .endif
-
- ; determine if stack is already enabled. We are using the DefType MSR for this determination.
- ; It is =0 after reset; CAR setup sets it to enable the MTRRs
- mov eax, cr0 ; Is cache enabled? (CD or NW bit set)
- CR0_MASK TEXTEQU %((1 SHL CR0_CD) OR (1 SHL CR0_NW))
- .if (!(eax & CR0_MASK))
- mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF
- _RDMSR ; Are either of the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)
- MSR_MASK TEXTEQU %((1 SHL MTRR_DEF_TYPE_EN)+(1 SHL MTRR_DEF_TYPE_FIX_EN))
- .if (eax & MSR_MASK)
- bts esi, FLAG_STACK_REENTRY ; indicate stack has already been initialized
- .endif
- .endif
-
- ; Set node to map the first 16MB to node 0; 0000_0000 to 00FF_FFFF as DRAM
- mov ebx, esi ; Get my Node/Core info
- xor bl, bl
- shl bh, 3 ; Isolate my node#, match alignment for PCI Dev#
- mov eax, 8000C144h ; D18F1x44:DRAM Base/Limit; N is Base, N+4 is Limit
- add ah, bh
- mov ebx, eax ; Save PCI address for Base/Limit pair
-
- mov dx, 0CF8h
- out dx, eax
- add dx, 4
- xor eax, eax ; Least Significant bit is AD24 so 0 sets mask of 00FF_FFFF (16MB)
- out dx, eax ; DRAM Limit = node0, no interleave
-
- mov eax, ebx
- sub eax, 4 ; Now point to the Base register
- mov dx, 0CF8h
- out dx, eax
- add dx, 4
- mov eax, 00000003h ; Set the read and write enable bits
- out dx, eax ; DRAM Base = 0x0000, R/W
-
- AMD_ENABLE_STACK_FAMILY_HOOK
-
- ; Init CPU MSRs for our init routines
- mov ecx, MTRR_SYS_CFG ; SYS_CFG
- _RDMSR
- bts eax, MTRR_FIX_DRAM_MOD_EN ; Turn on modification enable bit
- _WRMSR
-
- mov eax, esi
- bt eax, FLAG_STACK_REENTRY ; Is this a 2nd entry?
- .if (!carry?) ; On a re-entry, do not clear MTRRs or reset TOM; just reset the stack SS:ESP
- bt eax, FLAG_IS_PRIMARY ; Is this core the primary in a compute unit?
- .if (carry?) ; Families using shared groups do not need to clear the MTRRs since that is done at power-on reset
- ; Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores
- ; Clear all variable and Fixed MTRRs for non-shared cores
- mov ecx, AMD_MTRR_VARIABLE_BASE0
- xor eax, eax
- xor edx, edx
- .while (cl != 10h) ; Variable MTRRphysBase[n] and MTRRphysMask[n]
- _WRMSR
- inc cl
- .endw
- mov cx, AMD_MTRR_FIX64k_00000 ; MSR:0000_0250
- _WRMSR
- mov cx, AMD_MTRR_FIX16k_80000 ; MSR:0000_0258
- _WRMSR
- mov cx, AMD_MTRR_FIX16k_A0000 ; MSR:0000_0259
- _WRMSR
- mov cx, AMD_MTRR_FIX4k_C0000 ; Fixed 4Ks: MTRRfix4K_C0000 to MTRRfix4K_F8000
- .while (cl != 70h)
- _WRMSR
- inc cl
- .endw
-
- ; Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init.
- ; - not strictly needed since the FixedMTRRs take presedence.
- mov eax, (16 * 1024 * 1024)
- mov ecx, TOP_MEM ; MSR:C001_001A
- _WRMSR
- .endif ; End Is_Primary
- .endif ; End Stack_ReEntry
-
- ; Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores
- xor eax, eax
- xor edx, edx
- mov ecx, IORR_BASE ; MSR:C001_0016 - 0019
- .while (cl != 1Ah)
- _WRMSR
- inc cl
- .endw
- mov ecx, TOP_MEM2 ; MSR:C001_001D
- _WRMSR
-
- ; setup MTRRs for stacks
- ; A speculative read can be generated by a speculative fetch mis-aligned in a code zone
- ; or due to a data zone being interpreted as code. When a speculative read occurs outside a
- ; controlled region (intentionally used by software), it could cause an unwanted cache eviction.
- ; To prevent speculative reads from causing an eviction, the unused cache ranges are set
- ; to UC type. Only the actively used regions (stack, heap) are reflected in the MTRRs.
- ; Note: some core stack regions will share an MTRR since the control granularity is much
- ; larger than the allocated stack zone. The allocation algorithm must account for this 'extra'
- ; space covered by the MTRR when parseling out cache space for the various uses. In some cases
- ; this could reduce the amount of EXE cache available to a core. see cpuCacheInit.c
- ;
- ; Outcome of this block is that: (Note the MTRR map at the top of the file)
- ; ebp - start address of stack block
- ; ebx - [31:16] - MTRR MSR address
- ; - [15:8] - slot# in MTRR register
- ; - [7:0] - block size in #4K blocks
- ; review: ESI[31:24]=Flags; SI[15,8]= Node#; SI[7,0]= core# (relative to node)
- ;
-
- mov ax, si ; Load node, core
- .if (al == 0) ; Is a core 0?
- .if (ah == 0) ; Is Node 0? (BSP)
- ; Is BSP, assign a 64K stack
- mov ebx, ((AMD_MTRR_FIX64k_00000 SHL 16) + (3 SHL 8) + (BSP_STACK_SIZE / 1000h))
- mov ebp, BSP_STACK_BASE_ADDR
- .else ; node 1 to 7, core0
- ; Is a Core0 of secondary node, assign 16K stacks
- mov bx, AMD_MTRR_FIX16k_80000
- shl ebx, 16 ;
- mov bh, ah ; Node# is used as slot#
- mov bl, (CORE0_STACK_SIZE / 1000h)
- mov al, ah ; Base = (Node# * Size);
- mul bl ;
- movzx eax, ax ;
- shl eax, 12 ; Expand back to full byte count (* 4K)
- add eax, CORE0_STACK_BASE_ADDR
- mov ebp, eax
- .endif
- .else ;core 1 thru core 7
- ; Is core 1-7 of any node, assign 4K stacks
- mov al, 8 ; CoreIndex = ( (Node# * 8) ...
- mul ah ;
- mov bx, si ;
- add al, bl ; ... + Core#);
-
- mov bx, AMD_MTRR_FIX64k_00000
- shl ebx, 16 ;
- mov bh, al ; Slot# = (CoreIndex / 16) + 4;
- shr bh, 4 ;
- add bh, 4 ;
- mov bl, (CORE1_STACK_SIZE / 1000h)
-
- mul bl ; Base = ( (CoreIndex * Size) ...
- movzx eax, ax ;
- shl eax, 12 ; Expand back to full byte count (* 4K)
- add eax, CORE1_STACK_BASE_ADDR ; ... + Base_Addr);
- mov ebp, eax
- .endif
-
- ; Now set the MTRR. Add this to already existing settings (don't clear any MTRR)
- mov edi, WB_DRAM_TYPE ; Load Cache type in 1st slot
- mov cl, bh ; ShiftCount = ((slot# ...
- and cl, 03h ; ... % 4) ...
- shl cl, 3 ; ... * 8);
- shl edi, cl ; Cache type is now in correct position
- ror ebx, 16 ; Get the MTRR address
- movzx ecx, bx ;
- rol ebx, 16 ; Put slot# & size back in BX
- _RDMSR ; Read-modify-write the MSR
- .if (bh < 4) ; Is value in lower or upper half of MSR?
- or eax, edi ;
- .else ;
- or edx, edi ;
- .endif ;
- _WRMSR ;
-
- ; Enable MTRR defaults as UC type
- mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF
- _RDMSR ; Read-modify-write the MSR
- bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn
- bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn
- _WRMSR
-
- ; Close the modification window on the Fixed MTRRs
- mov ecx, MTRR_SYS_CFG ; MSR:0C001_0010
- _RDMSR
- bts eax, MTRR_FIX_DRAM_EN ; MtrrFixDramEn
- bts eax, MTRR_VAR_DRAM_EN ; variable MTRR enable bit
- btr eax, MTRR_FIX_DRAM_MOD_EN ; Turn off modification enable bit
- _WRMSR
-
- ; Enable caching in CR0
- mov eax, CR0 ; Enable WT/WB cache
- btr eax, CR0_PG ; Make sure paging is disabled
- btr eax, CR0_CD ; Clear CR0 NW and CD
- btr eax, CR0_NW
- mov CR0, eax
-
- ; Use the Stack Base & size to calculate SS and ESP values
- ; review:
- ; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
- ; ebp - start address of stack block
- ; ebx - [31:16] - MTRR MSR address
- ; - [15:8] - slot# in MTRR register
- ; - [7:0] - block size in #4K blocks
- ;
- mov esp, ebp ; Initialize the stack pointer
- mov edi, esp ; Copy the stack start to edi
- movzx bx, bl
- movzx ebx, bx ; Clear upper ebx, don't need MSR addr anymore
- shl ebx, 12 ; Make size full byte count (* 4K)
- add esp, ebx ; Set the Stack Pointer as full linear address
- sub esp, 4
- ;
- ; review:
- ; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
- ; edi - 32b start address of stack block
- ; ebx - size of stack block
- ; esp - 32b linear stack pointer
- ;
-
- ; Determine mode for SS base;
- mov ecx, CR0 ; Check for 32-bit protect mode
- bt ecx, CR0_PE ;
- .if (!carry?) ; PE=0 means real mode
- mov cx, cs ;
- .if (cx >= 0D000h) ; If CS >= D000, it's a real mode segment. PM selector would be 08-> 1000
- ; alter SS:ESP for 16b Real Mode:
- mov eax, edi ;
- shr eax, 4 ; Create a Real Mode segment for ss, ds, es
- mov ss, ax ;
- mov ds, ax ;
- mov es, ax ;
- shl eax, 4 ;
- sub edi, eax ; Adjust the clearing pointer for Seg:Offset mode
- mov esp, ebx ; Make SP an offset from SS
- sub esp, 4 ;
- .endif ; endif
- ; else
- ; Default is to use Protected 32b Mode
- .endif
- ;
- ; Clear The Stack
- ; Now that we have set the location and the MTRRs, initialize the cache by
- ; reading then writing to zero all of the stack area.
- ; review:
- ; ss - Stack base
- ; esp - stack pointer
- ; ebx - size of stack block
- ; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
- ; edi - address of start of stack block
- ;
- shr ebx, 2 ;
- mov cx, bx ; set cx for size count of DWORDS
- ; Check our flags - Don't clear an existing stack
- .if ( !(esi & (1 SHL FLAG_STACK_REENTRY)) )
- cld
- mov esi, edi
- rep lods DWORD PTR [esi] ; Pre-load the range
- xor eax, eax
- mov cx, bx
- mov esi, edi ; Preserve base for push on stack
- rep stos DWORD PTR [edi] ; Clear the range
- mov DWORD PTR [esp], 0ABCDDCBAh ; Put marker in top stack dword
- shl ebx, 2 ; Put stack size and base
- push ebx ; in top of stack
- push esi
-
- mov ecx, ebx ; Return size of stack in bytes
- mov eax, AGESA_SUCCESS ; eax = AGESA_SUCCESS : no error return code
- .else
- movzx ecx, cx
- shl ecx, 2 ; Return size of stack, in bytes
- mov eax, esi
- shr eax, 24 ; Keep the flags as part of the error report
- or eax, 40000000h ; eax = AGESA_WARNING (Stack has already been set up)
- .endif
-AmdEnableStackExit:
- movd ebx, mm0 ; Restore return address
- movd ebp, mm1
-ENDM
-
-;======================================================================
-; AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine
-; should only be executed on the BSP
-;
-; In:
-; none
-;
-; Out:
-; EAX = AGESA_SUCCESS
-;
-; Preserved:
-; ebx
-; Destroyed:
-; eax, ecx, edx, esp
-;======================================================================
-AMD_DISABLE_STACK MACRO
-
- mov esp, ebx ; Save return address
-
- ; get node/core/flags of current executing core
- GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
-
- ; Turn on modification enable bit
- mov ecx, MTRR_SYS_CFG ; MSR:C001_0010
- _RDMSR
- bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable modifications
- _WRMSR
-
- ; Set lower 640K MTRRs for Write-Back memory caching
- mov ecx, AMD_MTRR_FIX64k_00000
- mov eax, 1E1E1E1Eh
- mov edx, eax
- _WRMSR ; 0 - 512K = WB Mem
- mov ecx, AMD_MTRR_FIX16k_80000
- _WRMSR ; 512K - 640K = WB Mem
-
- ; Turn off modification enable bit
- mov ecx, MTRR_SYS_CFG ; MSR:C001_0010
- _RDMSR
- btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable modification
- _WRMSR
-
- AMD_DISABLE_STACK_FAMILY_HOOK ; Re-Enable 'normal' cache operations
-
- mov ebx, esp ; restore return address (ebx)
- xor eax, eax
-
-ENDM
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/PlatformMemoryConfiguration.inc b/src/vendorcode/amd/agesa/f15/Legacy/PlatformMemoryConfiguration.inc
deleted file mode 100644
index cf111ac2b7..0000000000
--- a/src/vendorcode/amd/agesa/f15/Legacy/PlatformMemoryConfiguration.inc
+++ /dev/null
@@ -1,670 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * AMD Platform Specific Memory Configuration
-; *
-; * Contains AMD AGESA Memory Configuration Override Interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 22910 $ @e \$Date: 2009-11-27 04:50:20 -0600 (Fri, 27 Nov 2009) $
-;
-; ****************************************************************************
-; *
-; * Copyright (C) 2012 Advanced Micro Devices, Inc.
-; * All rights reserved.
-; *
-; * Redistribution and use in source and binary forms, with or without
-; * modification, are permitted provided that the following conditions are met:
-; * * Redistributions of source code must retain the above copyright
-; * notice, this list of conditions and the following disclaimer.
-; * * Redistributions in binary form must reproduce the above copyright
-; * notice, this list of conditions and the following disclaimer in the
-; * documentation and/or other materials provided with the distribution.
-; * * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; * its contributors may be used to endorse or promote products derived
-; * from this software without specific prior written permission.
-; *
-; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; *
-; *
-; **************************************************************************
-IFNDEF PSO_ENTRY
- PSO_ENTRY TEXTEQU <UINT8>; < Platform Configuration Table Entry
-ENDIF
-; *****************************************************************************************
-; *
-; * PLATFORM SPECIFIC MEMORY DEFINITIONS
-; *
-; *****************************************************************************************
-; */
-;
-; < Memory Speed and DIMM Population Masks
-;
-; < DDR Speed Masks
-;
-ANY_SPEED EQU 0FFFFFFFFh
-DDR400 EQU ( 1 SHL (DDR400_FREQUENCY / 66))
-DDR533 EQU ( 1 SHL (DDR533_FREQUENCY / 66))
-DDR667 EQU ( 1 SHL (DDR667_FREQUENCY / 66))
-DDR800 EQU ( 1 SHL (DDR800_FREQUENCY / 66))
-DDR1066 EQU ( 1 SHL (DDR1066_FREQUENCY / 66))
-DDR1333 EQU ( 1 SHL (DDR1333_FREQUENCY / 66))
-DDR1600 EQU ( 1 SHL (DDR1600_FREQUENCY / 66))
-DDR1866 EQU ( 1 SHL (DDR1866_FREQUENCY / 66))
-DDR2133 EQU ( 1 SHL (DDR2133_FREQUENCY / 66))
-DDR2400 EQU ( 1 SHL (DDR2400_FREQUENCY / 66))
-; <
-; < DIMM POPULATION MASKS
-;
-ANY_ EQU 0FFh
-SR_DIMM0 EQU 0001h
-SR_DIMM1 EQU 0010h
-SR_DIMM2 EQU 0100h
-SR_DIMM3 EQU 1000h
-DR_DIMM0 EQU 0002h
-DR_DIMM1 EQU 0020h
-DR_DIMM2 EQU 0200h
-DR_DIMM3 EQU 2000h
-QR_DIMM0 EQU 0004h
-QR_DIMM1 EQU 0040h
-QR_DIMM2 EQU 0400h
-QR_DIMM3 EQU 4000h
-LR_DIMM0 EQU 0001h
-LR_DIMM1 EQU 0010h
-LR_DIMM2 EQU 0100h
-LR_DIMM3 EQU 1000h
-ANY_DIMM0 EQU 000Fh
-ANY_DIMM1 EQU 00F0h
-ANY_DIMM2 EQU 0F00h
-ANY_DIMM3 EQU 0F000h
-; <
-; < CS POPULATION MASKS
-;
-CS_ANY_ EQU 0FFh
-CS0_ EQU 01h
-CS1_ EQU 02h
-CS2_ EQU 04h
-CS3_ EQU 08h
-CS4_ EQU 10h
-CS5_ EQU 20h
-CS6_ EQU 40h
-CS7_ EQU 80h
-;
-; Number of Dimms
-;
-ANY_NUM EQU 0FFh
-NO_DIMM EQU 00h
-ONE_DIMM EQU 01h
-TWO_DIMM EQU 02h
-THREE_DIMM EQU 04h
-FOUR_DIMM EQU 08h
-;
-; DIMM VOLTAGE MASK
-;
-VOLT_ANY_ EQU 0FFh
-VOLT1_5_ EQU 01h
-VOLT1_35_ EQU 02h
-VOLT1_25_ EQU 04h
-;
-; NOT APPLICIABLE
-;
-NA_ EQU 00h
-; *****************************************************************************************
-; *
-; * Platform Specific Override Definitions for Socket, Channel and Dimm
-; * This indicates where a platform override will be applied.
-; *
-; *****************************************************************************************
-;
-; SOCKET MASKS
-;
-ANY_SOCKET EQU 0FFh
-SOCKET0 EQU 01h
-SOCKET1 EQU 02h
-SOCKET2 EQU 04h
-SOCKET3 EQU 08h
-SOCKET4 EQU 10h
-SOCKET5 EQU 20h
-SOCKET6 EQU 40h
-SOCKET7 EQU 80h
-;
-; CHANNEL MASKS
-;
-ANY_CHANNEL EQU 0FFh
-CHANNEL_A EQU 01h
-CHANNEL_B EQU 02h
-CHANNEL_C EQU 04h
-CHANNEL_D EQU 08h
-;
-; DIMM MASKS
-;
-ALL_DIMMS EQU 0FFh
-DIMM0 EQU 01h
-DIMM1 EQU 02h
-DIMM2 EQU 04h
-DIMM3 EQU 08h
-;
-; REGISTER ACCESS MASKS
-;
-ACCESS_NB0 EQU 0h
-ACCESS_NB1 EQU 01h
-ACCESS_NB2 EQU 02h
-ACCESS_NB3 EQU 03h
-ACCESS_NB4 EQU 04h
-ACCESS_PHY EQU 05h
-ACCESS_DCT_XT EQU 06h
-; *****************************************************************************************
-; *
-; * Platform Specific Overriding Table Definitions
-; *
-; *****************************************************************************************
-PSO_END EQU 0 ; < Table End
-PSO_CKE_TRI EQU 1 ; < CKE Tristate Map
-PSO_ODT_TRI EQU 2 ; < ODT Tristate Map
-PSO_CS_TRI EQU 3 ; < CS Tristate Map
-PSO_MAX_DIMMS EQU 4 ; < Max Dimms per channel
-PSO_CLK_SPEED EQU 5 ; < Clock Speed
-PSO_DIMM_TYPE EQU 6 ; < Dimm Type
-PSO_MEMCLK_DIS EQU 7 ; < MEMCLK Disable Map
-PSO_MAX_CHNLS EQU 8 ; < Max Channels per Socket
-PSO_BUS_SPEED EQU 9 ; < Max Memory Bus Speed
-PSO_MAX_CHIPSELS EQU 10 ; < Max Chipsel per Channel
-PSO_MEM_TECH EQU 11 ; < Channel Memory Type
-PSO_WL_SEED EQU 12 ; < DDR3 Write Levelization Seed delay
-PSO_RXEN_SEED EQU 13 ; < Hardwared based RxEn seed
-PSO_NO_LRDIMM_CS67_ROUTING EQU 14 ; < CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
-PSO_SOLDERED_DOWN_SODIMM_TYPE EQU 15 ; < Soldered down SODIMM type
-PSO_LVDIMM_VOLT1_5_SUPPORT EQU 16 ; < Force LvDimm voltage to 1.5V
-PSO_MIN_RD_WR_DATAEYE_WIDTH EQU 17 ; < Min RD/WR dataeye width
-PSO_CPU_FAMILY_TO_OVERRIDE EQU 18 ; < CPU family signature to tell following PSO macros are CPU family dependent
-; **********************************
-; * CONDITIONAL PSO SPECIFIC ENTRIES
-; **********************************
-; Condition Types
-CONDITIONAL_PSO_MIN EQU 100 ; < Start of Conditional Entry Types
-PSO_CONDITION_AND EQU 100 ; < And Block - Start of Conditional block
-PSO_CONDITION_LOC EQU 101 ; < Location - Specify Socket, Channel, Dimms to be affected
-PSO_CONDITION_SPD EQU 102 ; < SPD - Specify a specific SPD value on a Dimm on the channel
-PSO_CONDITION_REG EQU 103 ; Reserved
-PSO_CONDITION_MAX EQU 103 ; < End Of Condition Entry Types
-; Action Types
-PSO_ACTION_MIN EQU 120 ; < Start of Action Entry Types
-PSO_ACTION_ODT EQU 120 ; < ODT values to override
-PSO_ACTION_ADDRTMG EQU 121 ; < Address/Timing values to override
-PSO_ACTION_ODCCONTROL EQU 122 ; < ODC Control values to override
-PSO_ACTION_SLEWRATE EQU 123 ; < Slew Rate value to override
-PSO_ACTION_REG EQU 124 ; Reserved
-PSO_ACTION_SPEEDLIMIT EQU 125 ; < Memory Bus speed Limit based on configuration
-PSO_ACTION_MAX EQU 125 ; < End of Action Entry Types
-CONDITIONAL_PSO_MAX EQU 139 ; < End of Conditional Entry Types
-; **********************************
-; * TABLE DRIVEN PSO SPECIFIC ENTRIES
-; **********************************
-; Condition descriptor
-PSO_TBLDRV_CONFIG EQU 200 ; < Configuration Descriptor
-
-; Overriding entry types
-PSO_TBLDRV_START EQU 210 ; < Start of Table Driven Overriding Entry Types
-PSO_TBLDRV_SPEEDLIMIT EQU 210 ; < Speed Limit
-PSO_TBLDRV_ODT_RTTNOM EQU 211 ; < RttNom
-PSO_TBLDRV_ODT_RTTWR EQU 212 ; < RttWr
-PSO_TBLDRV_ODTPATTERN EQU 213 ; < Odt Patterns
-PSO_TBLDRV_ADDRTMG EQU 214 ; < Address/Timing values
-PSO_TBLDRV_ODCCTRL EQU 215 ; < ODC Control values
-PSO_TBLDRV_SLOWACCMODE EQU 216 ; < Slow Access Mode
-PSO_TBLDRV_MR0_CL EQU 217 ; < MR0[CL]
-PSO_TBLDRV_MR0_WR EQU 218 ; < MR0[WR]
-PSO_TBLDRV_RC2_IBT EQU 219 ; < RC2[IBT]
-PSO_TBLDRV_RC10_OPSPEED EQU 220 ; < RC10[Opearting Speed]
-PSO_TBLDRV_LRDIMM_IBT EQU 221 ; < LrDIMM IBT
-PSO_TBLDRV____TRAINING EQU 222 ; < training
-PSO_TBLDRV_INVALID_TYPE EQU 223 ; < Invalid Type
-PSO_TBLDRV_END EQU 223 ; < End of Table Driven Overriding Entry Types
-
-
-; *****************************************************************************************
-; *
-; * CONDITIONAL OVERRIDE TABLE MACROS
-; *
-; *****************************************************************************************
-CPU_FAMILY_TO_OVERRIDE MACRO CpuFamilyRevision:REQ
- DB PSO_CPU_FAMILY_TO_OVERRIDE
- DB 4
- DD CpuFamilyRevision
-ENDM
-
-MEMCLK_DIS_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
- DB PSO_MEMCLK_DIS
- DB 11
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB Bit0Map
- DB Bit1Map
- DB Bit2Map
- DB Bit3Map
- DB Bit4Map
- DB Bit5Map
- DB Bit6Map
- DB Bit7Map
-ENDM
-
-CKE_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ
- DB PSO_CKE_TRI
- DB 5
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB Bit0Map
- DB Bit1Map
-ENDM
-
-ODT_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ
- DB PSO_ODT_TRI
- DB 7
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB Bit0Map
- DB Bit1Map
- DB Bit2Map
- DB Bit3Map
-ENDM
-
-CS_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
- DB PSO_CS_TRI
- DB 11
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB Bit0Map
- DB Bit1Map
- DB Bit2Map
- DB Bit3Map
- DB Bit4Map
- DB Bit5Map
- DB Bit6Map
- DB Bit7Map
-ENDM
-
-NUMBER_OF_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfDimmSlotsPerChannel:REQ
- DB PSO_MAX_DIMMS
- DB 4
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB NumberOfDimmSlotsPerChannel
-ENDM
-
-NUMBER_OF_CHIP_SELECTS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfChipSelectsPerChannel:REQ
- DB PSO_MAX_CHIPSELS
- DB 4
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB NumberOfChipSelectsPerChannel
-ENDM
-
-NUMBER_OF_CHANNELS_SUPPORTED MACRO SocketID:REQ, NumberOfChannelsPerSocket:REQ
- DB PSO_MAX_CHNLS
- DB 4
- DB SocketID
- DB ANY_CHANNEL
- DB ALL_DIMMS
- DB NumberOfChannelsPerSocket
-ENDM
-
-OVERRIDE_DDR_BUS_SPEED MACRO SocketID:REQ, ChannelID:REQ, TimingMode:REQ, BusSpeed:REQ
- PSO_BUS_SPEED
- DB 11
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DD TimingMode
- DD BusSpeed
-ENDM
-
-DRAM_TECHNOLOGY MACRO SocketID:REQ, MemTechType:REQ
- DB PSO_MEM_TECH
- DB 7
- DB SocketID
- DB ANY_CHANNEL
- DB ALL_DIMMS
- DD MemTechType
-ENDM
-
-WRITE_LEVELING_SEED MACRO SocketID:REQ, ChannelID:REQ, DimmID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
-Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
- DB PSO_WL_SEED
- DB 12
- DB SocketID
- DB ChannelID
- DB DimmID
- DB Byte0Seed
- DB Byte1Seed
- DB Byte2Seed
- DB Byte3Seed
- DB Byte4Seed
- DB Byte5Seed
- DB Byte6Seed
- DB Byte7Seed
- DB ByteEccSeed
-ENDM
-
-HW_RXEN_SEED MACRO SocketID:REQ, ChannelID:REQ, DimmID: REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
-Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
- DB PSO_RXEN_SEED
- DB 21
- DB SocketID
- DB ChannelID
- DB DimmID
- DW Byte0Seed
- DW Byte1Seed
- DW Byte2Seed
- DW Byte3Seed
- DW Byte4Seed
- DW Byte5Seed
- DW Byte6Seed
- DW Byte7Seed
- DW ByteEccSeed
-ENDM
-
-NO_LRDIMM_CS67_ROUTING MACRO SocketID:REQ, ChannelID:REQ
- DB PSO_NO_LRDIMM_CS67_ROUTING
- DB 4
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB 1
-ENDM
-
-SOLDERED_DOWN_SODIMM_TYPE MACRO SocketID:REQ, ChannelID:REQ
- DB PSO_SOLDERED_DOWN_SODIMM_TYPE
- DB 4
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB 1
-ENDM
-
-LVDIMM_FORCE_VOLT1_5_FOR_D0 MACRO
- DB PSO_LVDIMM_VOLT1_5_SUPPORT
- DB 4
- DB ANY_SOCKET
- DB ANY_CHANNEL
- DB ALL_DIMMS
- DB 1
-ENDM
-
-MIN_RD_WR_DATAEYE_WIDTH MACRO SocketID:REQ, ChannelID:REQ, MinRdDataeyeWidth:REQ, MinWrDataeyeWidth:REQ
- DB PSO_MIN_RD_WR_DATAEYE_WIDTH
- DB 5
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB MinRdDataeyeWidth
- DB MinWrDataeyeWidth
-ENDM
-
-; *****************************************************************************************
-; *
-; * CONDITIONAL OVERRIDE TABLE MACROS
-; *
-; *****************************************************************************************
-CONDITION_AND MACRO
- DB PSO_CONDITION_AND
- DB 0
-ENDM
-
-COND_LOC MACRO SocketMsk:REQ, ChannelMsk:REQ, DimmMsk:REQ
- DB PSO_CONDITION_LOC
- DB 3
- DB SocketMsk
- DB ChannelMsk
- DB DimmMsk
-ENDM
-
-COND_SPD MACRO Byte:REQ, Mask:REQ, Value:REQ
- DB PSO_CONDITION_SPD
- DB 3
- DB Byte
- DB Mask
- DB Value
-ENDM
-
-COND_REG MACRO Access:REQ, Offset:REQ, Mask:REQ, Value:REQ
- DB PSO_CONDITION_REG
- DB 11
- DB Access
- DW Offset
- DD Mask
- DD Value
-ENDM
-
-ACTION_ODT MACRO Frequency:REQ, Dimms:REQ, QrDimms:REQ, DramOdt:REQ, QrDramOdt:REQ, DramDynOdt:REQ
- DB PSO_ACTION_ODT
- DB 9
- DD Frequency
- DB Dimms
- DB QrDimms
- DB DramOdt
- DB QrDramOdt
- DB DramDynOdt
-ENDM
-
-ACTION_ADDRTMG MACRO Frequency:REQ, DimmConfig:REQ, AddrTmg:REQ
- DB PSO_ACTION_ADDRTMG
- DB 10
- DD Frequency
- DW DimmConfig
- DD AddrTmg
-ENDM
-
-ACTION_ODCCTRL MACRO Frequency:REQ, DimmConfig:REQ, OdcCtrl:REQ
- DB PSO_ACTION_ODCCONTROL
- DB 10
- DD Frequency
- DW DimmConfig
- DD OdcCtrl
-ENDM
-
-ACTION_SLEWRATE MACRO Frequency:REQ, DimmConfig:REQ, SlewRate:REQ
- DB PSO_ACTION_SLEWRATE
- DB 10
- DD Frequency
- DW DimmConfig
- DD SlewRate
-ENDM
-
-ACTION_SPEEDLIMIT MACRO DimmConfig:REQ, Dimms:REQ, SpeedLimit15:REQ, SpeedLimit135:REQ, SpeedLimit125:REQ
- DB PSO_ACTION_SPEEDLIMIT
- DB 9
- DW DimmConfig
- DB Dimms
- DW SpeedLimit15
- DW SpeedLimit135
- DW SpeedLimit125
-ENDM
-
-; *****************************************************************************************
-; *
-; * END OF CONDITIONAL OVERRIDE TABLE MACROS
-; *
-; *****************************************************************************************
-; *****************************************************************************************
-; *
-; * TABLE DRIVEN OVERRIDE MACROS
-; *
-; *****************************************************************************************
-; Configuration sub-descriptors
-CONFIG_GENERAL EQU 0
-CONFIG_SPEEDLIMIT EQU 1
-CONFIG_RC2IBT EQU 2
-CONFIG_DONT_CARE EQU 3
-Config_Type TEXTEQU <DWORD>
-;
-; Configuration Macros
-;
-TBLDRV_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Frequency:REQ, DimmVolt:REQ, DimmConfig:REQ
- DB PSO_TBLDRV_CONFIG
- DB 9
- DB CONFIG_GENERAL
- DB DimmPerCH
- DB DimmVolt
- DD Frequency
- DW DimmConfig
-ENDM
-
-TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Dimms:REQ, NumOfSR:REQ, NumOfDR:REQ, NumOfQR:REQ, NumOfLRDimm:REQ
- DB PSO_TBLDRV_CONFIG
- DB 7
- DB CONFIG_SPEEDLIMIT
- DB DimmPerCH
- DB Dimms
- DB NumOfSR
- DB NumOfDR
- DB NumOfQR
- DB NumOfLRDimm
-ENDM
-
-TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Frequency:REQ, DimmVolt:REQ, DimmConfig:REQ, NumOfReg:REQ
- DB PSO_TBLDRV_CONFIG
- DB 10
- DB CONFIG_RC2IBT
- DB DimmPerCH
- DB DimmVolt
- DD Frequency
- DW DimmConfig
- DB NumOfReg
-ENDM
-;
-; Overriding Macros
-;
-TBLDRV_CONFIG_ENTRY_SPEEDLIMIT MACRO SpeedLimit1_5:REQ, SpeedLimit1_35:REQ, SpeedLimit1_25:REQ
- DB PSO_TBLDRV_SPEEDLIMIT
- DB 6
- DW SpeedLimit1_5
- DW SpeedLimit1_35
- DW SpeedLimit1_25
-ENDM
-
-TBLDRV_CONFIG_ENTRY_ODT_RTTNOM MACRO TgtCS:REQ, RttNom:REQ
- DB PSO_TBLDRV_ODT_RTTNOM
- DB 2
- DB TgtCS
- DB RttNom
-ENDM
-
-TBLDRV_CONFIG_ENTRY_ODT_RTTWR MACRO TgtCS:REQ, RttWr:REQ
- DB PSO_TBLDRV_ODT_RTTWR
- DB 2
- DB TgtCS
- DB RttWr
-ENDM
-
-TBLDRV_CONFIG_ENTRY_ODTPATTERN MACRO RdODTCSHigh:REQ, RdODTCSLow:REQ, WrODTCSHigh:REQ, WrODTCSLow:REQ
- DB PSO_TBLDRV_ODTPATTERN
- DB 16
- DD RdODTCSHigh
- DD RdODTCSLow
- DD WrODTCSHigh
- DD WrODTCSLow
-ENDM
-
-TBLDRV_CONFIG_ENTRY_ADDRTMG MACRO AddrTmg:REQ
- DB PSO_TBLDRV_ADDRTMG
- DB 4
- DD AddrTmg
-ENDM
-
-TBLDRV_CONFIG_ENTRY_ODCCTRL MACRO OdcCtrl:REQ
- DB PSO_TBLDRV_ODCCTRL
- DB 4
- DD OdcCtrl
-ENDM
-
-TBLDRV_CONFIG_ENTRY_SLOWACCMODE MACRO SlowAccMode:REQ
- DB PSO_TBLDRV_SLOWACCMODE
- DB 1
- DB SlowAccMode
-ENDM
-
-TBLDRV_CONFIG_ENTRY_RC2_IBT MACRO TgtDimm:REQ, IBT:REQ
- DB PSO_TBLDRV_RC2_IBT
- DB 2
- DB TgtDimm
- DB IBT
-ENDM
-
-TBLDRV_OVERRIDE_MR0_CL MACRO RegValOfTcl:REQ, MR0CL13:REQ, MR0CL0:REQ
- DB PSO_TBLDRV_CONFIG
- DB 1
- DB CONFIG_DONT_CARE
- DB PSO_TBLDRV_MR0_CL
- DB 3
- DB RegValOfTcl
- DB MR0CL13
- DB MR0CL0
-ENDM
-
-TBLDRV_OVERRIDE_MR0_WR MACRO RegValOfTwr:REQ, MR0WR:REQ
- DB PSO_TBLDRV_CONFIG
- DB 1
- DB CONFIG_DONT_CARE
- DB PSO_TBLDRV_MR0_WR
- DB 2
- DB RegValOfTcl
- DB MR0WR
-ENDM
-
-TBLDRV_OVERRIDE_RC10_OPSPEED MACRO Frequency:REQ, MR10OPSPEED:REQ
- DB PSO_TBLDRV_CONFIG
- DB 1
- DB CONFIG_DONT_CARE
- DB PSO_TBLDRV_RC10_OPSPEED
- DB 5
- DD Frequency
- DB MR10OPSPEED
-ENDM
-
-TBLDRV_CONFIG_ENTRY_LRDMM_IBT MACRO F0RC8:REQ, F1RC0:REQ, F1RC1:REQ, F1RC2:REQ
- DB PSO_TBLDRV_LRDIMM_IBT
- DB 4
- DB F0RC8
- DB F1RC0
- DB F1RC1
- DB F1RC2
-ENDM
-
-TBLDRV_CONFIG_ENTRY____TRAINING MACRO Training__Mode:REQ
- DB PSO_TBLDRV____TRAINING
- DB 1
- DB Training__Mode
-ENDM
-
-;
-; Macros for removing entries
-;
-INVALID_CONFIG_FLAG EQU 8000h
-
-TBLDRV_INVALID_CONFIG MACRO
- DB PSO_TBLDRV_INVALID_TYPE
- DB 0
-ENDM
-; *****************************************************************************************
-; *
-; * END OF TABLE DRIVEN OVERRIDE MACROS
-; *
-; ***************************************************************************************** \ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/arch2008.asm b/src/vendorcode/amd/agesa/f15/Legacy/Proc/arch2008.asm
deleted file mode 100644
index fcc18bf278..0000000000
--- a/src/vendorcode/amd/agesa/f15/Legacy/Proc/arch2008.asm
+++ /dev/null
@@ -1,2676 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; Workfile: arch2008.asm $Revision: 50871 $ $Date: 2011-04-14 15:39:51 -0600 (Thu, 14 Apr 2011) $
-;
-; Description: ARCH2008.ASM - AGESA Architecture 2008 Wrapper Template
-;
-;*****************************************************************************
-;
-; Copyright (C) 2012 Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- .XLIST
- INCLUDE agesa.inc
- INCLUDE acwrapg.inc ; Necessary support file as part of wrapper, including but not limited to segment start/end macros.
- INCLUDE acwrap.inc ; IBVs may specify host BIOS-specific include files required when building.
- INCLUDE cpcarmac.inc
- INCLUDE bridge32.inc
- .LIST
- .586p
- .mmx
-
-
-;----------------------------------------------------------------------------
-; Local definitions
-;----------------------------------------------------------------------------
-
-sOemCallout STRUCT
- FuncName DD ? ; Call out function name
- FuncPtr DW ? ; Call out function pointer
-sOemCallout ENDS
-
-sOemEventHandler STRUCT
- ClassCode DD ? ; AGESA event log sub-class code
- FuncPtr DW ? ; Event handler function pointer
-sOemEventHandler ENDS
-
-;; A typical legacy BIOS implementation may require the E000 and F000 segments
-;; to be cached.
-EXE_CACHE_REGION_BASE_0 EQU 0E0000h
-EXE_CACHE_REGION_SIZE_0 EQU 20000h
-
-;; In this sample implementation, the B1 and B2 images are placed next to each
-;; other in the BIOS ROM to help with the maximization of cached code.
-EXE_CACHE_REGION_BASE_1 EQU AGESA_B1_ADDRESS
-EXE_CACHE_REGION_SIZE_1 EQU 40000h
-
-;; The third region is not needed in our example.
-EXE_CACHE_REGION_BASE_2 EQU 0
-EXE_CACHE_REGION_SIZE_2 EQU 0
-
-
-;----------------------------------------------------------------------------
-; PERSISTENT SEGMENT
-; This segment is required to be present throughout all BIOS execution.
-;----------------------------------------------------------------------------
-
-AMD_PERSISTENT_START
-
-
-;----------------------------------------------------------------------------
-; Instantiate the global descriptor table
-;----------------------------------------------------------------------------
-
-AMD_BRIDGE_32_GDT AMD_GDT ; Instantiate the global descriptor table
- ; required by the push-high mechanism.
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the persistent segment
-;----------------------------------------------------------------------------
-
-;+-------------------------------------------------------------------------
-;
-; AmdDfltRet
-;
-; Entry:
-; None
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Near stub procedure. Simply perform a retn instruction.
-;
-EXTERN AmdDfltRet:NEAR
-
-
-;+-------------------------------------------------------------------------
-;
-; AmdDfltRetFar
-;
-; Entry:
-; None
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Far stub procedure. Simply perform a retf instruction.
-;
-EXTERN AmdDfltRetFar:FAR
-
-
-;----------------------------------------------------------------------------
-; Declare the optional external routines in the persistent segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myModuleTypeMismatchHandler (Example)
-;
-; Entry:
-; ESI - Pointer to the EVENT_PARAMS structure of the failure.
-; [ESI].DataParam1 - Socket
-; [ESI].DataParam2 - DCT
-; [ESI].DataParam3 - Channel
-; [ESI].DataParam4 - 0x00000000
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure can be used to react to a memory module type
-; mismatch error discovered by the AGESA code. Actions taken
-; may include, but are not limited to:
-; Logging the event to NV for display later
-; Reset, excluding the mismatch on subsequent reboot
-; Do nothing
-;
-; Dependencies:
-; None
-;
-EXTERN myModuleTypeMismatchHandler(AmdDfltRet):NEAR
-
-;+---------------------------------------------------------------------------
-;
-; oemPlatformConfigInit (Optional)
-;
-; Entry:
-; EDI - 32-bit flat pointer to the PLATFORM_CONFIGURATION to be
-; passed in to the next AGESA entry point.
-;
-; typedef struct {
-; IN PERFORMANCE_PROFILE PlatformProfile;
-; IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList;
-; IN UINT8 CoreLevelingMode;
-; IN PLATFORM_C1E_MODES C1eMode;
-; IN UINT32 C1ePlatformData;
-; IN UINT32 C1ePlatformData1;
-; IN UINT32 C1ePlatformData2;
-; IN UINT32 C1ePlatformData3;
-; IN BOOLEAN UserOptionDmi;
-; IN BOOLEAN UserOptionPState;
-; IN BOOLEAN UserOptionSrat;
-; IN BOOLEAN UserOptionSlit;
-; IN BOOLEAN UserOptionWhea;
-; IN UINT32 PowerCeiling;
-; IN BOOLEAN PstateIndependent;
-; } PLATFORM_CONFIGURATION;
-;
-; typedef struct {
-; IN UINT8 Socket;
-; IN UINT8 Link;
-; IN UINT8 LoFreq;
-; IN UINT8 HighFreq;
-; IN PLATFORM_DEEMPHASIS_LEVEL ReceiverDeemphasis;
-; IN PLATFORM_DEEMPHASIS_LEVEL DcvDeemphasis;
-; } CPU_HT_DEEMPHASIS_LEVEL;
-;
-; typedef struct {
-; IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode;
-; IN BOOLEAN UseHtAssist;
-; IN BOOLEAN UseAtmMode;
-; IN BOOLEAN Use32ByteRefresh;
-; IN BOOLEAN UseVariableMctIsocPriority;
-; } PERFORMANCE_PROFILE;
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Provide a single hook routine to modify the parameters of a
-; PLATFORM_CONFIGURATION structure before any entry point that
-; has such a structure as an input.
-;
-; Dependencies:
-; None
-;
-; Example:
-; If your platform is running in UMA mode, the following code
-; may be added:
-; mov (PLATFORM_CONFIGURATION PTR [edi]).PlatformProfile.PlatformControlFlowMode, UmaDr
-;
-EXTERN oemPlatformConfigInit(AmdDfltRetFar):FAR
-
-;+---------------------------------------------------------------------------
-;
-; oemCallout (Optional)
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The default call out router function which resides in the same
-; segment as the push-high bridge code.
-;
-; Dependencies:
-; None
-;
-EXTERN oemCallout(AmdDfltRet):NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the persistent segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdBridge32
-;
-; Entry:
-; EDX - A Real Mode FAR pointer using seg16:Offset16 format that
-; points to a local host environment call-out router. If
-; this pointer is not equal to zero, then this pointer is
-; used as the call-out router instead of the standard
-; OemCallout. This may be useful when the call-out router
-; is not located in the same segment as the AmdBridge32 and
-; AmdCallout16 routines.
-; ESI - A Flat Mode pointer (32-bit address) that points to the
-; configuration block (AMD_CONFIG_PARAMS) for the AGESA
-; software function.
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; Execute an AGESA software function through the Push-High interface.
-;
-; Dependencies:
-; This procedure requires a stack. The host environment must use the
-; provided service function to establish the stack environment prior
-; to making the call to this procedure.
-;
-AmdBridge32 PROC FAR PUBLIC
- AMD_BRIDGE_32 AMD_GDT ; use the macro for the body
- ret
-AmdBridge32 ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdEnableStack
-;
-; Entry:
-; BX - Return address
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; SS:ESP - Points to the private stack location for this processor core.
-; ECX - Upon success, contains this processor core's stack size in bytes.
-;
-; Modified:
-; EAX, ECX, EDX, EDI, ESI, ESP, DS, ES
-;
-; Purpose:
-; This procedure is used to establish the stack within the host environment.
-;
-; Dependencies:
-; The host environment must use this procedure and not rely on any other
-; sources to create the stack region.
-;
-AmdEnableStack PROC NEAR PUBLIC
- AMD_ENABLE_STACK
- ;; EAX = AGESA_SUCCESS, The stack space has been allocated for this core.
- ;; EAX = AGESA_WARNING, The stack has already been set up. SS:ESP is set
- ;; to stack top, and ECX is the stack size in bytes.
- jmp bx
-AmdEnableStack ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdDisableStack
-;
-; Entry:
-; BX - Return address
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; EAX, ECX, EDX, ESI, ESP
-;
-; Purpose:
-; This procedure is used to remove the pre-memory stack from within the
-; host environment.
-; The exit state for the BSP is described as follows:
-; Memory region 00000-9FFFF MTRRS are set as WB memory.
-; Processor Cache is enabled (CD bit is cleared).
-; MTRRs used for execution cache are kept.
-; Cache content is flushed (invalidated without write-back).
-; Any family-specific clean-up done.
-; The exit state for the APs is described as follows:
-; Memory region 00000-9FFFF MTRRS are set as WB memory.
-; Memory region A0000-DFFFF MTRRS are set as UC IO.
-; Memory region E0000-FFFFF MTRRS are set as UC memory.
-; MTRRs used for execution cache are cleared.
-; Processor Cache is disabled (CD bit is set).
-; Top-of-Memory (TOM) set to the system top of memory as determined
-; by the memory initialization routines.
-; System lock command is enabled.
-; Any family-specific clean-up done.
-;
-; Dependencies:
-; The host environment must use this procedure and not rely on any other
-; sources to break down the stack region.
-; If executing in 16-bit code, the host environment must establish the
-; "Big Real" mode of 32-bit addressing of data.
-;
-AmdDisableStack PROC NEAR PUBLIC
- AMD_DISABLE_STACK
- ;; EAX = AGESA_SUCCESS, The stack space has been disabled for this core.
- jmp bx
-AmdDisableStack ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCallout16
-;
-; Entry:
-; [esp+8] - Func
-; [esp+12] - Data
-; [esp+16] - Configuration Block
-; [esp+4] - Return address to AGESA
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; Execute callback from the push-high interface.
-;
-; Dependencies:
-; None
-;
-AmdCallout16 PROC FAR PUBLIC ; declare the procedure
- AMD_CALLOUT_16 oemCallout ; use the macro for the body
- ret
-AmdCallout16 ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdProcessAgesaErrors (Optional)
-;
-; Entry:
-; AL - Heap status of the AGESA entry point that was just invoked.
-; EBX - AGESA image base address.
-; EDX - Segment / Offset of the appropriate callout router function.
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure is used to handle any errors that may have occurred
-; during an AGESA entry point.
-;
-; Dependencies:
-; None
-;
-AmdProcessAgesaErrors PROC FAR PUBLIC
- LOCAL localCpuInterfaceBlock:EVENT_PARAMS
-
- pushad
- xor edi, edi
- mov di, ss
- shl edi, 4
- lea esi, localCpuInterfaceBlock
- add esi, edi
-
- ; Fill default config block
- mov (EVENT_PARAMS PTR [esi]).StdHeader.Func, AMD_READ_EVENT_LOG
- mov (EVENT_PARAMS PTR [esi]).StdHeader.ImageBasePtr, ebx
- mov (EVENT_PARAMS PTR [esi]).StdHeader.AltImageBasePtr, 0
- mov (EVENT_PARAMS PTR [esi]).StdHeader.HeapStatus, al
- mov edi, SEG AmdCallout16
- shl edi, 4
- add edi, OFFSET AmdCallout16
- mov (EVENT_PARAMS PTR [esi]).StdHeader.CalloutPtr, edi
-
- ; Flush the event log searching for, and handling all monitored events
- xor eax, eax
- .while (eax == 0)
- push edx
- call AmdBridge32
- pop edx
- .if (eax == AGESA_SUCCESS)
- mov eax, (EVENT_PARAMS PTR [esi]).EventInfo
- .if (eax != 0)
- lea di, cs:AgesaEventTable
-
-loopThruTable:
- cmp di, OFFSET cs:AgesaEventTableEnd
- jae unhandledEvent
-
- cmp eax, cs:[di].sOemEventHandler.ClassCode
- je FoundMatch
- add di, SIZEOF sOemEventHandler
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemEventHandler.FuncPtr
- call bx
-
-unhandledEvent:
- xor eax, eax
- .else
- mov al, 1
- .endif
- .endif
- .endw
- popad
- ret
-
-AmdProcessAgesaErrors ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the error handler table
-;----------------------------------------------------------------------------
-
-AgesaEventTable LABEL BYTE
- ;; Add entries as desired
- ;;---------
- ;; EXAMPLE
- ;;---------
- sOemEventHandler <MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, OFFSET myModuleTypeMismatchHandler>
-AgesaEventTableEnd LABEL BYTE
-
-
-AMD_PERSISTENT_END
-
-
-
-
-;----------------------------------------------------------------------------
-; RECOVERY SEGMENT
-; This segment resides in the classic 'boot-block,' and is used
-; for recovery.
-;----------------------------------------------------------------------------
-
-AMD_RECOVERY_START
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the recovery segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myReadSPDRecovery (Required for proper recovery mode operation)
-;
-; Entry:
-; ESI - Pointer to an AGESA_READ_SPD_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT8 SocketId;
-; IN UINT8 MemChannelId;
-; IN UINT8 DimmId;
-; IN OUT UINT8 *Buffer;
-; IN OUT MEM_DATA_STRUCT *MemData;
-; } AGESA_READ_SPD_PARAMS;
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS Indicates the SPD block for the indicated
-; DIMM was read successfully.
-; AGESA_BOUNDS_CHK The specified DIMM is not present.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function and no memory initialized.
-; AGESA_ERROR The DIMM SPD read process has generated
-; communication errors.
-;
-; Modified:
-; None
-;
-; Purpose:
-; This call out reads a block of memory SPD data and places it
-; into the provided buffer.
-;
-; Dependencies:
-; None
-;
-EXTERN myReadSPDRecovery:NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the recovery segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitResetWrapper
-;
-; Entry:
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; A minimal initialization of the processor core is performed. This
-; procedure must be called by all processor cores. The code path
-; separates the BSP from the APs and performs a separate and appropriate
-; list of tasks for each class of core.
-; For the BSP, the following actions are performed:
-; Internal heap sub-system initialization
-; Primary non-coherent HyperTransportT link initialization
-; Return to the host environment to test for Recovery Mode.
-; The AP processor cores do not participate in the recovery process.
-; However, they execute this routine after being released to execute
-; by the BSP during the main boot process. Their actions include the
-; following:
-; Internal heap sub-system initialization
-; Proceed to a wait loop waiting for commands from the BSP
-;
-; For the cache regions, up to three regions of execution cache can be
-; allocated following the following rules:
-; 1. Once a region is allocated, it cannot be de-allocated. However, it
-; can be expanded.
-; 2. At most, two of the three regions can be located above 1 MByte. A
-; region failing this rule is ignored.
-; 3. All region addresses must be at or above the 0x000D0000 linear
-; address. A region failing this rule is ignored.
-; 4. The address is aligned on a 32-KByte boundary. Starting addresses
-; is rounded down to the nearest 32-Kbyte boundary.
-; 5. The execution cache size must be a multiple of 32 KByte. Size is
-; rounded up to the next multiple of 32 KByte.
-; 6. A region must not span either the 1-MByte boundary or the 4-GByte
-; boundary. Allocated size is truncated to not span the boundary.
-; 7. The granted cached execution regions, address, and size are calculated
-; based on the available cache resources of the processor core.
-; Allocations are made up to the limit of cache available on the
-; installed processor.
-; Warning: Enabling instruction cache outside of this interface can cause
-; data corruption.
-;
-; Dependencies:
-; This procedure is expected to be executed soon after a system reset
-; for the main boot path or resume path of execution.
-;
-; This procedure requires a stack.
-;
-; Because the heap system is not yet operational at the point of the
-; interface call, the host environment must allocate the storage for
-; the AMD_RESET_PARAMS structure before making the first call to
-; AmdCreateStruct. This is the ByHost method of allocation.
-;
-AmdInitResetWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
- local localResetParams:AMD_RESET_PARAMS
-
- pushad
-
- ; Prepare for the call to initialize the input parameters for AmdInitReset
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B1_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- ; Use the 'ByHost' allocation method because the heap has not been initialized as of yet.
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RESET
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, ByHost
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, sizeof AMD_RESET_PARAMS
- lea edx, localResetParams
- add edx, eax
- push edx
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr, edx
- mov dx, SEG AmdCalloutRouterRecovery
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterRecovery
- push edx
- call AmdBridge32
- pop edx
- pop esi
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- ; Allocate the execution cache to maximize the amount of code in ROM that is cached.
- ; Placing the B1 and B2 images near one another is a good way to ensure the AGESA code
- ; is cached.
- mov (AMD_RESET_PARAMS ptr [esi]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_0
- mov (AMD_RESET_PARAMS ptr [esi]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_0
- mov (AMD_RESET_PARAMS ptr [esi + sizeof EXECUTION_CACHE_REGION]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_1
- mov (AMD_RESET_PARAMS ptr [esi + sizeof EXECUTION_CACHE_REGION]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_1
- mov (AMD_RESET_PARAMS ptr [esi + (2 * sizeof EXECUTION_CACHE_REGION)]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_2
- mov (AMD_RESET_PARAMS ptr [esi + (2 * sizeof EXECUTION_CACHE_REGION)]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_2
-
- ; Call in to the AmdInitReset entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS Early initialization completed successfully.
- ;; AGESA_WARNING One or more of the execution cache allocation
- ;; rules were violated, but an adjustment was made
- ;; and space was allocated.
- ;; AGESA_ERROR One or more of the execution cache allocation rules
- ;; were violated, which resulted in a requested cache
- ;; region to not be allocated.
- ;; The storage space allocated for the AMD_RESET_PARAMS
- ;; structure is insufficient.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_RESET_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B1_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
-
- ;; Here are what the MTRRs should look like based off of the CacheRegions specified above:
-
- ;; Fixed-Range MTRRs
- ;; Name Address Value
- ;; ---------------- -------- ----------------
- ;; MTRRfix4k_E0000 0000026C 0505050505050505
- ;; MTRRfix4k_E8000 0000026D 0505050505050505
- ;; MTRRfix4k_F0000 0000026E 0505050505050505
- ;; MTRRfix4k_F8000 0000026F 0505050505050505
- ;; MTRRdefType 000002FF 0000000000000C00
- ;;
- ;; Variable-Range MTRRs and IO Range
- ;; MTRRphysBase(n) MTRRphysMask(n)
- ;; ----------------- -----------------
- ;; n=0 0000000000000000 0000000000000000
- ;; n=1 0000000000000000 0000000000000000
- ;; n=2 0000000000000000 0000000000000000
- ;; n=3 0000000000000000 0000000000000000
- ;; n=4 0000000000000000 0000000000000000
- ;; n=5 Heap Base (Varies by core) 0000FFFFFFFF0800
- ;; n=6 AGESA_B1_ADDRESS | 6 0000FFFFFFFC0800
- ;; n=7 0000000000000000 0000000000000000
-
-
- ;; Because the allocation method is 'ByHost,' the call to AMD_RELEASE_STRUCT is
- ;; not necessary. Stack space reclamation is left up to the host BIOS.
-
- popad
- ret
-
-
-AmdInitResetWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitRecoveryWrapper
-;
-; Entry:
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Perform a minimum initialization of the processor and memory to
-; support a recovery mode flash ROM update.
-; For the BSP, the following actions are performed:
-; Configuration of CPU core for recovery process
-; Minimal initialization of some memory
-; The AP processor cores do not participate in the recovery process.
-; No actions or tasks are performed by the AP cores for this time point.
-;
-; Dependencies:
-; This procedure requires a stack. The host environment must use one of
-; the provided service functions to establish the stack environment prior
-; to making the call to this procedure.
-;
-AmdInitRecoveryWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitRecovery
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B1_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RECOVERY
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterRecovery
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterRecovery
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
-
- ; Call in to the AmdInitRecovery entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_WARNING One or more of the allocation rules were violated,
- ;; but an adjustment was made and space was allocated.
- ;; AGESA_ERROR One or more of the allocation rules were violated,
- ;; which resulted in a requested cache region to not be
- ;; allocated.
- ;; AGESA_FATAL No memory was found in the system.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_RECOVERY_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B1_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitRecovery
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-AmdInitRecoveryWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCalloutRouterRecovery
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The call out router function for AmdInitReset and
-; AmdInitRecovery.
-;
-; Dependencies:
-; None
-;
-AmdCalloutRouterRecovery PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
- xor ax, ax
- mov ds, ax
- mov es, ax
- lea di, cs:CalloutRouterTableRecovery
- mov eax, AGESA_UNSUPPORTED
-
-loopThruTable:
- cmp di, OFFSET cs:CalloutRouterTableRecoveryEnd
- jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
- cmp ecx, cs:[di].sOemCallout.FuncName
- je FoundMatch
- add di, SIZEOF sOemCallout
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemCallout.FuncPtr
- call bx
-
-amdCpuCalloutExit:
- ret
-AmdCalloutRouterRecovery ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the callout dispatch table for the recovery segment
-;----------------------------------------------------------------------------
-
-CalloutRouterTableRecovery LABEL BYTE
- ;; Standard B1 implementations only need the SPD reader call out function to be implemented.
- sOemCallout <AGESA_READ_SPD, OFFSET myReadSPDRecovery>
-CalloutRouterTableRecoveryEnd LABEL BYTE
-
-
-AMD_RECOVERY_END
-
-
-
-;----------------------------------------------------------------------------
-; PRE-MEMORY SEGMENT
-; This segment must be uncompressed in the ROM image.
-;----------------------------------------------------------------------------
-
-AMD_PREMEM_START
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the recovery segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myReadSPDPremem (Required)
-;
-; Entry:
-; ESI - Pointer to an AGESA_READ_SPD_PARAMS structure
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT8 SocketId;
-; IN UINT8 MemChannelId;
-; IN UINT8 DimmId;
-; IN OUT UINT8 *Buffer;
-; IN OUT MEM_DATA_STRUCT *MemData;
-; } AGESA_READ_SPD_PARAMS;
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS Indicates the SPD block for the indicated
-; DIMM was read successfully.
-; AGESA_BOUNDS_CHK The specified DIMM is not present.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function and no memory initialized.
-; AGESA_ERROR The DIMM SPD read process has generated
-; communication errors.
-;
-; Modified:
-; None
-;
-; Purpose:
-; This call out reads a block of memory SPD data and places it
-; into the provided buffer.
-;
-; Dependencies:
-; None
-;
-EXTERN myReadSPDPremem:NEAR
-
-;+-------------------------------------------------------------------------
-;
-; AmdDfltRetPremem
-;
-; Entry:
-; None
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Near stub procedure in the prememory segment. Simply perform a
-; retn instruction.
-;
-EXTERN AmdDfltRetPremem:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myDoReset (Required)
-;
-; Entry:
-; EDX - Reset type
-; 1 - Warm reset whenever
-; 2 - Cold reset whenever
-; 3 - Warm reset immediately
-; 4 - Cold reset immediately
-; ESI - Pointer to an AMD_CONFIG_PARAMS structure.
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function.
-;
-; Modified:
-; None
-;
-; Purpose:
-; This host environment function must initiate the specified type
-; of system reset.
-;
-; Implementation of this function by the host environment is
-; REQUIRED. Some host environments may record this as a request
-; allowing other elements in the system to perform some additional
-; tasks before the actual reset is issued.
-;
-; Dependencies:
-; The AMD processor contains 3 bits (BiosRstDet[2:0]) in a PCI
-; register (F0x6C Link Initialization Control Register) that
-; indicate the reset status. These bits are reserved for use by
-; the AGESA software and should not be modified by the host
-; environment.
-;
-EXTERN myDoReset:NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myGetNonVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; None
-;
-; Exit:
-; EBX - Pointer to the non-volatile S3 context block
-; ECX - Size in bytes of the non-volatile S3 context block
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must return the pointer to the data
-; saved during the mySaveNonVolatileS3Context routine.
-;
-; Dependencies:
-; None
-;
-EXTERN myGetNonVolatileS3Context:NEAR
-
-
-;----------------------------------------------------------------------------
-; Declare the optional external routines in the prememory segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myAgesaHookBeforeExitSelfRefresh (Optional)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 44h
-; ESI - Pointer to a data structure containing the memory information
-;
-; Exit:
-; After returning control to AGESA, AGESA will display: - AGESA_TESTPOINT - 45h
-; EAX - Contains the AGESA_STATUS return code
-; AGESA_SUCCESS The function has completed successfully
-; AGESA_UNSUPPORTED This function is not implemented by the host environment
-; AGESA_WARNING A non-critical issue has occued in the host environment
-;
-; Modified:
-; None
-;
-; Purpose:
-; General purpose hook called before the exiting self refresh
-; This procedure is called once per channel
-;
-; Implementation of this function is optional for the host environment
-; This call-out is an opportunity for the host environment to make dynamic
-; modifications to the memory timing settings specific to the board or host
-; environment before exiting self refresh on S3 resume
-;
-; Dependencies:
-; This procedure is called before the exit self refresh bit is set in the resume
-; sequence. The host environment must initiate the OS restart process. This procedure
-; requires a stack. The host environment must establish the stack environment prior
-; to making the call to this procedure
-;
-EXTERN myAgesaHookBeforeExitSelfRefresh(AmdDfltRetPremem):NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myHookBeforeDramInit (Optional)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 40h
-; ESI - Pointer to a data structure containing the memory information
-;
-; Exit:
-; After returning control to AGESA, AGESA will display - AGESA_TESTPOINT - 41h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This function is not implemented by the host environment
-;
-; Modified:
-; None
-;
-; Purpose:
-; General-purpose hook called before the DRAM_Init bit is set. Called
-; once per MCT
-;
-; Implementation of this function is optional for the host environment
-; This call-out is an opportunity for the host environment to make
-; dynamic modifications to the memory timing settings specific to the
-; board or host environment
-;
-; Dependencies:
-; None
-;
-EXTERN myHookBeforeDramInit(AmdDfltRetPremem):NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myHookBeforeDQSTraining (Optional)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 42h
-; ESI - Pointer to a data structure containing the memory information.
-;
-; Exit:
-; After returning control to AGESA, AGESA will display - AGESA_TESTPOINT - 43h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This function is not implemented by the
-; host environment.
-;
-; Modified:
-; None
-;
-; Purpose:
-; General-purpose hook called just before the memory training processes
-; begin. Called once per MCT.
-;
-; Implementation of this function is optional for the host environment.
-; This call-out is an opportunity for the host environment to make
-; dynamic modifications to the memory timing settings specific to the
-; board or host environment.
-;
-; The host environment may also use this call-out for some board-
-; specific features that should be activated at this time point,
-; such as:
-; Low voltage DIMMs-the host environment should set the recommended
-; voltages found in the memory data structure for each memory
-; channel. This needs to occur before training begins.
-;
-; Dependencies:
-; None
-;
-EXTERN myHookBeforeDQSTraining(AmdDfltRetPremem):NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the prememory segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitEarlyWrapper
-;
-; Entry:
-; On Entry to "AmdInitEarly" AGESA will display AGESA_TESTPOINT - C4h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitEarly" AGESA will display AGESA_TESTPOINT - C5h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; A full initialization of the processor is performed. Action details
-; differ for the BSP and AP processor cores.
-; For the BSP, the following actions are performed:
-; Full HyperTransportT link initialization, coherent and non-coherent
-; Processor register loading
-; Microcode patch load
-; Errata workaround processing
-; Launch all processor cores
-; Configure the processor power management capabilities
-; Request a warm reset if needed
-; For the AP, the following actions are performed:
-; Processor register loading
-; Microcode patch load
-; Errata workaround processing
-; Configure the processor power management capabilities
-;
-; Dependencies:
-; This procedure is expected to be called before main memory initialization
-; and before the system warm reset. Prior to this, the basic configuration
-; done by the AmdInitReset routine must be completed.
-;
-; This procedure requires a stack. The host environment must use one of the
-; provided service functions to establish the stack environment prior to
-; making the call to this procedure.
-;
-; The processes performed at this time point require communication between
-; processor cores.
-;
-; The host environment must recognize that all processor cores are running
-; in parallel and avoid activities that might interfere with the core-to-core
-; communication, such as modifying the MTRR settings or writing to the APIC
-; registers.
-;
-AmdInitEarlyWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitEarly
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_EARLY
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPremem
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPremem
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + (3 * (SIZEOF EXECUTION_CACHE_REGION)))
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitEarly entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ALERT An HyperTransportT link CRC error was observed.
- ;; AGESA_WARNING One of more of the allocation rules were violated,
- ;; but an adjustment was made and space was allocated.
- ;; Or a HyperTransport device does not have the expected
- ;; capabilities, or unusable redundant HyperTransport
- ;; links were found.
- ;; AGESA_ERROR One or more of the allocation rules were violated, which
- ;; resulted in a requested cache region to not be allocated.
- ;; Or, a HyperTransport device failed to initialize.
- ;; AGESA_CRITICAL An illegal or unsupported mixture of processor types was
- ;; found, or the processors installed were found to have an
- ;; insufficient MP capability rating for this platform.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_EARLY_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitEarly
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitEarlyWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitPostWrapper
-;
-; Entry:
-; On Entry to "AmdInitPost" AGESA will display AGESA_TESTPOINT - C6h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitPost" AGESA will display AGESA_TESTPOINT - C7h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The main system memory is located, initialized, and brought on-line.
-; The processor(s) are prepared for full operation and control by the
-; host environment. Action details differ for the BSP and AP processor
-; cores.
-; For the BSP, the following actions are performed:
-; Full memory initialization and configuration. BSP is the master for
-; this process and may delegate some tasks to APs.
-; AP collection of data for use later.
-; Transfer the HOBs including the artifact data out of the pre-memory
-; cache storage into a temporary holding buffer in the main memory.
-; Check the BIST status of the BSP
-; Shut down the APs.
-; Prepare for the host environment to begin main boot activity.
-; Disable the pre-memory stack.
-; For the APs, the following actions are performed:
-; Report core identity information.
-; Execute indicated memory initialization processes as directed.
-; Check the BIST status of the AP
-; Disable the pre-memory stack.
-; Prepare to halt, giving control to host environment.
-; The entire range of system memory is enabled for Write-Back cache.
-; The fixed MTRRs and the variable MTRRs[7:6] are not changed in order
-; to leave in place any flash ROM region currently set for Write-Protect
-; execution cache.
-;
-; Dependencies:
-; This procedure is called after the host environment has determined that
-; a normal boot to operating system should be performed after any system
-; warm reset is completed and after the configuration done by AmdInitEarly
-; has completed.
-;
-; This procedure requires a stack. The host environment must use one of the
-; provided service functions to establish the stack environment prior to
-; making the call to this procedure.
-;
-; The processes performed at this time point require communication between
-; processor cores. The host environment must recognize that all processor
-; cores are running in parallel and avoid activities that might interfere
-; with the core-to-core communication, such as modifying the MTRR settings
-; or writing to the APIC registers.
-;
-AmdInitPostWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitPost
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_POST
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPremem
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPremem
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitPost entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ALERT A BIST error was found on one of the cores.
- ;; AGESA_WARNING HT Assist feature is running sub-optimally.
- ;; AGESA_FATAL Memory initialization failed.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_POST_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitPost
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitPostWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitResumeWrapper
-;
-; Entry:
-; On Entry to "AmdInitResume" AGESA will display AGESA_TESTPOINT - D0h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitResume" AGESA will display AGESA_TESTPOINT - D1h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure initializes or re-initializes the silicon components
-; for the resume boot path. For the processor, main memory is brought
-; out of self-refresh mode. This procedure will use the context data
-; in the NvStorage area of the input structure to re-start the main
-; memory. The host environment must fill the AMD_S3_PARAMS NvStorage
-; and VolatileStorage pointers and related size elements to describe
-; the location of the context data. Note that for this procedure, the
-; two data areas do not need to be contained in one buffer zone, they
-; can be anywhere in the accessible memory address space. If the host
-; environment uses a non-volatile storage device accessed on the system
-; address bus such as flashROM, then the context data does not need to
-; be moved prior to this call. If the host environment uses a non-
-; volatile storage device not located on the system address bus (e.g.
-; CMOS or SSEPROM) then the host environment must transfer the context
-; data to a buffer in main memory prior to calling this procedure.
-;
-; Dependencies:
-; The host environment must have determined that the system should take
-; the resume path prior to calling this procedure. The configuration
-; done by AmdInitEarly and any necessary warm reset must be complete.
-; After this procedure, execution proceeds to general system restoration.
-;
-; This procedure requires a stack. The host environment must use one of
-; the provided service functions to establish the stack environment prior
-; to making the call to this procedure.
-;
-AmdInitResumeWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitResume
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RESUME
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPremem
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPremem
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
- call oemPlatformConfigInit
-
- call myGetNonVolatileS3Context
- mov (AMD_RESUME_PARAMS ptr [esi]).S3DataBlock.NvStorage, ebx
- mov (AMD_RESUME_PARAMS ptr [esi]).S3DataBlock.NvStorageSize, ecx
-
- ; Call in to the AmdInitResume entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS Re-initialization has been completed successfully.
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_RESUME_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
-
- ; Allow AGESA to free the space used by AmdInitResume
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitResumeWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCalloutRouterPremem
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The call out router function for AmdInitEarly,
-; AmdInitPost, and AmdInitResume.
-;
-; Dependencies:
-; None
-;
-AmdCalloutRouterPremem PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
- xor ax, ax
- mov ds, ax
- mov es, ax
- lea di, cs:CalloutRouterTablePremem
- mov eax, AGESA_UNSUPPORTED
-
-loopThruTable:
- cmp di, OFFSET cs:CalloutRouterTablePrememEnd
- jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
- cmp ecx, cs:[di].sOemCallout.FuncName
- je FoundMatch
- add di, SIZEOF sOemCallout
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemCallout.FuncPtr
- call bx
-
-amdCpuCalloutExit:
- ret
-AmdCalloutRouterPremem ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the callout dispatch table for the prememory segment
-;----------------------------------------------------------------------------
-
-CalloutRouterTablePremem LABEL BYTE
- ;; Add entries as desired.
- sOemCallout <AGESA_READ_SPD, OFFSET myReadSPDPremem>
- sOemCallout <AGESA_HOOKBEFORE_DRAM_INIT, OFFSET myHookBeforeDramInit>
- sOemCallout <AGESA_HOOKBEFORE_DQS_TRAINING, OFFSET myHookBeforeDQSTraining>
- sOemCallout <AGESA_HOOKBEFORE_EXIT_SELF_REF, OFFSET myAgesaHookBeforeExitSelfRefresh>
- sOemCallout <AGESA_DO_RESET, OFFSET myDoReset>
- sOemCallout <AGESA_EXTERNAL____TRAIN_VREF_CHANGE, OFFSET my__TrainVrefChange>
-CalloutRouterTablePrememEnd LABEL BYTE
-
-
-
-AMD_PREMEM_END
-
-
-;----------------------------------------------------------------------------
-; POST SEGMENT
-; This segment may be decompressed and run from system RAM.
-;----------------------------------------------------------------------------
-
-AMD_POST_START
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the POST segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myAllocateBuffer (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E2h
-; ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 BufferLength;
-; IN UINT32 BufferHandle;
-; OUT VOID *BufferPointer;
-; } AGESA_BUFFER_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E3h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The requested size of memory has been
-; successfully allocated.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function.
-; AGESA_ERROR Less than the requested amount of memory
-; was allocated.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of memory allocation.
-; This function must allocate a buffer of the requested size or
-; larger. This function is required to be implemented by the host
-; environment.
-;
-; Dependencies:
-; The following call-outs must work together in the host system.
-; Parameters of the same name have the same function and must be
-; treated the same in each function:
-; AgesaAllocateBuffer
-; AgesaDeallocateBuffer
-; AgesaLocateBuffer
-; AgesaRunFcnOnAp
-; The host environment may need to reserve a location in the buffer
-; to store any host environment specific value(s). The returned
-; pointer must not include this reserved space. The host environment
-; on the AgesaDeallocateBuffer call needs to account for the reserved
-; space. This reserved space may be an identifier or the "handle"
-; used to identify the specific memory block.
-;
-EXTERN myAllocateBuffer:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myDeallocateBuffer (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E4h
-; ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 BufferLength;
-; IN UINT32 BufferHandle;
-; OUT VOID *BufferPointer;
-; } AGESA_BUFFER_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E5h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_BOUNDS_CHK The BufferHandle is invalid. The AGESA
-; software continues with its function.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of memory allocation.
-; This function releases a valid working buffer. This function is
-; required for the host environment to implement.
-;
-; Dependencies:
-; The following call-outs must work together in the host system.
-; Parameters of the same name have the same function and must be
-; treated the same in each function:
-; AgesaAllocateBuffer
-; AgesaDeallocateBuffer
-; AgesaLocateBuffer
-; AgesaRunFcnOnAp
-;
-EXTERN myDeallocateBuffer:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myLocateBuffer (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E6h
-; ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 BufferLength;
-; IN UINT32 BufferHandle;
-; OUT VOID *BufferPointer;
-; } AGESA_BUFFER_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E7h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_BOUNDS_CHK The presented handle is invalid or the
-; buffer could not be located.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of memory allocation.
-; This function must locate the buffer related to the indicated
-; handle and return the address of the buffer and its length.
-; This function is required to be implemented in the host
-; environment.
-;
-; Dependencies:
-; The following call-outs must work together in the host system.
-; Parameters of the same name have the same function and must be
-; treated the same in each function:
-; AgesaAllocateBuffer
-; AgesaDeallocateBuffer
-; AgesaLocateBuffer
-; AgesaRunFcnOnAp
-;
-EXTERN myLocateBuffer:NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myRunFuncOnAp (Required)
-;
-; Entry:
-; EDX - Local APIC ID of the target core.
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must route execution to the target AP and
-; have that AP call the AmdLateRunApTaskWrapper routine defined
-; above.
-;
-; Dependencies:
-; None
-;
-EXTERN myRunFuncOnAp:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; mySaveNonVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; EBX - Pointer to the non-volatile S3 context block
-; ECX - Size in bytes of the non-volatile S3 context block
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must save the non-volatile data to an area
-; that will not lose context while in the ACPI S3 sleep state, but
-; cannot be placed in system RAM. This data will need to be
-; available during the call to AmdInitResume.
-;
-; Dependencies:
-; None
-;
-EXTERN mySaveNonVolatileS3Context:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; mySaveVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; EBX - Pointer to the volatile S3 context block
-; ECX - Size in bytes of the volatile S3 context block
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must save the volatile data to an area
-; that will not lose context while in the ACPI S3 sleep state.
-; This data will need to be available during the call to
-; AmdS3LateRestore.
-;
-; Dependencies:
-; None
-;
-EXTERN mySaveVolatileS3Context:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myGetVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; None
-;
-; Exit:
-; EBX - Pointer to the volatile S3 context block
-; ECX - Size in bytes of the volatile S3 context block
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must return the pointer to the data
-; saved during the mySaveVolatileS3Context routine.
-;
-; Dependencies:
-; None
-;
-EXTERN myGetVolatileS3Context:NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the POST segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitEnvWrapper
-;
-; Entry:
-; On Entry to "AmdInitEnv" AGESA will display AGESA_TESTPOINT - C8h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitEnv" AGESA will display AGESA_TESTPOINT - C9h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure uses the AgesaAllocateBuffer call-out to acquire
-; permanent buffer space for the UEFI Hand-Off Blocks (HOBs). This
-; is also known as, or includes, artifact data being used by the
-; AGESA software. Upon entry to this procedure, the data is being
-; held in a temporary memory location and it must be moved to a
-; location controlled and protected by the host environment.
-;
-; These actions are performed by the BSP. The APs are not assigned
-; any tasks at this time point.
-;
-; Dependencies:
-; This procedure must be called after full memory is initialized and
-; the host environment has taken control of main memory allocation.
-; This procedure should be called before the PCI enumeration takes
-; place and as soon as possible after the host environment memory
-; allocation sub-system has started.
-;
-; This procedure requires a stack. The host environment must use one
-; of the provided service functions to establish the stack environment
-; prior to making the call to this procedure.
-;
-AmdInitEnvWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitEnv
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_ENV
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitEnv entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ERROR The artifact data could not be found or the host
- ;; environment failed to allocate sufficient buffer space.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_ENV_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitEnv
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitEnvWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitMidWrapper
-;
-; Entry:
-; On Entry to "AmdInitMid" AGESA will display AGESA_TESTPOINT - CAh
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitMid" AGESA will display AGESA_TESTPOINT - CBh
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure call performs special configuration requirements for
-; the graphics display hardware.
-;
-; These actions are performed by the BSP. The APs are not assigned any
-; tasks at this time point.
-;
-; Dependencies:
-; This procedure must be called after PCI enumeration has allocated
-; resources, but before the video BIOS call is performed.
-;
-; This procedure requires a stack. The host environment must use one
-; of the provided service functions to establish the stack environment
-; prior to making the call to this procedure.
-;
-AmdInitMidWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitMid
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_MID
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitMid entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_MID_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitMid
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-
-AmdInitMidWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitLateWrapper
-;
-; Entry:
-; On Entry to "AmdInitLate" AGESA will display AGESA_TESTPOINT - CCh
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitLate" AGESA will display AGESA_TESTPOINT - CDh
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The main purpose of this function is to generate informational
-; data tables used by the operating system. The individual tables
-; can be selected for generation through the user selection entries
-; on the input parameters.
-;
-; This routine uses the Call-Out AgesaAllocateBuffer to allocate a
-; buffer of the proper size to contain the data.
-;
-; The code path separates the BSP from the APs and perform a separate
-; and appropriate list of tasks for each class of core.
-; For the BSP, the following actions are performed:
-; Allocate buffer space for the tables.
-; Generate the table contents.
-; Make sure that the CPU is in a known good power state before
-; proceeding to boot the OS.
-; For the APs, the following actions are performed:
-; Final register settings preparing for entry to OS.
-; Establish the final PState for entry to OS.
-;
-; Dependencies:
-; This routine is expected to be executed late in the boot sequence
-; after main memory has been initialized, after PCI enumeration has
-; completed, after the host environment ACPI sub-system has started,
-; after the host environment has taken control of the APs, but just
-; before the start of OS boot.
-;
-; The host environment must provide the required call-outs listed in
-; the "Required Call-Out Procedures" section of the AGESA interface
-; specification to provide the buffer space in main memory and execute
-; code on the APs. The host environment must register the created ACPI
-; table in the main ACPI pointer tables. This may require moving the
-; generated tables to another location in memory.
-;
-; This procedure requires a stack. The host environment must establish
-; the stack environment prior to making the call to this procedure.
-; Some functions depend upon the preservation of the heap data across
-; the shift from pre-memory environment to a post-memory environment.
-; If that data was not preserved, then those functions cannot complete
-; and an error is returned.
-;
-AmdInitLateWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitLate
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_LATE
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitLate entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ALERT
- ;; AGESA_ERROR The system could not allocate the needed amount of
- ;; buffer space; or could not locate the artifact data block in
- ;; memory. Likely cause: the host environment may not have preserved
- ;; the data properly.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_LATE_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- push es
- mov ax, SEG AmdAcpiSratPointer
- mov es, ax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiSrat
- mov es:AmdAcpiSratPointer, ebx
- mov eax, DWORD PTR [ebx + 4]
- mov es:AmdAcpiSratSize, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiSlit
- mov es:AmdAcpiSlitPointer, ebx
- mov eax, DWORD PTR [ebx + 4]
- mov es:AmdAcpiSlitSize, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiPState
- mov es:AmdAcpiSsdtPointer, ebx
- mov eax, DWORD PTR [ebx + 4]
- mov es:AmdAcpiSsdtSize, eax
-
- xor eax, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiWheaMce
- mov es:AmdAcpiWheaMcePointer, ebx
- mov ax, WORD PTR [ebx]
- mov es:AmdAcpiWheaMceSize, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiWheaMce
- mov es:AmdAcpiWheaCmcPointer, ebx
- mov ax, WORD PTR [ebx]
- mov es:AmdAcpiWheaCmcSize, eax
-
- mov eax, (AMD_LATE_PARAMS ptr [esi]).DmiTable
- mov es:AmdDmiInfoPointer, eax
- pop es
-
-
- ; Allow AGESA to free the space used by AmdInitLate
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-
-AmdInitLateWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdS3SaveWrapper
-;
-; Entry:
-; On Entry to "AmdS3Save" AGESA will display AGESA_TESTPOINT - CEh
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Entry to "AmdS3Save" AGESA will display AGESA_TESTPOINT - CFh
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure saves critical registers and/or configuration
-; information for preservation across a system suspend mode. All
-; actions needed to prepare the processor for suspend mode is
-; performed, however this procedure does NOT initiate the suspend
-; process. The host environment is expected to perform that duty.
-;
-; These actions are performed by the BSP. The APs are not assigned
-; any tasks at this time point.
-;
-; The initializer routine will NULL out the save area pointers and
-; sizes. This procedure will determine the size of storage needed
-; for all the processor context, and make a call out to the environment
-; for allocation of one buffer to store all of the data. Upon exit, the
-; pointers and sizes within the AMD_S3_PARAMS structure will be updated
-; with the appropriate addresses within the buffer that was allocated.
-; The host environment is expected to then transfer the data pointed to
-; by NvStorage to a non-volatile storage area, and the data pointed to
-; by VolatileStorage to either a non-volatile storage area or system
-; RAM that retains its content across suspend.
-;
-; Dependencies:
-; The host environment must initiate the suspend process.
-;
-; This procedure requires a stack. The host environment must establish
-; the stack environment prior to making the call to this procedure.
-;
-AmdS3SaveWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdS3Save
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_S3_SAVE
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
- call oemPlatformConfigInit
-
- ; Call in to the AmdS3Save entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS All suspend duties have been completed successfully.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_S3SAVE_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- mov ecx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.NvStorageSize
- .if (ecx != 0)
- mov ebx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.NvStorage
- call mySaveNonVolatileS3Context
- .endif
-
- mov ecx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.VolatileStorageSize
- .if (ecx != 0)
- mov ebx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.VolatileStorage
- call mySaveVolatileS3Context
- .endif
-
- ; Allow AGESA to free the space used by AmdS3Save
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-
-AmdS3SaveWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdS3LateRestoreWrapper
-;
-; Entry:
-; On Entry to "AmdS3LateRestore" AGESA will display AGESA_TESTPOINT - D2h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdS3LateRestore" AGESA will display AGESA_TESTPOINT - D3h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure restores the processor state, reloads critical
-; silicon component registers, and performs any re-initialization
-; required by the silicon. This procedure will use the context data
-; in the VolatileStorage area of the input structure to restore the
-; processor registers.
-;
-; The host environment must fill the AMD_S3_PARAMS NvStorage and
-; VolatileStorage pointers and related size elements to describe
-; the location of the context data. Note that for this procedure,
-; the two data areas do not need to be contained in one buffer zone,
-; they can be anywhere in the accessible memory address space. If
-; the host environment uses a non-volatile storage device accessed
-; on the system address bus such as flashROM, then the context data
-; does not need to be moved prior to this call. If the host
-; environment uses a non-volatile storage device not located on the
-; system address bus (e.g. CMOS or SSEPROM) then the host environment
-; must transfer the context data to a buffer in main memory prior to
-; calling this procedure.
-;
-; These actions are performed by the BSP. The APs are not assigned
-; any tasks at this time point.
-;
-; Dependencies:
-; This procedure is called late in the resume sequence, after the
-; PCI control space is restored and just before resuming operating
-; system execution.
-;
-; The host environment must initiate the OS restart process.
-;
-; This procedure requires a stack. The host environment must establish
-; the stack environment prior to making the call to this procedure.
-;
-AmdS3LateRestoreWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdS3LateRestore
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_S3LATE_RESTORE
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
- call oemPlatformConfigInit
-
- call myGetVolatileS3Context
- mov (AMD_S3LATE_PARAMS ptr [esi]).S3DataBlock.VolatileStorage, ebx
- mov (AMD_S3LATE_PARAMS ptr [esi]).S3DataBlock.VolatileStorageSize, ecx
-
- ; Call in to the AmdS3LateRestore entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS All resume processes have been completed successfully.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_S3LATE_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdS3LateRestore
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-AmdS3LateRestoreWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdLateRunApTaskWrapper
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - D4h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - D5h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This entry point is tightly connected with the "AgesaRunFcnOnAp"
-; call out. The AGESA software will call the call-out "AgesaRunFcnOnAp";
-; the host environment will then call this entry point to have the AP
-; execute the requested function. This is needed late in the Post and
-; Resume branches for running an AP task since the AGESA software has
-; relinquished control of the APs to the host environment.
-;
-; Dependencies:
-; The host environment must implement the"AgesaRunFcnOnAp" call-out
-; and route execution to the target AP.
-;
-AmdLateRunApTaskWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdLateRunApTask
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_LATE_RUN_AP_TASK
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- push es
- mov ax, SEG AmdRunCodeOnApDataPointer
- mov es, ax
- mov eax, es:AmdRunCodeOnApDataPointer
- mov (AP_EXE_PARAMS PTR [esi]).RelatedDataBlock, eax
- mov eax, es:AmdRunCodeOnApDataSize
- mov (AP_EXE_PARAMS PTR [esi]).RelatedBlockLength, eax
- mov eax, es:AmdRunCodeOnApFunction
- mov (AP_EXE_PARAMS PTR [esi]).FunctionNumber, eax
- pop es
-
- ; Call in to the AmdLateRunApTask dispatcher
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- push es
- mov bx, SEG AmdRunCodeOnApStatus
- mov es, bx
- mov es:AmdRunCodeOnApStatus, eax
- pop es
-
- ; Allow AGESA to free the space used by AmdLateRunApTask
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-
-AmdLateRunApTaskWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdRunFuncOnAp (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E8h
-; EDX - Local APIC ID of the target core.
-; ESI - Pointer to an AP_EXE_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 FunctionNumber;
-; IN VOID *RelatedDataBlock;
-; IN UINT32 RelatedDataBlockLength;
-; } AP_EXE_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E9h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This is a required function, so this value
-; being returned causes a critical error
-; response value from the AGESAT software
-; function and no memory initialized.
-; AGESA_WARNING The AP did not respond.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of AP task dispatching.
-; This function must cause the indicated function code to be executed
-; upon the specified Application Processor. This procedure must be
-; executed in 32-bit mode. This function is required to be implemented
-; in the host environment.
-;
-; Dependencies:
-; The host environment must route execution to the target AP and
-; have that AP call the"AmdLateRunApTask" entry point.
-;
-AmdRunFuncOnAp PROC NEAR PUBLIC
-
- push es
- mov ax, SEG AmdRunCodeOnApDataPointer
- mov es, ax
- mov eax, (AP_EXE_PARAMS PTR [esi]).RelatedDataBlock
- mov es:AmdRunCodeOnApDataPointer, eax
- mov eax, (AP_EXE_PARAMS PTR [esi]).RelatedBlockLength
- mov es:AmdRunCodeOnApDataSize, eax
- mov eax, (AP_EXE_PARAMS PTR [esi]).FunctionNumber
- mov es:AmdRunCodeOnApFunction, eax
- mov eax, AGESA_UNSUPPORTED
- mov es:AmdRunCodeOnApStatus, eax
- pop es
-
- call myRunFuncOnAp
-
- push es
- mov ax, SEG AmdRunCodeOnApStatus
- mov es, ax
- mov eax, es:AmdRunCodeOnApStatus
- pop es
- ret
-AmdRunFuncOnAp ENDP
-
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCalloutRouterPost
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The call out router function for AmdInitEnv,
-; AmdInitMid, AmdInitLate, AmdS3Save, and
-; AmdS3LateRestore.
-;
-; Dependencies:
-; None
-;
-AmdCalloutRouterPost PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
- xor ax, ax
- mov ds, ax
- mov es, ax
- lea di, cs:CalloutRouterTablePost
- mov eax, AGESA_UNSUPPORTED
-
-loopThruTable:
- cmp di, OFFSET cs:CalloutRouterTablePostEnd
- jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
- cmp ecx, cs:[di].sOemCallout.FuncName
- je FoundMatch
- add di, SIZEOF sOemCallout
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemCallout.FuncPtr
- call bx
-
-amdCpuCalloutExit:
- ret
-AmdCalloutRouterPost ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the callout dispatch table for the POST segment
-;----------------------------------------------------------------------------
-
-CalloutRouterTablePost LABEL BYTE
- ;; Add entries as desired.
- sOemCallout <AGESA_ALLOCATE_BUFFER, OFFSET myAllocateBuffer>
- sOemCallout <AGESA_DEALLOCATE_BUFFER, OFFSET myDeallocateBuffer>
- sOemCallout <AGESA_LOCATE_BUFFER, OFFSET myLocateBuffer>
- sOemCallout <AGESA_RUNFUNC_ONAP, OFFSET AmdRunFuncOnAp>
-CalloutRouterTablePostEnd LABEL BYTE
-
-AMD_POST_END
-
-
-;----------------------------------------------------------------------------
-; CPU DATA SEGMENT
-; This segment must be writable, and present at the time that
-; AmdInitLate is run.
-;----------------------------------------------------------------------------
-
-CPU_DATASEG_START
-
- ;; Data used to store pointers for later use by the host environment.
- PUBLIC AmdAcpiSratPointer
- PUBLIC AmdAcpiSratSize
- PUBLIC AmdAcpiSlitPointer
- PUBLIC AmdAcpiSlitSize
- PUBLIC AmdAcpiSsdtPointer
- PUBLIC AmdAcpiSsdtSize
- PUBLIC AmdAcpiWheaMcePointer
- PUBLIC AmdAcpiWheaMceSize
- PUBLIC AmdAcpiWheaCmcPointer
- PUBLIC AmdAcpiWheaCmcSize
- PUBLIC AmdDmiInfoPointer
- AmdAcpiSratPointer DWORD ?
- AmdAcpiSratSize DWORD ?
- AmdAcpiSlitPointer DWORD ?
- AmdAcpiSlitSize DWORD ?
- AmdAcpiSsdtPointer DWORD ?
- AmdAcpiSsdtSize DWORD ?
- AmdAcpiWheaMcePointer DWORD ?
- AmdAcpiWheaMceSize DWORD ?
- AmdAcpiWheaCmcPointer DWORD ?
- AmdAcpiWheaCmcSize DWORD ?
- AmdDmiInfoPointer DWORD ?
-
- ;; Data used for communication between the AP and the BSP.
- PUBLIC AmdRunCodeOnApDataPointer
- PUBLIC AmdRunCodeOnApDataSize
- PUBLIC AmdRunCodeOnApFunction
- PUBLIC AmdRunCodeOnApStatus
- AmdRunCodeOnApDataPointer DWORD ?
- AmdRunCodeOnApDataSize DWORD ?
- AmdRunCodeOnApFunction DWORD ?
- AmdRunCodeOnApStatus DWORD ?
-
-CPU_DATASEG_END
-
-
-END
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/agesa.inc b/src/vendorcode/amd/agesa/f15/Legacy/agesa.inc
deleted file mode 100644
index 617be484b0..0000000000
--- a/src/vendorcode/amd/agesa/f15/Legacy/agesa.inc
+++ /dev/null
@@ -1,2989 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * Agesa structures and definitions
-; *
-; * Contains AMD AGESA core interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 60222 $ @e \$Date: 2011-10-10 23:39:36 -0600 (Mon, 10 Oct 2011) $
-;
-; ****************************************************************************
-; *
-; * Copyright (C) 2012 Advanced Micro Devices, Inc.
-; * All rights reserved.
-; *
-; * Redistribution and use in source and binary forms, with or without
-; * modification, are permitted provided that the following conditions are met:
-; * * Redistributions of source code must retain the above copyright
-; * notice, this list of conditions and the following disclaimer.
-; * * Redistributions in binary form must reproduce the above copyright
-; * notice, this list of conditions and the following disclaimer in the
-; * documentation and/or other materials provided with the distribution.
-; * * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; * its contributors may be used to endorse or promote products derived
-; * from this software without specific prior written permission.
-; *
-; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; *
-; *
-; **************************************************************************
-
-INCLUDE amd.inc
-UINT64 TEXTEQU <QWORD>
-UINT32 TEXTEQU <DWORD>
-UINT16 TEXTEQU <WORD>
-UINT8 TEXTEQU <BYTE>
-CHAR8 TEXTEQU <BYTE>
-BOOLEAN TEXTEQU <BYTE>
-POINTER TEXTEQU <DWORD>
-
- ; AGESA Types and Definitions
-
-
-
- ; AGESA BASIC CALLOUTS
- AGESA_MEM_RELEASE EQU 00028000h
-
- ; AGESA ADVANCED CALLOUTS, Processor
- AGESA_CHECK_UMA EQU 00028100h
- AGESA_DO_RESET EQU 00028101h
- AGESA_ALLOCATE_BUFFER EQU 00028102h
- AGESA_DEALLOCATE_BUFFER EQU 00028103h
- AGESA_LOCATE_BUFFER EQU 00028104h
- AGESA_RUNFUNC_ONAP EQU 00028105h
-
- ; AGESA ADVANCED CALLOUTS, HyperTransport
-
- ; AGESA ADVANCED CALLOUTS, Memory
- AGESA_READ_SPD EQU 00028140h
- AGESA_HOOKBEFORE_DRAM_INIT EQU 00028141h
- AGESA_HOOKBEFORE_DQS_TRAINING EQU 00028142h
- AGESA_READ_SPD_RECOVERY EQU 00028143h
- AGESA_HOOKBEFORE_EXIT_SELF_REF EQU 00028144h
- AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY EQU 00028145h
- AGESA_EXTERNAL____TRAIN_VREF_CHANGE EQU 00028146h
-
- ; AGESA IDS CALLOUTS
- AGESA_GET_IDS_INIT_DATA EQU 00028200h
-
- ; AGESA GNB CALLOUTS
- AGESA_GNB_PCIE_SLOT_RESET EQU 00028301h
-
- ; AGESA FCH CALLOUTS
- AGESA_FCH_OEM_CALLOUT EQU 00028401h
-
-; ------------------------------------------------------------------------
-
- ; HyperTransport Interface
-
-
-
-; -----------------------------------------------------------------------------
- ; HT DEFINITIONS AND MACROS
-
-; -----------------------------------------------------------------------------
-
-
- ; Width equates for call backs
- HT_WIDTH_8_BITS EQU 8
- HT_WIDTH_16_BITS EQU 16
- HT_WIDTH_4_BITS EQU 4
- HT_WIDTH_2_BITS EQU 2
- HT_WIDTH_NO_LIMIT EQU HT_WIDTH_16_BITS
-
- ; Frequency Limit equates for call backs which take a frequency supported mask.
- HT_FREQUENCY_LIMIT_200M EQU 1
- HT_FREQUENCY_LIMIT_400M EQU 7
- HT_FREQUENCY_LIMIT_600M EQU 1Fh
- HT_FREQUENCY_LIMIT_800M EQU 3Fh
- HT_FREQUENCY_LIMIT_1000M EQU 7Fh
- HT_FREQUENCY_LIMIT_HT1_ONLY EQU 7Fh
- HT_FREQUENCY_LIMIT_1200M EQU 0FFh
- HT_FREQUENCY_LIMIT_1400M EQU 1FFh
- HT_FREQUENCY_LIMIT_1600M EQU 3FFh
- HT_FREQUENCY_LIMIT_1800M EQU 7FFh
- HT_FREQUENCY_LIMIT_2000M EQU 0FFFh
- HT_FREQUENCY_LIMIT_2200M EQU 1FFFh
- HT_FREQUENCY_LIMIT_2400M EQU 3FFFh
- HT_FREQUENCY_LIMIT_2600M EQU 7FFFh
- HT_FREQUENCY_LIMIT_2800M EQU 27FFFh
- HT_FREQUENCY_LIMIT_3000M EQU 67FFFh
- HT_FREQUENCY_LIMIT_3200M EQU 0E7FFFh
- HT_FREQUENCY_LIMIT_3600M EQU 1E7FFFh
- HT_FREQUENCY_LIMIT_MAX EQU HT_FREQUENCY_LIMIT_3600M
- HT_FREQUENCY_NO_LIMIT EQU 0FFFFFFFFh
-
- ; Unit ID Clumping special values
- HT_CLUMPING_DISABLE EQU 00000000h
- HT_CLUMPING_NO_LIMIT EQU 0FFFFFFFFh
-
- HT_LIST_TERMINAL EQU 0FFh
- HT_LIST_MATCH_ANY EQU 0FEh
- HT_LIST_MATCH_INTERNAL_LINK EQU 0FDh
-
- ; Event Notify definitions
-
- ; Event definitions.
-
- ; Coherent subfunction events
- HT_EVENT_COH_EVENTS EQU 10001000h
- HT_EVENT_COH_NO_TOPOLOGY EQU 10011000h
- HT_EVENT_COH_OBSOLETE000 EQU 10021000h
- HT_EVENT_COH_PROCESSOR_TYPE_MIX EQU 10031000h
- HT_EVENT_COH_NODE_DISCOVERED EQU 10041000h
- HT_EVENT_COH_MPCAP_MISMATCH EQU 10051000h
-
- ; Non-coherent subfunction events
- HT_EVENT_NCOH_EVENTS EQU 10002000h
- HT_EVENT_NCOH_BUID_EXCEED EQU 10012000h
- HT_EVENT_NCOH_OBSOLETE000 EQU 10022000h
- HT_EVENT_NCOH_BUS_MAX_EXCEED EQU 10032000h
- HT_EVENT_NCOH_CFG_MAP_EXCEED EQU 10042000h
- HT_EVENT_NCOH_DEVICE_FAILED EQU 10052000h
- HT_EVENT_NCOH_AUTO_DEPTH EQU 10062000h
-
- ; Optimization subfunction events
- HT_EVENT_OPT_EVENTS EQU 10003000h
- HT_EVENT_OPT_REQUIRED_CAP_RETRY EQU 10013000h
- HT_EVENT_OPT_REQUIRED_CAP_GEN3 EQU 10023000h
- HT_EVENT_OPT_UNUSED_LINKS EQU 10033000h
- HT_EVENT_OPT_LINK_PAIR_EXCEED EQU 10043000h
-
- ; HW Fault events
- HT_EVENT_HW_EVENTS EQU 10004000h
- HT_EVENT_HW_SYNCFLOOD EQU 10014000h
- HT_EVENT_HW_HTCRC EQU 10024000h
-
- ; The Recovery HT component uses 0x10005000 for events.
- ; For consistency, we avoid that range here.
-
- HT_MAX_NC_BUIDS EQU 32
-; ----------------------------------------------------------------------------
- ; HT TYPEDEFS, STRUCTURES, ENUMS
-
-; ----------------------------------------------------------------------------
-MATCHED EQU 0 ; < The link matches the requested customization.
-POWERED_OFF EQU 1 ; < Power the link off.
-UNMATCHED EQU 2 ; < The link should be processed according to normal defaults.
-MaxFinalLinkState EQU 3 ; < Not a final link state, use for limit checking.
-FINAL_LINK_STATE TEXTEQU <DWORD>
-
- ; Swap a device from its current id to a new one.
-
-BUID_SWAP_ITEM STRUCT
- FromId UINT8 ? ; < The device responding to FromId,
- ToId UINT8 ? ; < will be moved to ToId.
-BUID_SWAP_ITEM ENDS
-
-
- ; Each Non-coherent chain may have a list of device swaps. After performing the swaps,
- ; the final in order list of device ids is provided. (There can be more swaps than devices.)
- ; The unused entries in both are filled with 0xFF.
-
-BUID_SWAP_LIST STRUCT
- Swaps BUID_SWAP_ITEM (HT_MAX_NC_BUIDS) DUP ({}) ; < The BUID Swaps to perform
- FinalIds UINT8 (HT_MAX_NC_BUIDS) DUP (?) ; < The ordered final BUIDs, resulting from the swaps
-BUID_SWAP_LIST ENDS
-
-
- ; Control Manual Initialization of Non-Coherent Chains
-
- ; This interface is checked every time a non-coherent chain is
- ; processed. BUID assignment may be controlled explicitly on a
- ; non-coherent chain. Provide a swap list. Swaps controls the
- ; BUID assignment and FinalIds provides the device to device
- ; Linking. Device orientation can be detected automatically, or
- ; explicitly. See interface documentation for more details.
-
- ; If a manual swap list is not supplied,
- ; automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
- ; based on each device's unit count.
-
-MANUAL_BUID_SWAP_LIST STRUCT
- ; Match fields
- Socket UINT8 ? ; < The Socket on which this chain is located
- Link UINT8 ? ; < The Link on the host for this chain
- ; Override fields
- SwapList BUID_SWAP_LIST {} ; < The swap list
-MANUAL_BUID_SWAP_LIST ENDS
-
-
- ; Override options for DEVICE_CAP_OVERRIDE.
-
- ; Specify which override actions should be performed. For Checks, 1 means to check the item
- ; and 0 means to skip the check. For the override options, 1 means to apply the override and
- ; 0 means to ignore the override.
-
-DEVICE_CAP_OVERRIDE_OPTIONS STRUCT
- IsCheckDevVenId UINT32 ?
-; IN UINT32 IsCheckDevVenId:1; ; < Check Match on Device/Vendor id
-; IN UINT32 IsCheckRevision:1; ; < Check Match on device Revision
-; IN UINT32 IsOverrideWidthIn:1; ; < Override Width In
-; IN UINT32 IsOverrideWidthOut:1; ; < Override Width Out
-; IN UINT32 IsOverrideFreq:1; ; < Override Frequency
-; IN UINT32 IsOverrideClumping:1; ; < Override Clumping
-; IN UINT32 IsDoCallout:1; ; < Make the optional callout
-DEVICE_CAP_OVERRIDE_OPTIONS ENDS
-
- ; Override capabilities of a device.
-
- ; This interface is checked once for every Link on every IO device.
- ; Provide the width and frequency capability if needed for this device.
- ; This is used along with device capabilities, the limit interfaces, and northbridge
- ; limits to compute the default settings. The components of the device's PCI config
- ; address are provided, so its settings can be consulted if need be.
- ; The optional callout is a catch all.
-
-DEVICE_CAP_OVERRIDE STRUCT
- ; Match fields
- HostSocket UINT8 ? ; < The Socket on which this chain is located.
- HostLink UINT8 ? ; < The Link on the host for this chain.
- Depth UINT8 ? ; < The Depth in the I/O chain from the Host.
- DevVenId UINT32 ? ; < The Device's PCI Vendor + Device ID (offset 0x00).
- Revision UINT8 ? ; < The Device's PCI Revision field (offset 0x08).
- Link UINT8 ? ; < The Device's Link number (0 or 1).
- Options DEVICE_CAP_OVERRIDE_OPTIONS {} ; < The options for this device override.
- ; Override fields
- LinkWidthIn UINT8 ? ; < modify to change the Link Width In.
- LinkWidthOut UINT8 ? ; < modify to change the Link Width Out.
- FreqCap UINT32 ? ; < modify to change the Link's frequency capability.
- Clumping UINT32 ? ; < modify to change Unit ID clumping support.
- Callout CALLOUT_ENTRY ? ; < optional call for really complex cases, or NULL.
-DEVICE_CAP_OVERRIDE ENDS
-
- ; Callout param struct for override capabilities of a device.
-
- ; If the optional callout is implemented this param struct is passed to it.
-
-DEVICE_CAP_CALLOUT_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < The header
- ; Match fields
- HostSocket UINT8 ? ; < The Socket on which this chain is located.
- HostLink UINT8 ? ; < The Link on the host for this chain.
- Depth UINT8 ? ; < The Depth in the I/O chain from the Host.
- DevVenId UINT32 ? ; < The Device's PCI Vendor + Device ID (offset 0x00).
- Revision UINT8 ? ; < The Device's PCI Revision field (offset 0x08).
- Link UINT8 ? ; < The Device's Link number (0 or 1).
- PciAddress PCI_ADDR {} ; < The Device's PCI Address.
- ; Override fields
- LinkWidthIn POINTER ? ; < modify to change the Link Width In.
- LinkWidthOut POINTER ? ; < modify to change the Link Width Out.
- FreqCap POINTER ? ; < modify to change the Link's frequency capability.
- Clumping POINTER ? ; < modify to change Unit ID clumping support.
-DEVICE_CAP_CALLOUT_PARAMS ENDS
-
- ; Limits for CPU to CPU Links.
-
- ; For each coherent connection this interface is checked once.
- ; Provide the frequency and width if needed for this Link (usually based on board
- ; restriction). This is used with CPU device capabilities and northbridge limits
- ; to compute the default settings.
-
-CPU_TO_CPU_PCB_LIMITS STRUCT
- ; Match fields
- SocketA UINT8 ? ; < One Socket on which this Link is located
- LinkA UINT8 ? ; < The Link on this Node
- SocketB UINT8 ? ; < The other Socket on which this Link is located
- LinkB UINT8 ? ; < The Link on that Node
- ; Limit fields
- ABLinkWidthLimit UINT8 ? ; < modify to change the Link Width A->B
- BALinkWidthLimit UINT8 ? ; < modify to change the Link Width B-<A
- PcbFreqCap UINT32 ? ; < modify to change the Link's frequency capability
-CPU_TO_CPU_PCB_LIMITS ENDS
-
- ; Get limits for non-coherent Links.
-
- ; For each non-coherent connection this interface is checked once.
- ; Provide the frequency and width if needed for this Link (usually based on board
- ; restriction). This is used with device capabilities, device overrides, and northbridge limits
- ; to compute the default settings.
-
-IO_PCB_LIMITS STRUCT
- ; Match fields
- HostSocket UINT8 ? ; < The Socket on which this Link is located
- HostLink UINT8 ? ; < The Link about to be initialized
- Depth UINT8 ? ; < The Depth in the I/O chain from the Host
- ; Limit fields
- DownstreamLinkWidthLimit UINT8 ? ; < modify to change the Link Width going away from processor
- UpstreamLinkWidthLimit UINT8 ? ; < modify to change the Link Width moving toward processor
- PcbFreqCap UINT32 ? ; < modify to change the Link's frequency capability
-IO_PCB_LIMITS ENDS
-
- ; Manually control bus number assignment.
-
- ; This interface is checked every time a non-coherent chain is processed.
- ; If a system can not use the auto Bus numbering feature for non-coherent chain bus
- ; assignments, this interface can provide explicit control. For each chain, provide
- ; the bus number range to use.
-
-OVERRIDE_BUS_NUMBERS STRUCT
- ; Match fields
- Socket UINT8 ? ; < The Socket on which this chain is located
- Link UINT8 ? ; < The Link on the host for this chain
- ; Override fields
- SecBus UINT8 ? ; < Secondary Bus number for this non-coherent chain
- SubBus UINT8 ? ; < Subordinate Bus number
-OVERRIDE_BUS_NUMBERS ENDS
-
-
- ; Ignore a Link.
-
- ; This interface is checked every time a coherent Link is found and then every
- ; time a non-coherent Link from a CPU is found.
- ; Any coherent or non-coherent Link from a CPU can be ignored and not used
- ; for discovery or initialization. Useful for connection based systems.
- ; (Note: not checked for IO device to IO Device Links.)
-
-IGNORE_LINK STRUCT
- ; Match fields
- Socket UINT8 ? ; < The Socket on which this Link is located
- Link UINT8 ? ; < The Link about to be initialized
- ; Customization fields
- LinkState FINAL_LINK_STATE ? ; < The link may be left unitialized, or powered off.
-IGNORE_LINK ENDS
-
-
- ; Skip reganging of subLinks.
-
- ; This interface is checked whenever two subLinks are both connected to the same CPUs.
- ; Normally, unganged sublinks between the same two CPUs are reganged.
- ; Provide a matching structure to leave the Links unganged.
-
-SKIP_REGANG STRUCT
- ; Match fields
- SocketA UINT8 ? ; < One Socket on which this Link is located
- LinkA UINT8 ? ; < The Link on this Node
- SocketB UINT8 ? ; < The other Socket on which this Link is located
- LinkB UINT8 ? ; < The Link on that Node
- ; Customization fields
- LinkState FINAL_LINK_STATE ? ; < The paired sublink may be active, or powered off.
-SKIP_REGANG ENDS
-
- ; The System Socket layout, which sockets are physically connected.
-
- ; The hardware method for Socket naming is preferred. Use this software method only
- ; if required.
-
-SYSTEM_PHYSICAL_SOCKET_MAP STRUCT
- CurrentSocket UINT8 ? ; < The socket from which this connection originates.
- CurrentLink UINT8 ? ; < The Link from the source socket connects to another socket.
- TargetSocket UINT8 ? ; < The target socket which is connected on that link.
-SYSTEM_PHYSICAL_SOCKET_MAP ENDS
-
-; ----------------------------------------------------------------------------
-
- ; This is the input structure for AmdHtInitialize.
-
-AMD_HT_INTERFACE STRUCT
- ; Basic level customization
- AutoBusStart UINT8 ? ; < For automatic bus number assignment, starting bus number usually zero.
- AutoBusMax UINT8 ? ; < For automatic bus number assignment, do not assign above max.
- AutoBusIncrement UINT8 ? ; < For automatic bus number assignment, each chain gets this many busses.
-
- ; Advanced Level Customization
- ManualBuidSwapList POINTER ? ; < Provide Manual Swap List, if any.
- DeviceCapOverrideList POINTER ? ; < Provide Device Overrides, if any.
- CpuToCpuPcbLimitsList POINTER ? ; < Provide CPU PCB Limits, if any.
- IoPcbLimitsList POINTER ? ; < Provide IO PCB Limits, if any.
- OverrideBusNumbersList POINTER ? ; < Provide manual Bus Number assignment, if any.
- ; < Use either auto bus numbering or override bus
- ; < numbers, not both.
-
- IgnoreLinkList POINTER ? ; < Provide links to ignore, if any.
- SkipRegangList POINTER ? ; < Provide links to remain unganged, if any.
-
- ; Expert Level Customization
- Topolist POINTER ? ; < Use this topology list in addition to the built in, if not NULL.
- SystemPhysicalSocketMap POINTER ?
- ; < The hardware socket naming method is preferred,
- ; < If it can't be used, this provides a software method.
-AMD_HT_INTERFACE ENDS
-
-; -----------------------------------------------------------------------------
-
- ; HT Recovery Interface
-
-
-
-; -----------------------------------------------------------------------------
-; * HT Recovery DEFINITIONS AND MACROS
-; *
-; *-----------------------------------------------------------------------------
-;
-
- ; BBHT subfunction events
- HT_EVENT_BB_EVENTS EQU 10005000h
- HT_EVENT_BB_BUID_EXCEED EQU 10015000h
- HT_EVENT_BB_DEVICE_FAILED EQU 10055000h
- HT_EVENT_BB_AUTO_DEPTH EQU 10065000h
-
-; ----------------------------------------------------------------------------
-; * HT Recovery TYPEDEFS, STRUCTURES, ENUMS
-; *
-; *----------------------------------------------------------------------------
-;
-
-
- ; The Interface structure to Recovery HT.
-
-AMD_HT_RESET_INTERFACE STRUCT
- ManualBuidSwapList POINTER ? ; < Option to manually control SB link init
- Depth UINT32 ? ; < If auto init was used this is set to the depth of the chain,
- ; < else, for manual init unmodified.
-AMD_HT_RESET_INTERFACE ENDS
-
-
-;-----------------------------------------------------------------------------
-; FCH DEFINITIONS AND MACROS
-;
-;-----------------------------------------------------------------------------
-
-; Configuration values for SdConfig
- SdDisable EQU 0 ; Disabled
- SdAmda EQU 1 ; AMDA, set 24,18,16, default
- SdDma EQU 2 ; DMA clear 24, 16, set 18
- SdPio EQU 3 ; PIO clear 24,18,16
-SD_MODE TEXTEQU <DWORD>
-
-; Configuration values for SdClockControl
- Sd50MhzTraceCableLengthWithinSixInches EQU 4 ; 50Mhz, default
- Sd40MhzTraceCableLengthSix2ElevenInches EQU 6 ; 40Mhz
- Sd25MhzTraceCableLengthEleven2TwentyfourInches EQU 7 ; 25Mhz
-SD_CLOCK_CONTROL TEXTEQU <DWORD>
-
-; Configuration values for AzaliaController
- AzAuto EQU 0 ; Auto - Detect Azalia controller automatically
- AzDisable EQU 1 ; Diable - Disable Azalia controller
- AzEnable EQU 2 ; Enable - Enable Azalia controller
-HDA_CONFIG TEXTEQU <DWORD>
-
-; Configuration values for IrConfig
- IrDisable EQU 0 ; Disable
- IrRxTx0 EQU 1 ; Rx and Tx0
- IrRxTx1 EQU 2 ; Rx and Tx1
- IrRxTx0Tx1 EQU 3 ; Rx and both Tx0,Tx1
-IR_CONFIG TEXTEQU <DWORD>
-
-; Configuration values for SataClass
- SataNativeIde EQU 0 ; Native IDE mode
- SataRaid EQU 1 ; RAID mode
- SataAhci EQU 2 ; AHCI mode
- SataLegacyIde EQU 3 ; Legacy IDE mode
- SataIde2Ahci EQU 4 ; IDE->AHCI mode
- SataAhci7804 EQU 5 ; AHCI mode as 7804 ID (AMD driver)
- SataIde2Ahci7804 EQU 6 ; IDE->AHCI mode as 7804 ID (AMD driver)
-SATA_CLASS TEXTEQU <DWORD>
-
-; Configuration values for GppLinkConfig
- PortA4 EQU 0 ; 4:0:0:0
- PortA2B2 EQU 2 ; 2:2:0:0
- PortA2B1C1 EQU 3 ; 2:1:1:0
- PortA1B1C1D1 EQU 4 ; 1:1:1:1
-GPP_LINKMODE TEXTEQU <DWORD>
-
-; Configuration values for FchPowerFail
- AlwaysOff EQU 0 ; Always power off after power resumes
- AlwaysOn EQU 1 ; Always power on after power resumes
- UsePrevious EQU 3 ; Resume to same setting when power fails
-POWER_FAIL TEXTEQU <DWORD>
-
-; Configuration values for SATA Link Speed
- Gen1 EQU 1 ; SATA port GEN1 speed
- Gen2 EQU 2 ; SATA port GEN2 speed
- Gen3 EQU 3 ; SATA port GEN3 speed
-SATA_SPEED TEXTEQU <DWORD>
-
-; Configuration values for GPIO function
- Function0 EQU 0 ; GPIO Function 1
- Function1 EQU 1 ; GPIO Function 1
- Function2 EQU 2 ; GPIO Function 2
- Function3 EQU 3 ; GPIO Function 3
-GPIO_FUN TEXTEQU <DWORD>
-
-; Configuration values for GPIO_CFG
- OwnedByEc EQU 1 ; This bit can only be written by EC
- OwnedByHost EQU 2 ; This bit can only be written by host (BIOS)
- Sticky EQU 4 ; If set, [6:3] are sticky
- PullUpB EQU 8 ; 0: Pullup enable; 1: Pullup disabled
- PullDown EQU 16 ; 0: Pulldown disabled; 1: Pulldown enable
- GpioOutEnB EQU 32 ; 0: Output enable; 1: Output disable
- GpioOut EQU 64 ; Output state when GpioOutEnB is 0
- GpioIn EQU 128 ; This bit is read only - current pin state
-CFG_BYTE TEXTEQU <DWORD>
-
-; FCH GPIO CONTROL
-GPIO_CONTROL STRUCT
- GpioPin UINT8 ? ; Gpio Pin, valid range: 0-67, 128-150, 160-228
- PinFunction GPIO_FUN ? ; Multi-function selection
- CfgByte CFG_BYTE ? ; GPIO Register value
-GPIO_CONTROL ENDS
-
-; FCH SCI MAP CONTROL
-SCI_MAP_CONTROL STRUCT
- InputPin UINT8 ? ; Input Pin, valid range 0-63
- GpeMap UINT8 ? ; Gpe Map, valid range 0-31
-SCI_MAP_CONTROL ENDS
-
-; FCH SATA PHY CONTROL
-SATA_PHY_CONTROL STRUCT
- CommonPhy BOOLEAN ? ; Common PHY or not
- Gen SATA_SPEED ? ; SATA speed
- Port UINT8 ? ; Port number, valid range: 0-7
- PhyData UINT32 ? ; SATA PHY data, valid range: 0-0xFFFFFFFF
-SATA_PHY_CONTROL ENDS
-
-;
-; FCH Component Data Structure in InitReset stage
-;
-FCH_RESET_INTERFACE STRUCT
- UmiGen2 BOOLEAN ? ; Enable Gen2 data rate of UMI
- ; FALSE - Disable Gen2
- ; TRUE - Enable Gen2
-
- SataEnable BOOLEAN ? ; SATA controller function
- ; FALSE - SATA controller is disabled
- ; TRUE - SATA controller is enabled
-
- IdeEnable BOOLEAN ? ; SATA IDE controller mode enabled/disabled
- ; FALSE - IDE controller is disabled
- ; TRUE - IDE controller is enabled
-
- GppEnable BOOLEAN ? ; Master switch of GPP function
- ; FALSE - GPP disabled
- ; TRUE - GPP enabled
-
- Xhci0Enable BOOLEAN ? ; XHCI0 controller function
- ; FALSE - XHCI0 controller disabled
- ; TRUE - XHCI0 controller enabled
-
- Xhci1Enable BOOLEAN ? ; XHCI1 controller function
- ; FALSE - XHCI1 controller disabled
- ; TRUE - XHCI1 controller enabled
-
-FCH_RESET_INTERFACE ENDS
-
-
-;
-; FCH Component Data Structure from InitEnv stage
-;
-FCH_INTERFACE STRUCT
- SdConfig SD_MODE ? ; Secure Digital (SD) controller mode
- AzaliaController HDA_CONFIG ? ; Azalia HD Audio Controller
- IrConfig IR_CONFIG ? ; Infrared (IR) Configuration
- UmiGen2 BOOLEAN ? ; Enable Gen2 data rate of UMI
- ; FALSE - Disable Gen2
- ; TRUE - Enable Gen2
- SataClass SATA_CLASS ? ; SATA controller mode
- SataEnable BOOLEAN ? ; SATA controller function
- ; FALSE - SATA controller is disabled
- ; TRUE - SATA controller is enabled
- IdeEnable BOOLEAN ? ; SATA IDE controller mode enabled/disabled
- ; FALSE - IDE controller is disabled
- ; TRUE - IDE controller is enabled
- SataIdeMode BOOLEAN ? ; Native mode of SATA IDE controller
- ; FALSE - Legacy IDE mode
- ; TRUE - Native IDE mode
- Ohci1Enable BOOLEAN ? ; OHCI controller #1 Function
- ; FALSE - OHCI1 is disabled
- ; TRUE - OHCI1 is enabled
- Ohci2Enable BOOLEAN ? ; OHCI controller #2 Function
- ; FALSE - OHCI2 is disabled
- ; TRUE - OHCI2 is enabled
- Ohci3Enable BOOLEAN ? ; OHCI controller #3 Function
- ; FALSE - OHCI3 is disabled
- ; TRUE - OHCI3 is enabled
- Ohci4Enable BOOLEAN ? ; OHCI controller #4 Function
- ; FALSE - OHCI4 is disabled
- ; TRUE - OHCI4 is enabled
- XhciSwitch BOOLEAN ? ; XHCI controller Function
- ; FALSE - XHCI is disabled
- ; TRUE - XHCI is enabled
- GppEnable BOOLEAN ? ; Master switch of GPP function
- ; FALSE - GPP disabled
- ; TRUE - GPP enabled
- FchPowerFail POWER_FAIL ? ; FCH power failure option
-FCH_INTERFACE ENDS
-
-
-; ---------------------------------------------------------------------------
-; CPU Feature related info
-; ---------------------------------------------------------------------------
- ; Build Configuration values for BLDCFG_PLATFORM_C1E_MODE
- C1eModeDisabled EQU 0 ; < Disabled
- C1eModeAuto EQU 1 ; < Auto mode enables the best C1e method for the
- ; < currently installed processor
- C1eModeHardware EQU 2 ; < Hardware method
- C1eModeMsgBased EQU 3 ; < Message-based method
- C1eModeSoftwareDeprecated EQU 4 ; < Deprecated software SMI method
- C1eModeHardwareSoftwareDeprecated EQU 5 ; < Hardware or Deprecated software SMI method
- MaxC1eMode EQU 6 ; < Not a valid value, used for verifying input
-PLATFORM_C1E_MODES TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
- CStateModeDisabled EQU 0 ; < Disabled
- CStateModeC6 EQU 1 ; < C6 State
- MaxCStateMode EQU 2 ; < Not a valid value, used for verifying input
-PLATFORM_CSTATE_MODES TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_PLATFORM_CPB_MODE
- CpbModeAuto EQU 0 ; < Auto
- CpbModeDisabled EQU 1 ; < Disabled
- MaxCpbMode EQU 2 ; < Not a valid value, used for verifying input
-PLATFORM_CPB_MODES TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_LOW_POWER_PSTATE_FOR_PROCHOT_MODE
- LOW_POWER_PSTATE_FOR_PROCHOT_AUTO EQU 0 ; < Auto
- LOW_POWER_PSTATE_FOR_PROCHOT_DISABLE EQU 1 ; < Disabled
- MAX_LOW_POWER_PSTATE_FOR_PROCHOT_MODE EQU 2 ; < Not a valid value, used for verifying input
-PLATFORM_LOW_POWER_PSTATE_MODES TEXTEQU <DWORD>
-
-;----------------------------------------------------------------------------
-; GNB PCIe configuration info
-;----------------------------------------------------------------------------
-
-GNB_EVENT_INVALID_CONFIGURATION EQU 20010000h ; User configuration invalid
-GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION EQU 20010001h ; Requested lane allocation for PCIe port can not be supported
-GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION EQU 20010002h ; Requested incorrect PCIe port device address
-GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION EQU 20010003h ; Incorrect parameter in DDI link configuration
-GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION EQU 20010004h ; Invalid with for PCIe port or DDI link
-GNB_EVENT_INVALID_LANES_CONFIGURATION EQU 20010005h ; Lane double subscribe lanes
-GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION EQU 20010006h ; Requested lane allocation for DDI link(s) can not be supported
-GNB_EVENT_LINK_TRAINING_FAIL EQU 20020000h ; PCIe Link training fail
-GNB_EVENT_BROKEN_LANE_RECOVERY EQU 20030000h ; Broken lane workaround applied to recover link training
-GNB_EVENT_GEN2_SUPPORT_RECOVERY EQU 20040000h ; Scale back to GEN1 to recover link training
-
-DESCRIPTOR_TERMINATE_LIST EQU 80000000h
-DESCRIPTOR_IGNORE EQU 40000000h
-
-PCIe_PORT_MISC_CONTROL STRUCT
- LinkComplianceMode UINT8 ?
- ;IN UINT8 LinkComplianceMode :1; ;< Force port into compliance mode (device will not be trained, port output compliance pattern)
-PCIe_PORT_MISC_CONTROL ENDS
-
-PCIe_PORT_DATA STRUCT
- PortPresent UINT8 ? ; < Enable PCIe port for initialization.
- ChannelType UINT8 ? ; < Channel type.
- ; 0 - "lowLoss",
- ; 1 - "highLoss",
- ; 2 - "mob0db",
- ; 3 - "mob3db",
- ; 4 - "extnd6db"
- ; 5 - "extnd8db"
- ;
- DeviceNumber UINT8 ? ; < Device number for port. Available device numbers may very on different CPUs.
- FunctionNumber UINT8 ? ; < Reserved for future use
- LinkSpeedCapability UINT8 ? ; < Advertised Gen Capability
- ; 0 - Maximum supported by silicon
- ; 1 - Gen1
- ; 2 - Gen2
- ; 3 - Gen3
- ;
- LinkAspm UINT8 ? ; < ASPM control. (see OemPcieLinkAspm for additional option to control ASPM)
- ; 0 - Disabled
- ; 1 - L0s only
- ; 2 - L1 only
- ; 2 - L0s and L1
- ;
- LinkHotplug UINT8 ? ; < Hotplug control.
- ; 0 - Disabled
- ; 1 - Basic
- ; 2 - Server
- ; 3 - Enhanced
- ;
- ResetId UINT8 ? ; < Arbitrary number greater than 0 assigned by platform firmware for GPIO
- ; identification which control reset for given port.
- ; Each port with unique GPIO should have unique ResetId assigned.
- ; All ports use same GPIO to control reset should have same ResetId assigned.
- ; see AgesaPcieSlotResetControl
- ;
- MiscControls PCIe_PORT_MISC_CONTROL {} ; < Misc extended controls
-PCIe_PORT_DATA ENDS
-
-;DDI channel lane mapping
-
-CHANNEL_MAPPING STRUCT ;
- Lane0 UINT8 ? ;
- ;IN UINT8 Lane0 :2; ;
- ;IN UINT8 Lane1 :2; ///< Lane 1 mapping (see "Lane 0 mapping")
- ;IN UINT8 Lane2 :2; ///< Lane 2 mapping (see "Lane 0 mapping")
- ;IN UINT8 Lane3 :2; ///< Lane 3 mapping (see "Lane 0 mapping")
-CHANNEL_MAPPING ENDS ;
-
-CONN_CHANNEL_MAPPING UNION
- ChannelMappingValue UINT8 ? ; < Raw lane mapping
- ChannelMapping CHANNEL_MAPPING {} ;
-CONN_CHANNEL_MAPPING ENDS ;
-
-; DDI Configuration
-PCIe_DDI_DATA STRUCT
- ConnectorType UINT8 ? ; < Display Connector Type
- ; 0 - DP
- ; 1 - eDP
- ; 2 - Single Link DVI
- ; 3 - Dual Link DVI
- ; 4 - HDMI
- ; 5 - Travis DP-to-VGA
- ; 6 - Travis DP-to-LVDS
- ; 7 - Hudson-2 NutMeg DP-to-VGA
- ; 8 - Single Link DVI-I
- ; 9 - CRT (VGA)
- ; 10 - LVDS
- ; 11 - VBIOS auto detect connector type
- AuxIndex UINT8 ? ; < Indicates which AUX or DDC Line is used
- ; 0 - AUX1
- ; 1 - AUX2
- ; 2 - AUX3
- ; 3 - AUX4
- ; 4 - AUX5
- ; 5 - AUX6
- ;
- HdpIndex UINT8 ? ; < Indicates which HDP pin is used
- ; 0 - HDP1
- ; 1 - HDP2
- ; 2 - HDP3
- ; 3 - HDP4
- ; 4 - HDP5
- ; 5 - HDP6
- Mapping CONN_CHANNEL_MAPPING (2) DUP ({}) ;< Set specific mapping of lanes to connector pins
- ;Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane
- ;Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only
- ;applicable for Dual DDI link)
- ;if Mapping[x] set to 0 than default mapping assumed
- LanePnInversionMask UINT8 ? ; < Specifies whether to invert the state of P and N for each lane. Each bit represents a PCIe lane on the DDI port
- ; 0 - Do not invert (default)
- ; 1 - Invert P and N on this lane
-PCIe_DDI_DATA ENDS
-
-
-; Engine Configuration
-PCIe_ENGINE_DATA STRUCT
- EngineType UINT8 ? ; < Engine type
- ; 0 - Ignore engine configuration
- ; 1 - PCIe port
- ; 2 - DDI
- StartLane UINT16 ? ; < Start lane number (in reversed configuration StartLane > EndLane).
- EndLane UINT16 ? ; < End lane number (in reversed configuration StartLane > EndLane).
-PCIe_ENGINE_DATA ENDS
-
-; PCIe port descriptor
-PCIe_PORT_DESCRIPTOR STRUCT
- Flags UINT32 ? ; < Descriptor flags
- ; Bit31 - last descriptor in complex
- EngineData PCIe_ENGINE_DATA {} ; < Engine data
- Port PCIe_PORT_DATA {} ; < PCIe port specific configuration info
-PCIe_PORT_DESCRIPTOR ENDS
-
-; DDI descriptor
-PCIe_DDI_DESCRIPTOR STRUCT
- Flags UINT32 ? ; < Descriptor flags
- EngineData PCIe_ENGINE_DATA {} ; < Engine data
- Ddi PCIe_DDI_DATA {} ; < DDI port specific configuration info
-PCIe_DDI_DESCRIPTOR ENDS
-
-; Slot Reset Info
-PCIe_SLOT_RESET_INFO STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < AGESA Standard Header
- ResetId UINT8 ? ; < Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
- ResetControl UINT8 ? ; < Reset control as defined by PCIE_RESET_CONTROL
-PCIe_SLOT_RESET_INFO ENDS
-
-
-; PCIe Complex descriptor
-PCIe_COMPLEX_DESCRIPTOR STRUCT
- Flags UINT32 ? ; < Descriptor flags
- ; Bit31 - last descriptor in topology
- ;
- ;
- SocketId UINT32 ? ; < Socket Id
- PciePortList POINTER ? ;< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
- DdiLinkList POINTER ? ;< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
- Reserved POINTER ? ;< Reserved for future use
-PCIe_COMPLEX_DESCRIPTOR ENDS
-
- AssertSlotReset EQU 0
- DeassertSlotReset EQU 1
-PCIE_RESET_CONTROL TEXTEQU <DWORD>
-
- PcieUnusedEngine EQU 0
- PciePortEngine EQU 1
- PcieDdiEngine EQU 2
- MaxPcieEngine EQU 3 ; < Not a valid value, used for verifying input
-PCIE_ENGINE_TYPE TEXTEQU <DWORD>
-
- PcieGenMaxSupported EQU 0
- PcieGen1 EQU 1
- PcieGen2 EQU 2
- MaxPcieGen EQU 3 ; < Not a valid value, used for verifying input
-PCIE_LINK_SPEED_CAP TEXTEQU <DWORD>
-
- PsppDisabled EQU 0
- PsppPerformance EQU 1
- PsppBalanceHigh EQU 2
- PsppBalanceLow EQU 3
- PsppPowerSaving EQU 4
- MaxPspp EQU 5 ; < Not a valid value, used for verifying input
-PCIE_PSPP_POLICY TEXTEQU <DWORD>
-
- ConnectorTypeDP EQU 0
- ConnectorTypeEDP EQU 1
- ConnectorTypeSingleLinkDVI EQU 2
- ConnectorTypeDualLinkDVI EQU 3
- ConnectorTypeHDMI EQU 4
- ConnectorTypeTravisDpToVga EQU 5
- ConnectorTypeTravisDpToLvds EQU 6
- ConnectorTypeNutmegDpToVga EQU 7
- ConnectorTypeSingleLinkDviI EQU 8
- ConnectorTypeCrt EQU 9
- ConnectorTypeLvds EQU 10
- ConnectorTypeAutoDetect EQU 11
- MaxConnectorType EQU 12 ; < Not a valid value, used for verifying input
-PCIE_CONNECTOR_TYPE TEXTEQU <DWORD>
-
- ChannelTypeLowLoss EQU 0
- ChannelTypeHighLoss EQU 1
- ChannelTypeMob0db EQU 2
- ChannelTypeMob3db EQU 3
- ChannelTypeExt6db EQU 4
- ChannelTypeExt8db EQU 5
- MaxChannelType EQU 6 ; < Not a valid value, used for verifying input
-PCIE_CHANNEL_TYPE TEXTEQU <DWORD>
-
- AspmDisabled EQU 0
- AspmL0s EQU 1
- AspmL1 EQU 2
- AspmL0sL1 EQU 3
- MaxAspm EQU 4 ; < Not a valid value, used for verifying input
-PCIE_ASPM_TYPE TEXTEQU <DWORD>
-
- HotplugDisabled EQU 0
- HotplugBasic EQU 1
- HotplugServer EQU 2
- HotplugEnhanced EQU 3
- HotplugInboard EQU 4
- MaxHotplug EQU 5 ; < Not a valid value, used for verifying input
-PCIE_HOTPLUG_TYPE TEXTEQU <DWORD>
-
- PortDisabled EQU 0
- PortEnabled EQU 1
-PCIE_PORT_ENABLE TEXTEQU <DWORD>
-
- Aux1 EQU 0
- Aux2 EQU 1
- Aux3 EQU 2
- Aux4 EQU 3
- Aux5 EQU 4
- Aux6 EQU 5
- MaxAux EQU 6 ; < Not a valid value, used for verifying input
-PCIE_AUX_TYPE TEXTEQU <DWORD>
-
- Hdp1 EQU 0
- Hdp2 EQU 1
- Hdp3 EQU 2
- Hdp4 EQU 3
- Hdp5 EQU 4
- Hdp6 EQU 5
- MaxHdp EQU 6 ; < Not a valid value, used for verifying input
-PCIE_HDP_TYPE TEXTEQU <DWORD>
-
-
-;IOMMU requestor ID
-IOMMU_REQUESTOR_ID STRUCT
- Bus UINT16 ? ; <[15:8] - Bus number, [7:3] - Device number, [2:0] - Function number
-IOMMU_REQUESTOR_ID ENDS
-
-;IVMD exclusion range descriptor
-IOMMU_EXCLUSION_RANGE_DESCRIPTOR STRUCT
- Flags UINT32 ? ; Descriptor flags
- ; @li @b Flags[31] - Terminate descriptor array.
- ; @li @b Flags[30] - Ignore descriptor.
- RequestorIdStart IOMMU_REQUESTOR_ID {} ; Requestor ID start
- RequestorIdEnd IOMMU_REQUESTOR_ID {} ; Requestor ID end (use same as start for single ID)
- RangeBaseAddress UINT64 ? ; Phisical base address of exclusion range
- RangeLength UINT64 ? ; Length of exclusion range in bytes
-IOMMU_EXCLUSION_RANGE_DESCRIPTOR ENDS
-
-;----------------------------------------------------------------------------
-; GNB configuration info
-;----------------------------------------------------------------------------
-;
-
-; LVDS Misc Control Field
-LVDS_MISC_CONTROL_FIELD STRUCT
- FpdiMode UINT8 ?
- ;IN UINT8 FpdiMode:1;
- ;IN UINT8 DlChSwap:1;
- ;IN UINT8 VsyncActiveLow:1;
- ;IN UINT8 HsyncActiveLow:1;
- ;IN UINT8 BLONActiveLow:1;
- ;IN UINT8 Reserved:3;
-LVDS_MISC_CONTROL_FIELD ENDS
-
-; LVDS Misc Control
-LVDS_MISC_CONTROL UNION
- Field LVDS_MISC_CONTROL_FIELD {}
- Value UINT8 ?
-LVDS_MISC_CONTROL ENDS
-
-; Configuration settings for GNB.
-GNB_ENV_CONFIGURATION STRUCT
- Gnb3dStereoPinIndex UINT8 ? ;< 3D Stereo Pin ID.
- ; @li 0 = Stereo 3D is disabled (default).
- ; @li 1 = Use processor pin HPD1.
- ; @li 2 = Use processor pin HPD2
- ; @li 3 = Use processor pin HPD3
- ; @li 4 = Use processor pin HPD4
- ; @li 5 = Use processor pin HPD5
- ; @li 6 = Use processor pin HPD6
- IommuSupport BOOLEAN ? ; IOMMU support.
- ; TRUE = Disable and hide IOMMU device.
- ; FLASE = Initialize IOMMU subsystem. Generate ACPI IVRS table.
- LvdsSpreadSpectrum UINT16 ? ; Spread spectrum value in 0.01 %
- LvdsSpreadSpectrumRate UINT16 ? ; Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
- LvdsPowerOnSeqDigonToDe UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqDeToVaryBl UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqDeToDigon UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqVaryBlToDe UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqOnToOffDelay UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqVaryBlToBlon UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqBlonToVaryBl UINT8 ? ; This item configures panel initialization timing.
- LvdsMaxPixelClockFreq UINT16 ? ; This item configures the maximum pixel clock frequency supported.
- LcdBitDepthControlValue UINT32 ? ; This item configures the LCD bit depth control settings.
- Lvds24bbpPanelMode UINT8 ? ; This item configures the LVDS 24 BBP mode.
- LvdsMiscControl LVDS_MISC_CONTROL {} ; This item configures LVDS swap/Hsync/Vsync/BLON
- PcieRefClkSpreadSpectrum UINT16 ? ; Spread spectrum value in 0.01 %
- GnbRemoteDisplaySupport BOOLEAN ? ; This item enables Wireless Display Support
-GNB_ENV_CONFIGURATION ENDS
-
-; GNB configuration info
-GNB_CONFIGURATION STRUCT
- PcieComplexList POINTER ? ; Pointer to array of PCIe_COMPLEX_DESCRIPTOR structures describe PCIe topology on each processor package or NULL.
- ; Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST
- ;
- ;
- ;
- ; Topology organization definition assume PCIe_COMPLEX_DESCRIPTOR defined first following
- ; PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR for given PCIe_COMPLEX_DESCRIPTOR
- ; defined in arbitrary sequence:
- ; Example of topology definition for single socket system:
- ; PlatfromTopology LABEL DWORD
- ;
- ; Port0_2 PCIe_PORT_DESCRIPTOR <>;
- ; Port0_3 PCIe_PORT_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST> ;
- ; ...
- ; Ddi0_A PCIe_DDI_DESCRIPTOR <>;
- ; Ddi0_B PCIe_DDI_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST,>;
- ; ...
- ; Cpu0 PCIe_COMPLEX_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST, 0, Port0_2, Ddi0_A>
- ;
- ;
- PsppPolicy UINT8 ? ;< PSPP (PCIe Speed Power Policy)
- ; @li @b 0 - Disabled
- ; @li @b 1 - Performance
- ; @li @b 2 - Balance-High
- ; @li @b 3 - Balance-Low
- ; @li @b 4 - Power Saving
- ;
-GNB_CONFIGURATION ENDS
-
-
-; ---------------------------------------------------------------------------
-
-; MEMORY-SPECIFIC DATA STRUCTURES
-
-; ---------------------------------------------------------------------------
-
-
- ; AGESA MAXIMIUM VALUES
-
- ; These Max values are used to define array sizes and associated loop
- ; counts in the code. They reflect the maximum values that AGESA
- ; currently supports and does not necessarily reflect the hardware
- ; capabilities of configuration.
-
-
- MAX_SOCKETS_SUPPORTED EQU 8 ; < Max number of sockets in system
- MAX_CHANNELS_PER_SOCKET EQU 4 ; < Max Channels per sockets
- MAX_DIMMS_PER_CHANNEL EQU 4 ; < Max DIMMs on a memory channel (independent of platform)
- NUMBER_OF_DELAY_TABLES EQU 9 ; < Number of tables defined in CH_DEF_STRUCT.
- ; < Eg: UINT16 *RcvEnDlys;
- ; < UINT8 *WrDqsDlys;
- ; < UINT8 *RdDqsDlys;
- ; < UINT8 *WrDatDlys;
- ; < UINT8 *RdDqsMinDlys;
- ; < UINT8 *RdDqsMaxDlys;
- ; < UINT8 *WrDatMinDlys;
- ; < UINT8 *WrDatMaxDlys;
- NUMBER_OF_FAILURE_MASK_TABLES EQU 1 ; < Number of failure mask tables
- MAX_PLATFORM_TYPES EQU 16 ; < Platform types per system
-
- MCT_TRNG_KEEPOUT_START EQU 00004000h ; < base [39:8]
- MCT_TRNG_KEEPOUT_END EQU 00007FFFh ; < base [39:8]
-
- UMA_ATTRIBUTE_INTERLEAVE EQU 80000000h ; < Uma Region is interleaved
- UMA_ATTRIBUTE_ON_DCT0 EQU 40000000h ; < UMA resides on memory that belongs to DCT0
- UMA_ATTRIBUTE_ON_DCT1 EQU 20000000h ; < UMA resides on memory that belongs to DCT1
-
- PSO_TABLE TEXTEQU <UINT8>; < Platform Configuration Table
-
- ; AGESA DEFINITIONS
-
- ; Many of these are derived from the platform and hardware specific definitions
-
- ; EccSymbolSize override value
- ECCSYMBOLSIZE_USE_BKDG EQU 0 ; < Use BKDG Recommended Value
- ECCSYMBOLSIZE_FORCE_X4 EQU 4 ; < Force to x4
- ECCSYMBOLSIZE_FORCE_X8 EQU 8 ; < Force to x8
- ; CPU Package Type
- PT_L1 EQU 0 ; < L1 Package type
- PT_M2 EQU 1 ; < AM Package type
- PT_S1 EQU 2 ; < S1 Package type
-
- ; Structures use to pass system Logical CPU-ID
-CPU_LOGICAL_ID STRUCT
- Family UINT64 ? ; < Indicates logical ID Family
- Revision UINT64 ? ; < Indicates logical ID Family
-CPU_LOGICAL_ID ENDS
-
- ; Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
-
- AMD_PLATFORM_SERVER EQU 8000h ; < Server
- AMD_PLATFORM_DESKTOP EQU 10000h ; < Desktop
- AMD_PLATFORM_MOBILE EQU 20000h ; < Mobile
-AMD_PLATFORM_TYPE TEXTEQU <DWORD>
-
- ; Dram technology type
-
- DDR2_TECHNOLOGY EQU 0 ; < DDR2 technology
- DDR3_TECHNOLOGY EQU 1 ; < DDR3 technology
-TECHNOLOGY_TYPE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
-
- DDR400_FREQUENCY EQU 200 ; < DDR 400
- DDR533_FREQUENCY EQU 266 ; < DDR 533
- DDR667_FREQUENCY EQU 333 ; < DDR 667
- DDR800_FREQUENCY EQU 400 ; < DDR 800
- DDR1066_FREQUENCY EQU 533 ; < DDR 1066
- DDR1333_FREQUENCY EQU 667 ; < DDR 1333
- DDR1600_FREQUENCY EQU 800 ; < DDR 1600
- DDR1866_FREQUENCY EQU 933 ; < DDR 1866
- DDR2100_FREQUENCY EQU 1050 ; < DDR 2100
- DDR2133_FREQUENCY EQU 1066 ; < DDR 2133
- DDR2400_FREQUENCY EQU 1200 ; < DDR 2400
- UNSUPPORTED_DDR_FREQUENCY EQU 1201 ; < Highest limit of DDR frequency
-MEMORY_BUS_SPEED TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
-
- QUADRANK_REGISTERED EQU 0
- QUADRANK_UNBUFFERED EQU 1
-QUANDRANK_TYPE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_TIMING_MODE_SELECT
-
- TIMING_MODE_AUTO EQU 0 ; < Use best rate possible
- TIMING_MODE_LIMITED EQU 1 ; < Set user top limit
- TIMING_MODE_SPECIFIC EQU 2 ; < Set user specified speed
-USER_MEMORY_TIMING_MODE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_POWER_DOWN_MODE
-
- POWER_DOWN_BY_CHANNEL EQU 0
- POWER_DOWN_BY_CHIP_SELECT EQU 1
- POWER_DOWN_AUTO EQU 2
-POWER_DOWN_MODE TEXTEQU <DWORD>
-
- ; Low voltage support
-
- VOLT_INITIAL EQU 0 ; < Initial value for VDDIO
- VOLT1_5 EQU 1 ; < 1.5 Volt
- VOLT1_35 EQU 2 ; < 1.35 Volt
- VOLT1_25 EQU 3 ; < 1.25 Volt
- VOLT_UNSUPPORTED EQU 0FFh ; < No common voltage found
-DIMM_VOLTAGE TEXTEQU <DWORD>
-
- ; UMA Mode
-
- UMA_NONE EQU 0 ; < UMA None
- UMA_SPECIFIED EQU 1 ; < UMA Specified
- UMA_AUTO EQU 2 ; < UMA Auto
-UMA_MODE TEXTEQU <DWORD>
-
- ; Force Training Mode
-
- FORCE_TRAIN_1D EQU 0 ; < 1D Training only
- FORCE_TRAIN___ EQU 1 ; <
- FORCE_TRAIN_AUTO EQU 2 ; < Auto
-FORCE_TRAIN_MODE TEXTEQU <DWORD>
-
-; The possible DRAM prefetch mode settings.
- DRAM_PREFETCHER_AUTO EQU 0 ; Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
- DISABLE_DRAM_PREFETCH_FOR_IO EQU 1 ; Disable DRAM prefetching for I/O requests only.
- DISABLE_DRAM_PREFETCH_FOR_CPU EQU 2 ; Disable DRAM prefetching for requests from processor cores only.
- DISABLE_DRAM_PREFETCHER EQU 3 ; Disable DRAM prefetching.
- MAX_DRAM_FREFETCH_MODE EQU 4 ; Not a DRAM prefetch mode, use for limit checking.
-DRAM_PREFETCH_MODE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_UMA_ALIGNMENT
-
- NO_UMA_ALIGNED EQU 00FFFFFFh
- UMA_4MB_ALIGNED EQU 00FFFFC0h
- UMA_128MB_ALIGNED EQU 00FFF800h
- UMA_256MB_ALIGNED EQU 00FFF000h
- UMA_512MB_ALIGNED EQU 00FFE000h
-UMA_ALIGNMENT TEXTEQU <DWORD>
- ; ===============================================================================
- ; Global MCT Configuration Status Word (GStatus)
- ; ===============================================================================
-
- GsbMTRRshort EQU 0 ; < Ran out of MTRRs while mapping memory
- GsbAllECCDimms EQU 1 ; < All banks of all Nodes are ECC capable
- GsbDramECCDis EQU 2 ; < Dram ECC requested but not enabled.
- GsbSoftHole EQU 3 ; < A Node Base gap was created
- GsbHWHole EQU 4 ; < A HW dram remap was created
- GsbNodeIntlv EQU 5 ; < Node Memory interleaving was enabled
- GsbSpIntRemapHole EQU 6 ; < Special condition for Node Interleave and HW remapping
- GsbEnDIMMSpareNW EQU 7 ; < Indicates that DIMM Spare can be used without a warm reset
-
- GsbEOL EQU 8 ; < End of list
-GLOBAL_STATUS_FIELD TEXTEQU <DWORD>
-
-; ===============================================================================
- ; Local Error Status (DIE_STRUCT.ErrStatus[31:0])
-; ===============================================================================
-
- EsbNoDimms EQU 0 ; < No DIMMs
- EsbSpdChkSum EQU 1 ; < SPD Checksum fail
- EsbDimmMismatchM EQU 2 ; < dimm module type(buffer) mismatch
- EsbDimmMismatchT EQU 3 ; < dimm CL/T mismatch
- EsbDimmMismatchO EQU 4 ; < dimm organization mismatch (128-bit)
- EsbNoTrcTrfc EQU 5 ; < SPD missing Trc or Trfc info
- EsbNoCycTime EQU 6 ; < SPD missing byte 23 or 25
- EsbBkIntDis EQU 7 ; < Bank interleave requested but not enabled
- EsbDramECCDis EQU 8 ; < Dram ECC requested but not enabled
- EsbSpareDis EQU 9 ; < Online spare requested but not enabled
- EsbMinimumMode EQU 10 ; < Running in Minimum Mode
- EsbNoRcvrEn EQU 11 ; < No DQS Receiver Enable pass window found
- EsbSmallRcvr EQU 12 ; < DQS Rcvr En pass window too small (far right of dynamic range)
- EsbNoDqsPos EQU 13 ; < No DQS-DQ passing positions
- EsbSmallDqs EQU 14 ; < DQS-DQ passing window too small
- EsbDCBKScrubDis EQU 15 ; < DCache scrub requested but not enabled
-
- EsbEMPNotSupported EQU 16 ; < Processor is not capable for EMP.
- EsbEMPConflict EQU 17 ; < EMP requested but cannot be enabled since
- ; < channel interleaving, bank interleaving, or bank swizzle is enabled.
- EsbEMPDis EQU 18 ; < EMP requested but cannot be enabled since
- ; < memory size of each DCT is not a power of two.
-
- EsbEOL EQU 19 ; < End of list
-ERROR_STATUS_FIELD TEXTEQU <DWORD>
-
-; ===============================================================================
- ; Local Configuration Status (DIE_STRUCT.Status[31:0])
-; ===============================================================================
-
- SbRegistered EQU 0 ; < All DIMMs are Registered
- SbEccDimms EQU 1 ; < All banks ECC capable
- SbParDimms EQU 2 ; < All banks Addr/CMD Parity capable
- SbDiagClks EQU 3 ; < Jedec ALL slots clock enable diag mode
- Sb128bitmode EQU 4 ; < DCT in 128-bit mode operation
- Sb64MuxedMode EQU 5 ; < DCT in 64-bit mux'ed mode.
- Sb2TMode EQU 6 ; < 2T CMD timing mode is enabled.
- SbSWNodeHole EQU 7 ; < Remapping of Node Base on this Node to create a gap.
- SbHWHole EQU 8 ; < Memory Hole created on this Node using HW remapping.
- SbOver400Mhz EQU 9 ; < DCT freq greater than or equal to 400MHz flag
- SbDQSPosPass2 EQU 10 ; < Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
- SbDQSRcvLimit EQU 11 ; < Used for DQSRcvEnTrain to know we have reached the upper bound.
- SbExtConfig EQU 12 ; < Indicate the default setting for extended PCI configuration support
- SbLrdimms EQU 13 ; < All DIMMs are LRDIMMs
- SbEOL EQU 14 ; < End of list
-LOCAL_STATUS_FIELD TEXTEQU <DWORD>
-
-
-; < CPU MSR Register definitions ------------------------------------------
- SYS_CFG EQU 0C0010010h
- TOP_MEM EQU 0C001001Ah
- TOP_MEM2 EQU 0C001001Dh
- HWCR EQU 0C0010015h
- NB_CFG EQU 0C001001Fh
-
- FS_BASE EQU 0C0000100h
- IORR0_BASE EQU 0C0010016h
- IORR0_MASK EQU 0C0010017h
- BU_CFG EQU 0C0011023h
- BU_CFG2 EQU 0C001102Ah
- COFVID_STAT EQU 0C0010071h
- TSC EQU 10h
-
-; ===============================================================================
- ; SPD Data for each DIMM
-; ===============================================================================
-SPD_DEF_STRUCT STRUCT
- DimmPresent BOOLEAN ? ; < Indicates that the DIMM is present and Data is valid
- Data UINT8 (256) DUP (?) ; < Buffer for 256 Bytes of SPD data from DIMM
-SPD_DEF_STRUCT ENDS
-
-; ===============================================================================
- ; Channel Definition Structure
- ; This data structure defines entries that are specific to the channel initialization
-; ===============================================================================
-CH_DEF_STRUCT STRUCT
- ChannelID UINT8 ? ; < Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
- TechType TECHNOLOGY_TYPE ? ; < Technology type of this channel
- ChDimmPresent UINT8 ? ; < For each bit n 0..7, 1 = DIMM n is present.
- ; < DIMM# Select Signal
- ; < 0 MA0_CS_L[0, 1]
- ; < 1 MB0_CS_L[0, 1]
- ; < 2 MA1_CS_L[0, 1]
- ; < 3 MB1_CS_L[0, 1]
- ; < 4 MA2_CS_L[0, 1]
- ; < 5 MB2_CS_L[0, 1]
- ; < 6 MA3_CS_L[0, 1]
- ; < 7 MB3_CS_L[0, 1]
-
- DCTPtr POINTER ? ; < Pointer to the DCT data of this channel.
- MCTPtr POINTER ? ; < Pointer to the node data of this channel.
- SpdPtr POINTER ? ; < Pointer to the SPD data for this channel. (Setup by NB Constructor)
- DimmSpdPtr POINTER (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Array of pointers to
- ; < SPD Data for each Dimm. (Setup by Tech Block Constructor)
- ChDimmValid UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved.
- RegDimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved.
- LrDimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
- SODimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is a SO-DIMM where 4..7 are reserved.
- Loads UINT8 ? ; < Number of devices loading bus
- Dimms UINT8 ? ; < Number of DIMMs loading Channel
- Ranks UINT8 ? ; < Number of ranks loading Channel DATA
- SlowMode BOOLEAN ? ; < 1T or 2T CMD mode (slow access mode)
- ; < FALSE = 1T
- ; < TRUE = 2T
- ; < The following pointers will be pointed to dynamically allocated buffers.
- ; < Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
- ; < Example: If DIMM and Byte based training, then
- ; < XX is a value in Hex
- ; < BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
- ; < Row1 - Logical DIMM0 XX XX XX XX XX XX XX XX XX
- ; < Row2 - Logical DIMM1 XX XX XX XX XX XX XX XX XX
- RcvEnDlys POINTER ? ; < DQS Receiver Enable Delays
- WrDqsDlys POINTER ? ; < Write DQS delays (only valid for DDR3)
- RdDqsDlys POINTER ? ; < Read Dqs delays
- WrDatDlys POINTER ? ; < Write Data delays
- RdDqs__Dlys POINTER ? ; < Read DQS data
- RdDqsMinDlys POINTER ? ; < Minimum Window for Read DQS
- RdDqsMaxDlys POINTER ? ; < Maximum Window for Read DQS
- WrDatMinDlys POINTER ? ; < Minimum Window for Write data
- WrDatMaxDlys POINTER ? ; < Maximum Window for Write data
- RcvEnDlysMemPs1 POINTER ? ; < DQS Receiver Enable Delays for Memory Pstate 1
- WrDqsDlysMemPs1 POINTER ? ; < Write DQS delays for Memory Pstate 1 (only valid for DDR3)
- RdDqsDlysMemPs1 POINTER ? ; < Read Dqs delays for Memory Pstate 1
- WrDatDlysMemPs1 POINTER ? ; < Write Data delays for Memory Pstate 1
- RdDqs__DlysMemPs1 POINTER ? ; < Read DQS data for Memory Pstate 1
- RdDqsMinDlysMemPs1 POINTER ? ; < Minimum Window for Read DQS for Memory Pstate 1
- RdDqsMaxDlysMemPs1 POINTER ? ; < Maximum Window for Read DQS for Memory Pstate 1
- WrDatMinDlysMemPs1 POINTER ? ; < Minimum Window for Write data for Memory Pstate 1
- WrDatMaxDlysMemPs1 POINTER ? ; < Maximum Window for Write data for Memory Pstate 1
- RowCount UINT8 ? ; < Number of rows of the allocated buffer.
- ColumnCount UINT8 ? ; < Number of columns of the allocated buffer.
-
- FailingBitMask POINTER ? ; < Table of masks to Track Failing bits
- FailingBitMaskMemPs1 POINTER ? ; < Table of masks to Track Failing bits for Memory Pstate 1
- DctOdcCtl UINT32 ? ; < Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
- DctAddrTmg UINT32 ? ; < Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
- PhyRODTCSLow UINT32 ? ; < Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h)
- PhyRODTCSHigh UINT32 ? ; < Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h)
- PhyWODTCSLow UINT32 ? ; < Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h)
- PhyWODTCSHigh UINT32 ? ; < Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183)
- PhyWLODT UINT8 (4) DUP (?) ; < Write Levelization ODT Pattern for Dimm 0-3 (see BKDG FN2:Offset 9Ch, index 0x8[11:8])
- DctEccDqsLike UINT16 ? ; < DCT DQS ECC UINT8 like...
- DctEccDqsScale UINT8 ? ; < DCT DQS ECC UINT8 scale
- PtrPatternBufA UINT16 ? ; < Ptr on stack to aligned DQS testing pattern
- PtrPatternBufB UINT16 ? ; < Ptr on stack to aligned DQS testing pattern
- ByteLane UINT8 ? ; < Current UINT8 Lane (0..7)
- Direction UINT8 ? ; < Current DQS-DQ training write direction (0=read, 1=write)
- Pattern UINT8 ? ; < Current pattern
- DqsDelay UINT8 ? ; < Current DQS delay value
- HostBiosSrvc1 UINT16 ? ; < UINT16 sized general purpose field for use by host BIOS. Scratch space.
- HostBiosSrvc2 UINT32 ? ; < UINT32 sized general purpose field for use by host BIOS. Scratch space.
- DctMaxRdLat UINT16 (4) DUP (?) ; < Max Read Latency (ns) for the DCT
- ; < DctMaxRdLat [i] is for NBPstate i DIMMValidCh UINT8 ? ; < DIMM# in CH
- DIMMValidCh UINT8 ? ; < DIMM# in CH
- MaxCh UINT8 ? ; < Max number of CH in system
- Dct UINT8 ? ; < Dct pointer
- WrDatGrossH UINT8 ? ; < Write Data Gross delay high value
- DqsRcvEnGrossL UINT8 ? ; < DQS Receive Enable Gross Delay low
-
- TrwtWB UINT8 ? ; < Non-SPD timing value for TrwtWB
- CurrRcvrDctADelay UINT8 ? ; < for keep current RcvrEnDly
- T1000 UINT16 ? ; < get the T1000 figure (cycle time (ns) * 1K)
- DqsRcvEnPass UINT8 ? ; < for TrainRcvrEn UINT8 lane pass flag
- DqsRcvEnSaved UINT8 ? ; < for TrainRcvrEn UINT8 lane saved flag
- SeedPass1Remainder UINT8 ? ; < for Phy assisted DQS receiver enable training
-
- ClToNbFlag UINT8 ? ; < is used to restore ClLinesToNbDis bit after memory
- NodeSysBase UINT32 ? ; < for channel interleave usage
- RefRawCard UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Array of rawcards detected
- CtrlWrd02 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 2 values per DIMM
- CtrlWrd03 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 3 values per DIMM
- CtrlWrd04 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 4 values per DIMM
- CtrlWrd05 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 5 values per DIMM
- CtrlWrd08 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 8 values per DIMM
-
- CsPresentDCT UINT16 ? ; < For each bit n 0..7, 1 = Chip-select n is present
- DimmMirrorPresent UINT8 ? ; < For each bit n 0..7, 1 = DIMM n is OnDimmMirror capable
- DimmSpdCse UINT8 ? ; < For each bit n 0..7, 1 = DIMM n SPD checksum error
- DimmExclude UINT8 ? ; < For each bit n 0..7, 1 = DIMM n gets excluded
- DimmYr06 UINT8 ? ; < Bitmap indicating which Dimms have a manufacturer's year code <= 2006
- DimmWk2406 UINT8 ? ; < Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
- DimmPlPresent UINT8 ? ; < Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
- DimmQrPresent UINT8 ? ; < QuadRank DIMM present?
- DimmDrPresent UINT8 ? ; < Bitmap indicating that Dual Rank Dimms are present
- DimmSRPresent UINT8 ? ; < Bitmap indicating that Single Rank Dimms are present
- Dimmx4Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved.
- Dimmx8Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved.
- Dimmx16Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved.
- LrdimmPhysicalRanks UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Number of Physical Ranks for LRDIMMs
- LrDimmLogicalRanks UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Number of LRDIMM Logical ranks in this configuration
- LrDimmRankMult UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Rank Multipication factor per dimm.
- DimmNibbleAccess UINT8 ? ; < For each bit n 0..3, 1 = DIMM n will use nibble signaling. Where 4..7 are reserved.
- MemClkDisMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
- ; < base on this array to disable unused MemClk to save power.
- ; <
- ; < The array must have 8 entries. Each entry, which associates with
- ; < one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
- ; < Example:
- ; < BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package
- ; < is like below:
- ; < Bit AM3/S1g3 pin name
- ; < 0 M[B,A]_CLK_H/L[0]
- ; < 1 M[B,A]_CLK_H/L[1]
- ; < 2 M[B,A]_CLK_H/L[2]
- ; < 3 M[B,A]_CLK_H/L[3]
- ; < 4 M[B,A]_CLK_H/L[4]
- ; < 5 M[B,A]_CLK_H/L[5]
- ; < 6 M[B,A]_CLK_H/L[6]
- ; < 7 M[B,A]_CLK_H/L[7]
- ; < And platform has the following routing:
- ; < CS0 M[B,A]_CLK_H/L[4]
- ; < CS1 M[B,A]_CLK_H/L[2]
- ; < CS2 M[B,A]_CLK_H/L[3]
- ; < CS3 M[B,A]_CLK_H/L[5]
- ; < Then MemClkDisMap should be pointed to the following array:
- ; < CLK_2 CLK_3 CLK_4 CLK_5
- ; < 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00
- ; < Each entry of the array is the bitmask of 8 chip selects.
-
- CKETriMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of CKE pins to the DIMMs' ranks.
- ; < The array must have 2 entries. Each entry, which associates with
- ; < one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
- ; < AGESA will base on this array to disable unused CKE pins to save power.
-
- ODTTriMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of ODT pins to the DIMMs' ranks.
- ; < The array must have 4 entries. Each entry, which associates with
- ; < one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
- ; < AGESA will base on this array to disable unused ODT pins to save power.
-
- ChipSelTriMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of chip select pins to the DIMMs' ranks.
- ; < The array must have 8 entries. Each entry is a bitmap of 8 CS.
- ; < AGESA will base on this array to disable unused Chip select pins to save power.
-
- ExtendTmp BOOLEAN ? ; < If extended temperature is supported on all dimms on a channel.
-
- MaxVref UINT8 ? ; < Maximum Vref Value for channel
-
- Reserved UINT8 (100) DUP (?) ; < Reserved
-CH_DEF_STRUCT ENDS
-
-; ===============================================================================
- ; DCT Channel Timing Parameters
- ; This data structure sets timings that are specific to the channel
-; ===============================================================================
-CH_TIMING_STRUCT STRUCT
- DctDimmValid UINT16 ? ; < For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved.
- DimmMirrorPresent UINT16 ? ; < For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved.
- DimmSpdCse UINT16 ? ; < For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved.
- DimmExclude UINT16 ? ; < For each bit n 0..3, 1 = DIMM n gets excluded because of no common voltage is found
- CsPresent UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is present
- CsEnabled UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is enabled
- CsTestFail UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is present but disabled
- CsTrainFail UINT16 ? ; < Bitmap showing which chipselects failed training
- DIMM1KPage UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved.
- DimmQrPresent UINT16 ? ; < QuadRank DIMM present?
- DimmDrPresent UINT16 ? ; < Bitmap indicating that Dual Rank Dimms are present
- DimmSRPresent UINT8 ? ; < Bitmap indicating that Single Rank Dimms are present
- Dimmx4Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved.
- Dimmx8Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved.
- Dimmx16Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved.
-
- DIMMTrcd UINT16 ? ; < Minimax Trcd*40 (ns) of DIMMs
- DIMMTrp UINT16 ? ; < Minimax Trp*40 (ns) of DIMMs
- DIMMTrtp UINT16 ? ; < Minimax Trtp*40 (ns) of DIMMs
- DIMMTras UINT16 ? ; < Minimax Tras*40 (ns) of DIMMs
- DIMMTrc UINT16 ? ; < Minimax Trc*40 (ns) of DIMMs
- DIMMTwr UINT16 ? ; < Minimax Twr*40 (ns) of DIMMs
- DIMMTrrd UINT16 ? ; < Minimax Trrd*40 (ns) of DIMMs
- DIMMTwtr UINT16 ? ; < Minimax Twtr*40 (ns) of DIMMs
- DIMMTfaw UINT16 ? ; < Minimax Tfaw*40 (ns) of DIMMs
- TargetSpeed UINT16 ? ; < Target DRAM bus speed in MHz
- Speed UINT16 ? ; < DRAM bus speed in MHz
- ; < 400 (MHz)
- ; < 533 (MHz)
- ; < 667 (MHz)
- ; < 800 (MHz)
- ; < and so on...
- CasL UINT8 ? ; < CAS latency DCT setting (busclocks)
- Trcd UINT8 ? ; < DCT Trcd (busclocks)
- Trp UINT8 ? ; < DCT Trp (busclocks)
- Trtp UINT8 ? ; < DCT Trtp (busclocks)
- Tras UINT8 ? ; < DCT Tras (busclocks)
- Trc UINT8 ? ; < DCT Trc (busclocks)
- Twr UINT8 ? ; < DCT Twr (busclocks)
- Trrd UINT8 ? ; < DCT Trrd (busclocks)
- Twtr UINT8 ? ; < DCT Twtr (busclocks)
- Tfaw UINT8 ? ; < DCT Tfaw (busclocks)
- Trfc0 UINT8 ? ; < DCT Logical DIMM0 Trfc
- ; < 0 = 75ns (for 256Mb devs)
- ; < 1 = 105ns (for 512Mb devs)
- ; < 2 = 127.5ns (for 1Gb devs)
- ; < 3 = 195ns (for 2Gb devs)
- ; < 4 = 327.5ns (for 4Gb devs)
- Trfc1 UINT8 ? ; < DCT Logical DIMM1 Trfc (see Trfc0 for format)
- Trfc2 UINT8 ? ; < DCT Logical DIMM2 Trfc (see Trfc0 for format)
- Trfc3 UINT8 ? ; < DCT Logical DIMM3 Trfc (see Trfc0 for format)
- DctMemSize UINT32 ? ; < Base[47:16], total DRAM size controlled by this DCT.
- SlowMode BOOLEAN ? ; < 1T or 2T CMD mode (slow access mode)
- ; < FALSE = 1T
- ; < TRUE = 2T
- TrwtTO UINT8 ? ; < DCT TrwtTO (busclocks)
- Twrrd UINT8 ? ; < DCT Twrrd (busclocks)
- Twrwr UINT8 ? ; < DCT Twrwr (busclocks)
- Trdrd UINT8 ? ; < DCT Trdrd (busclocks)
- TrwtWB UINT8 ? ; < DCT TrwtWB (busclocks)
- TrdrdSD UINT8 ? ; < DCT TrdrdSD (busclocks)
- TwrwrSD UINT8 ? ; < DCT TwrwrSD (busclocks)
- TwrrdSD UINT8 ? ; < DCT TwrrdSD (busclocks)
- MaxRdLat UINT16 ? ; < Max Read Latency
- WrDatGrossH UINT8 ? ; < Temporary variables must be removed
- DqsRcvEnGrossL UINT8 ? ; < Temporary variables must be removed
-CH_TIMING_STRUCT ENDS
-
-; ===============================================================================
- ; Data for each DCT
- ; This data structure defines data used to configure each DRAM controller
-; ===============================================================================
-DCT_STRUCT STRUCT
- Dct UINT8 ? ; < Current Dct
- Timings CH_TIMING_STRUCT {} ; < Channel Timing structure
- TimingsMemPs1 POINTER ? ; < Pointed to channel timing structure for Memory Pstate 1
- ChData POINTER ? ; < Pointed to a dynamically allocated array of Channel structures
- ChannelCount UINT8 ? ; < Number of channel per this DCT
- BkIntDis BOOLEAN ? ; < Bank interleave requested but not enabled on current DCT
-DCT_STRUCT ENDS
-
-
-; ===============================================================================
- ; Data Structure defining each Die
- ; This data structure contains information that is used to configure each Die
-; ===============================================================================
-DIE_STRUCT STRUCT
-
- ; Advanced:
-
- NodeId UINT8 ? ; < Node ID of current controller
- SocketId UINT8 ? ; < Socket ID of this Die
- DieId UINT8 ? ; < ID of this die relative to the socket
- PciAddr PCI_ADDR {} ; < Pci bus and device number of this controller.
- ErrCode AGESA_STATUS ? ; < Current error condition of Node
- ; < 0x0 = AGESA_SUCCESS
- ; < 0x1 = AGESA_UNSUPPORTED
- ; < 0x2 = AGESA_BOUNDS_CHK
- ; < 0x3 = AGESA_ALERT
- ; < 0x4 = AGESA_WARNING
- ; < 0x5 = AGESA_ERROR
- ; < 0x6 = AGESA_CRITICAL
- ; < 0x7 = AGESA_FATAL
- ; <
- ErrStatus BOOLEAN (EsbEOL) DUP (?) ; < Error Status bit Field
- Status BOOLEAN (SbEOL) DUP (?) ; < Status bit Field
- NodeMemSize UINT32 ? ; < Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
- NodeSysBase UINT32 ? ; < Base[47:16] (system address) DRAM base address of this Node.
- NodeHoleBase UINT32 ? ; < If not zero, Base[47:16] (system address) of dram hole for HW remapping. Dram hole exists on this Node
- NodeSysLimit UINT32 ? ; < Base[47:16] (system address) DRAM limit address of this Node.
- DimmPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is present.
- ; < DIMM# Select Signal
- ; < 0 MA0_CS_L[0, 1]
- ; < 1 MB0_CS_L[0, 1]
- ; < 2 MA1_CS_L[0, 1]
- ; < 3 MB1_CS_L[0, 1]
- ; < 4 MA2_CS_L[0, 1]
- ; < 5 MB2_CS_L[0, 1]
- ; < 6 MA3_CS_L[0, 1]
- ; < 7 MB3_CS_L[0, 1]
- DimmValid UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
- RegDimmPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is registered DIMM
- LrDimmPresent UINT32 ? ; < For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
- DimmEccPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is ECC capable.
- DimmParPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
- DimmTrainFail UINT16 ? ; < Bitmap showing which dimms failed training
- ChannelTrainFail UINT16 ? ; < Bitmap showing the channel information about failed Chip Selects
- ; < 0 in any bit field indicates Channel 0
- ; < 1 in any bit field indicates Channel 1
- Dct UINT8 ? ; < Need to be removed
- ; < DCT pointer
- GangedMode BOOLEAN ? ; < Ganged mode
- ; < 0 = disabled
- ; < 1 = enabled
- LogicalCpuid CPU_LOGICAL_ID {} ; < The logical CPUID of the node
- HostBiosSrvc1 UINT16 ? ; < UINT16 sized general purpose field for use by host BIOS. Scratch space.
- HostBiosSrvc2 UINT32 ? ; < UINT32 sized general purpose field for use by host BIOS. Scratch space.
- MLoad UINT8 ? ; < Need to be removed
- ; < Number of devices loading MAA bus
- MaxAsyncLat UINT8 ? ; < Legacy wrapper
- ChbD3Rcvrdly UINT8 ? ; < Legacy wrapper
- ChaMaxRdLat UINT16 ? ; < Max Read Latency (ns) for DCT 0
- ChbD3BcRcvrdly UINT8 ? ; < CHB DIMM 3 Check UINT8 Receiver Enable Delay
-
- DctData POINTER ? ; < Pointed to a dynamically allocated array of DCT_STRUCTs
- DctCount UINT8 ? ; < Number of DCTs per this Die
- Reserved UINT8 (16) DUP (?) ; < Reserved
-DIE_STRUCT ENDS
-
-; *********************************************************************
-; * S3 Support structure
-; *********************************************************************
- ; AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure
-AMD_S3_PARAMS STRUCT
- Signature UINT32 ? ; < "ASTR" for AMD Suspend-To-RAM
- Version UINT16 ? ; < S3 Params version number
- Flags UINT32 ? ; < Indicates operation
- NvStorage POINTER ? ; < Pointer to memory critical save state data
- NvStorageSize UINT32 ? ; < Size in bytes of the NvStorage region
- VolatileStorage POINTER ? ; < Pointer to remaining AMD save state data
- VolatileStorageSize UINT32 ? ; < Size in bytes of the VolatileStorage region
-AMD_S3_PARAMS ENDS
-
-; ===============================================================================
- ; MEM_PARAMETER_STRUCT
- ; This data structure is used to pass wrapper parameters to the memory configuration code
-; ===============================================================================
-MEM_PARAMETER_STRUCT STRUCT
-
- ; Basic (Return parameters)
- ; (This section contains the outbound parameters from the memory init code)
-
- GStatus BOOLEAN (GsbEOL) DUP (?) ; < Global Status bitfield
- HoleBase UINT32 ? ; < If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping.
- Sub4GCacheTop UINT32 ? ; < If not zero, the 32-bit top of cacheable memory.
- Sub1THoleBase UINT32 ? ; < If not zero Base[47:16] (system address) of sub 1TB dram hole.
- SysLimit UINT32 ? ; < Limit[47:16] (system address)
- DDR3Voltage DIMM_VOLTAGE ? ; < Find support voltage and send back to platform BIOS.
- ExternalVrefValue UINT8 ? ; < Target reference voltage for external Vref for training
- MemData POINTER ? ; < Pointer to MEM_DATA_STRUCT
- ; Advanced (Optional parameters)
- ; Optional (all defaults values will be initialized by the
- ; 'AmdMemInitDataStructDef' based on AMD defaults. It is up
- ; to the IBV/OEM to change the defaults after initialization
- ; but prior to the main entry to the memory code):
-
- ; Memory Map/Mgt.
-
- BottomIo UINT16 ? ; < Bottom of 32-bit IO space (8-bits)
- ; < NV_BOTTOM_IO[7:0]=Addr[31:24]
- MemHoleRemapping BOOLEAN ? ; < Memory Hole Remapping (1-bit)
- ; < FALSE = disable
- ; < TRUE = enable
- LimitMemoryToBelow1Tb BOOLEAN ? ; < Limit memory address space to below 1 TB
- ; < FALSE = disable
- ; < TRUE = enable
- ; Dram Timing
-
- UserTimingMode USER_MEMORY_TIMING_MODE ? ; < User Memclock Mode
-
- MemClockValue MEMORY_BUS_SPEED ? ; < Memory Clock Value
-
- ; Dram Configuration
-
- EnableBankIntlv BOOLEAN ? ; < Dram Bank (chip-select) Interleaving (1-bit)
- ; < FALSE =disable (AMD default)
- ; < TRUE =enable
- EnableNodeIntlv BOOLEAN ? ; < Node Memory Interleaving (1-bit)
- ; < FALSE = disable (AMD default)
- ; < TRUE = enable
- EnableChannelIntlv BOOLEAN ? ; < Channel Interleaving (1-bit)
- ; < FALSE = disable (AMD default)
- ; < TRUE = enable
- ; ECC
-
- EnableEccFeature BOOLEAN ? ; < enable ECC error to go into MCE
- ; < FALSE = disable (AMD default)
- ; < TRUE = enable
- ; Dram Power
-
- EnablePowerDown BOOLEAN ? ; < CKE based power down mode (1-bit)
- ; < FALSE =disable (AMD default)
- ; < TRUE =enable
- ; Online Spare
-
- EnableOnLineSpareCtl BOOLEAN ? ; < Chip Select Spare Control bit 0:
- ; < FALSE = disable Spare (AMD default)
- ; < TRUE = enable Spare
- TableBasedAlterations POINTER ? ; < Point to an array of data bytes describing desired modifications to register settings.
-
- PlatformMemoryConfiguration POINTER ?
- ; < Points to a table that contains platform specific settings
- ; < (i.e. MemClk routing, the number of DIMM slots per channel,...)
- ; < AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that
- ; < contains default conservative settings. Platform BIOS can either tweak
- ; < DefaultPlatformMemoryConfiguration or reassign this pointer to its own table.
- ; <
- EnableParity BOOLEAN ? ; < Parity control
- ; < TRUE = enable
- ; < FALSE = disable (AMD default)
- EnableBankSwizzle BOOLEAN ? ; < BankSwizzle control
- ; < FALSE = disable
- ; < TRUE = enable (AMD default)
- EnableMemClr BOOLEAN ? ; < Memory Clear functionality control
- ; < FALSE = disable
- ; < TRUE = enable (AMD default)
- ; Uma Configuration
-
- UmaMode UMA_MODE ? ; < Uma Mode
- ; < 0 = None
- ; < 1 = Specified
- ; < 2 = Auto
- UmaSize UINT32 ? ; < The size of shared graphics dram (16-bits)
- ; < NV_UMA_Size[31:0]=Addr[47:16]
- ; <
- UmaBase UINT32 ? ; < The allocated Uma base address (32-bits)
- ; < NV_UMA_Base[31:0]=Addr[47:16]
- ; <
-
- ; Memory Restore Feature
-
- MemRestoreCtl BOOLEAN ? ; < Memory context restore control
- ; < FALSE = perform memory init as normal (AMD default)
- ; < TRUE = restore memory context and skip training. This requires
- ; < MemContext is valid before AmdInitPost
- SaveMemContextCtl BOOLEAN ? ; < Control switch to save memory context at the end of MemAuto
- ; < TRUE = AGESA will setup MemContext block before exit AmdInitPost
- ; < FALSE = AGESA will not setup MemContext block. Platform is
- ; < expected to call S3Save later in POST if it wants to
- ; < use memory context restore feature.
- MemContext AMD_S3_PARAMS {} ; < Memory context block describes the data that platform needs to
- ; < save and restore for memory context restore feature to work.
- ; < It uses the subset of S3Save block to save/restore. Hence platform
- ; < may save only S3 block and uses it for both S3 resume and
- ; < memory context restore.
- ; < - If MemRestoreCtl is TRUE, platform needs to pass in MemContext
- ; < before AmdInitPost.
- ; < - If SaveMemContextCtl is TRUE, platform needs to save MemContext
- ; < right after AmdInitPost.
- ExternalVrefCtl BOOLEAN ? ; < Control the use of external Vref
- ; < TRUE = AGESA will use the function defined in "AGESA_EXTERNAL____TRAIN_VREF_CHANGE" in function list
- ; < to change the vref
- ; < FALSE = AGESA will will use the internal vref control.
- ForceTrainMode FORCE_TRAIN_MODE ? ; < Training Mode
- ; < 0 = Force 1D Training for all configurations
- ; < 1 = Force training for all configurations
- ; < 2 = Auto - AGESA will control
-MEM_PARAMETER_STRUCT ENDS
-
-
-; ===============================================================================
- ; Function definition
- ; This data structure passes function pointers to the memory configuration code.
- ; The wrapper can use this structure with customized versions
-; ================================================================================
-MEM_FUNCTION_STRUCT STRUCT
-
- ; PUBLIC required Internal functions
-
- amdMemGetPsCfgU POINTER ? ; < Proc for Unbuffered DIMMs, platform specific
- amdMemGetPsCfgR POINTER ? ; < Proc for Registered DIMMs, platform specific
-
- ; PUBLIC optional functions
-
- amdMemEccInit POINTER ? ; < NB proc for ECC feature
- amdMemChipSelectInterleaveInit POINTER ? ; < NB proc for CS interleave feature
- amdMemDctInterleavingInit POINTER ? ; < NB proc for Channel interleave feature
- amdMemMctInterleavingInit POINTER ? ; < NB proc for Node interleave feature
- amdMemParallelTraining POINTER ? ; < NB proc for parallel training feature
- amdMemEarlySampleSupport POINTER ? ; < NB code for early sample support feature
- amdMemMultiPartInitSupport POINTER ? ; < NB code for 'multi-part'
- amdMemOnlineSpareSupport POINTER ? ; < NB code for On-Line Spare feature
- amdMemUDimmInit POINTER ? ; < NB code for UDIMMs
- amdMemRDimmInit POINTER ? ; < NB code for RDIMMs
- amdMemLrDimmInit POINTER ? ; < NB code for LRDIMMs
- Reserved UINT32 (100) DUP (?) ; < Reserved for later function definition
-MEM_FUNCTION_STRUCT ENDS
-
-; ===============================================================================
- ; Socket Structure
-
-; ===============================================================================
-MEM_SOCKET_STRUCT STRUCT
- ChannelPtr POINTER (MAX_CHANNELS_PER_SOCKET) DUP (?) ; < Pointers to each channels training data
-
- TimingsPtr POINTER (MAX_CHANNELS_PER_SOCKET) DUP (?) ; < Pointers to each channels timing data
-
-MEM_SOCKET_STRUCT ENDS
-
-; ===============================================================================
- ; MEM_DATA_STRUCT
-; ===============================================================================
-MEM_DATA_STRUCT STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < AGESA Standard Header
-
- ParameterListPtr POINTER ? ; < List of input Parameters
-
- FunctionList MEM_FUNCTION_STRUCT {} ; < List of function Pointers
-
- GetPlatformCfg POINTER (MAX_PLATFORM_TYPES) DUP (?) ; < look-up platform info
-
- ErrorHandling POINTER ? ; < Error Handling
-
- ; SocketList is a shortcut for IBVs to retrieve training
- ; and timing data for each channel indexed by socket/channel,
- ; eliminating their need to parse die/dct/channel etc.
- ; It contains pointers to the populated data structures for
- ; each channel and skips the channel structures that are
- ; unpopulated. In the case of channels sharing the same DCT,
- ; the pTimings pointers will point to the same DCT Timing data.
-
- SocketList MEM_SOCKET_STRUCT (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Socket list for memory code
-
- DiesPerSystem POINTER ? ; < Pointed to an array of DIE_STRUCTs
- DieCount UINT8 ? ; < Number of MCTs in the system.
-
- SpdDataStructure POINTER ? ; < Pointer to SPD Data structure
-
- PlatFormConfig POINTER ? ; < Pointer to Platform profile/build option config structure
-
- IsFlowControlSupported BOOLEAN ? ; < Indicates if flow control is supported
-
- TscRate UINT32 ? ; < The rate at which the TSC increments in megahertz.
-
-MEM_DATA_STRUCT ENDS
-
-; ===============================================================================
-; UMA_INFO_STRUCT
-; ===============================================================================
-UMA_INFO STRUCT
- UmaBase UINT64 ? ; < UmaBase[63:0] = Addr[63:0]
- UmaSize UINT32 ? ; < UmaSize[31:0] = Addr[31:0]
- UmaAttributes UINT32 ? ; < Indicate the attribute of Uma
- UmaMode UINT8 ? ; < Indicate the mode of Uma
- MemClock UINT16 ? ; < Indicate memory running speed in MHz
- Reserved UINT8 (3) DUP (?) ; < Reserved for future usage
-UMA_INFO ENDS
-
-; ===============================================================================
-; Bitfield for ID
-; ===============================================================================
-ID_FIELD STRUCT
- SocketId UINT16 ?
-; OUT UINT16 SocketId:8; ; < Socket ID
-; OUT UINT16 ModuleId:8; ; < Module ID
-ID_FIELD ENDS
-
-; ===============================================================================
-; Union for ID of socket and module that will be passed out in call out
-; ===============================================================================
-ID_INFO UNION
- IdField ID_FIELD {} ; < Bitfield for ID
- IdInformation UINT16 ? ; < ID information for call out
-ID_INFO ENDS
-
- ; AGESA MEMORY ERRORS
-
- ; AGESA_ALERT Memory Errors
-MEM_ALERT_USER_TMG_MODE_OVERRULED EQU 04010000h ; < TIMING_MODE_SPECIFIC is requested but
- ; < cannot be applied to current configurations.
-MEM_ALERT_ORG_MISMATCH_DIMM EQU 04010100h ; < DIMM organization miss-match
-MEM_ALERT_BK_INT_DIS EQU 04010200h ; < Bank interleaving disable for internal issue
-
- ; AGESA_ERROR Memory Errors
-MEM_ERROR_NO_DQS_POS_RD_WINDOW EQU 04010300h ; < No DQS Position window for RD DQS
-MEM_ERROR_SMALL_DQS_POS_RD_WINDOW EQU 04020300h ; < Small DQS Position window for RD DQS
-MEM_ERROR_NO_DQS_POS_WR_WINDOW EQU 04030300h ; < No DQS Position window for WR DQS
-MEM_ERROR_SMALL_DQS_POS_WR_WINDOW EQU 04040300h ; < Small DQS Position window for WR DQS
-MEM_ERROR_ECC_DIS EQU 04010400h ; < ECC has been disabled as a result of an internal issue
-MEM_ERROR_DIMM_SPARING_NOT_ENABLED EQU 04010500h ; < DIMM sparing has not been enabled for an internal issues
-MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE EQU 04050300h ; < Receive Enable value is too large
-MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW EQU 04060300h ; < There is no DQS receiver enable window
-MEM_ERROR_DRAM_ENABLED_TIME_OUT EQU 04010600h ; < Time out when polling DramEnabled bit
-MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT EQU 04010700h ; < Time out when polling DctAccessDone bit
-MEM_ERROR_SEND_CTRL_WORD_TIME_OUT EQU 04010800h ; < Time out when polling SendCtrlWord bit
-MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT EQU 04010900h ; < Time out when polling PrefDramTrainMode bit
-MEM_ERROR_ENTER_SELF_REF_TIME_OUT EQU 04010A00h ; < Time out when polling EnterSelfRef bit
-MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT EQU 04010B00h ; < Time out when polling FreqChgInProg bit
-MEM_ERROR_EXIT_SELF_REF_TIME_OUT EQU 04020A00h ; < Time out when polling ExitSelfRef bit
-MEM_ERROR_SEND_MRS_CMD_TIME_OUT EQU 04010C00h ; < Time out when polling SendMrsCmd bit
-MEM_ERROR_SEND_ZQ_CMD_TIME_OUT EQU 04010D00h ; < Time out when polling SendZQCmd bit
-MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT EQU 04010E00h ; < Time out when polling DctExtraAccessDone bit
-MEM_ERROR_MEM_CLR_BUSY_TIME_OUT EQU 04010F00h ; < Time out when polling MemClrBusy bit
-MEM_ERROR_MEM_CLEARED_TIME_OUT EQU 04020F00h ; < Time out when polling MemCleared bit
-MEM_ERROR_FLUSH_WR_TIME_OUT EQU 04011000h ; < Time out when polling FlushWr bit
-MEM_ERROR_MAX_LAT_NO_WINDOW EQU 04070300h ; < Fail to find pass during Max Rd Latency training
-MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL EQU 04080300h ; < Fail to launch training code on an AP
-MEM_ERROR_PARALLEL_TRAINING_TIME_OUT EQU 04090300h ; < Fail to finish parallel training
-MEM_ERROR_NO_ADDRESS_MAPPING EQU 04011100h ; < No address mapping found for a dimm
-MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT EQU 040A0300h ; < There is no DQS receiver enable window and the value is equal to the largest value
-MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE EQU 040B0300h ; < Receive Enable value is too large and is 1 less than limit
-MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR EQU 04011200h ; < SPD Checksum error for NV_SPDCHK_RESTRT
-MEM_ERROR_NO_CHIPSELECT EQU 04011300h ; < No chipselects found
-MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM EQU 04011500h ; < Unbuffered dimm is not supported at 333MHz
-MEM_ERROR_WL_PRE_OUT_OF_RANGE EQU 040C0300h ; < Returned PRE value during write levelization was out of range
-MEM_ERROR_NO____RDDQS_WINDOW EQU 040D0300h ; < No RdDqs Window
-MEM_ERROR_NO____RDDQS_HEIGHT EQU 040E0300h ; < No RdDqs Height
-MEM_ERROR____DQS_ERROR EQU 040F0300h ; < RdDqs Error
-MEM_ERROR_INVALID____RDDQS_VALUE EQU 04022400h ; < RdDqs invalid value found
-MEM_ERROR____DQS_VREF_MARGIN_ERROR EQU 04023400h ; < RdDqs Vef Margin error found
-MEM_ERROR_LR_IBT_NOT_FOUND EQU 04013500h ; < No LR dimm IBT value is found
-MEM_ERROR_MR0_NOT_FOUND EQU 04023500h ; < No MR0 value is found
-MEM_ERROR_ODT_PATTERN_NOT_FOUND EQU 04033500h ; < No odt pattern value is found
-MEM_ERROR_RC2_IBT_NOT_FOUND EQU 04043500h ; < No RC2 IBT value is found
-MEM_ERROR_RC10_OP_SPEED_NOT_FOUND EQU 04053500h ; < No RC10 op speed is found
-MEM_ERROR_RTT_NOT_FOUND EQU 04063500h ; < No RTT value is found
-MEM_ERROR_P___NOT_FOUND EQU 04073500h ; < No training config value is found
-MEM_ERROR_SAO_NOT_FOUND EQU 04083500h ; < No slow access mode, Address timing and Output driver compensation value is found
-MEM_ERROR_CLK_DIS_MAP_NOT_FOUND EQU 04093500h ; < No CLK disable map is found
-MEM_ERROR_CKE_TRI_MAP_NOT_FOUND EQU 040A3500h ; < No CKE tristate map is found
-MEM_ERROR_ODT_TRI_MAP_NOT_FOUND EQU 040B3500h ; < No ODT tristate map is found
-MEM_ERROR_CS_TRI_MAP_NOT_FOUND EQU 040C3500h ; < No CS tristate map is found
-MEM_ERROR_TRAINING_SEED_NOT_FOUND EQU 040D3500h ; < No training seed is found
-
- ; AGESA_WARNING Memory Errors
- MEM_WARNING_UNSUPPORTED_QRDIMM EQU 04011600h ; < QR DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_UDIMM EQU 04021600h ; < U DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_SODIMM EQU 04031600h ; < SO-DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_X4DIMM EQU 04041600h ; < x4 DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_RDIMM EQU 04051600h ; < R DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_LRDIMM EQU 04061600h ; < LR DIMMs detected but not supported
-
- MEM_WARNING_EMP_NOT_SUPPORTED EQU 04011700h ; < Processor is not capable for EMP
- MEM_WARNING_EMP_CONFLICT EQU 04021700h ; < EMP cannot be enabled if channel interleaving,
- ; < bank interleaving, or bank swizzle is enabled.
- MEM_WARNING_EMP_NOT_ENABLED EQU 04031700h ; < Memory size is not power of two.
- MEM_WARNING_ECC_DIS EQU 04041700h ; < ECC has been disabled as a result of an internal issue
- MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED EQU 04011800h ; < Performance has been enabled, but battery life is preferred.
- MEM_WARNING_NO_SPDTRC_FOUND EQU 04011900h ; < No Trc timing value found in SPD of a dimm.
- MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED EQU 04012000h ; < Node Interleaveing Requested, but could not be enabled
- MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED EQU 04012100h ; < Channel Interleaveing Requested, but could not be enabled
- MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED EQU 04012200h ; < Bank Interleaveing Requested, but could not be enabled
- MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED EQU 04012300h ; < Voltage 1.35 determined, but could not be supported
- MEM_WARNING_INITIAL_DDR3VOLT_NONZERO EQU 04012400h ; < DDR3 voltage initial value is not 0
- MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO EQU 04012500h ; < Cannot find a commonly supported VDDIO
-
- ; AGESA_FATAL Memory Errors
- MEM_ERROR_MINIMUM_MODE EQU 04011A00h ; < Running in minimum mode
- MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM EQU 04011B00h ; < DIMM modules are miss-matched
- MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM EQU 04011C00h ; < No DIMMs have been found on system
- MEM_ERROR_MISMATCH_DIMM_CLOCKS EQU 04011D00h ; < DIMM clocks miss-matched
- MEM_ERROR_NO_CYC_TIME EQU 04011E00h ; < No cycle time found
- MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS EQU 04011F00h ; < Heap allocation error with dynamic storing of trained timings
- MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs EQU 04021F00h ; < Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
- MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV EQU 04031F00h ; < Heap allocation error with REMOTE_TRAINING_ENV
- MEM_ERROR_HEAP_ALLOCATE_FOR_SPD EQU 04041F00h ; < Heap allocation error for SPD data
- MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA EQU 04051F00h ; < Heap allocation error for RECEIVED_DATA during parallel training
- MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS EQU 04061F00h ; < Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
- MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA EQU 04071F00h ; < Heap allocation error for Training Data
- MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK EQU 04081F00h ; < Heap allocation error for DIMM Identify "MEM_NB_BLOCK
- MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM EQU 04022300h ; < No Constructor for DIMM Identify
- MEM_ERROR_VDDIO_UNSUPPORTED EQU 04022500h ; < VDDIO of the dimms on the board is not supported
- MEM_ERROR_HEAP_ALLOCATE_FOR___ EQU 040B1F00h ; < Heap allocation error for training data
- MEM_ERROR_HEAP_DEALLOCATE_FOR___ EQU 040C1F00h ; < Heap de-allocation error for training data
-
- ; AGESA_CRITICAL Memory Errors
- MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 EQU 04091F00h ; < Heap allocation error for DMI table for DDR3
- MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 EQU 040A1F00h ; < Heap allocation error for DMI table for DDR2
- MEM_ERROR_UNSUPPORTED_DIMM_CONFIG EQU 04011400h ; < Dimm population is not supported
-
-
-; ----------------------------------------------------------------------------
-; *
-; * END OF MEMORY-SPECIFIC DATA STRUCTURES
-; *
-; *----------------------------------------------------------------------------
-;
-
-
-; ----------------------------------------------------------------------------
-; *
-; * CPU RELATED DEFINITIONS
-; *
-; *----------------------------------------------------------------------------
-;
-
-; CPU Event definitions.
-
-; Defines used to filter CPU events based on functional blocks
-CPU_EVENT_PM_EVENT_MASK EQU 0FF00FF00h
-CPU_EVENT_PM_EVENT_CLASS EQU 008000400h
-
-;================================================================
-; CPU General events
-; Heap allocation (AppFunction = 01h)
-CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT EQU 008000100h
-CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED EQU 008010100h
-CPU_ERROR_HEAP_IS_FULL EQU 008020100h
-CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED EQU 008030100h
-CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT EQU 008040100h
-; BrandId (AppFunction = 02h)
-CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE EQU 008000200h
-; Micro code patch (AppFunction = 03h)
-CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED EQU 008000300h
-; Power management (AppFunction = 04h)
-CPU_EVENT_PM_PSTATE_OVERCURRENT EQU 008000400h
-CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT EQU 008010400h
-CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE EQU 008020400h
-CPU_ERROR_PM_NB_PSTATE_MISMATCH EQU 008030400h
-; Other CPU events (AppFunction = 05h)
-CPU_EVENT_BIST_ERROR EQU 008000500h
-CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY EQU 008010500h
-CPU_EVENT_STACK_REENTRY EQU 008020500h
-CPU_EVENT_CORE_NOT_IDENTIFIED EQU 008030500h
-;=================================================================
-; CPU Feature events
-; Execution cache (AppFunction = 21h)
-; AGESA_CACHE_SIZE_REDUCED 2101
-; AGESA_CACHE_REGIONS_ACROSS_1MB 2102
-; AGESA_CACHE_REGIONS_ACROSS_4GB 2103
-; AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 2104
-; AGESA_CACHE_START_ADDRESS_LESS_D0000 2105
-; AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 2106
-; AGESA_DEALLOCATE_CACHE_REGIONS 2107
-CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR EQU 008002100h
-; Core Leveling (AppFunction = 22h)
-CPU_WARNING_ADJUSTED_LEVELING_MODE EQU 008002200h
-; HT Assist (AppFunction = 23h)
-CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG EQU 008002300h
-
-; CPU Build Configuration structures and definitions
-
-; Build Configuration values for BLDGCFG_AP_MTRR_SETTINGS
-AP_MTRR_SETTINGS STRUCT
- MsrAddr UINT32 ? ; < Fixed-Sized MTRR address
- MsrData UINT64 ? ; < MTRR Settings
-AP_MTRR_SETTINGS ENDS
-
-AMD_AP_MTRR_FIX64k_00000 EQU 000000250h
-AMD_AP_MTRR_FIX16k_80000 EQU 000000258h
-AMD_AP_MTRR_FIX16k_A0000 EQU 000000259h
-AMD_AP_MTRR_FIX4k_C0000 EQU 000000268h
-AMD_AP_MTRR_FIX4k_C8000 EQU 000000269h
-AMD_AP_MTRR_FIX4k_D0000 EQU 00000026Ah
-AMD_AP_MTRR_FIX4k_D8000 EQU 00000026Bh
-AMD_AP_MTRR_FIX4k_E0000 EQU 00000026Ch
-AMD_AP_MTRR_FIX4k_E8000 EQU 00000026Dh
-AMD_AP_MTRR_FIX4k_F0000 EQU 00000026Eh
-AMD_AP_MTRR_FIX4k_F8000 EQU 00000026Fh
-CPU_LIST_TERMINAL EQU 0FFFFFFFFh
-
-; ***********************************************************************
-; *
-; * AGESA interface Call-Out function parameter structures
-; *
-; **********************************************************************
-
- ; Parameters structure for interface call-out AgesaAllocateBuffer
-AGESA_BUFFER_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- BufferLength UINT32 ? ; < Size of buffer to allocate
- BufferHandle UINT32 ? ; < Identifier or name for the buffer
- BufferPointer POINTER ? ; < location of the created buffer
-AGESA_BUFFER_PARAMS ENDS
-
- ; Parameters structure for interface call-out AgesaRunCodeOnAp
-AP_EXE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- FunctionNumber UINT32 ? ; < Index of the procedure to execute
- RelatedDataBlock POINTER ? ; < Location of data structure the procedure will use
- RelatedBlockLength UINT32 ? ; < Size of the related data block
-AP_EXE_PARAMS ENDS
-
- ; Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery
-AGESA_READ_SPD_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < standard header
- SocketId UINT8 ? ; < Address of SPD - socket ID
- MemChannelId UINT8 ? ; < Address of SPD - memory channel ID
- DimmId UINT8 ? ; < Address of SPD - DIMM ID
- Buffer POINTER ? ; < Location where to place the SPD content
- MemData POINTER ? ; < Location of the MemData structure, for reference
-AGESA_READ_SPD_PARAMS ENDS
-
- ; Buffer Handles
- AMD_DMI_INFO_BUFFER_HANDLE EQU 000D000h ; < Assign 0x000D000 buffer handle to DMI function
- AMD_PSTATE_DATA_BUFFER_HANDLE EQU 000D001h ; < Assign 0x000D001 buffer handle to Pstate data
- AMD_PSTATE_ACPI_BUFFER_HANDLE EQU 000D002h ; < Assign 0x000D002 buffer handle to Pstate table
- AMD_BRAND_ID_BUFFER_HANDLE EQU 000D003h ; < Assign 0x000D003 buffer handle to Brand ID
- AMD_ACPI_SLIT_BUFFER_HANDLE EQU 000D004h ; < Assign 0x000D004 buffer handle to SLIT function
- AMD_SRAT_INFO_BUFFER_HANDLE EQU 000D005h ; < Assign 0x000D005 buffer handle to SRAT function
- AMD_WHEA_BUFFER_HANDLE EQU 000D006h ; < Assign 0x000D006 buffer handle to WHEA function
- AMD_S3_INFO_BUFFER_HANDLE EQU 000D007h ; < Assign 0x000D007 buffer handle to S3 function
- AMD_S3_NB_INFO_BUFFER_HANDLE EQU 000D008h ; < Assign 0x000D008 buffer handle to S3 NB device info
- AMD_ACPI_ALIB_BUFFER_HANDLE EQU 000D009h ; < Assign 0x000D009 buffer handle to ALIB SSDT table
- AMD_ACPI_IVRS_BUFFER_HANDLE EQU 000D00Ah ; < Assign 0x000D00A buffer handle to IOMMU IVRS table
-AMD_BUFFER_HANDLE TEXTEQU <DWORD>
-; ***********************************************************************
-; *
-; * AGESA interface Call-Out function prototypes
-; *
-; **********************************************************************
-
-; ***********************************************************************
-; *
-; * AGESA interface structure definition and function prototypes
-; *
-; **********************************************************************
-
-; *********************************************************************
-; * Platform Configuration: The parameters in boot branch function
-; *********************************************************************
-
-; The possible platform control flow settings.
- Nfcm EQU 0 ; < Normal Flow Control Mode.
- UmaDr EQU 1 ; < UMA using Display Refresh flow control.
- UmaIfcm EQU 2 ; < UMA using Isochronous Flow Control.
- Ifcm EQU 3 ; < Isochronous Flow Control Mode (other than for UMA).
- Iommu EQU 4 ; < An IOMMU is in use in the system.
- MaxControlFlow EQU 5 ; < Not a control flow mode, use for limit checking.
-PLATFORM_CONTROL_FLOW TEXTEQU <DWORD>
-
-; Platform Deemphasis Levels.
- DeemphasisLevelNone EQU 0 ; < No Deemphasis.
- DeemphasisLevelMinus3 EQU 1 ; < Minus 3 db deemphasis.
- DeemphasisLevelMinus6 EQU 2 ; < Minus 6 db deemphasis.
- DeemphasisLevelMinus8 EQU 3 ; < Minus 8 db deemphasis.
- DeemphasisLevelMinus11 EQU 4 ; < Minus 11 db deemphasis.
- DeemphasisLevelMinus11pre8 EQU 5 ; < Minus 11, Minus 8 precursor db deemphasis.
- DcvLevelNone EQU 16 ; < No DCV Deemphasis.
- DcvLevelMinus2 EQU 17 ; < Minus 2 db DCV deemphasis.
- DcvLevelMinus3 EQU 18 ; < Minus 3 db DCV deemphasis.
- DcvLevelMinus5 EQU 19 ; < Minus 5 db DCV deemphasis.
- DcvLevelMinus6 EQU 20 ; < Minus 6 db DCV deemphasis.
- DcvLevelMinus7 EQU 21 ; < Minus 7 db DCV deemphasis.
- DcvLevelMinus8 EQU 22 ; < Minus 8 db DCV deemphasis.
- DcvLevelMinus9 EQU 23 ; < Minus 9 db DCV deemphasis.
- DcvLevelMinus11 EQU 24 ; < Minus 11 db DCV deemphasis.
- MaxPlatformDeemphasisLevel EQU 25 ; < Not a deemphasis level, use for limit checking.
-PLATFORM_DEEMPHASIS_LEVEL TEXTEQU <DWORD>
-
-; Provide Deemphasis Levels for HT Links.
-;
-; For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will
-; be checked for a match. The item matches for a Socket, Link if the link frequency is
-; is in the inclusive range HighFreq:LoFreq.
-; AGESA does not set deemphasis in IO devices, only in processors.
-
-CPU_HT_DEEMPHASIS_LEVEL STRUCT
- ; Match fields
- Socket UINT8 ? ; < One Socket on which this Link is located
- Link UINT8 ? ; < The Link on this Processor.
- LoFreq UINT8 ? ; < If the link is set to this frequency or greater, apply these levels, and
- HighFreq UINT8 ? ; < If the link is set to this frequency or less, apply these levels.
- ; Value fields
- ReceiverDeemphasis PLATFORM_DEEMPHASIS_LEVEL ? ; < The deemphasis level for this link
- DcvDeemphasis PLATFORM_DEEMPHASIS_LEVEL ? ; < The DCV, or far transmitter deemphasis level.
-CPU_HT_DEEMPHASIS_LEVEL ENDS
-
-; The possible hardware prefetch mode settings.
- HARDWARE_PREFETCHER_AUTO EQU 0 ; Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
- DISABLE_L1_PREFETCHER EQU 1 ; Use the recommended settings for the hardware prefetcher, but disable L1 prefetching.
- DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES EQU 2 ; Use the recommended setting for the hardware prefetcher, but disable training on software prefetches.
- DISABLE_L1_PREFETCHER_AND_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES EQU 3 ; Use the recommended settings for the hardware prefetcher, but disable both the L1 prefetcher and training on software prefetches.
- DISABLE_HARDWARE_PREFETCH EQU 4 ; Disable hardware prefetching.
- MAX_HARDWARE_PREFETCH_MODE EQU 5 ; Not a hardware prefetch mode, use for limit checking.
-HARDWARE_PREFETCH_MODE TEXTEQU <DWORD>
-
-; The possible software prefetch mode settings.
- SOFTWARE_PREFETCHES_AUTO EQU 0 ; Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
- DISABLE_SOFTWARE_PREFETCHES EQU 1 ; Disable software prefetches (convert software prefetch instructions to NOP).
- MAX_SOFTWARE_PREFETCH_MODE EQU 2 ; Not a software prefetch mode, use for limit checking.
-SOFTWARE_PREFETCH_MODE TEXTEQU <DWORD>
-
-; Advanced performance tunings, prefetchers.
-; These settings provide for performance tuning to optimize for specific workloads.
-ADVANCED_PERFORMANCE_PROFILE STRUCT
- HardwarePrefetchMode HARDWARE_PREFETCH_MODE ? ; This value provides for advanced performance tuning by controlling the hardware prefetcher setting.
- SoftwarePrefetchMode SOFTWARE_PREFETCH_MODE ? ; This value provides for advanced performance tuning by controlling the software prefetch instructions.
- DramPrefetchMode DRAM_PREFETCH_MODE ? ; This value provides for advanced performance tuning by controlling the DRAM prefetcher setting.
-ADVANCED_PERFORMANCE_PROFILE ENDS
-
-; The possible platform power policy settings.
- Performance EQU 0 ; < Optimize for performance.
- BatteryLife EQU 1 ; < Optimize for battery life.
- MaxPowerPolicy EQU 2 ; < Not a power policy mode, use for limit checking.
-PLATFORM_POWER_POLICY TEXTEQU <DWORD>
-
-; Platform performance settings for optimized settings.
-; Several configuration settings for the processor depend upon other parts and
-; general designer choices for the system. The determination of these data points
-; is not standard for all platforms, so the host environment needs to provide these
-; to specify how the system is to be configured.
-PERFORMANCE_PROFILE STRUCT
- PlatformControlFlowMode PLATFORM_CONTROL_FLOW ? ; < The platform's control flow mode for optimum platform performance.
- UseHtAssist BOOLEAN ? ; < HyperTransport link traffic optimization.
- UseAtmMode BOOLEAN ? ; < HyperTransport link traffic optimization.
- Use32ByteRefresh BOOLEAN ? ; < Display Refresh traffic generates 32 byte requests.
- UseVariableMctIsocPriority BOOLEAN ? ; < The Memory controller will be set to Variable Isoc Priority.
- AdvancedPerformanceProfile ADVANCED_PERFORMANCE_PROFILE {} ; < The advanced platform performance settings.
- PlatformPowerPolicy PLATFORM_POWER_POLICY ? ; < The platform's desired power policy
-PERFORMANCE_PROFILE ENDS
-
-; Platform settings that describe the voltage regulator modules of the system.
-; Many power management settings are dependent upon the characteristics of the
-; on-board voltage regulator module (VRM). The host environment needs to provide
-; these to specify how the system is to be configured.
-PLATFORM_VRM_CONFIGURATION STRUCT
- CurrentLimit UINT32 ? ; < Vrm Current Limit.
- LowPowerThreshold UINT32 ? ; < Vrm Low Power Threshold.
- SlewRate UINT32 ? ; < Vrm Slew Rate.
- AdditionalDelay UINT32 ? ; < Vrm Additional Delay.
- HiSpeedEnable BOOLEAN ? ; < Select high speed VRM.
- InrushCurrentLimit UINT32 ? ; < Vrm Inrush Current Limit.
-PLATFORM_VRM_CONFIGURATION ENDS
-
-; The VRM types to characterize.
- CoreVrm EQU 0 ; < VDD plane.
- NbVrm EQU 1 ; < VDDNB plane.
- MaxVrmType EQU 2 ; < Not a valid VRM type, use for limit checking.
-PLATFORM_VRM_TYPE TEXTEQU <DWORD>
-
-; FCH Platform Configuration Policy
-FCH_PLATFORM_POLICY STRUCT
- CfgSmbus0BaseAddress UINT16 ? ; SMBUS0 Controller Base Address
- CfgSmbus1BaseAddress UINT16 ? ; SMBUS1 Controller Base Address
- CfgSioPmeBaseAddress UINT16 ? ; I/O base address for LPC I/O target range
- CfgAcpiPm1EvtBlkAddr UINT16 ? ; I/O base address of ACPI power management Event Block
- CfgAcpiPm1CntBlkAddr UINT16 ? ; I/O base address of ACPI power management Control Block
- CfgAcpiPmTmrBlkAddr UINT16 ? ; I/O base address of ACPI power management Timer Block
- CfgCpuControlBlkAddr UINT16 ? ; I/O base address of ACPI power management CPU Control Block
- CfgAcpiGpe0BlkAddr UINT16 ? ; I/O base address of ACPI power management General Purpose Event Block
- CfgSmiCmdPortAddr UINT16 ? ; I/O base address of ACPI SMI Command Block
- CfgAcpiPmaCntBlkAddr UINT16 ? ; I/O base address of ACPI power management additional control block
- CfgGecShadowRomBase UINT32 ? ; 32-bit base address to the GEC shadow ROM
- CfgWatchDogTimerBase UINT32 ? ; Watchdog Timer base address
- CfgSpiRomBaseAddress UINT32 ? ; Base address for the SPI ROM controller
- CfgHpetBaseAddress UINT32 ? ; HPET MMIO base address
- CfgAzaliaSsid UINT32 ? ; Subsystem ID of HD Audio controller
- CfgSmbusSsid UINT32 ? ; Subsystem ID of SMBUS controller
- CfgIdeSsid UINT32 ? ; Subsystem ID of IDE controller
- CfgSataAhciSsid UINT32 ? ; Subsystem ID of SATA controller in AHCI mode
- CfgSataIdeSsid UINT32 ? ; Subsystem ID of SATA controller in IDE mode
- CfgSataRaid5Ssid UINT32 ? ; Subsystem ID of SATA controller in RAID5 mode
- CfgSataRaidSsid UINT32 ? ; Subsystem ID of SATA controller in RAID mode
- CfgEhciSsid UINT32 ? ; Subsystem ID of EHCI
- CfgOhciSsid UINT32 ? ; Subsystem ID of OHCI
- CfgLpcSsid UINT32 ? ; Subsystem ID of LPC ISA Bridge
- CfgSdSsid UINT32 ? ; Subsystem ID of SecureDigital controller
- CfgXhciSsid UINT32 ? ; Subsystem ID of XHCI
- CfgFchPort80BehindPcib BOOLEAN ? ; Is port80 cycle going to the PCI bridge
- CfgFchEnableAcpiSleepTrap BOOLEAN ? ; ACPI sleep SMI enable/disable
- CfgFchGppLinkConfig GPP_LINKMODE ? ; FCH GPP link configuration
- CfgFchGppPort0Present BOOLEAN ? ; Is FCH GPP port 0 present
- CfgFchGppPort1Present BOOLEAN ? ; Is FCH GPP port 1 present
- CfgFchGppPort2Present BOOLEAN ? ; Is FCH GPP port 2 present
- CfgFchGppPort3Present BOOLEAN ? ; Is FCH GPP port 3 present
- CfgFchGppPort0HotPlug BOOLEAN ? ; Is FCH GPP port 0 hotplug capable
- CfgFchGppPort1HotPlug BOOLEAN ? ; Is FCH GPP port 1 hotplug capable
- CfgFchGppPort2HotPlug BOOLEAN ? ; Is FCH GPP port 2 hotplug capable
- CfgFchGppPort3HotPlug BOOLEAN ? ; Is FCH GPP port 3 hotplug capable
-
- CfgFchEsataPortBitMap UINT8 ? ; ESATA Port definition, eg: [0]=1, means port 0 is ESATA capable
- CfgFchIrPinControl UINT8 ? ; Register bitfield describing Infrared Pin Control:
- CfgFchSdClockControl SD_CLOCK_CONTROL ? ; FCH SD Clock Control
- CfgFchSciMapControl POINTER ? ; FCH SCI Mapping Control
- CfgFchSataPhyControl POINTER ? ; FCH SATA PHY Control
- CfgFchGpioControl POINTER ? ; FCH GPIO Control
-FCH_PLATFORM_POLICY ENDS
-
-
-; Build Option/Configuration Boolean Structure
-BUILD_OPT_CFG STRUCT
- ; Build Option Area
- VersionString AMD_CODE_HEADER {} ; < AMD embedded code version string
- OptionUDimms BOOLEAN ? ; < UDIMMS
- OptionRDimms BOOLEAN ? ; < RDIMMS
- OptionLrDimms BOOLEAN ? ; < LRDIMMS
- OptionEcc BOOLEAN ? ; < ECC
- OptionBankInterleave BOOLEAN ? ; < BANK_INTERLEAVE
- OptionDctInterleave BOOLEAN ? ; < DCT_INTERLEAVE
- OptionNodeInterleave BOOLEAN ? ; < NODE_INTERLEAVE
- OptionParallelTraining BOOLEAN ? ; < PARALLEL_TRAINING
- OptionOnlineSpare BOOLEAN ? ; < ONLINE_SPARE
- OptionMemRestore BOOLEAN ? ; < MEM CONTEXT RESTORE
- OptionMultisocket BOOLEAN ? ; < MULTISOCKET
- OptionAcpiPstates BOOLEAN ? ; < ACPI_PSTATES
- OptionPStatesInHpcMode BOOLEAN ? ; < PSTATES_HPC_MODE
- OptionSrat BOOLEAN ? ; < SRAT
- OptionSlit BOOLEAN ? ; < SLIT
- OptionWhea BOOLEAN ? ; < WHEA
- OptionDmi BOOLEAN ? ; < DMI
- OptionEarlySamples BOOLEAN ? ; < EARLY_SAMPLES
- OptionAddrToCsTranslator BOOLEAN ? ; < ADDR_TO_CS_TRANSLATOR
-
- ; Build Configuration Area
- CfgPciMmioAddress UINT64 ? ; < PciMmioBase
- CfgPciMmioSize UINT32 ? ; < PciMmioSize
- CfgPlatVrmCfg PLATFORM_VRM_CONFIGURATION (MaxVrmType) DUP ({}) ; < Several configuration settings for the voltage regulator modules.
- CfgPlatNumIoApics UINT32 ? ; < PlatformApicIoNumber
- CfgMemInitPstate UINT32 ? ; < MemoryInitPstate
- CfgPlatformC1eMode PLATFORM_C1E_MODES ? ; < PlatformC1eMode
- CfgPlatformC1eOpData UINT32 ? ; < PlatformC1eOpData
- CfgPlatformC1eOpData1 UINT32 ? ; < PlatformC1eOpData1
- CfgPlatformC1eOpData2 UINT32 ? ; < PlatformC1eOpData2
- CfgPlatformC1eOpData3 UINT32 ? ; < PlatformC1eOpData3
- CfgPlatformCStateMode PLATFORM_CSTATE_MODES ? ; < PlatformCStateMode
- CfgPlatformCStateOpData UINT32 ? ; < PlatformCStateOpData
- CfgPlatformCStateIoBaseAddress UINT16 ? ; < PlatformCStateIoBaseAddress
- CfgPlatformCpbMode PLATFORM_CPB_MODES ? ; < PlatformCpbMode
- CfgLowPowerPstateForProcHot PLATFORM_LOW_POWER_PSTATE_MODES ? ; < Low power Pstate for PROCHOT mode
- CfgCoreLevelingMode UINT32 ? ; < CoreLevelingCofig
- CfgPerformanceProfile PERFORMANCE_PROFILE {} ; < The platform's control flow mode and platform performance settings.
- CfgPlatformDeemphasisList POINTER ? ; < HT Deemphasis
- CfgAmdPlatformType UINT32 ? ; < AmdPlatformType
- CfgAmdPstateCapValue UINT32 ? ; < Amd pstate ceiling enabling deck
-
- CfgMemoryBusFrequencyLimit MEMORY_BUS_SPEED ? ; < Memory Bus Frequency Limit
- CfgMemoryModeUnganged BOOLEAN ? ; < Memory Mode Unganged
- CfgMemoryQuadRankCapable BOOLEAN ? ; < Memory Quad Rank Capable
- CfgMemoryQuadrankType QUANDRANK_TYPE ? ; < Memory Quadrank Type
- CfgMemoryRDimmCapable BOOLEAN ? ; < Memory RDIMM Capable
- CfgMemoryLRDimmCapable BOOLEAN ? ; < Memory LRDIMM Capable
- CfgMemoryUDimmCapable BOOLEAN ? ; < Memory UDIMM Capable
- CfgMemorySODimmCapable BOOLEAN ? ; < Memory SODimm Capable
- CfgLimitMemoryToBelow1Tb BOOLEAN ? ; < Limit memory address space to below 1TB
- CfgMemoryEnableBankInterleaving BOOLEAN ? ; < Memory Enable Bank Interleaving
- CfgMemoryEnableNodeInterleaving BOOLEAN ? ; < Memory Enable Node Interleaving
- CfgMemoryChannelInterleaving BOOLEAN ? ; < Memory Channel Interleaving
- CfgMemoryPowerDown BOOLEAN ? ; < Memory Power Down
- CfgPowerDownMode POWER_DOWN_MODE ? ; < Power Down Mode
- CfgOnlineSpare BOOLEAN ? ; < Online Spare
- CfgMemoryParityEnable BOOLEAN ? ; < Memory Parity Enable
- CfgBankSwizzle BOOLEAN ? ; < Bank Swizzle
- CfgTimingModeSelect USER_MEMORY_TIMING_MODE ? ; < Timing Mode Select
- CfgMemoryClockSelect MEMORY_BUS_SPEED ? ; < Memory Clock Select
- CfgDqsTrainingControl BOOLEAN ? ; < Dqs Training Control
- CfgIgnoreSpdChecksum BOOLEAN ? ; < Ignore Spd Checksum
- CfgUseBurstMode BOOLEAN ? ; < Use Burst Mode
- CfgMemoryAllClocksOn BOOLEAN ? ; < Memory All Clocks On
- CfgEnableEccFeature BOOLEAN ? ; < Enable ECC Feature
- CfgEccRedirection BOOLEAN ? ; < ECC Redirection
- CfgScrubDramRate UINT16 ? ; < Scrub Dram Rate
- CfgScrubL2Rate UINT16 ? ; < Scrub L2Rate
- CfgScrubL3Rate UINT16 ? ; < Scrub L3Rate
- CfgScrubIcRate UINT16 ? ; < Scrub Ic Rate
- CfgScrubDcRate UINT16 ? ; < Scrub Dc Rate
- CfgEccSyncFlood BOOLEAN ? ; < ECC Sync Flood
- CfgEccSymbolSize UINT16 ? ; < ECC Symbol Size
- CfgHeapDramAddress UINT64 ? ; < Heap contents will be temporarily stored in this address during the transition
- CfgNodeMem1GBAlign BOOLEAN ? ; < Node Mem 1GB boundary Alignment
- CfgS3LateRestore BOOLEAN ? ; < S3 Late Restore
- CfgAcpiPstateIndependent BOOLEAN ? ; < PSD method dependent/Independent
- CfgApMtrrSettingsList POINTER ? ; < The AP's MTRR settings before final halt
- CfgUmaMode UMA_MODE ? ; < Uma Mode
- CfgUmaSize UINT32 ? ; < Uma Size [31:0]=Addr[47:16]
- CfgUmaAbove4G BOOLEAN ? ; < Uma Above 4G Support
- CfgUmaAlignment UMA_ALIGNMENT ? ; < Uma alignment
- CfgProcessorScopeInSb BOOLEAN ? ; < ACPI Processor Object in \_SB scope
- CfgProcessorScopeName0 CHAR8 ? ; < OEM specific 1st character of processor scope name.
- CfgProcessorScopeName1 CHAR8 ? ; < OEM specific 2nd character of processor scope name.
- CfgGnbHdAudio UINT8 ? ; < Gnb HD Audio Enable
- CfgAbmSupport UINT8 ? ; < ABM support
- CfgDynamicRefreshRate UINT8 ? ; < Dynamic refresh rate
- CfgLcdBackLightControl UINT16 ? ; < Lcd back light control
- CfgGnb3dStereoPinIndex UINT8 ? ; < 3D Stereo Pin ID
- CfgTempPcieMmioBaseAddress UINT32 ? ; < Temp pcie MMIO base address
- CfgGnbIGPUSSID UINT32 ? ; < Gnb internal GPU SSID
- CfgGnbHDAudioSSID UINT32 ? ; < Gnb HD Audio SSID
- CfgGnbPcieSSID UINT32 ? ; < Gnb PCIe SSID
- CfgLvdsSpreadSpectrum UINT16 ? ; < Lvds Spread Spectrum. Build-time customizable only
- CfgLvdsSpreadSpectrumRate UINT16 ? ; < Lvds Spread Spectrum Rate. Build-time customizable only
- FchBldCfg POINTER ? ; < FCH platform build configuration policy
- CfgIommuSupport BOOLEAN ? ; IOMMU support
- CfgLvdsPowerOnSeqDigonToDe UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqDeToVaryBl UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqDeToDigon UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqVaryBlToDe UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqOnToOffDelay UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqVaryBlToBlon UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqBlonToVaryBl UINT8 ? ; Panel initialization timing
- CfgLvdsMaxPixelClockFreq UINT16 ? ; The maximum pixel clock frequency supported
- CfgLcdBitDepthControlValue UINT32 ? ; The LCD bit depth control settings
- CfgLvds24bbpPanelMode UINT8 ? ; The LVDS 24 BBP mode
- CfgLvdsMiscControl LVDS_MISC_CONTROL {}; THe LVDS Misc control
- CfgPcieRefClkSpreadSpectrum UINT16 ? ; PCIe Reference Clock Spread Spectrum
- CfgExternalVrefCtlFeature BOOLEAN ? ; External Vref control
- CfgForceTrainMode FORCE_TRAIN_MODE ? ; < Force Train Mode
- CfgGnbRemoteDisplaySupport BOOLEAN ? ; Wireless Display Support
- CfgIvrsExclusionRangeList POINTER ? ; IOMMU Exclusion Range List
- Reserved BOOLEAN ? ; < reserved...
-BUILD_OPT_CFG ENDS
-
- ; A structure containing platform specific operational characteristics. This
- ; structure is initially populated by the initializer with a copy of the same
- ; structure that was created at build time using the build configuration controls.
-PLATFORM_CONFIGURATION STRUCT
- PlatformProfile PERFORMANCE_PROFILE {} ; < Several configuration settings for the processor.
- PlatformDeemphasisList POINTER ? ; < Deemphasis levels for the platform's HT links.
- CoreLevelingMode UINT8 ? ; < Indicates how to balance the number of cores per processor.
- C1eMode PLATFORM_C1E_MODES ? ; < Specifies the method of C1e enablement - Disabled, HW, or message based.
- C1ePlatformData UINT32 ? ; < If C1eMode is HW, specifies the P_LVL3 I/O port of the platform.
- C1ePlatformData1 UINT32 ? ; < If C1eMode is SW, specifies the address of chipset's SMI command port.
- C1ePlatformData2 UINT32 ? ; < If C1eMode is SW, specifies the unique number used by the SMI handler to identify SMI source.
- C1ePlatformData3 UINT32 ? ; < If C1eMode is Auto, specifies the P_LVL3 I/O port of the platform for HW C1e
- CStateMode PLATFORM_CSTATE_MODES ? ; < Specifies the method of C-State enablement - Disabled, or C6.
- CStatePlatformData UINT32 ? ; < This element specifies some pertinent data needed for the operation of the Cstate feature
- ; < If CStateMode is CStateModeC6, this item is reserved
- CStateIoBaseAddress UINT16 ? ; < This item specifies a free block of 8 consecutive bytes of I/O ports that
- ; < can be used to allow the CPU to enter Cstates.
- CpbMode PLATFORM_CPB_MODES ? ; < Specifies the method of core performance boost enablement - Disabled, or Auto.
- UserOptionDmi BOOLEAN ? ; < When set to TRUE, the DMI data table is generated.
- UserOptionPState BOOLEAN ? ; < When set to TRUE, the PState data tables are generated.
- UserOptionSrat BOOLEAN ? ; < When set to TRUE, the SRAT data table is generated.
- UserOptionSlit BOOLEAN ? ; < When set to TRUE, the SLIT data table is generated.
- UserOptionWhea BOOLEAN ? ; < When set to TRUE, the WHEA data table is generated.
- LowPowerPstateForProcHot PLATFORM_LOW_POWER_PSTATE_MODES ? ; < Specifies the method of low power Pstate for PROCHOT enablement - Disabled, or Auto.
- PowerCeiling UINT32 ? ; < P-State Ceiling Enabling Deck - Max power milli-watts.
- ForcePstateIndependent BOOLEAN ? ; < P-State _PSD independence or dependence.
- PStatesInHpcMode BOOLEAN ? ; < High performance computing (HPC) mode
- NumberOfIoApics UINT32 ? ; < Number of I/O APICs in the system
- VrmProperties PLATFORM_VRM_CONFIGURATION (MaxVrmType) DUP ({}) ; < Several configuration settings for the voltage regulator modules.
- ProcessorScopeInSb BOOLEAN ? ; < ACPI Processor Object in \_SB scope
- ProcessorScopeName0 CHAR8 ? ; < OEM specific 1st character of processor scope name.
- ProcessorScopeName1 CHAR8 ? ; < OEM specific 2nd character of processor scope name.
- GnbHdAudio UINT8 ? ; < Control GFX HD Audio controller(Used for HDMI and DP display output),
- ; < essentially it enables function 1 of graphics device.
- ; < @li 0 = HD Audio disable
- ; < @li 1 = HD Audio enable
- AbmSupport UINT8 ? ; < Automatic adjust LVDS/eDP Back light level support.It is
- ; < characteristic specific to display panel which used by platform design.
- ; < @li 0 = ABM support disabled
- ; < @li 1 = ABM support enabled
- DynamicRefreshRate UINT8 ? ; < Adjust refresh rate on LVDS/eDP.
- LcdBackLightControl UINT16 ? ; < The PWM frequency to LCD backlight control.
- ; < If equal to 0 backlight not controlled by iGPU.
-PLATFORM_CONFIGURATION ENDS
-
-
-; *********************************************************************
-; * Structures for: AmdInitLate
-; *********************************************************************
- PROC_VERSION_LENGTH EQU 48
- MAX_DIMMS_PER_SOCKET EQU 16
-
-
- ; Interface Parameter Structures
- ; DMI Type4 - Processor ID
-TYPE4_PROC_ID STRUCT
- ProcIdLsd UINT32 ? ; < Lower half of 64b ID
- ProcIdMsd UINT32 ? ; < Upper half of 64b ID
-TYPE4_PROC_ID ENDS
-
- ; DMI Type 4 - Processor information
-TYPE4_DMI_INFO STRUCT
- T4ProcType UINT8 ? ; < CPU Type
- T4ProcFamily UINT8 ? ; < Family 1
- T4ProcId TYPE4_PROC_ID {} ; < Id
- T4Voltage UINT8 ? ; < Voltage
- T4ExternalClock UINT16 ? ; < External clock
- T4MaxSpeed UINT16 ? ; < Max speed
- T4CurrentSpeed UINT16 ? ; < Current speed
- T4Status UINT8 ? ; < Status
- T4ProcUpgrade UINT8 ? ; < Up grade
- T4CoreCount UINT8 ? ; < Core count
- T4CoreEnabled UINT8 ? ; < Core Enable
- T4ThreadCount UINT8 ? ; < Thread count
- T4ProcCharacteristics UINT16 ? ; < Characteristics
- T4ProcFamily2 UINT16 ? ; < Family 2
- T4ProcVersion CHAR8 (PROC_VERSION_LENGTH) DUP (?) ; < Cpu version
-TYPE4_DMI_INFO ENDS
-
- ; DMI Type 7 - Cache information
-TYPE7_DMI_INFO STRUCT
- T7CacheCfg UINT16 ? ; < Cache cfg
- T7MaxCacheSize UINT16 ? ; < Max size
- T7InstallSize UINT16 ? ; < Install size
- T7SupportedSramType UINT16 ? ; < Supported Sram Type
- T7CurrentSramType UINT16 ? ; < Current type
- T7CacheSpeed UINT8 ? ; < Speed
- T7ErrorCorrectionType UINT8 ? ; < ECC type
- T7SystemCacheType UINT8 ? ; < Cache type
- T7Associativity UINT8 ? ; < Associativity
-TYPE7_DMI_INFO ENDS
-
- ; DMI Type 16 offset 04h - Location
-
- OtherLocation EQU 01h ; < Assign 01 to Other
- UnknownLocation EQU 2 ; < Assign 02 to Unknown
- SystemboardOrMotherboard EQU 3 ; < Assign 03 to systemboard or motherboard
- IsaAddonCard EQU 4 ; < Assign 04 to ISA add-on card
- EisaAddonCard EQU 5 ; < Assign 05 to EISA add-on card
- PciAddonCard EQU 6 ; < Assign 06 to PCI add-on card
- McaAddonCard EQU 7 ; < Assign 07 to MCA add-on card
- PcmciaAddonCard EQU 8 ; < Assign 08 to PCMCIA add-on card
- ProprietaryAddonCard EQU 9 ; < Assign 09 to proprietary add-on card
- NuBus EQU 10 ; < Assign 0A to NuBus
- Pc98C20AddonCard EQU 11 ; < Assign 0A0 to PC-98/C20 add-on card
- Pc98C24AddonCard EQU 12 ; < Assign 0A1 to PC-98/C24 add-on card
- Pc98EAddoncard EQU 13 ; < Assign 0A2 to PC-98/E add-on card
- Pc98LocalBusAddonCard EQU 14 ; < Assign 0A3 to PC-98/Local bus add-on card
-DMI_T16_LOCATION TEXTEQU <DWORD> ;} DMI_T16_LOCATION;
-
- ; DMI Type 16 offset 05h - Memory Error Correction
-
- OtherUse EQU 01h ; < Assign 01 to Other
- UnknownUse EQU 2 ; < Assign 02 to Unknown
- SystemMemory EQU 3 ; < Assign 03 to system memory
- VideoMemory EQU 4 ; < Assign 04 to video memory
- FlashMemory EQU 5 ; < Assign 05 to flash memory
- NonvolatileRam EQU 6 ; < Assign 06 to non-volatile RAM
- CacheMemory EQU 7 ; < Assign 07 to cache memory
-DMI_T16_USE TEXTEQU <DWORD> ;} DMI_T16_USE;
-
- ; DMI Type 16 offset 07h - Maximum Capacity
-
- Dmi16OtherErrCorrection EQU 01h ; < Assign 01 to Other
- Dmi16UnknownErrCorrection EQU 2 ; < Assign 02 to Unknown
- Dmi16NoneErrCorrection EQU 3 ; < Assign 03 to None
- Dmi16Parity EQU 4 ; < Assign 04 to parity
- Dmi16SingleBitEcc EQU 5 ; < Assign 05 to Single-bit ECC
- Dmi16MultiBitEcc EQU 6 ; < Assign 06 to Multi-bit ECC
- Dmi16Crc EQU 7 ; < Assign 07 to CRC
-DMI_T16_ERROR_CORRECTION TEXTEQU <DWORD> ;} DMI_T16_ERROR_CORRECTION;
-
- ; DMI Type 16 - Physical Memory Array
-TYPE16_DMI_INFO STRUCT
- Location DMI_T16_LOCATION ? ; < The physical location of the Memory Array,
- ; < whether on the system board or an add-in board.
- Use DMI_T16_USE ? ; < Identifies the function for which the array
- ; < is used.
- MemoryErrorCorrection DMI_T16_ERROR_CORRECTION ? ; < The primary hardware error correction or
- ; < detection method supported by this memory array.
- MaximumCapacity UINT32 ? ; < The maximum memory capacity, in kilobytes,
- ; < for the array.
- NumberOfMemoryDevices UINT16 ? ; < The number of slots or sockets available
- ; < for memory devices in this array.
- ExtMaxCapacity UINT64 ? ; < The maximum memory capacity, in bytes,
- ; < for this array.
-TYPE16_DMI_INFO ENDS
-
- ; DMI Type 17 offset 0Eh - Form Factor
- OtherFormFactor EQU 01h ; < Assign 01 to Other
- UnknowFormFactor EQU 2 ; < Assign 02 to Unknown
- SimmFormFactor EQU 3 ; < Assign 03 to SIMM
- SipFormFactor EQU 4 ; < Assign 04 to SIP
- ChipFormFactor EQU 5 ; < Assign 05 to Chip
- DipFormFactor EQU 6 ; < Assign 06 to DIP
- ZipFormFactor EQU 7 ; < Assign 07 to ZIP
- ProprietaryCardFormFactor EQU 8 ; < Assign 08 to Proprietary Card
- DimmFormFactorFormFactor EQU 9 ; < Assign 09 to DIMM
- TsopFormFactor EQU 10 ; < Assign 10 to TSOP
- RowOfChipsFormFactor EQU 11 ; < Assign 11 to Row of chips
- RimmFormFactor EQU 12 ; < Assign 12 to RIMM
- SodimmFormFactor EQU 13 ; < Assign 13 to SODIMM
- SrimmFormFactor EQU 14 ; < Assign 14 to SRIMM
- FbDimmFormFactor EQU 15 ; < Assign 15 to FB-DIMM
-DMI_T17_FORM_FACTOR TEXTEQU <DWORD>
-
- ; DMI Type 17 offset 12h - Memory Type
- OtherMemType EQU 01h ; < Assign 01 to Other
- UnknownMemType EQU 2 ; < Assign 02 to Unknown
- DramMemType EQU 3 ; < Assign 03 to DRAM
- EdramMemType EQU 4 ; < Assign 04 to EDRAM
- VramMemType EQU 5 ; < Assign 05 to VRAM
- SramMemType EQU 6 ; < Assign 06 to SRAM
- RamMemType EQU 7 ; < Assign 07 to RAM
- RomMemType EQU 8 ; < Assign 08 to ROM
- FlashMemType EQU 9 ; < Assign 09 to Flash
- EepromMemType EQU 10 ; < Assign 10 to EEPROM
- FepromMemType EQU 11 ; < Assign 11 to FEPROM
- EpromMemType EQU 12 ; < Assign 12 to EPROM
- CdramMemType EQU 13 ; < Assign 13 to CDRAM
- ThreeDramMemType EQU 14 ; < Assign 14 to 3DRAM
- SdramMemType EQU 15 ; < Assign 15 to SDRAM
- SgramMemType EQU 16 ; < Assign 16 to SGRAM
- RdramMemType EQU 17 ; < Assign 17 to RDRAM
- DdrMemType EQU 18 ; < Assign 18 to DDR
- Ddr2MemType EQU 19 ; < Assign 19 to DDR2
- Ddr2FbdimmMemType EQU 20 ; < Assign 20 to DDR2 FB-DIMM
- Ddr3MemType EQU 24 ; < Assign 24 to DDR3
- Fbd2MemType EQU 25 ; < Assign 25 to FBD2
-DMI_T17_MEMORY_TYPE TEXTEQU <DWORD>
-
- ; DMI Type 17 offset 13h - Type Detail
-DMI_T17_TYPE_DETAIL STRUCT
- Reserved1 UINT16 ?
-; OUT UINT16 Reserved1:1; ; < Reserved
-; OUT UINT16 Other:1; ; < Other
-; OUT UINT16 Unknown:1; ; < Unknown
-; OUT UINT16 FastPaged:1; ; < Fast-Paged
-; OUT UINT16 StaticColumn:1; ; < Static column
-; OUT UINT16 PseudoStatic:1; ; < Pseudo-static
-; OUT UINT16 Rambus:1; ; < RAMBUS
-; OUT UINT16 Synchronous:1; ; < Synchronous
-; OUT UINT16 Cmos:1; ; < CMOS
-; OUT UINT16 Edo:1; ; < EDO
-; OUT UINT16 WindowDram:1; ; < Window DRAM
-; OUT UINT16 CacheDram:1; ; < Cache Dram
-; OUT UINT16 NonVolatile:1; ; < Non-volatile
-; OUT UINT16 Reserved2:3; ; < Reserved
-DMI_T17_TYPE_DETAIL ENDS
-
- ; DMI Type 17 - Memory Device
-TYPE17_DMI_INFO STRUCT
- TotalWidth UINT16 ? ; < Total Width, in bits, of this memory device, including any check or error-correction bits.
- DataWidth UINT16 ? ; < Data Width, in bits, of this memory device.
- MemorySize UINT16 ? ; < The size of the memory device.
- FormFactor DMI_T17_FORM_FACTOR ? ; < The implementation form factor for this memory device.
- DeviceSet UINT8 ? ; < Identifies when the Memory Device is one of a set of
- ; < Memory Devices that must be populated with all devices of
- ; < the same type and size, and the set to which this device belongs.
- DeviceLocator CHAR8 (8) DUP (?) ; < The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
- BankLocator CHAR8 (10) DUP (?) ; < The string number of the string that identifies the physically labeled bank where the memory device is located.
- MemoryType DMI_T17_MEMORY_TYPE ? ; < The type of memory used in this device.
- TypeDetail DMI_T17_TYPE_DETAIL {} ; < Additional detail on the memory device type
- Speed UINT16 ? ; < Identifies the speed of the device, in megahertz (MHz).
- ManufacturerIdCode UINT64 ? ; < Manufacturer ID code.
- SerialNumber CHAR8 (9) DUP (?) ; < Serial Number.
- PartNumber CHAR8 (19) DUP (?) ; < Part Number.
- Attributes UINT8 ? ; < Bits 7-4: Reserved, Bits 3-0: rank.
- ExtSize UINT32 ? ; < Extended Size.
- ConfigSpeed UINT16 ? ; < Configured memory clock speed
-TYPE17_DMI_INFO ENDS
-
- ; Memory DMI Type 17 and 20 - for memory use
-MEM_DMI_INFO STRUCT
- TotalWidth UINT16 ? ; < Total Width, in bits, of this memory device, including any check or error-correction bits.
- DataWidth UINT16 ? ; < Data Width, in bits, of this memory device.
- MemorySize UINT16 ? ; < The size of the memory device.
- FormFactor DMI_T17_FORM_FACTOR ? ; < The implementation form factor for this memory device.
- DeviceLocator UINT8 ? ; < The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
- BankLocator UINT8 ? ; < The string number of the string that identifies the physically labeled bank where the memory device is located.
- Speed UINT16 ? ; < Identifies the speed of the device, in megahertz (MHz).
- ManufacturerIdCode UINT64 ? ; < Manufacturer ID code.
- SerialNumber UINT8 (4) DUP (?) ; < Serial Number.
- PartNumber UINT8 (18) DUP (?) ; < Part Number.
- Attributes UINT8 ? ; < Bits 7-4: Reserved, Bits 3-0: rank.
- ExtSize UINT32 ? ; < Extended Size.
- Socket UINT8 ?
-; OUT UINT8 Socket:3 ; < Socket ID
-; OUT UINT8 Channel:2 ; < Channel ID
-; OUT UINT8 Dimm:2 ; < DIMM ID
-; OUT UINT8 DimmPresent:1 ; < Dimm Present
- StartingAddr UINT32 ? ; < The physical address, in kilobytes, of a range
- ; < of memory mapped to the referenced Memory Device.
- EndingAddr UINT32 ? ; < The handle, or instance number, associated with
- ; < the Memory Device structure to which this address
- ; < range is mapped.
- ConfigSpeed UINT16 ? ; < Configured memory clock speed
- ExtStartingAddr UINT64 ? ; < The physical address, in bytes, of a range of
- ; < memory mapped to the referenced Memory Device.
- ExtEndingAddr UINT64 ? ; < The physical ending address, in bytes, of the last of
- ; < a range of addresses mapped to the referenced Memory Device.
-MEM_DMI_INFO ENDS
-
- ; DMI Type 19 - Memory Array Mapped Address
-TYPE19_DMI_INFO STRUCT
- StartingAddr UINT32 ? ; < The physical address, in kilobytes,
- ; < of a range of memory mapped to the
- ; < specified physical memory array.
- EndingAddr UINT32 ? ; < The physical ending address of the
- ; < last kilobyte of a range of addresses
- ; < mapped to the specified physical memory array.
- MemoryArrayHandle UINT16 ? ; < The handle, or instance number, associated
- ; < with the physical memory array to which this
- ; < address range is mapped.
- PartitionWidth UINT8 ? ; < Identifies the number of memory devices that
- ; < form a single row of memory for the address
- ; < partition defined by this structure.
- ExtStartingAddr UINT64 ? ; < The physical address, in bytes, of a range of
- ; < memory mapped to the specified Physical Memory Array.
- ExtEndingAddr UINT64 ? ; < The physical address, in bytes, of a range of
- ; < memory mapped to the specified Physical Memory Array.
-TYPE19_DMI_INFO ENDS
-
-; DMI Type 20 - Memory Device Mapped Address
-TYPE20_DMI_INFO STRUCT
- StartingAddr UINT32 ? ; < The physical address, in kilobytes, of a range
- ; < of memory mapped to the referenced Memory Device.
- EndingAddr UINT32 ? ; < The handle, or instance number, associated with
- ; < the Memory Device structure to which this address
- ; < range is mapped.
- MemoryDeviceHandle UINT16 ? ; < The handle, or instance number, associated with
- ; < the Memory Device structure to which this address
- ; < range is mapped.
- MemoryArrayMappedAddressHandle UINT16 ? ; < The handle, or instance number, associated
- ; < with the Memory Array Mapped Address structure to
- ; < which this device address range is mapped.
- PartitionRowPosition UINT8 ? ; < Identifies the position of the referenced Memory
- ; < Device in a row of the address partition.
- InterleavePosition UINT8 ? ; < The position of the referenced Memory Device in
- ; < an interleave.
- InterleavedDataDepth UINT8 ? ; < The maximum number of consecutive rows from the
- ; < referenced Memory Device that are accessed in a
- ; < single interleaved transfer.
- ExtStartingAddr UINT64 ? ; < The physical address, in bytes, of a range of
- ; < memory mapped to the referenced Memory Device.
- ExtEndingAddr UINT64 ? ; < The physical ending address, in bytes, of the last of
- ; < a range of addresses mapped to the referenced Memory Device.
-TYPE20_DMI_INFO ENDS
-
- ; Collection of pointers to the DMI records
-DMI_INFO STRUCT
- T4 TYPE4_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 4 struc
- T7L1 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 1
- T7L2 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 2
- T7L3 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 3
- T16 TYPE16_DMI_INFO {} ; < Type 16 struc
- T17 TYPE17_DMI_INFO (MAX_SOCKETS_SUPPORTED * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL) DUP ({}) ; < Type 17 struc
- T19 TYPE19_DMI_INFO {} ; < Type 19 struc
- T20 TYPE20_DMI_INFO (MAX_SOCKETS_SUPPORTED * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL) DUP ({}) ; < Type 20 struc
-DMI_INFO ENDS
-
-
-
-; *********************************************************************
-; * Interface call: AllocateExecutionCache
-; *********************************************************************
- MAX_CACHE_REGIONS EQU 3
-
- ; AllocateExecutionCache sub param structure for cached memory region
-EXECUTION_CACHE_REGION STRUCT
- ExeCacheStartAddr UINT32 ? ; < Start address
- ExeCacheSize UINT32 ? ; < Size
-EXECUTION_CACHE_REGION ENDS
-
-; *********************************************************************
-; * Interface call: AmdGetAvailableExeCacheSize
-; *********************************************************************
- ; Get available Cache remain
-AMD_GET_EXE_SIZE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- AvailableExeCacheSize UINT32 ? ; < Remain size
-AMD_GET_EXE_SIZE_PARAMS ENDS
-
-
-
-
-
-
- ; Selection type for core leveling
- CORE_LEVEL_LOWEST EQU 0 ; < Level to lowest common denominator
- CORE_LEVEL_TWO EQU 1 ; < Level to 2 cores
- CORE_LEVEL_POWER_OF_TWO EQU 2 ; < Level to 1,2,4 or 8
- CORE_LEVEL_NONE EQU 3 ; < Do no leveling
- CORE_LEVEL_COMPUTE_UNIT EQU 4 ; < Level cores to one core per compute unit
- CORE_LEVEL_ONE EQU 5 ; < Level to 1 core
- CORE_LEVEL_THREE EQU 6 ; < Level to 3 cores
- CORE_LEVEL_FOUR EQU 7 ; < Level to 4 cores
- CORE_LEVEL_FIVE EQU 8 ; < Level to 5 cores
- CORE_LEVEL_SIX EQU 9 ; < Level to 6 cores
- CORE_LEVEL_SEVEN EQU 10 ; < Level to 7 cores
- CORE_LEVEL_EIGHT EQU 11 ; < Level to 8 cores
- CORE_LEVEL_NINE EQU 12 ; < Level to 9 cores
- CORE_LEVEL_TEN EQU 13 ; < Level to 10 cores
- CORE_LEVEL_ELEVEN EQU 14 ; < Level to 11 cores
- CORE_LEVEL_TWELVE EQU 15 ; < Level to 12 cores
- CORE_LEVEL_THIRTEEN EQU 16 ; < Level to 13 cores
- CORE_LEVEL_FOURTEEN EQU 17 ; < Level to 14 cores
- CORE_LEVEL_FIFTEEN EQU 18 ; < Level to 15 cores
- CoreLevelModeMax EQU 19 ; < Used for bounds checking
-CORE_LEVELING_TYPE TEXTEQU <DWORD>
-
-
-; ***********************************************************************
-; *
-; * AGESA Basic Level interface structure definition and function prototypes
-; *
-; **********************************************************************
-
-; *********************************************************************
-; * Interface call: AmdCreateStruct
-; *********************************************************************
-
-; *********************************************************************
-; * Interface call: AmdReleaseStruct
-; *********************************************************************
-
-; *********************************************************************
-; * Interface call: AmdInitReset
-; *********************************************************************
- ; AmdInitReset param structure
-AMD_RESET_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < The cached memory region
- HtConfig AMD_HT_RESET_INTERFACE {} ; < The interface for Ht Recovery
- FchInterface FCH_RESET_INTERFACE {} ; Interface for FCH configuration
-AMD_RESET_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitEarly
-; *********************************************************************
- ; InitEarly param structure
-
- ; Provide defaults or customizations to each service performed in AmdInitEarly.
-
-AMD_EARLY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < The standard header
- CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < Execution Map Interface
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- HtConfig AMD_HT_INTERFACE {} ; < HyperTransport Interface
- GnbConfig GNB_CONFIGURATION {} ; < GNB configuration
-AMD_EARLY_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitPost
-; *********************************************************************
- ; AmdInitPost param structure
-AMD_POST_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- MemConfig MEM_PARAMETER_STRUCT {} ; < Memory post param
-AMD_POST_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitEnv
-; *********************************************************************
- ; AmdInitEnv param structure
-AMD_ENV_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- GnbEnvConfiguration GNB_ENV_CONFIGURATION {} ; < platform operational characteristics.
- FchInterface FCH_INTERFACE {} ; FCH configuration
-AMD_ENV_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitMid
-; *********************************************************************
- ; AmdInitMid param structure
-AMD_MID_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- FchInterface FCH_INTERFACE {} ; FCH configuration
-AMD_MID_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitLate
-; *********************************************************************
- ; AmdInitLate param structure
-AMD_LATE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- IvrsExclusionRangeList POINTER ? ; < IVMD exclusion range descriptor
- DmiTable POINTER ? ; < DMI Interface
- AcpiPState POINTER ? ; < Acpi Pstate SSDT Table
- AcpiSrat POINTER ? ; < SRAT Table
- AcpiSlit POINTER ? ; < SLIT Table
- AcpiWheaMce POINTER ? ; < WHEA MCE Table
- AcpiWheaCmc POINTER ? ; < WHEA CMC Table
- AcpiAlib POINTER ? ; < ALIB Table
- AcpiIvrs POINTER ? ; < IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table
-AMD_LATE_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitRecovery
-; *********************************************************************
- ; CPU Recovery Parameters
-AMD_CPU_RECOVERY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard Header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics
-AMD_CPU_RECOVERY_PARAMS ENDS
-
- ; AmdInitRecovery param structure
-AMD_RECOVERY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- MemConfig MEM_PARAMETER_STRUCT {} ; < Memory post param
- CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < The cached memory region. And the max cache region is 3
- CpuRecoveryParams AMD_CPU_RECOVERY_PARAMS {} ; < Params for CPU related recovery init.
-AMD_RECOVERY_PARAMS ENDS
-
-
-; *********************************************************************
-; * Interface call: AmdInitResume
-; *********************************************************************
- ; AmdInitResume param structure
-AMD_RESUME_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < Platform operational characteristics
- S3DataBlock AMD_S3_PARAMS {} ; < Save state data
-AMD_RESUME_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdS3LateRestore
-; *********************************************************************
- ; AmdS3LateRestore param structure
-AMD_S3LATE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- S3DataBlock AMD_S3_PARAMS {} ; < Save state data
-AMD_S3LATE_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdS3Save
-; *********************************************************************
- ; AmdS3Save param structure
-AMD_S3SAVE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- S3DataBlock AMD_S3_PARAMS {} ; < Standard header
- FchInterface FCH_INTERFACE {} ; FCH configuration
-AMD_S3SAVE_PARAMS ENDS
-
- ; General Services API
-
-
-; *********************************************************************
-; * Interface service call: AmdGetApicId
-; *********************************************************************
- ; Request the APIC ID of a particular core.
-
-AMD_APIC_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- Socket UINT8 ? ; < The Core's Socket.
- Core UINT8 ? ; < The Core id.
- IsPresent BOOLEAN ? ; < The Core is present, and ApicAddress is valid.
- ApicAddress UINT8 ? ; < The Core's APIC ID.
-AMD_APIC_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdGetPciAddress
-; *********************************************************************
- ; Request the PCI Address of a Processor Module (that is, its Northbridge)
-
-AMD_GET_PCI_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- Socket UINT8 ? ; < The Processor's socket
- Module UINT8 ? ; < The Module in that Processor
- IsPresent BOOLEAN ? ; < The Core is present, and PciAddress is valid.
- PciAddress PCI_ADDR {} ; < The Processor's PCI Config Space address (Function 0, Register 0)
-AMD_GET_PCI_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdIdentifyCore
-; *********************************************************************
- ; Request the identity (Socket, Module, Core) of the current Processor Core
-
-AMD_IDENTIFY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- Socket UINT8 ? ; < The current Core's Socket
- Module UINT8 ? ; < The current Core's Processor Module
- Core UINT8 ? ; < The current Core's core id.
-AMD_IDENTIFY_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdReadEventLog
-; *********************************************************************
- ; An Event Log Entry.
-EVENT_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- EventClass UINT32 ? ; < The severity of this event, matches AGESA_STATUS.
- EventInfo UINT32 ? ; < The unique event identifier, zero means "no event".
- DataParam1 UINT32 ? ; < Data specific to the Event.
- DataParam2 UINT32 ? ; < Data specific to the Event.
- DataParam3 UINT32 ? ; < Data specific to the Event.
- DataParam4 UINT32 ? ; < Data specific to the Event.
-EVENT_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdIdentifyDimm
-; *********************************************************************
- ; Request the identity of dimm from system address
-
-AMD_IDENTIFY_DIMM STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- MemoryAddress UINT64 ? ; < System Address that needs to be translated to dimm identification.
- SocketId UINT8 ? ; < The socket on which the targeted address locates.
- MemChannelId UINT8 ? ; < The channel on which the targeted address locates.
- DimmId UINT8 ? ; < The dimm on which the targeted address locates.
-AMD_IDENTIFY_DIMM ENDS
-
- ; Data structure for the Mapping Item between Unified ID for IDS Setup Option
- ; and the option value.
-
-IDS_NV_ITEM STRUCT
- IdsNvId UINT16 ? ; < Unified ID for IDS Setup Option.
- IdsNvValue UINT16 ? ; < The value of IDS Setup Option.
-IDS_NV_ITEM ENDS
-
- ; Data Structure for IDS CallOut Function
-IDS_CALLOUT_STRUCT STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < The Standard Header for AGESA Service
- IdsNvPtr POINTER ? ; < Memory Pointer of IDS NV Table
- Reserved UINT32 ? ; < reserved
-IDS_CALLOUT_STRUCT ENDS
-
- AGESA_IDS_DFT_VAL EQU 0FFFFh; < Default value of every uninitlized NV item, the action for it will be ignored
- AGESA_IDS_NV_END EQU 0FFFFh; < Flag specify end of option structure
-; WARNING: Don't change the comment below, it used as signature for script
-; AGESA IDS NV ID Definitions
- AGESA_IDS_EXT_ID_START EQU 0000h; < specify the start of external NV id
-
- AGESA_IDS_NV_UCODE EQU 0001h; < Enable or disable microcode patching
-
- AGESA_IDS_NV_TARGET_PSTATE EQU 0002h; < Set the P-state required to be activated
- AGESA_IDS_NV_POSTPSTATE EQU 0003h; < Set the P-state required to be activated through POST
-
- AGESA_IDS_NV_BANK_INTERLEAVE EQU 0004h; < Enable or disable Bank Interleave
- AGESA_IDS_NV_CHANNEL_INTERLEAVE EQU 0005h; < Enable or disable Channel Interleave
- AGESA_IDS_NV_NODE_INTERLEAVE EQU 0006h; < Enable or disable Node Interleave
- AGESA_IDS_NV_MEMHOLE EQU 0007h; < Enables or disable memory hole
-
- AGESA_IDS_NV_SCRUB_REDIRECTION EQU 0008h; < Enable or disable a write to dram with corrected data
- AGESA_IDS_NV_DRAM_SCRUB EQU 0009h; < Set the rate of background scrubbing for DRAM
- AGESA_IDS_NV_DCACHE_SCRUB EQU 000Ah; < Set the rate of background scrubbing for the DCache.
- AGESA_IDS_NV_L2_SCRUB EQU 000Bh; < Set the rate of background scrubbing for the L2 cache
- AGESA_IDS_NV_L3_SCRUB EQU 000Ch; < Set the rate of background scrubbing for the L3 cache
- AGESA_IDS_NV_ICACHE_SCRUB EQU 000Dh; < Set the rate of background scrubbing for the Icache
- AGESA_IDS_NV_SYNC_ON_ECC_ERROR EQU 000Eh; < Enable or disable the sync flood on un-correctable ECC error
- AGESA_IDS_NV_ECC_SYMBOL_SIZE EQU 000Fh; < Set ECC symbol size
-
- AGESA_IDS_NV_ALL_MEMCLKS EQU 0010h; < Enable or disable all memory clocks enable
- AGESA_IDS_NV_DCT_GANGING_MODE EQU 0011h; < Set the Ganged mode
- AGESA_IDS_NV_DRAM_BURST_LENGTH32 EQU 0012h; < Set the DRAM Burst Length 32
- AGESA_IDS_NV_MEMORY_POWER_DOWN EQU 0013h; < Enable or disable Memory power down mode
- AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE EQU 0014h; < Set the Memory power down mode
- AGESA_IDS_NV_DLL_SHUT_DOWN EQU 0015h; < Enable or disable DLLShutdown
- AGESA_IDS_NV_ONLINE_SPARE EQU 0016h; < Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap
-
- AGESA_IDS_NV_HT_ASSIST EQU 0017h; < Enable or Disable HT Assist
- AGESA_IDS_NV_ATMMODE EQU 0018h; < Enable or Disable ATM mode
-
- AGESA_IDS_NV_HDTOUT EQU 0019h; < Enable or disable HDTOUT feature
-
- AGESA_IDS_NV_HTLINKSOCKET EQU 001Ah; < HT Link Socket
- AGESA_IDS_NV_HTLINKPORT EQU 001Bh; < HT Link Port
- AGESA_IDS_NV_HTLINKFREQ EQU 001Ch; < HT Link Frequency
- AGESA_IDS_NV_HTLINKWIDTHIN EQU 001Dh; < HT Link In Width
- AGESA_IDS_NV_HTLINKWIDTHOUT EQU 001Eh; < HT Link Out Width
-
- AGESA_IDS_NV_GNBHDAUDIOEN EQU 001Fh; < Enable or disable GNB HD Audio
-
- AGESA_IDS_NV_CPB_EN EQU 0020h; < Core Performance Boost
-
- AGESA_IDS_NV_HTC_EN EQU 0021h; < HTC Enable
- AGESA_IDS_NV_HTC_OVERRIDE EQU 0022h; < HTC Override
- AGESA_IDS_NV_HTC_PSTATE_LIMIT EQU 0023h; < HTC P-state limit select
- AGESA_IDS_NV_HTC_TEMP_HYS EQU 0024h; < HTC Temperature Hysteresis
- AGESA_IDS_NV_HTC_ACT_TEMP EQU 0025h; < HTC Activation Temp
-
- AGESA_IDS_NV_POWER_POLICY EQU 0026h; < Select Platform Power Policy
- AGESA_IDS_EXT_ID_END EQU 0027h; < specify the end of external NV ID
-
- IDS_EX_NV_ID TEXTEQU <DWORD>
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/amd.inc b/src/vendorcode/amd/agesa/f15/Legacy/amd.inc
deleted file mode 100644
index d89c942ebf..0000000000
--- a/src/vendorcode/amd/agesa/f15/Legacy/amd.inc
+++ /dev/null
@@ -1,460 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * Agesa structures and definitions
-; *
-; * Contains AMD AGESA core interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-;
-; ****************************************************************************
-; *
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; *
-; **************************************************************************
-
-
-UINT64 TEXTEQU <QWORD>
-UINT32 TEXTEQU <DWORD>
-UINT16 TEXTEQU <WORD>
-UINT8 TEXTEQU <BYTE>
-CHAR8 TEXTEQU <BYTE>
-BOOLEAN TEXTEQU <BYTE>
-POINTER TEXTEQU <DWORD>
-
- ; AGESA Types and Definitions
-
- AGESA_REVISION EQU "Arch2008"
- AGESA_ID EQU "AGESA"
-
- LAST_ENTRY EQU 0FFFFFFFFh
- IMAGE_SIGNATURE EQU 'DMA$'
- IOCF8 EQU 0CF8h
- IOCFC EQU 0CFCh
-
- ; The return status for all AGESA public services.
-
- ; Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
- ; will have log entries with more detail.
-
- AGESA_SUCCESS EQU 0 ; < The service completed normally. Info may be logged.
- AGESA_UNSUPPORTED EQU 1 ; < The dispatcher or create struct had an unimplemented function requested.
- ; < Not logged.
- AGESA_BOUNDS_CHK EQU 2 ; < A dynamic parameter was out of range and the service was not provided.
- ; < Example, memory address not installed, heap buffer handle not found.
- ; < Not Logged.
- ; AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
- AGESA_ALERT EQU 3 ; < An observed condition, but no loss of function.
- ; < See log. Example, HT CRC.
- AGESA_WARNING EQU 4 ; < Possible or minor loss of function. See Log.
- AGESA_ERROR EQU 5 ; < Significant loss of function, boot may be possible. See Log.
- AGESA_CRITICAL EQU 6 ; < Continue boot only to notify user. See Log.
- AGESA_FATAL EQU 7 ; < Halt booting. See Log.
- AgesaStatusMax EQU 8 ; < Not a status, use for limit checking.
-AGESA_STATUS TEXTEQU <DWORD>
-
-; For checking whether a status is at or above the mandatory log level.
-AGESA_STATUS_LOG_LEVEL EQU AGESA_ALERT
-
- CALLOUT_ENTRY TEXTEQU <POINTER>
- IMAGE_ENTRY TEXTEQU <POINTER>
- MODULE_ENTRY TEXTEQU <POINTER>
-
-; This allocation type is used by the AmdCreateStruct entry point
- PreMemHeap EQU 0 ; < Create heap in cache.
- PostMemDram EQU 1 ; < Create heap in memory.
- ByHost EQU 2 ; < Create heap by Host.
-ALLOCATION_METHOD TEXTEQU <DWORD>
-
- ; These width descriptors are used by the library function, and others, to specify the data size
- AccessWidth8 EQU 1 ; < Access width is 8 bits.
- AccessWidth16 EQU 2 ; < Access width is 16 bits.
- AccessWidth32 EQU 3 ; < Access width is 32 bits.
- AccessWidth64 EQU 4 ; < Access width is 64 bits.
-
- AccessS3SaveWidth8 EQU 81h ; < Save 8 bits data.
- AccessS3SaveWidth16 EQU 130 ; < Save 16 bits data.
- AccessS3SaveWidth32 EQU 131 ; < Save 32 bits data.
- AccessS3SaveWidth64 EQU 132 ; < Save 64 bits data.
-ACCESS_WIDTH TEXTEQU <DWORD>
-
- ; AGESA struct name
-
- ; AGESA BASIC FUNCTIONS
- AMD_INIT_RECOVERY EQU 00020000h
- AMD_CREATE_STRUCT EQU 00020001h
- AMD_INIT_EARLY EQU 00020002h
- AMD_INIT_ENV EQU 00020003h
- AMD_INIT_LATE EQU 00020004h
- AMD_INIT_MID EQU 00020005h
- AMD_INIT_POST EQU 00020006h
- AMD_INIT_RESET EQU 00020007h
- AMD_INIT_RESUME EQU 00020008h
- AMD_RELEASE_STRUCT EQU 00020009h
- AMD_S3LATE_RESTORE EQU 0002000Ah
- AMD_S3_SAVE EQU 0002000Bh
- AMD_GET_APIC_ID EQU 0002000Ch
- AMD_GET_PCI_ADDRESS EQU 0002000Dh
- AMD_IDENTIFY_CORE EQU 0002000Eh
- AMD_READ_EVENT_LOG EQU 0002000Fh
- AMD_GET_EXECACHE_SIZE EQU 00020010h
- AMD_LATE_RUN_AP_TASK EQU 00020011h
- AMD_IDENTIFY_DIMMS EQU 00020012h
-AGESA_STRUCT_NAME TEXTEQU <DWORD>
-
-
- ; ResetType constant values
- WARM_RESET_WHENEVER EQU 1
- COLD_RESET_WHENEVER EQU 2
- WARM_RESET_IMMEDIATELY EQU 3
- COLD_RESET_IMMEDIATELY EQU 4
-
-
- ; AGESA Structures
-
- ; The standard header for all AGESA services.
-AMD_CONFIG_PARAMS STRUCT
- ImageBasePtr UINT32 ? ; < The AGESA Image base address.
- Func UINT32 ? ; < The service desired, @sa dispatch.h.
- AltImageBasePtr UINT32 ? ; < Alternate Image location
- CalloutPtr CALLOUT_ENTRY ? ; < For Callout from AGESA
- HeapStatus UINT8 ? ; < For heap status from boot time slide.
- HeapBasePtr UINT64 ? ; < Location of the heap
- Reserved UINT8 (7) DUP (?) ; < This space is reserved for future use.
-AMD_CONFIG_PARAMS ENDS
-
-
- ; Create Struct Interface.
-AMD_INTERFACE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Config header
- AgesaFunctionName AGESA_STRUCT_NAME ? ; < The service to init, @sa dispatch.h
- AllocationMethod ALLOCATION_METHOD ? ; < How to handle buffer allocation
- NewStructSize UINT32 ? ; < The size of the allocated data, in for ByHost, else out only.
- NewStructPtr POINTER ? ; < The struct for the service.
- ; < The struct to init for ByHost allocation,
- ; < the initialized struct on return.
-AMD_INTERFACE_PARAMS ENDS
-
- FUNC_0 EQU 0 ; bit-placed for PCI address creation
- FUNC_1 EQU 1
- FUNC_2 EQU 2
- FUNC_3 EQU 3
- FUNC_4 EQU 4
- FUNC_5 EQU 5
- FUNC_6 EQU 6
- FUNC_7 EQU 7
-
- ; AGESA Binary module header structure
-AMD_IMAGE_HEADER STRUCT
- Signature UINT32 ? ; < Binary Signature
- CreatorID CHAR8 (8) DUP (?) ; < 8 characters ID
- Version CHAR8 (12) DUP (?) ; < 12 characters version
- ModuleInfoOffset UINT32 ? ; < Offset of module
- EntryPointAddress UINT32 ? ; < Entry address
- ImageBase UINT32 ? ; < Image base
- RelocTableOffset UINT32 ? ; < Relocate Table offset
- ImageSize UINT32 ? ; < Size
- Checksum UINT16 ? ; < Checksum
- ImageType UINT8 ? ; < Type
- V_Reserved UINT8 ? ; < Reserved
-AMD_IMAGE_HEADER ENDS
- ; AGESA Binary module header structure
-AMD_MODULE_HEADER STRUCT
- ModuleHeaderSignature UINT32 ? ; < Module signature
- ModuleIdentifier CHAR8 (8) DUP (?) ; < 8 characters ID
- ModuleVersion CHAR8 (12) DUP (?) ; < 12 characters version
- ModuleDispatcher POINTER ? ; < A pointer point to dispatcher
- NextBlock POINTER ? ; < Next module header link
-AMD_MODULE_HEADER ENDS
-
-; AMD_CODE_HEADER Signatures.
-AGESA_CODE_SIGNATURE TEXTEQU <'!', '!', 'A', 'G', 'E', 'S', 'A', ' '>
-CIMXNB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'>
-CIMXSB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'>
-
-; AGESA_CODE_SIGNATURE
-AMD_CODE_HEADER STRUCT
- Signature CHAR8 (8) DUP (?) ; < code header Signature
- ComponentName CHAR8 (8) DUP (?) ; < 8 character name of the code module
- Version CHAR8 (12) DUP (?) ; < 12 character version string
- TerminatorNull CHAR8 ? ; < null terminated string
- VerReserved CHAR8 (7) DUP (?) ; < reserved space
-AMD_CODE_HEADER ENDS
-
- ; Extended PCI address format
-EXT_PCI_ADDR STRUCT
- Register UINT32 ?
-; IN OUT UINT32 Register:12; ; < Register offset
-; IN OUT UINT32 Function:3; ; < Function number
-; IN OUT UINT32 Device:5; ; < Device number
-; IN OUT UINT32 Bus:8; ; < Bus number
-; IN OUT UINT32 Segment:4; ; < Segment
-EXT_PCI_ADDR ENDS
-
- ; Union type for PCI address
-PCI_ADDR UNION
- AddressValue UINT32 ? ; < Formal address
- Address EXT_PCI_ADDR {} ; < Extended address
-PCI_ADDR ENDS
-
- ; SBDFO - Segment Bus Device Function Offset
- ; 31:28 Segment (4-bits)
- ; 27:20 Bus (8-bits)
- ; 19:15 Device (5-bits)
- ; 14:12 Function(3-bits)
- ; 11:00 Offset (12-bits)
-
-
-
- ILLEGAL_SBDFO EQU 0FFFFFFFFh
-
- ; CPUID data received registers format
-CPUID_DATA STRUCT
- EAX_Reg UINT32 ? ; < CPUID instruction result in EAX
- EBX_Reg UINT32 ? ; < CPUID instruction result in EBX
- ECX_Reg UINT32 ? ; < CPUID instruction result in ECX
- EDX_Reg UINT32 ? ; < CPUID instruction result in EDX
-CPUID_DATA ENDS
-
- ; HT frequency for external callbacks
-;typedef enum {
- HT_FREQUENCY_200M EQU 0 ; < HT speed 200 for external callbacks
- HT_FREQUENCY_400M EQU 2 ; < HT speed 400 for external callbacks
- HT_FREQUENCY_600M EQU 4 ; < HT speed 600 for external callbacks
- HT_FREQUENCY_800M EQU 5 ; < HT speed 800 for external callbacks
- HT_FREQUENCY_1000M EQU 6 ; < HT speed 1000 for external callbacks
- HT_FREQUENCY_1200M EQU 7 ; < HT speed 1200 for external callbacks
- HT_FREQUENCY_1400M EQU 8 ; < HT speed 1400 for external callbacks
- HT_FREQUENCY_1600M EQU 9 ; < HT speed 1600 for external callbacks
- HT_FREQUENCY_1800M EQU 10 ; < HT speed 1800 for external callbacks
- HT_FREQUENCY_2000M EQU 11 ; < HT speed 2000 for external callbacks
- HT_FREQUENCY_2200M EQU 12 ; < HT speed 2200 for external callbacks
- HT_FREQUENCY_2400M EQU 13 ; < HT speed 2400 for external callbacks
- HT_FREQUENCY_2600M EQU 14 ; < HT speed 2600 for external callbacks
- HT_FREQUENCY_2800M EQU 17 ; < HT speed 2800 for external callbacks
- HT_FREQUENCY_3000M EQU 18 ; < HT speed 3000 for external callbacks
- HT_FREQUENCY_3200M EQU 19 ; < HT speed 3200 for external callbacks
- HT_FREQUENCY_MAX EQU 20 ; < Limit Check.
-HT_FREQUENCIES TEXTEQU <DWORD> ;} HT_FREQUENCIES;
-
-HT3_FREQUENCY_MIN EQU HT_FREQUENCY_1200M
-
-IFNDEF BIT0
- BIT0 EQU 0000000000000001h
-ENDIF
-IFNDEF BIT1
- BIT1 EQU 0000000000000002h
-ENDIF
-IFNDEF BIT2
- BIT2 EQU 0000000000000004h
-ENDIF
-IFNDEF BIT3
- BIT3 EQU 0000000000000008h
-ENDIF
-IFNDEF BIT4
- BIT4 EQU 0000000000000010h
-ENDIF
-IFNDEF BIT5
- BIT5 EQU 0000000000000020h
-ENDIF
-IFNDEF BIT6
- BIT6 EQU 0000000000000040h
-ENDIF
-IFNDEF BIT7
- BIT7 EQU 0000000000000080h
-ENDIF
-IFNDEF BIT8
- BIT8 EQU 0000000000000100h
-ENDIF
-IFNDEF BIT9
- BIT9 EQU 0000000000000200h
-ENDIF
-IFNDEF BIT10
- BIT10 EQU 0000000000000400h
-ENDIF
-IFNDEF BIT11
- BIT11 EQU 0000000000000800h
-ENDIF
-IFNDEF BIT12
- BIT12 EQU 0000000000001000h
-ENDIF
-IFNDEF BIT13
- BIT13 EQU 0000000000002000h
-ENDIF
-IFNDEF BIT14
- BIT14 EQU 0000000000004000h
-ENDIF
-IFNDEF BIT15
- BIT15 EQU 0000000000008000h
-ENDIF
-IFNDEF BIT16
- BIT16 EQU 0000000000010000h
-ENDIF
-IFNDEF BIT17
- BIT17 EQU 0000000000020000h
-ENDIF
-IFNDEF BIT18
- BIT18 EQU 0000000000040000h
-ENDIF
-IFNDEF BIT19
- BIT19 EQU 0000000000080000h
-ENDIF
-IFNDEF BIT20
- BIT20 EQU 0000000000100000h
-ENDIF
-IFNDEF BIT21
- BIT21 EQU 0000000000200000h
-ENDIF
-IFNDEF BIT22
- BIT22 EQU 0000000000400000h
-ENDIF
-IFNDEF BIT23
- BIT23 EQU 0000000000800000h
-ENDIF
-IFNDEF BIT24
- BIT24 EQU 0000000001000000h
-ENDIF
-IFNDEF BIT25
- BIT25 EQU 0000000002000000h
-ENDIF
-IFNDEF BIT26
- BIT26 EQU 0000000004000000h
-ENDIF
-IFNDEF BIT27
- BIT27 EQU 0000000008000000h
-ENDIF
-IFNDEF BIT28
- BIT28 EQU 0000000010000000h
-ENDIF
-IFNDEF BIT29
- BIT29 EQU 0000000020000000h
-ENDIF
-IFNDEF BIT30
- BIT30 EQU 0000000040000000h
-ENDIF
-IFNDEF BIT31
- BIT31 EQU 0000000080000000h
-ENDIF
-IFNDEF BIT32
- BIT32 EQU 0000000100000000h
-ENDIF
-IFNDEF BIT33
- BIT33 EQU 0000000200000000h
-ENDIF
-IFNDEF BIT34
- BIT34 EQU 0000000400000000h
-ENDIF
-IFNDEF BIT35
- BIT35 EQU 0000000800000000h
-ENDIF
-IFNDEF BIT36
- BIT36 EQU 0000001000000000h
-ENDIF
-IFNDEF BIT37
- BIT37 EQU 0000002000000000h
-ENDIF
-IFNDEF BIT38
- BIT38 EQU 0000004000000000h
-ENDIF
-IFNDEF BIT39
- BIT39 EQU 0000008000000000h
-ENDIF
-IFNDEF BIT40
- BIT40 EQU 0000010000000000h
-ENDIF
-IFNDEF BIT41
- BIT41 EQU 0000020000000000h
-ENDIF
-IFNDEF BIT42
- BIT42 EQU 0000040000000000h
-ENDIF
-IFNDEF BIT43
- BIT43 EQU 0000080000000000h
-ENDIF
-IFNDEF BIT44
- BIT44 EQU 0000100000000000h
-ENDIF
-IFNDEF BIT45
- BIT45 EQU 0000200000000000h
-ENDIF
-IFNDEF BIT46
- BIT46 EQU 0000400000000000h
-ENDIF
-IFNDEF BIT47
- BIT47 EQU 0000800000000000h
-ENDIF
-IFNDEF BIT48
- BIT48 EQU 0001000000000000h
-ENDIF
-IFNDEF BIT49
- BIT49 EQU 0002000000000000h
-ENDIF
-IFNDEF BIT50
- BIT50 EQU 0004000000000000h
-ENDIF
-IFNDEF BIT51
- BIT51 EQU 0008000000000000h
-ENDIF
-IFNDEF BIT52
- BIT52 EQU 0010000000000000h
-ENDIF
-IFNDEF BIT53
- BIT53 EQU 0020000000000000h
-ENDIF
-IFNDEF BIT54
- BIT54 EQU 0040000000000000h
-ENDIF
-IFNDEF BIT55
- BIT55 EQU 0080000000000000h
-ENDIF
-IFNDEF BIT56
- BIT56 EQU 0100000000000000h
-ENDIF
-IFNDEF BIT57
- BIT57 EQU 0200000000000000h
-ENDIF
-IFNDEF BIT58
- BIT58 EQU 0400000000000000h
-ENDIF
-IFNDEF BIT59
- BIT59 EQU 0800000000000000h
-ENDIF
-IFNDEF BIT60
- BIT60 EQU 1000000000000000h
-ENDIF
-IFNDEF BIT61
- BIT61 EQU 2000000000000000h
-ENDIF
-IFNDEF BIT62
- BIT62 EQU 4000000000000000h
-ENDIF
-IFNDEF BIT63
- BIT63 EQU 8000000000000000h
-ENDIF
-
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/bridge32.inc b/src/vendorcode/amd/agesa/f15/Legacy/bridge32.inc
deleted file mode 100644
index 043c589c32..0000000000
--- a/src/vendorcode/amd/agesa/f15/Legacy/bridge32.inc
+++ /dev/null
@@ -1,575 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * Agesa structures and definitions
-; *
-; * Contains AMD AGESA core interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-;
-; ****************************************************************************
-;
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*****************************************************************************
-
-PARAM1 textequ <[bp+8]>
-PARAM2 textequ <[bp+12]>
-PARAM3 textequ <[bp+16]>
-RETAddress textequ <[bp+4]>
-
-AMD_PRIVATE_PARAMS STRUCT
- Gate16_CS DW ? ; Segment of AMD_BRIDGE_32 and AMD_CALLOUT_16
- Gate16_SS DW ? ; RM stack segment
- Router_Seg DW ? ; Segment of oem router
- Router_Off DW ? ; Offset of oem router
-AMD_PRIVATE_PARAMS ENDS
-
-; OEM may pre-define the GDT and selector offsets. If they do not, use our defaults.
-IFNDEF AGESA_SELECTOR_GDT
- AGESA_SELECTOR_GDT EQU 00h
-ENDIF
-IFNDEF AGESA_SELECTOR_CODE16
- AGESA_SELECTOR_CODE16 EQU 08h
-ENDIF
-IFNDEF AGESA_SELECTOR_DATA16
- AGESA_SELECTOR_DATA16 EQU 10h
-ENDIF
-IFNDEF AGESA_SELECTOR_CODE32
- AGESA_SELECTOR_CODE32 EQU 18h
-ENDIF
-IFNDEF AGESA_SELECTOR_DATA32
- AGESA_SELECTOR_DATA32 EQU 20h
-ENDIF
-
-
-AMD_BRIDGE_32_GDT MACRO GDT_Name:REQ
-
- GDT_Name LABEL BYTE
- DD 000000000h, 000000000h ; NULL descriptor
- DD 00000ffffh, 000009b00h ; 16-bit code, fixed up
- DD 00000ffffh, 000009300h ; 16-bit data, fixed up
- DD 00000ffffh, 000CF9B00h ; 32-bit protected mode code
- DD 00000ffffh, 000CF9300h ; 32-bit protected mode data
- GDT_Length EQU ($-GDT_Name)
-
-ENDM
-
-;+-------------------------------------------------------------------------
-;
-; AMD_BRIDGE_32 - Execute Agesa through Pushhigh interface
-;
-; Processing:
-; The following steps are taken:
-; 1) Enter 32bit Protected Mode (PM32)
-; 2) Run AGESA code
-; 3) Restore Real Mode (RM)
-;
-; Entry:
-; [big real mode] : ds, es set to base 0 limit 4G segment
-; EDX - if not 0, provides a FAR PTR to oem router (Seg | Offset)
-; ESI - configuration block pointer
-;
-; Exit:
-; EAX - return value
-; ESI - configuration block pointer
-; ds, es, fs, gs - Set to 4GB segment limit for Big Real Mode
-;
-; Modified:
-; None
-;
-
-AMD_BRIDGE_32 MACRO GDT_Name
-
- local copyGDT
- local flushTo16PM
- local agesaReturnAddress
- local leave32bitPM
- local flush2RM
-
- push gs
- push fs
- push ebx
- push ecx
- push edi
- mov eax, esp
- push eax
- movzx esp, sp
-;
-; Do not use any locals here, BP will be changed frequently during RM->PM32->RM
-;
- pushf
- cli ; Disable interrupts during AGESA
- cld ; Need known direction flag during AGESA
-
-;
-; Save the FAR PTR input parameter
-;
- mov gs, dx ; Offset
- shr edx, 16
- mov fs, dx ; Segment
-;
-; Determine where our binary file is and get entry point
-;
- mov edx, (AMD_CONFIG_PARAMS PTR [esi]).ImageBasePtr
- add edx, (AMD_IMAGE_HEADER PTR [edx]).EntryPointAddress
-;
-; Figure out the return address we will use after calling AGESA
-; and store it in ebx until we have our stack set up properly
-;
- mov ebx, cs
- shl ebx, 4
- add ebx, OFFSET agesaReturnAddress
-;
-; Save our current RM stack AND entry EBP
-;
- push ebp
-; push esp
- push ss
-
-;
-; BEGIN --- STACK MUST BE BALANCED AT THIS POINT --- BEGIN
-;
-; Copy the GDT onto the stack for modification
-;
- mov cx, GDT_Length
- sub sp, cx
- mov bp, sp
- lea di, GDT_Name
-copyGDT:
- mov al, cs:[di]
- mov [bp], al
- inc di
- inc bp
- loop copyGDT
-;
-; Patch 16-bit code and data descriptors on stack. We will
-; fix up CS and SS for PM16 during the callout if applicable.
-;
- mov bp, sp
-
- mov eax, cs
- shl eax, 4
- mov [bp+AGESA_SELECTOR_CODE16+2], ax
- shr eax, 16
- mov [bp+AGESA_SELECTOR_CODE16+4], al
-
- mov eax, ss
- shl eax, 4
- mov [bp+AGESA_SELECTOR_DATA16+2], ax
- shr eax, 16
- mov [bp+AGESA_SELECTOR_DATA16+4], al
-;
-; Need to place Length and Address on GDT
-;
- mov eax, ss
- shl eax, 4
- add eax, esp
- push eax
- push WORD PTR (GDT_Length-1)
-;
-; Load the GDT
-;
- mov bp, sp
- lgdt FWORD PTR [bp]
-;
-; TABLE 1
-;
-; Place PRIVATE DATA on stack DIRECTLY following GDT
-; During this routine, stack data is critical. If
-; order is changed or additional added, bad things
-; will happen!
-;
-; HIGHEST PHYSICAL ADDRESS
-;
-; | ... |
-; ------------------------
-; | old RM SP |
-; | old RM SS |
-; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS + (SIZEOF GDT_LENGTH + 6 {size, address})
-; | GDT_DATA32 |
-; | ... |
-; | GDT_NULL |
-; | GDT Addr, Length |
-; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS
-; | Priv.Gate16_SS |
-; | Priv.Gate16_CS |
-; ------------------------ sp
-; ------ THEN PUSH -------
-; | Return to 16-bit CS |
-; | Return to 16-bit Off |
-; | ... |
-;
-; LOWEST PHYSICAL ADDRESS
-;
- mov edi, esp
- sub edi, SIZEOF AMD_PRIVATE_PARAMS
- mov ax, cs
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS, ax
- mov ax, ss
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS, ax
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off, gs
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg, fs
-
- mov esp, edi
-;
-; Save an address for returning to 16 bit real mode on stack,
-; we'll use it in a far ret after turning off CR0.PE so that
-; we can take our address off and force a far jump. Be sure
-; no unexpected data is on the stack after this!
-;
- mov ax, cs
- push cs
- lea ax, flush2RM
- push ax
-;
-; Convert ss:esp to "flat"
-;
-
- mov ax, sp
- push ax
- mov eax, ss
- shl eax, 4
- add eax, esp
- mov esp, eax ; Load the zero based ESP
-
-;
-; Set CR0.PE
-;
- mov eax, CR0 ; Get CPU control word 0
- or al, 01 ; Enable CPU protected mode
- mov CR0, eax ; Write back to CPU control word 0
- jmp flushTo16PM
-
-flushTo16PM:
-;
-; 16-bit protected mode
-;
- mov ax, AGESA_SELECTOR_DATA32
- mov ds, ax
- mov es, ax
- mov fs, ax
- mov gs, ax
- mov ss, ax
-;
-; Push our parameters RIGHT TO LEFT, and then return address
-;
- push esi ; AGESA configuration block pointer (data)
- push ebx ; after AGESA return offset (32PM flat) - consumed by dispatcher ret
- pushd AGESA_SELECTOR_CODE32 ; AGESA entry selector (32PM flat)
- push edx ; AGESA entry point (32PM flat)
-
- DB 066h
- retf ; <><><> Enter AGESA 32-bit code!!! <><><>
-
-agesaReturnAddress:
-;
-; Returns from the Agesa 32-bit code still PM32
-;
- DB 0EAh
- DD OFFSET leave32bitPM
- DW AGESA_SELECTOR_CODE16
-
-leave32bitPM:
-;
-; Now in 16-bit PM
-;
- add esp, 4 ; +4 to remove our config block pointer
-;
-; Eax reserve AGESA_STATUS return code, save it
-;
- mov ebx, eax
-;
-; Turn off CR0.PE, restore 64K stack limit
-;
- pop ax
- mov sp, ax
- mov ax, AGESA_SELECTOR_DATA16
- mov ss, ax
-
- mov eax, CR0
- and al, NOT 1 ; Disable protected mode
- mov CR0, eax ; Write back CR0.PE
-;
-; Jump far to enter RM, we saved this address on the stack
-; already. Hopefully stack is balanced through AGESA
-; nor were any params added by pushing them on the stack and
-; not removing them between BEGIN-END comments.
-;
- retf
-
-flush2RM:
-;
-; Set segments registers for big real mode before returning
-;
- xor ax, ax
- mov ds, ax
- mov es, ax
- mov fs, ax
- mov gs, ax
-;
-; Discard GDT, +6 for GDT pointer/size, privates
-;
- add esp, GDT_Length + 6 + SIZEOF AMD_PRIVATE_PARAMS
-;
-; Restore real mode stack and entry EBP
-;
- pop cx
-; mov esp, [esp]
- mov ss, cx
- pop ebp
-;
-; Restore AGESA_STATUS return code to eax
-;
- mov eax, ebx
-;
-; END --- STACK MUST BE BALANCED TO THIS POINT --- END
-;
-
- popf
- pop ebx
- mov esp, ebx
- pop edi
- pop ecx
- pop ebx
- pop fs
- pop gs
- ; EXIT AMD_BRIDGE_32
-ENDM
-;+-------------------------------------------------------------------------
-;
-; AMD_CALLOUT_16 - Execute Callback from Pushhigh interface
-;
-; Processing:
-; The following steps are taken:
-; 1) Enter PM16
-; 2) Setup stack, get private params
-; 3) Enter RM
-; 4) Get 3 params
-; 5) Call oemCallout OR oem router
-; 6) Enter PM32
-; 7) Return to Agesa PH
-;
-; Entry:
-; [32-bit protected mode]
-; [esp+8] Func
-; [esp+12] Data
-; [esp+16] Configuration Block
-; [esp+4] return address to Agesa
-;
-; Exit:
-; [32-bit protected mode]
-;
-; Modified:
-; None
-;
-AMD_CALLOUT_16 MACRO LocalOemCalloutRouter
-;
-; Note that we are still PM32, so MASM may work strangely
-;
-
- push bp ; Save our original SP to access params
- mov bp, sp
- push bx
- push si
- push di
- push cx
- push dx
- push di
-
- DB 066h, 0EAh
- DW OFFSET PM16Entry
- DW AGESA_SELECTOR_CODE16
-
-PM16Entry:
-;
-; PM16 CS, but still PM32 SS, as we need to access our private params
-; before we enter RM.
-;
-; Note: we are working below the stack temporarily, and and it will
-; not affect our ability to get entry params
-;
- xor ecx, ecx
- xor edx, edx
-;
-; SGDT will give us the original location of the GDT on our CAS stack.
-; We need this value because our private parameters are located just
-; below the GDT.
-;
- mov edi, esp
- sub edi, GDT_Length + 6
- sgdt FWORD PTR [edi] ; [edi] = word size, dword address
- mov edi, DWORD PTR [edi+2] ; Get the PM32 address only
- sub edi, SIZEOF AMD_PRIVATE_PARAMS + 6
-;
-; cx = code segment of this code in RM
-; dx = stack segment of CAS in RM
-; fs = code segment of oem router (save for later)
-; gs = offset of oem router (save for later)
-; fs and gs are loaded after switch to real mode because we can't
-; use them as scratch pad registers in protected mode
-;
- mov cx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS
- mov dx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS
-
- mov eax, edi ; Save edi in eax for after RM switch
- mov edi, esp ; Save our current ESP for RM
-
- movzx ebx, dx
- shl ebx, 4
- sub esp, ebx
-
-;
-; We had been accessing the stack in PM32, we will now change to PM16 so we
-; will make the stack segment 64KB limit so SP needs to be fixed made PM16
-; compatible.
-;
- mov bx, AGESA_SELECTOR_DATA16
- mov ss, bx
-
-;
-; Save the RM segment and RM offset of the jump we will need to make in
-; order to enter RM so that code in this segment is relocatable.
-;
-; BEGIN --- Don't unbalance the stack --- BEGIN
-;
- push cx
- pushw OFFSET RMEntry
-
- mov ebx, CR0
- and bl, NOT 1
- mov CR0, ebx ; CR0.PE cleared
-;
-; Far jump to clear segment descriptor cache and enter RM
-;
- retf
-
-RMEntry:
-;
-; We are in RM, setup RM stack
-;
- movzx ebx, dx ; Get RM SS in ebx
- shl ebx, 4 ; Get our stack top on entry in EBP to
- sub ebp, ebx ; access our entry parameters
- sub eax, ebx ; save copy of parameters address
- mov ss, dx ; Set stack segment
-;
-; We are going to figure out the address to use when we return
-; and have to go back into PM32 while we have access to it
-;
- movzx ebx, cx ; Get original CS in ebx
- shl ebx, 4
- add ebx, OFFSET PM32Entry
-;
-; Now we put our data, func, block params into calling convention
-; for our hook
-;
-; ECX = Func
-; EDX = Data
-; ESI = config pointer
-;
- mov ecx, PARAM1 ; Func
- mov edx, PARAM2 ; Data
- mov esi, PARAM3 ; pointer
-
- push ebx ; Save PM32 mode switch address
- push edi ; Save PM32 stack pointer
- pushf
-;
-; Get Router Function Address
-;
- mov edi, eax
- mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg
- mov fs, ax
- mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off
- mov gs, ax
-
- mov eax, AGESA_UNSUPPORTED ; Default return value
-;
-; If AMD_BRIDGE_32 EDX == 0 call oemCallout
-; otherwise call FAR PTR EDX
-;
-; Critical:
-; sp+2 - EDI aka PM32 stack address
-; sp+4 - address of PM32Entry in PM32
-;
- mov bx, fs
- shl ebx, 16
- mov bx, gs
-
- .if (ebx == 0)
- call LocalOemCalloutRouter
- .else
-;
-; Make far call to Router function
-;
- push cs
- push offset CalloutReturn
- push ebx
- retf
-CalloutReturn:
- .endif
-;
-; Restore PM32 esp from RM stack
-;
- popf
- pop edi ; Our PM32 stack pointer
- pop edx ; Our PM32 mode switch address
-
- mov ebx, CR0
- or bl, 1 ; CR0.PE set
- mov CR0, ebx
-
- mov ebx, AGESA_SELECTOR_DATA32
- pushd AGESA_SELECTOR_CODE32 ; PM32 selector
- push edx ; PM32 entry point
-
- DB 066h
- retf ; Far jump to enter PM32
-
-PM32Entry:
-;
-; END --- Don't unbalance the stack --- END
-; We are now PM32, so remember MASM is assembling in 16-bit again
-;
- mov ss, bx
- mov ds, bx
- mov es, bx
- mov fs, bx
- mov gs, bx
-
- mov sp, di
- pop di
- pop dx
- pop cx
- pop di
- pop si
- pop bx
- pop bp
- ; EXIT AMD_CALLOUT_16
-ENDM
diff --git a/src/vendorcode/amd/agesa/f15/Lib/IA32/amdlib32.asm b/src/vendorcode/amd/agesa/f15/Lib/IA32/amdlib32.asm
deleted file mode 100644
index 5bebc1a29c..0000000000
--- a/src/vendorcode/amd/agesa/f15/Lib/IA32/amdlib32.asm
+++ /dev/null
@@ -1,671 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa library 32bit
-; *
-; * Contains AMD AGESA Library
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Lib
-; * @e \$Revision: 17071 $ @e \$Date: 2009-07-30 10:13:11 -0700 (Thu, 30 Jul 2009) $
-; */
-;*****************************************************************************
-;
-; Copyright (C) 2012 Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-.586p
-.xmm
-.model flat
-ASSUME FS:NOTHING
-.code
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write IO byte
-; *
-; * @param[in] Address IO port address
-; * @param[in] Data IO port Value
-; */
-
-public WriteIo8
-WriteIo8 PROC NEAR C USES DX AX Address:WORD, Data:Byte
- mov dx, Address
- mov al, Data
- out dx, al
- ret
-WriteIo8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write IO word
-; *
-; * @param[in] Address IO port address
-; * @param[in] Data IO port Value
-; */
-public WriteIo16
-WriteIo16 PROC NEAR C USES DX AX Address:WORD, Data:WORD
- mov dx, Address
- mov ax, Data
- out dx, ax
- ret
-WriteIo16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write IO dword
-; *
-; * @param[in] Address IO port address
-; * @param[in] Data IO port Value
-; */
-
-public WriteIo32
-WriteIo32 PROC NEAR C USES DX EAX Address:WORD, Data:DWORD
- mov dx, Address
- mov eax, Data
- out dx, eax
- ret
-WriteIo32 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read IO byte
-; *
-; * @param[in] - IO port address
-; * @retval IO port Value
-; */
-public ReadIo8
-ReadIo8 PROC NEAR C USES DX Address:WORD
- mov dx, Address
- in al, dx
- ret
-ReadIo8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read IO word
-; *
-; * @param[in] Address IO port address
-; * @retval IO port Value
-; */
-public ReadIo16
-ReadIo16 PROC NEAR C USES DX Address:WORD
- mov dx, Address
- in ax, dx
- ret
-ReadIo16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read IO dword
-; *
-; * @param[in] Address IO port address
-; * @retval IO port Value
-; */
-public ReadIo32
-ReadIo32 PROC NEAR C USES DX Address:WORD
- mov dx, Address
- in eax, dx
- ret
-ReadIo32 ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read MSR
-; *
-; * @param[in] Address MSR Address
-; * @param[in] Data Pointer to data
-; * @param[in] ConfigPtr (Optional)
-; */
-public LibAmdMsrRead
-LibAmdMsrRead PROC NEAR C USES ECX ESI EDX Address:DWORD, Value:PTR, ConfigPtr:PTR
- mov esi, ConfigPtr ;Dummy read to avoid compilation warning
- mov ecx, Address
- rdmsr
- mov esi, Value
- mov [esi], eax
- mov [esi+4], edx
- ret
-LibAmdMsrRead ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write MSR
-; *
-; * @param[in] Address MSR Address
-; * @param[in] Data Pointer to data
-; * @param[in] ConfigPtr (Optional)
-; */
-public LibAmdMsrWrite
-LibAmdMsrWrite PROC NEAR C USES ECX ESI EDX Address:DWORD, Data:PTR, ConfigPtr:PTR
- mov esi, ConfigPtr ;Dummy read to avoid compilation warning
- mov ecx, Address
- mov esi, Data
- mov eax, [esi]
- mov edx, [esi+4]
- wrmsr
- ret
-LibAmdMsrWrite ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read CPUID
-; *
-; * @param[in] Func CPUID function
-; * @param[in] DATA Pointer to CPUID_DATA to save cpuid data
-; * @param[in] ConfigPtr (Optional)
-; */
-public LibAmdCpuidRead
-LibAmdCpuidRead PROC NEAR C Func:DWORD, DATA:PTR, ConfigPtr:PTR
- pushad
- mov esi, ConfigPtr ;Dummy read to avoid compilation warning
- mov eax, Func
- cpuid
- mov esi, DATA
- mov [esi], eax
- mov [esi+4], ebx
- mov [esi+8], ecx
- mov [esi+12],edx
- popad
- ret
-LibAmdCpuidRead ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read TSC
-; *
-; *
-; *
-; */
-
-public ReadTSC
-ReadTSC PROC NEAR C
- rdtsc
- ret
-ReadTSC ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Set FS_BASE
-; *
-; *
-; *
-; * @param[in] esi - Low Dword of physical address
-; * @param[in] edi - High Dword of physical address
-; */
-SetFsBase PROC NEAR PUBLIC USES EAX EBX ECX EDX EDI
-
- mov eax, ecx
- mov ecx, 0C0010015h ; HWCR
- rdmsr
- mov ebx, eax
- bts eax, 17 ; HWCR.Wrap32Dis
- wrmsr
- xchg edx, edi
- mov eax, esi
- mov esi, ebx
-
- mov ecx, 0C0000100h ; FS_BASE
- wrmsr
- ret
-
-SetFsBase ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Restore MSR0C001_0015
-; *
-; * @param[in] esi - Low Dword
-; * @param[in] edi - High Dword
-; */
-RestoreHwcr PROC NEAR PUBLIC USES EAX ECX EDX
-
- mov ecx, 0C0010015h
- mov eax, esi
- mov edx, edi
- wrmsr
- ret
-
-RestoreHwcr ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read memory/MMIO byte
-; *
-; * @param[in] Address - Memory Address
-; * @retval Memory byte at given address
-; */
-Read64Mem8 PROC NEAR C PUBLIC USES EBX EDI ESI Address:QWORD
-
- mov esi, DWORD PTR Address[0]
- mov edi, DWORD PTR Address[4]
- test edi, edi
- jz AccesBelow4G
-
- push fs
- call SetFsBase
- xor ebx, ebx
- mov al, fs:[ebx]
- call RestoreHwcr
- pop fs
- jmp Done
-AccesBelow4G:
- mov al, ds:[esi]
-Done:
- ret
-
-Read64Mem8 ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read memory/MMIO word
-; *
-; * @param[in] Address - Memory Address
-; * @retval Memory word at given address
-; */
-Read64Mem16 PROC NEAR C PUBLIC USES EBX EDI ESI Address:QWORD
-
- mov esi, DWORD PTR Address[0]
- mov edi, DWORD PTR Address[4]
- test edi, edi
- jz AccesBelow4G
-
- push fs
- call SetFsBase
- xor ebx, ebx
- mov ax, fs:[ebx]
- call RestoreHwcr
- pop fs
- jmp Done
-AccesBelow4G:
- mov ax, ds:[esi]
-Done:
-
- ret
-
-Read64Mem16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read memory/MMIO dword
-; *
-; * @param[in] Address - Memory Address
-; * @retval Memory dword at given address
-; */
-Read64Mem32 PROC NEAR C PUBLIC USES EBX EDI ESI Address:QWORD
-
- mov esi, DWORD PTR Address[0]
- mov edi, DWORD PTR Address[4]
- test edi, edi
- jz AccesBelow4G
-
- push fs
- call SetFsBase
- xor ebx, ebx
- mov eax, fs:[ebx]
- call RestoreHwcr
- pop fs
- jmp Done
-AccesBelow4G:
- mov eax, ds:[esi]
-Done:
- ret
-
-Read64Mem32 ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write memory/MMIO byte
-; *
-; * @param[in] Address - Memory Address
-; * @param[in] Value - Value to write
-; */
-
-Write64Mem8 PROC NEAR C PUBLIC USES EBX EDI ESI Address:QWORD, Data:BYTE
-
- mov esi, DWORD PTR Address[0]
- mov edi, DWORD PTR Address[4]
- test edi, edi
- jz AccesBelow4G
-
- push fs
- call SetFsBase
- xor ebx, ebx
- mov al, Data
- mov fs:[ebx], al
- call RestoreHwcr
- pop fs
- jmp Done
-AccesBelow4G:
- mov al, Data
- mov ds:[esi], al
-Done:
-
- ret
-
-Write64Mem8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write memory/MMIO word
-; *
-; * @param[in] Address - Memory Address
-; * @param[in] Value - Value to write
-; */
-Write64Mem16 PROC NEAR C PUBLIC USES EBX EDI ESI Address:QWORD, Data:WORD
-
- mov esi, DWORD PTR Address[0]
- mov edi, DWORD PTR Address[4]
- test edi, edi
- jz AccesBelow4G
-
- push fs
- call SetFsBase
- xor ebx, ebx
- mov ax, Data
- mov fs:[ebx], ax
- call RestoreHwcr
- pop fs
- jmp Done
-AccesBelow4G:
- mov ax, Data
- mov ds:[esi], ax
-Done:
- ret
-
-Write64Mem16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write memory/MMIO dword
-; *
-; * @param[in] Address - Memory Address
-; * @param[in] Value - Value to write
-; */
-Write64Mem32 PROC NEAR C PUBLIC USES EBX EDI ESI Address:QWORD, Data:DWORD
-
- mov esi, DWORD PTR Address[0]
- mov edi, DWORD PTR Address[4]
- test edi, edi
- jz AccesBelow4G
-
- push fs
- call SetFsBase
- xor ebx, ebx
- mov eax, Data
- mov fs:[ebx], eax
- call RestoreHwcr
- pop fs
- jmp Done
-AccesBelow4G:
- mov eax, Data
- mov ds:[esi], eax
-
-Done:
-
- ret
-
-Write64Mem32 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read various CPU registers
-; *
-; * @param[in] Reg Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
-; * @param[in] Value Value to write
-; */
-
-LibAmdReadCpuReg PROC NEAR C Reg:BYTE, Value:NEAR PTR DWORD
- pushad
- push ds
-
- .if(Reg == 00h)
- mov eax, cr0
- .elseif(Reg == 04h)
- mov eax, cr4
- .elseif(Reg == 10h)
- mov eax, dr0
- .elseif(Reg == 11h)
- mov eax, dr1
- .elseif(Reg == 12h)
- mov eax, dr2
- .elseif(Reg == 13h)
- mov eax, dr3
- .elseif(Reg == 17h)
- mov eax, dr7
- .else
- xor eax,eax
- .endif
-
- mov edi, Value
- mov [edi], eax
-
- pop ds
- popad
- ret
-LibAmdReadCpuReg ENDP
-
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write various CPU registers
-; *
-; * @param[in] Reg Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
-; * @param[in] Value Value to write
-; */
-
-LibAmdWriteCpuReg PROC NEAR C Reg:BYTE, Value:DWORD
- mov eax, Value
-
- .if(Reg == 00h)
- mov cr0, eax
- .elseif(Reg == 4)
- mov cr4, eax
- .elseif(Reg == 10h)
- mov dr0, eax
- .elseif(Reg == 11h)
- mov dr1, eax
- .elseif(Reg == 12h)
- mov dr2, eax
- .elseif(Reg == 13h)
- mov dr3, eax
- .elseif(Reg == 17h)
- mov dr7, eax
- .endif
- ret
-LibAmdWriteCpuReg ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write back invalidate caches using wbinvd.
-; *
-; *
-; *
-; */
-
-PUBLIC LibAmdWriteBackInvalidateCache
-LibAmdWriteBackInvalidateCache PROC NEAR C
- wbinvd
- ret
-LibAmdWriteBackInvalidateCache ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Stop CPU
-; *
-; *
-; *
-; */
-
-PUBLIC StopHere
-StopHere PROC NEAR C
-@@:
- jmp short @b
-StopHere ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Enter debugger on SimNow
-; *
-; *
-; *
-; */
-PUBLIC LibAmdSimNowEnterDebugger
-LibAmdSimNowEnterDebugger PROC NEAR C
- pushad
- mov eax, 0BACCD00Bh ; Backdoor in SimNow
- mov ebx, 2 ; Select breakpoint feature
- cpuid
-@@:
- jmp short @b
- popad
- ret
-LibAmdSimNowEnterDebugger ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * IDS IO port write
-; *
-; * @param[in] Address IO Port Address
-; * @param[in] Value Value to write
-; * @param[in] Flag IDS flags
-; *
-; */
-
-PUBLIC IdsOutPort
-IdsOutPort PROC NEAR C Address:DWORD, Value:DWORD ,Flag:DWORD
- push edx
- push eax
- push ebx
- mov edx, Address
- mov eax, Value
- mov ebx, Flag
- out dx, eax
- pop ebx
- pop eax
- pop edx
- ret
-IdsOutPort ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Force breakpoint on HDT
-; *
-; *
-; */
-PUBLIC LibAmdHDTBreakPoint
-LibAmdHDTBreakPoint PROC NEAR C
-
- pushad
-
- mov ecx, 0C001100Ah ;bit 0 = HDT redirect
- mov edi, 09C5A203Ah ;Password
- RDMSR ;
- or al, 1 ;
- WRMSR ;
- mov al, 0B2h ;Marker = B2
- db 0F1h ;ICEBP
-
- popad
- ret
-
-LibAmdHDTBreakPoint ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Find the most right hand side non-zero bit with .
-; *
-; * @param[in] Value Value
-; */
-PUBLIC LibAmdBitScanForward
-LibAmdBitScanForward PROC NEAR C Value:DWORD
- mov eax, Value
- bsf eax, Value
- .if (Zero?)
- mov al,32
- .endif
- ret
-LibAmdBitScanForward ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Find the most left hand side non-zero bit.
-; *
-; * @param[in] Value Value
-; */
-PUBLIC LibAmdBitScanReverse
-LibAmdBitScanReverse PROC NEAR C Value:DWORD
- mov eax, Value
- bsr eax, Value
- .if (Zero?)
- mov al,0FFh
- .endif
- ret
-LibAmdBitScanReverse ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Flush specified number of cache line
-; *
-; * @param[in] Address Physical address to be flushed
-; * @param[in] Count number of cachelines to be flushed
-; */
-PUBLIC LibAmdCLFlush
-LibAmdCLFlush PROC NEAR C Address:QWORD, Count:BYTE
- pushad
- mov ecx, 0C0010015h ; HWCR
- rdmsr
- mov esi, eax
- mov edi, edx
- bts eax, 17 ; HWCR.Wrap32Dis
- wrmsr
- xor eax, eax
- mov edx, DWORD PTR Address[4]
- mov ecx, 0C0000100h ; FS_BASE
- wrmsr
- mov eax, DWORD PTR Address[0]
- movzx ecx, Count
- @@:
- mfence
- clflush fs:[eax]
- mfence
- add eax,64
- loop @B
- call RestoreHwcr
- popad
- ret
-LibAmdCLFlush ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f15/Lib/IA32/ms_shift.asm b/src/vendorcode/amd/agesa/f15/Lib/IA32/ms_shift.asm
deleted file mode 100644
index 18b8ee4dde..0000000000
--- a/src/vendorcode/amd/agesa/f15/Lib/IA32/ms_shift.asm
+++ /dev/null
@@ -1,110 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa library 32bit
-; *
-; * Contains AMD AGESA Library
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Lib
-; * @e \$Revision: 9201 $ @e \$Date: 2008-10-31 03:36:20 -0500 (Fri, 31 Oct 2008) $
-; */
-;*****************************************************************************
-;
-; Copyright (C) 2012 Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-.586p
-.model flat
-ASSUME FS:NOTHING
-.code
-;/*++
-;
-;Routine Description:
-;
-; Shifts a UINT64 to the right.
-;
-;Arguments:
-;
-; EDX:EAX - UINT64 value to be shifted
-; CL - Shift count
-;
-;Returns:
-;
-; EDX:EAX - shifted value
-;
-;--*/
-_aullshr PROC NEAR C PUBLIC
- .if (cl < 64)
- .if (cl >= 32)
- sub cl, 32
- mov eax, edx
- xor edx, edx
- .endif
- shrd eax, edx, cl
- shr edx, cl
- .else
- xor eax, eax
- xor edx, edx
- .endif
- ret
-_aullshr ENDP
-
-;/*++
-;
-;Routine Description:
-;
-; Shifts a UINT64 to the left.
-;
-;Arguments:
-;
-; EDX:EAX - UINT64 value to be shifted
-; CL - Shift count
-;
-;Returns:
-;
-; EDX:EAX - shifted value
-;
-;--*/
-_allshl PROC NEAR C PUBLIC USES CX
- .if (cl < 64)
- .if (cl >= 32)
- sub cl, 32
- mov edx, eax
- xor eax, eax
- .endif
- shld edx, eax, cl
- shl eax, cl
- .else
- xor eax, eax
- xor edx, edx
- .endif
- ret
-_allshl ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f15/Lib/IA32/msmemcpy.asm b/src/vendorcode/amd/agesa/f15/Lib/IA32/msmemcpy.asm
deleted file mode 100644
index 9c098a69ae..0000000000
--- a/src/vendorcode/amd/agesa/f15/Lib/IA32/msmemcpy.asm
+++ /dev/null
@@ -1,84 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa library 32bit
-; *
-; * Contains AMD AGESA Library
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Lib
-; * @e \$Revision: 9201 $ @e \$Date: 2008-10-31 03:36:20 -0500 (Fri, 31 Oct 2008) $
-; */
-;*****************************************************************************
-;
-; Copyright (C) 2012 Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-.586p
-.model flat
-ASSUME FS:NOTHING
-.code
-; void *memcpy( void *dest, void *src, size_t count );
-;
-; Copy count bytes from src to dest, returning dest.
-; ("c" is not legal as an assembly parameter name, replaced with value.)
-; Assume ES is set appropriately, 32 bit flat.
-;
-public memcpy
-memcpy PROC NEAR C PUBLIC USES ECX EDI ESI dest:DWORD, src:DWORD, count:DWORD
- pushf
- cld ; We will increment through *dest
- mov edi, dest
- mov esi, src
- mov ecx, count
- rep movsb
- mov eax, dest
- popf
- ret
-memcpy ENDP
-
-; void *memset( void *dest, int c, size_t count );
-;
-; At dest, set count bytes to byte value, returning dest.
-; ("c" is not legal as an assembly parameter name, replaced with value.)
-; Assume ES is set appropriately, 32 bit flat.
-;
-public memset
-memset PROC NEAR C PUBLIC USES ECX EDI dest:DWORD, value:DWORD, count:DWORD
- pushf
- cld ; We will increment through *dest
- mov edi, dest
- mov eax, value
- mov ecx, count
- rep stosb
- mov eax, edi
- popf
- ret
-memset ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f15/Lib/x64/amdlib64.asm b/src/vendorcode/amd/agesa/f15/Lib/x64/amdlib64.asm
deleted file mode 100644
index 8ec78d11da..0000000000
--- a/src/vendorcode/amd/agesa/f15/Lib/x64/amdlib64.asm
+++ /dev/null
@@ -1,591 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa library 64bit
-; *
-; * Contains AMD AGESA Library
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Lib
-; * @e \$Revision: 17071 $ @e \$Date: 2009-07-30 10:13:11 -0700 (Thu, 30 Jul 2009) $
-; */
-;*****************************************************************************
-;
-; Copyright (C) 2012 Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-.code
-;/*++
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write IO byte
-; *
-; * @param[in] CX IO port address
-; * @param[in] DL IO port Value
-; */
-
-PUBLIC WriteIo8
-WriteIo8 PROC
- mov al, dl
- mov dx, cx
- out dx, al
- ret
-WriteIo8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write IO word
-; *
-; * @param[in] CX IO port address
-; * @param[in] DX IO port Value
-; */
-PUBLIC WriteIo16
-WriteIo16 PROC
- mov ax, dx
- mov dx, cx
- out dx, ax
- ret
-WriteIo16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write IO dword
-; *
-; * @param[in] CX IO port address
-; * @param[in] EDX IO port Value
-; */
-
-PUBLIC WriteIo32
-WriteIo32 PROC
- mov eax, edx
- mov dx, cx
- out dx, eax
- ret
-WriteIo32 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read IO byte
-; *
-; * @param[in] CX IO port address
-; * @retval AL IO port Value
-; */
-PUBLIC ReadIo8
-ReadIo8 PROC
- mov dx, cx
- in al, dx
- ret
-ReadIo8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read IO word
-; *
-; * @param[in] CX IO port address
-; * @retval AX IO port Value
-; */
-PUBLIC ReadIo16
-ReadIo16 PROC
- mov dx, cx
- in ax, dx
- ret
-ReadIo16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read IO dword
-; *
-; * @param[in] CX IO port address
-; * @retval EAX IO port Value
-; */
-PUBLIC ReadIo32
-ReadIo32 PROC
- mov dx, cx
- in eax, dx
- ret
-ReadIo32 ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read MSR
-; *
-; * @param[in] RCX MSR Address
-; * @param[in] RDX Pointer to data
-; * @param[in] R8D ConfigPtr (Optional)
-; */
-PUBLIC LibAmdMsrRead
-LibAmdMsrRead PROC
- push rsi
- mov rsi, rdx
- rdmsr
- mov [rsi], eax
- mov [rsi+4], edx
- pop rsi
- ret
-LibAmdMsrRead ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write MSR
-; *
-; * @param[in] RCX MSR Address
-; * @param[in] RDX Pointer to data
-; * @param[in] R8D ConfigPtr (Optional)
-; */
-PUBLIC LibAmdMsrWrite
-LibAmdMsrWrite PROC
- push rsi
- mov rsi, rdx
- mov eax, [rsi]
- and rax, 0ffffffffh
- mov edx, [rsi+4]
- and rdx, 0ffffffffh
- wrmsr
- pop rsi
- ret
-LibAmdMsrWrite ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read CPUID
-; *
-; * @param[in] RCX CPUID function
-; * @param[in] RDX Pointer to CPUID_DATA to save cpuid data
-; * @param[in] R8D ConfigPtr (Optional)
-; */
-PUBLIC LibAmdCpuidRead
-LibAmdCpuidRead PROC
-
- push rbx
- push rsi
- mov rsi, rdx
- mov rax, rcx
- cpuid
- mov [rsi], eax
- mov [rsi+4], ebx
- mov [rsi+8], ecx
- mov [rsi+12],edx
- pop rsi
- pop rbx
- ret
-
-LibAmdCpuidRead ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read TSC
-; *
-; *
-; * @retval RAX Time stamp counter value
-; */
-
-PUBLIC ReadTSC
-ReadTSC PROC
- rdtsc
- and rax, 0ffffffffh
- shl rdx, 32
- or rax, rdx
- ret
-ReadTSC ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read memory/MMIO byte
-; *
-; * @param[in] RCX - Memory Address
-; * @retval Memory byte at given address
-; */
-PUBLIC Read64Mem8
-Read64Mem8 PROC
-
- xor rax, rax
- mov al, [rcx]
- ret
-
-Read64Mem8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read memory/MMIO word
-; *
-; * @param[in] RCX - Memory Address
-; * @retval Memory word at given address
-; */
-PUBLIC Read64Mem16
-Read64Mem16 PROC
-
- xor rax, rax
- mov ax, [rcx]
- ret
-
-Read64Mem16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read memory/MMIO dword
-; *
-; * @param[in] RCX - Memory Address
-; * @retval Memory dword at given address
-; */
-PUBLIC Read64Mem32
-Read64Mem32 PROC
-
- xor rax, rax
- mov eax, [rcx]
- ret
-
-Read64Mem32 ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write memory/MMIO byte
-; *
-; * @param[in] RCX Memory Address
-; * @param[in] DL Value to write
-; */
-
-PUBLIC Write64Mem8
-Write64Mem8 PROC
-
- xor rax, rax
- mov rax, rdx
- mov [rcx], al
- ret
-
-Write64Mem8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write memory/MMIO word
-; *
-; * @param[in] RCX Memory Address
-; * @param[in] DX Value to write
-; */
-PUBLIC Write64Mem16
-Write64Mem16 PROC
-
- xor rax, rax
- mov rax, rdx
- mov [rcx], ax
- ret
-
-Write64Mem16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write memory/MMIO dword
-; *
-; * @param[in] RCX Memory Address
-; * @param[in] EDX Value to write
-; */
-PUBLIC Write64Mem32
-Write64Mem32 PROC
-
- xor rax, rax
- mov rax, rdx
- mov [rcx], eax
- ret
-
-Write64Mem32 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read various CPU registers
-; *
-; * @param[in] CL Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
-; * @param[in] RDX Pointer to value
-; */
-
-PUBLIC LibAmdReadCpuReg
-LibAmdReadCpuReg PROC
-
- push rax
- xor rax, rax
-Reg00h:
- cmp cl, 00h
- jne Reg04h
- mov rax, cr0
- jmp RegRead
-Reg04h:
- cmp cl, 04h
- jne Reg10h
- mov rax, cr4
- jmp RegRead
-Reg10h:
- cmp cl, 10h
- jne Reg11h
- mov rax, dr0
- jmp RegRead
-Reg11h:
- cmp cl, 11h
- jne Reg12h
- mov rax, dr1
- jmp RegRead
-Reg12h:
- cmp cl, 12h
- jne Reg13h
- mov rax, dr2
- jmp RegRead
-Reg13h:
- cmp cl, 13h
- jne Reg17h
- mov rax, dr3
- jmp RegRead
-Reg17h:
- cmp cl, 17h
- jne RegRead
- mov rax, dr7
-RegRead:
- mov [rdx], eax
- pop rax
- ret
-LibAmdReadCpuReg ENDP
-
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write various CPU registers
-; *
-; * @param[in] CL Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
-; * @param[in] RDX Value to write
-; */
-
-PUBLIC LibAmdWriteCpuReg
-LibAmdWriteCpuReg PROC
-
- push rax
-Reg00h:
- cmp cl, 00h
- jne Reg04h
- mov rax, cr0
- mov eax, edx
- mov cr0, rax
- jmp Done
-Reg04h:
- cmp cl, 04h
- jne Reg10h
- mov rax, cr4
- mov eax, edx
- mov cr4, rax
- jmp Done
-Reg10h:
- cmp cl, 10h
- jne Reg11h
- mov rax, dr0
- mov eax, edx
- mov dr0, rax
- jmp Done
-Reg11h:
- cmp cl, 11h
- jne Reg12h
- mov rax, dr1
- mov eax, edx
- mov dr1, rax
- jmp Done
-Reg12h:
- cmp cl, 12h
- jne Reg13h
- mov rax, dr2
- mov eax, edx
- mov dr2, rax
- jmp Done
-Reg13h:
- cmp cl, 13h
- jne Reg17h
- mov rax, dr3
- mov eax, edx
- mov dr3, rax
- jmp Done
-Reg17h:
- cmp cl, 17h
- jne Done
- mov rax, dr7
- mov eax, edx
- mov dr7, rax
-Done:
- pop rax
- ret
-LibAmdWriteCpuReg ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write back invalidate caches using wbinvd.
-; *
-; *
-; *
-; */
-
-PUBLIC LibAmdWriteBackInvalidateCache
-LibAmdWriteBackInvalidateCache PROC
- wbinvd
- ret
-LibAmdWriteBackInvalidateCache ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Stop CPU
-; *
-; *
-; *
-; */
-
-PUBLIC StopHere
-StopHere PROC
-@@:
- jmp short @b
-StopHere ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Enter debugger on SimNow
-; *
-; *
-; *
-; */
-PUBLIC LibAmdSimNowEnterDebugger
-LibAmdSimNowEnterDebugger PROC
- pushfq
- mov rax, 0BACCD00Bh ; Backdoor in SimNow
- mov rbx, 2 ; Select breakpoint feature
- cpuid
-@@:
- jmp short @b
- popfq
- ret
-LibAmdSimNowEnterDebugger ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * IDS IO port write
-; *
-; * @param[in] ECX IO Port Address
-; * @param[in] EDX Value to write
-; * @param[in] R8D IDS flags
-; *
-; */
-
-PUBLIC IdsOutPort
-IdsOutPort PROC
- push rbx
- push rax
-
- mov ebx, r8d
- mov eax, edx
- mov edx, ecx
- out dx, eax
-
- pop rax
- pop rbx
- ret
-IdsOutPort ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Force breakpoint on HDT
-; *
-; *
-; */
-PUBLIC LibAmdHDTBreakPoint
-LibAmdHDTBreakPoint PROC
-
- push rbx
-
- mov rcx, 0C001100Ah ;bit 0 = HDT redirect
- mov rdi, 09C5A203Ah ;Password
- rdmsr
- and rax, 0ffffffffh
- or rax, 1
-
- wrmsr
-
- mov rax, 0B2h ;Marker = B2
- db 0F1h ;ICEBP
-
- pop rbx
- ret
-
-LibAmdHDTBreakPoint ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Find the most right hand side non-zero bit with
-; *
-; * @param[in] ECX Value
-; */
-PUBLIC LibAmdBitScanForward
-LibAmdBitScanForward PROC
- bsf eax, ecx
- jnz nonZeroSource
- mov al,32
-nonZeroSource:
- ret
-LibAmdBitScanForward ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Find the most left hand side non-zero bit.
-; *
-; * @param[in] ECX Value
-; */
-PUBLIC LibAmdBitScanReverse
-LibAmdBitScanReverse PROC
- bsr eax, ecx
- jnz nonZeroSource
- mov al,0FFh
-nonZeroSource:
- ret
-LibAmdBitScanReverse ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Flush specified number of cache line
-; *
-; * @param[in] RCX Physical address to be flushed
-; * @param[in] DL number of cachelines to be flushed
-; */
-PUBLIC LibAmdCLFlush
-LibAmdCLFlush PROC
- push rax
- mov rax, rcx
- movzx rcx, dl
- @@:
- mfence
- clflush [rax]
- mfence
- add rax,64
- loop @B
- pop rax
- ret
-LibAmdCLFlush ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevD32.asm b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevD32.asm
deleted file mode 100644
index 2ac72adfe0..0000000000
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevD32.asm
+++ /dev/null
@@ -1,113 +0,0 @@
-;/**
-; * @file
-; *
-; * AGESA Family 10h Revision D support routines.
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: CPU/F10
-; * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
-; */
-;*****************************************************************************
-;
-; Copyright (C) 2012 Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- .XLIST
- .LIST
-
- .586P
-
-;===============================================
-;===============================================
-;==
-;== M E M O R Y P R E S E N T S E G M E N T
-;==
-;===============================================
-;===============================================
- .MODEL flat
- .CODE
-
-;======================================================================
-; F10RevDProbeFilterCritical: Performs critical sequence for probe
-; filter initialization.
-;
-; In:
-; PciAddress Full PCI address of the node to init
-; LocalPciRegister Current value of F3x1D4
-;
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-F10RevDProbeFilterCritical PROC NEAR C PUBLIC USES EAX ECX EDX, PciAddress:DWORD, LocalPciRegister:DWORD
-
- mov ecx, 0C001001Fh
- rdmsr
- push eax
- push ecx
- push edx
- or dh, 40h
- wrmsr
-
- mov eax, 810003D4h
-
- mov ecx, LocalPciRegister
- mov edx, PciAddress
- shr edx, 4
- and dh, 0F8h
- or ah, dh
-
- or cl, 2
- db 0Fh, 0AEh, 0F0h ; MFENCE
-
- mov dx, 0CF8h ; Set Reg Config Space
- db 0Fh, 0AEh, 0F0h ; MFENCE
-
- out dx, eax
- db 0Fh, 0AEh, 0F0h ; MFENCE
-
- mov dl, 0FCh ; Set DX to Pci Config Data
- mov eax, ecx ;Set config Reg data
- db 0Fh, 0AEh, 0F0h ; MFENCE
-
- out dx, eax ; move data to return position
- db 0Fh, 0AEh, 0F0h ; MFENCE
-
- pop edx
- pop ecx
- pop eax
- wrmsr
- ret
-
-F10RevDProbeFilterCritical ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevD64.asm b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevD64.asm
deleted file mode 100644
index 4e531ea5ab..0000000000
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevD64.asm
+++ /dev/null
@@ -1,127 +0,0 @@
-;/**
-; * @file
-; *
-; * AGESA Family 10h Revision D support routines.
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: CPU/F10
-; * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
-; */
-;*****************************************************************************
-;
-; Copyright (C) 2012 Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- .XLIST
- .LIST
-
-;===============================================
-;===============================================
-;==
-;== M E M O R Y P R E S E N T S E G M E N T
-;==
-;===============================================
-;===============================================
- .CODE
-
-;======================================================================
-; F10RevDProbeFilterCritical: Performs critical sequence for probe
-; filter initialization.
-;
-; In:
-; PciAddress Full PCI address of the node to init
-; LocalPciRegister Current value of F3x1D4
-;
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-PUBLIC F10RevDProbeFilterCritical
-F10RevDProbeFilterCritical PROC
-
- push rax
- push rcx
- push rdx
- push rsi
- push rdi
-
- mov esi, ecx
- mov edi, edx
-
- mov ecx, 0C001001Fh
- rdmsr
- push rax
- push rcx
- push rdx
- or dh, 40h
- wrmsr
-
- mov eax, 810003D4h
-
- mov ecx, edi
- mov edx, esi
-
- shr edx, 4
- and dh, 0F8h
- or ah, dh
-
- or cl, 2
- mfence
-
- mov dx, 0CF8h ; Set Reg Config Space
- mfence
-
- out dx, eax
- mfence
-
- mov dl, 0FCh ; Set DX to Pci Config Data
- mov eax, ecx ;Set config Reg data
- mfence
-
- out dx, eax ; move data to return position
- mfence
-
- pop rdx
- pop rcx
- pop rax
- wrmsr
-
- pop rdi
- pop rsi
- pop rdx
- pop rcx
- pop rax
- ret
-
-F10RevDProbeFilterCritical ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.asm b/src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.asm
deleted file mode 100644
index 1ce62cdb4d..0000000000
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.asm
+++ /dev/null
@@ -1,362 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa pre-memory miscellaneous support, including ap halt loop.
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: CPU
-; * @e \$Revision: 47763 $ @e \$Date: 2011-02-27 18:11:57 -0700 (Sun, 27 Feb 2011) $
-; */
-;*****************************************************************************
-;
-; Copyright (C) 2012 Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- .XLIST
- INCLUDE agesa.inc
- INCLUDE cpcarmac.inc
- .LIST
-
- .586P
-
-;===============================================
-;===============================================
-;==
-;== M E M O R Y A B S E N T S E G M E N T
-;==
-;===============================================
-;===============================================
- .MODEL flat
- .CODE
-;======================================================================
-; ExecuteFinalHltInstruction: Disables the stack and performs
-; a hlt instruction on an AP.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; eax, ebx, ecx, edx, esp
-;
-;======================================================================
-PUBLIC ExecuteFinalHltInstruction
-ExecuteFinalHltInstruction PROC NEAR C USES ESI EDI HaltFlags:DWORD, ApMtrrSettingList:PTR, StandardHeader:PTR
-
- mov esi, StandardHeader ; The code must reference all parameters to avoid a build warning
- mov esi, HaltFlags
- mov edi, ApMtrrSettingList
- ; Do these special steps in case if the core is part of a compute unit
- ; Note: The following bits are family specific flags, that gets set during build time,
- ; and indicates things like "family cache control methodology", etc.
- ; esi bit0 = 0 -> not a Primary core
- ; esi bit0 = 1 -> Primary core
- ; esi bit1 = 0 -> Cache disable
- ; esi bit1 = 1 -> Cache enable
- .if (esi & 2h)
- ; Set CombineCr0Cd bit
- mov ecx, CU_CFG3
- _RDMSR
- bts edx, (COMBINE_CR0_CD - 32)
- _WRMSR
- ; Clear the CR0.CD bit
- mov eax, CR0 ; Make sure cache is enabled for all APs
- btr eax, CR0_CD
- btr eax, CR0_NW
- mov CR0, eax ; Write back to CR0
- .else
- mov eax, CR0 ; Make sure cache is disabled for all APs
- bts eax, CR0_CD ; Disable cache
- bts eax, CR0_NW
- mov CR0, eax ; Write back to CR0
- .endif
-
- .if (esi & 1h)
- ; This core is a primary core and needs to do all the MTRRs, including shared MTRRs.
- mov esi, edi ; Get ApMtrrSettingList
-
- ; Configure the MTRRs on the AP so
- ; when it runs remote code it will execute
- ; out of RAM instead of ROM.
-
- ; Disable MTRRs and turn on modification enable bit
- mov ecx, MTRR_SYS_CFG
- _RDMSR
- btr eax, MTRR_VAR_DRAM_EN ; Disable
- bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable
- btr eax, MTRR_FIX_DRAM_EN ; Disable
- bts eax, SYS_UC_LOCK_EN
- _WRMSR
-
- ; Setup default values for Fixed-Sized MTRRs
- ; Set 7FFFh-00000h as WB
- mov ecx, AMD_AP_MTRR_FIX64k_00000
- mov eax, 1E1E1E1Eh
- mov edx, eax
- _WRMSR
-
- ; Set 9FFFFh-80000h also as WB
- mov ecx, AMD_AP_MTRR_FIX16k_80000
- _WRMSR
-
- ; Set BFFFFh-A0000h as Uncacheable Memory-mapped IO
- mov ecx, AMD_AP_MTRR_FIX16k_A0000
- xor eax, eax
- xor edx, edx
- _WRMSR
-
- ; Set DFFFFh-C0000h as Uncacheable Memory-mapped IO
- xor eax, eax
- xor edx, edx
- mov ecx, AMD_AP_MTRR_FIX4k_C0000
-
-CDLoop:
- _WRMSR
- inc ecx
- cmp ecx, AMD_AP_MTRR_FIX4k_D8000
- jbe CDLoop
-
- ; Set FFFFFh-E0000h as Uncacheable Memory
- mov eax, 18181818h
- mov edx, eax
-
- mov ecx, AMD_AP_MTRR_FIX4k_E0000
-
-EFLoop:
- _WRMSR
- inc ecx
- cmp ecx, AMD_AP_MTRR_FIX4k_F8000
- jbe EFLoop
-
- ; If IBV provided settings for Fixed-Sized MTRRs,
- ; overwrite the default settings.
- .if ((esi != 0) && (esi != 0FFFFFFFFh))
- mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
- ; While we are not at the end of the list
- .while (ecx != CPU_LIST_TERMINAL)
- ; Ensure that the MSR address is valid for Fixed-Sized MTRRs
- .if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \
- (ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || (ecx == AMD_AP_MTRR_FIX16k_A0000))
- mov eax, dword ptr (AP_MTRR_SETTINGS ptr [esi]).MsrData
- mov edx, dword ptr (AP_MTRR_SETTINGS ptr [esi+4]).MsrData
- _WRMSR
- .endif
- add esi, sizeof (AP_MTRR_SETTINGS)
- mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
- .endw
- .endif
-
- ; Enable fixed-range and variable-range MTRRs
- mov ecx, AMD_MTRR_DEFTYPE
- _RDMSR
- bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn
- bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn
- _WRMSR
-
- ; Enable Top-of-Memory setting
- ; Enable use of RdMem/WrMem bits attributes
- mov ecx, MTRR_SYS_CFG
- _RDMSR
- bts eax, MTRR_VAR_DRAM_EN ; Enable
- btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable
- bts eax, MTRR_FIX_DRAM_EN ; Enable
- _WRMSR
-
- mov esi, (1 SHL FLAG_IS_PRIMARY)
- .else ; end if primary core
- xor esi, esi
- .endif
- ; Make sure not to touch any Shared MSR from this point on
-
- AMD_DISABLE_STACK_FAMILY_HOOK
-
- bt esi, FLAG_IS_PRIMARY
- .if (carry?)
- ; restore variable MTRR6 and MTRR7 to default states
- mov ecx, AMD_MTRR_VARIABLE_MASK7 ; clear MTRRPhysBase6 MTRRPhysMask6
- xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7
- xor edx, edx
- .while (cx >= AMD_MTRR_VARIABLE_BASE6)
- _WRMSR
- dec cx
- .endw
- .endif
-
-@@:
- cli
- hlt
- jmp @B ;ExecuteHltInstruction
- ret
-ExecuteFinalHltInstruction ENDP
-
-;======================================================================
-; ExecuteHltInstruction: Performs a hlt instruction.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; eax, ebx, ecx, edx, esp
-;
-;======================================================================
-PUBLIC ExecuteHltInstruction
-ExecuteHltInstruction PROC NEAR C
- cli
- hlt
- ret
-ExecuteHltInstruction ENDP
-
-;======================================================================
-; NmiHandler: Simply performs an IRET.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-PUBLIC NmiHandler
-NmiHandler PROC NEAR C
- iretd
-NmiHandler ENDP
-
-;======================================================================
-; GetCsSelector: Returns the current protected mode CS selector.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-PUBLIC GetCsSelector
-GetCsSelector PROC NEAR C, CsSelector:PTR
- push ax
- push ebx
-
- call FarCallGetCs
- mov ebx, CsSelector
- mov [ebx], ax
- pop ebx
- pop ax
- ret
-GetCsSelector ENDP
-
-;======================================================================
-; FarCallGetCs:
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; none
-;
-;======================================================================
-FarCallGetCs PROC FAR PRIVATE
-
- mov ax, ss:[esp + 4]
- retf
-
-FarCallGetCs ENDP
-
-;======================================================================
-; SetIdtr:
-;
-; In:
-; @param[in] IdtPtr Points to IDT table
-;
-; Out:
-; None
-;
-; Destroyed:
-; none
-;
-;======================================================================
-PUBLIC SetIdtr
-SetIdtr PROC NEAR C USES EBX, IdtPtr:PTR
- mov ebx, IdtPtr
- lidt fword ptr ss:[ebx]
- ret
-SetIdtr ENDP
-
-;======================================================================
-; GetIdtr:
-;
-; In:
-; @param[in] IdtPtr Points to IDT table
-;
-; Out:
-; None
-;
-; Destroyed:
-; none
-;
-;======================================================================
-PUBLIC GetIdtr
-GetIdtr PROC NEAR C USES EBX, IdtPtr:PTR
- mov ebx, IdtPtr
- sidt fword ptr ss:[ebx]
- ret
-GetIdtr ENDP
-
-;======================================================================
-; ExecuteWbinvdInstruction: Performs a wbinvd instruction.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-PUBLIC ExecuteWbinvdInstruction
-ExecuteWbinvdInstruction PROC NEAR C
- wbinvd ; Write back the cache tag RAMs
- ret
-ExecuteWbinvdInstruction ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt64.asm b/src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt64.asm
deleted file mode 100644
index 9c6974e702..0000000000
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt64.asm
+++ /dev/null
@@ -1,174 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa pre-memory miscellaneous support, including ap halt loop.
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: CPU
-; * @e \$Revision: 10071 $ @e \$Date: 2008-12-16 18:03:04 -0600 (Tue, 16 Dec 2008) $
-; */
-;*****************************************************************************
-;
-; Copyright (C) 2012 Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- text SEGMENT
-
-
-;======================================================================
-; ExecuteFinalHltInstruction: Performs a hlt instruction.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; eax, ebx, ecx, edx, esp
-;
-;======================================================================
-ExecuteFinalHltInstruction PROC PUBLIC
-@@:
- cli
- hlt
- jmp @B ;ExecuteHltInstruction
-ExecuteFinalHltInstruction ENDP
-
-;======================================================================
-; ExecuteHltInstruction: Performs a hlt instruction.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; eax, ebx, ecx, edx, esp
-;
-;======================================================================
-ExecuteHltInstruction PROC PUBLIC
- cli
- hlt
- ret
-ExecuteHltInstruction ENDP
-
-;======================================================================
-; NmiHandler: Simply performs an IRET.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-NmiHandler PROC PUBLIC
- iretq
-NmiHandler ENDP
-
-;======================================================================
-; GetCsSelector: Returns the current protected mode CS selector.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-GetCsSelector PROC PUBLIC
- ; This stub function is here to avoid compilation errors.
- ; At this time, there is no need to provide a 64 bit function.
- ret
-GetCsSelector ENDP
-
-;======================================================================
-; SetIdtr:
-;
-; In:
-; @param[in] IdtPtr Points to IDT table
-;
-; Out:
-; None
-;
-; Destroyed:
-; none
-;
-;======================================================================
-SetIdtr PROC PUBLIC
- ; This stub function is here to avoid compilation errors.
- ; At this time, there is no need to provide a 64 bit function.
- ret
-SetIdtr ENDP
-
-;======================================================================
-; GetIdtr:
-;
-; In:
-; @param[in] IdtPtr Points to IDT table
-;
-; Out:
-; None
-;
-; Destroyed:
-; none
-;
-;======================================================================
-GetIdtr PROC PUBLIC
- ; This stub function is here to avoid compilation errors.
- ; At this time, there is no need to provide a 64 bit function.
- ret
-GetIdtr ENDP
-
-;======================================================================
-; ExecuteWbinvdInstruction: Performs a wbinvd instruction.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-ExecuteWbinvdInstruction PROC PUBLIC
- wbinvd ; Write back the cache tag RAMs
- ret
-ExecuteWbinvdInstruction ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mu.asm b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mu.asm
deleted file mode 100644
index 61656df3e7..0000000000
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mu.asm
+++ /dev/null
@@ -1,497 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; $Workfile:: mu.asm $ $Revision:: 443#$ $Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
-; Description: Main memory controller system configuration for AGESA
-;
-;
-;*****************************************************************************
-;
-; Copyright (C) 2012 Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-;============================================================================
-
-
- .XLIST
- .LIST
-
- .686p
- .MODEL FLAT
- .CODE
- ASSUME FS: NOTHING
-
-; Define the calling convention used for the C library modules
-;@attention - This should be in a central include file
-CALLCONV EQU NEAR C
-
-
-;===============================================================================
-;memUOutPort:
-;
-; Do a 32 Bit IO Out operation using edx.
-; NOTE: This function will be obsolete in the future.
-;
-; In: Port - port number
-; Value - value to be written
-;
-; Out:
-;
-; All registers preserved.
-;===============================================================================
-MemUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD
- pushad
- mov edx,Port
- mov eax,Value
- out dx,al
- popad
- ret
-MemUOutPort ENDP
-
-
-;----------------------------------------------------------------------------
-; _SFENCE();
-;
-_SFENCE macro
- db 0Fh,0AEh,0F8h
- endm
-
-;----------------------------------------------------------------------------
-; _MFENCE();
-;
-_MFENCE macro
- db 0Fh,0AEh,0F0h
- endm
-
-;----------------------------------------------------------------------------
-; _EXECFENCE();
-;
-_EXECFENCE macro
- out 0EDh,al ;prevent speculative execution of following instructions
- endm
-
-;===============================================================================
-;MemUWriteCachelines:
-; Write a test pattern to DRAM
-;
-; In: Pattern - pointer to the write pattern
-; Address - Physical address to be read
-; ClCount - number of cachelines to be read
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUWriteCachelines PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD, ClCount:WORD
- pushad
- push ds
-
- mov eax,Address
- push ss
- pop ds
- xor edx,edx
- mov edx, DWORD PTR Pattern
- mov esi,edx
- mov edx,16
- _EXECFENCE
- xor ecx, ecx
- mov cx,ClCount
- shl ecx,2
- @@:
- db 66h, 0Fh,6Fh,06 ;MOVDQA xmm0,[esi]
- db 64h, 66h, 0Fh,0E7h,00 ;MOVNTDQ fs:[eax],xmm0 (xmm0 is 128 bits)
- add eax,edx
- add esi,edx
- loop @B
-
- pop ds
- popad
- ret
-MemUWriteCachelines ENDP
-
-;===============================================================================
-;MemUReadCachelines:
-;
-; Read a pattern of 72 bit times (per DQ), to test dram functionality. The
-;pattern is a stress pattern which exercises both ISI and crosstalk. The number
-;of cache lines to fill is dependent on DCT width mode and burstlength.
-;
-; In: Buffer - pointer to a buffer where read data will be stored
-; Address - Physical address to be read
-; ClCount - number of cachelines to be read
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUReadCachelines PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
-LOCAL Count:BYTE
- pushad
- ; First, issue continuous dummy reads to fill up the cache
- mov eax,Address
- .if (ClCount > 18)
- mov cx,ClCount
- shr cx,4
- mov Count,cl
- .while (Count != 0)
- push eax
- mov edi,eax
- add edi,128 ;bias value (to account for signed displacement)
- ;clflush opcode=0F AE /7
- mov esi,edi
- mov ebx,esi
- mov ecx,esi
- mov edx,esi
- add edi,4*64 ;TestAddr+4 cache lines
- add ebx,8*64 ;TestAddr+8 cache lines
- add ecx,12*64 ;TestAddr+12 cache lines
- add edx,16*64 ;TestAddr+16 cache lines
- sub edx,128
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- mov eax,fs:[edi] ;TestAddr+6 cache lines
- _MFENCE
- mov eax,fs:[edi+64] ;TestAddr+7 cache lines
- _MFENCE
- mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
- _MFENCE
- mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
- _MFENCE
- mov eax,fs:[ebx] ;TestAddr+10 cache lines
- _MFENCE
- mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
- _MFENCE
- mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
- _MFENCE
- mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
- _MFENCE
- mov eax,fs:[ecx] ;TestAddr+14 cache lines
- _MFENCE
- mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
- _MFENCE
- pop eax
- add eax,(16*64) ;Next 16CL
- dec Count
- .endw
- .else
- mov edi,eax
- add edi,128 ;bias value (to account for signed displacement)
- ;clflush opcode=0F AE /7
- mov esi,edi
- mov ebx,esi
- mov ecx,esi
- mov edx,esi
- add edi,4*64 ;TestAddr+4 cache lines
- add ebx,8*64 ;TestAddr+8 cache lines
- add ecx,12*64 ;TestAddr+12 cache lines
- add edx,16*64 ;TestAddr+16 cache lines
- sub edx,128
- .if(ClCount == 1)
- _MFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- .elseif(ClCount == 3)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- .elseif(ClCount == 6)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- .elseif(ClCount == 9)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- mov eax,fs:[edi] ;TestAddr+6 cache lines
- _MFENCE
- mov eax,fs:[edi+64] ;TestAddr+7 cache lines
- _MFENCE
- mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
- _MFENCE
- .elseif(ClCount == 18)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- mov eax,fs:[edi] ;TestAddr+6 cache lines
- _MFENCE
- mov eax,fs:[edi+64] ;TestAddr+7 cache lines
- _MFENCE
- mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
- _MFENCE
- mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
- _MFENCE
- mov eax,fs:[ebx] ;TestAddr+10 cache lines
- _MFENCE
- mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
- _MFENCE
- mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
- _MFENCE
- mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
- _MFENCE
- mov eax,fs:[ecx] ;TestAddr+14 cache lines
- _MFENCE
- mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
- _MFENCE
- mov eax,fs:[edx] ;TestAddr+16 cache lines
- _MFENCE
- mov eax,fs:[edx+64] ;TestAddr+17 cache lines
- _MFENCE
- .endif
- .endif
- _MFENCE
-
- ; Then, copy data to buffer
- mov esi,Address
- xor edx,edx
- mov edx,DWORD PTR Buffer
- mov edi,edx
- xor ecx, ecx
- mov cx,ClCount
- shl ecx,6
- @@:
- mov al,fs:[esi]
- mov ss:[edi],al
- inc esi
- inc edi
- loop @B
-
- popad
- ret
-MemUReadCachelines ENDP
-
-;===============================================================================
-;MemUDummyCLRead:
-;
-; Perform a single cache line read from a given physical address.
-;
-; In: Address - Physical address to be read
-; ClCount - number of cachelines to be read
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUDummyCLRead PROC CALLCONV PUBLIC Address:DWORD
- _SFENCE
- pushad
- mov eax,Address
- mov dl,fs:[eax]
- popad
- ret
-MemUDummyCLRead ENDP
-
-;===============================================================================
-;MemUFlushPattern:
-;
-; Flush a pattern of 72 bit times (per DQ) from cache. This procedure is used
-;to ensure cache miss on the next read training.
-;
-; In: Address - Physical address to be flushed
-; ClCount - number of cachelines to be flushed
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUFlushPattern PROC CALLCONV PUBLIC Address:DWORD, ClCount:WORD
- pushad
- mov edi,Address
- movzx ecx,ClCount
- @@:
- _MFENCE ; Force strong ordering of clflush
- db 64h,0Fh,0AEh,3Fh ; MemUClFlush fs:[edi]
- _MFENCE
- add edi,64
- loop @B
- popad
- ret
-MemUFlushPattern ENDP
-
-
-;===============================================================================
-;MemUGetWrLvNblErr:
-; Read ClCount number of cachelines then return the bitmap that indicates
-; the write leveling result of each byte lane.
-;
-; IN: ErrBitmap - pointer to a DWORD that will be assigned with WL result
-; Address - Physical address to be sampled
-; ClCount - number of cachelines to be read
-;
-; OUT: ErrBitmap - WL result
-;
-;All registers preserved
-;===============================================================================
-MemUGetWrLvNblErr PROC CALLCONV PUBLIC ErrBitmap:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
-LOCAL ZeroCount[32]:WORD
-
- pushad
- mov esi,Address
- _EXECFENCE
- ;Cache fill
- movzx ecx,ClCount
- @@:
- mov eax,fs:[esi]
- add esi,64
- loop @B
- _MFENCE
-
- ; Then, count the number of 0's
- ;push es
- ;push ss
- ;pop es
- lea edi,ZeroCount
- mov cx,SIZEOF ZeroCount
- mov al,0
- rep stosb
- ;pop es
-
- mov esi,Address
- lea edi,ZeroCount
- mov cx,ClCount
- shl cx,6
- .while(cx > 0)
- mov al,fs:[esi]
- test al,00Fh ;check lower nibble
- .if(ZERO?)
- inc WORD PTR [edi]
- .endif
- add edi,2
- test al,0F0h ;check upper nibble
- .if(ZERO?)
- inc WORD PTR [edi]
- .endif
- add edi,2
- inc esi
- dec cx
- test cx,07h
- .if(ZERO?)
- sub edi,(16*2)
- sub cx,8
- add esi,8
- .endif
- .endw
-
- ; Then, average and compress data to error bits
- lea esi,ZeroCount
- mov dx,ClCount
- shl dx,1
- xor eax,eax
- xor ecx,ecx
- mov cl,0
- .while(cl<16)
- .if(WORD PTR [esi] < dx)
- bts eax,ecx
- .endif
- add esi,2
- inc cl
- .endw
- xor edx,edx
- mov dx,WORD PTR ErrBitmap
- mov [edx], ax
-
- popad
- ret
-MemUGetWrLvNblErr ENDP
-
-;===============================================================================
-;AlignPointerTo16Byte:
-; Modifies BufferPtr to be 16 byte aligned
-;
-; In: BufferPtrPtr - Pointer to buffer pointer
-; Out: BufferPtrPtr - Pointer to buffer pointer that has been 16 byte aligned
-;
-;All registers preserved.
-;===============================================================================
-AlignPointerTo16Byte PROC CALLCONV PUBLIC BufferPtrPtr:NEAR PTR DWORD
- push edx
- push eax
- mov edx, BufferPtrPtr
- mov eax, [edx]
- add eax, 16
- and ax, 0FFF0h
- mov [edx], eax
- pop eax
- pop edx
- ret
-AlignPointerTo16Byte ENDP
-
-;===============================================================================
-;MemUMFenceInstr:
-; Serialize instruction
-;
-; In:
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUMFenceInstr PROC CALLCONV PUBLIC
- _MFENCE
- ret
-MemUMFenceInstr ENDP
-
- END
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mru.asm b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mru.asm
deleted file mode 100644
index 5520d8eafa..0000000000
--- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mru.asm
+++ /dev/null
@@ -1,187 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; $Workfile:: mu.asm $ $Revision:: 443#$ $Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
-; Description: Main memory controller system configuration for AGESA DDR 2
-;
-;
-;*****************************************************************************
-;
-; Copyright (C) 2012 Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-;============================================================================
-
-
- .XLIST
- .LIST
- .686p
- .MODEL FLAT
- .CODE
- ASSUME FS: NOTHING
-
-
-; Define the calling convention used for the C library modules
-;@attention - This should be in a central include file
-CALLCONV EQU NEAR C
-
-
-;===============================================================================
-;MemRecUOutPort:
-;
-; Do a 32 Bit IO Out operation using edx.
-; NOTE: This function will be obsolete in the future.
-;
-; In: Port - port number
-; Value - value to be written to port
-;
-; Out:
-;
-;All registers preserved except for "Out:"
-;===============================================================================
-MemRecUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD
- pushad
- mov edx,Port
- mov eax,Value
- out dx,al
- popad
- ret
-MemRecUOutPort ENDP
-
-
-
-;----------------------------------------------------------------------------
-; _MFENCE();
-;
-_MFENCE macro
- db 0Fh,0AEh,0F0h
- endm
-
-;----------------------------------------------------------------------------
-; _EXECFENCE();
-;
-_EXECFENCE macro
- out 0EDh,al ;prevent speculative execution of following instructions
- endm
-
-;===============================================================================
-;MemRecUWrite1CL:
-;
-; Write data from buffer to a system address
-;
-; In: Address - System address to read from
-; Pattern - pointer pattern.
-;
-; Out:
-;
-;All registers preserved except for "Out:"
-;===============================================================================
-MemRecUWrite1CL PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD
- pushad
- push ds
-
- mov eax,Address
- push ss
- pop ds
- xor edx,edx
- mov edx, DWORD PTR Pattern
- mov esi,edx
- mov edx,16
- _EXECFENCE
- mov ecx,4
- @@:
- db 66h,0Fh,6Fh,06 ;MOVDQA xmm0,[esi]
- db 64h,66h,0Fh,0E7h,00 ;MOVNTDQ fs:[eax],xmm0 (xmm0 is 128 bits)
- add eax,edx
- add esi,edx
- loop @B
-
- pop ds
- popad
- ret
-MemRecUWrite1CL ENDP
-
-;===============================================================================
-;MemRecURead1CL:
-;
-; Read one cacheline to buffer
-;
-; In: Buffer - pointer buffer.
-; : Address - System address to read from
-;
-; Out:
-;
-;All registers preserved except for "Out:"
-;===============================================================================
-MemRecURead1CL PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD
-
- pushad
-
- mov esi,Address
- xor edx,edx
- mov edx,DWORD PTR Buffer
- mov edi,edx
- mov ecx,64
- @@:
- mov al,fs:[esi]
- mov ss:[edi],al
- inc esi
- inc edi
- loop @B
-
- popad
- ret
-MemRecURead1CL ENDP
-
-
-;===============================================================================
-;MemRecUFlushPattern:
-;
-; Flush one cache line
-;
-; In: Address - System address [31:0]
-; Out:
-;
-;All registers preserved except for "Out:"
-;===============================================================================
-MemRecUFlushPattern PROC CALLCONV PUBLIC Address:DWORD
- pushad
- mov eax,Address
- _EXECFENCE
- ;clflush fs:[eax]
- db 064h ;access relative to FS BASE prefix
- db 00Fh ;opcode
- db 0AEh ;opcode
- db 038h ;eax indirect addressing
- _MFENCE
- popad
- ret
-MemRecUFlushPattern ENDP
-
-
-
- END
-
diff --git a/src/vendorcode/amd/agesa/f15/cpcarmac.inc b/src/vendorcode/amd/agesa/f15/cpcarmac.inc
deleted file mode 100644
index 8947491717..0000000000
--- a/src/vendorcode/amd/agesa/f15/cpcarmac.inc
+++ /dev/null
@@ -1,457 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; Workfile: cpcarmac.inc $Revision:: 50472 $ $Date:: 2011-04-11 01:57:56 -0600 (Mon, 11 Apr 2011) $
-;
-; Description: Code to setup and break down cache-as-stack
-;
-;*****************************************************************************
-;
-; Copyright (C) 2012 Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- .XLIST
- INCLUDE cpcar.inc
- .LIST
- .586P
- .mmx
-
-;======================================================================
-; AMD_ENABLE_STACK: Setup a stack
-;
-; In:
-; EBX = Return address (preserved)
-;
-; Out:
-; SS:ESP - Our new private stack location
-;
-; EAX = AGESA_STATUS
-; EDX = Return status code if EAX contains a return code of higher
-; severity than AGESA_SUCCESS
-; ECX = Stack size in bytes
-;
-; Requirements:
-; * This routine presently is limited to a max of 64 processor cores
-; Preserved:
-; ebx ebp
-; Destroyed:
-; eax, ecx, edx, edi, esi, ds, es, ss, esp
-; mmx0, mmx1, mmx5
-;
-; Description:
-; Fixed MTRR address allocation to cores:
-; The BSP gets 64K of stack, Core0 of each node gets 16K of stack, all other cores get 4K.
-; There is a max of 1 BSP, 7 core0s and 56 other cores.
-; Although each core has it's own cache storage, they share the address space. Each core must
-; be assigned a private and unique address space for its stack. To support legacy systems,
-; the stack needs to be within the legacy address space (1st 1Meg). Room must also be reserved
-; for the other legacy elements (Interrupt vectors, BIOS ROM, video buffer, etc.)
-;
-; 80000h 40000h 00000h
-; +----------+----------+----------+----------+----------+----------+----------+----------+
-; 64K | | | | | | | | | 64K ea
-; ea +----------+----------+----------+----------+----------+----------+----------+----------+
-; | MTRR 0000_0250 MTRRfix64K_00000 |
-; +----------+----------+----------+----------+----------+----------+----------+----------+
-; | 7 , 6 | 5 , 4 | 3 , 2 | 1 , 0 | 0 | | | | <-node
-; |7..1,7..1 |7..1,7..1 |7..1,7..1 |7..1,7..1 | 0 | | | | <-core
-; +----------+----------+----------+----------+----------+----------+----------+----------+
-;
-; C0000h B0000h A0000h 90000h 80000h
-; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
-;16K | | | | | | | | | | | | | | | | |
-; ea +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
-; | MTRR 0259 MTRRfix16K_A0000 | MTRR 0258 MTRRfix16K_80000 |
-; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
-; | > Dis|play B|uffer | < | | | | | 7 | 6 | 5 | 4 | 3 | 2 | 1 | | <-node
-; | > T| e m |p o r |a r y | B u |f f e |r A |r e a<| 0 | 0 | 0 | 0 | 0 | 0 | 0 | | <-core
-; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
-;
-; E0000h D0000h C0000h
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; 4K | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
-; ea +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | 026B MTRRfix4K_D8000 | 026A MTRRfix4K_D0000 | 0269 MTRRfix4K_C8000 | 0268 MTRRfix4K_C0000 |
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | | | | | | | | | | | | | | | | | >| V| I| D| E| O| |B |I |O |S | |A |r |e |a<|
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-;
-; 100000h F0000h E0000h
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | 026F MTRRfix4K_F8000 | 026E MTRRfix4K_F0000 | 026D MTRRfix4K_E8000 | 026C MTRRfix4K_E0000 |
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< |
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-;======================================================================
-AMD_ENABLE_STACK MACRO
- local AmdEnableStackExit
-
-; Note that SS:ESP will be default stack. Note that this stack
-; routine will not be used after memory has been initialized. Because
-; of its limited lifetime, it will not conflict with typical PCI devices.
- movd mm0, ebx ; Put return address in a safe place
- movd mm1, ebp ; Save some other user registers
-
- ; get node id and core id of current executing core
- GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
- ; Note: ESI[31:24] are used for flags: Unrecognized Family, Is_Primary core, Stack already established
-
- ; If we detected an unknown processor family or core combination, return AGESA_FATAL.
- .if (esi & (1 SHL FLAG_UNKNOWN_FAMILY))
- mov edx, CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY
- mov eax, AGESA_FATAL
- jmp AmdEnableStackExit
- .elseif (esi & (1 SHL FLAG_CORE_NOT_IDENTIFIED))
- mov edx, CPU_EVENT_CORE_NOT_IDENTIFIED
- mov eax, AGESA_FATAL
- jmp AmdEnableStackExit
- .endif
-
- ; determine if stack is already enabled. We are using the DefType MSR for this determination.
- ; It is =0 after reset; CAR setup sets it to enable the MTRRs
- mov eax, cr0 ; Is cache enabled? (CD or NW bit set)
- CR0_MASK TEXTEQU %((1 SHL CR0_CD) OR (1 SHL CR0_NW))
- .if (!(eax & CR0_MASK))
- mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF
- _RDMSR ; Are either of the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)
- MSR_MASK TEXTEQU %((1 SHL MTRR_DEF_TYPE_EN)+(1 SHL MTRR_DEF_TYPE_FIX_EN))
- .if (eax & MSR_MASK)
- bts esi, FLAG_STACK_REENTRY ; indicate stack has already been initialized
- .endif
- .endif
-
- ; Set node to map the first 16MB to node 0; 0000_0000 to 00FF_FFFF as DRAM
- mov ebx, esi ; Get my Node/Core info
- xor bl, bl
- shl bh, 3 ; Isolate my node#, match alignment for PCI Dev#
- mov eax, 8000C144h ; D18F1x44:DRAM Base/Limit; N is Base, N+4 is Limit
- add ah, bh
- mov ebx, eax ; Save PCI address for Base/Limit pair
-
- mov dx, 0CF8h
- out dx, eax
- add dx, 4
- xor eax, eax ; Least Significant bit is AD24 so 0 sets mask of 00FF_FFFF (16MB)
- out dx, eax ; DRAM Limit = node0, no interleave
-
- mov eax, ebx
- sub eax, 4 ; Now point to the Base register
- mov dx, 0CF8h
- out dx, eax
- add dx, 4
- mov eax, 00000003h ; Set the read and write enable bits
- out dx, eax ; DRAM Base = 0x0000, R/W
-
- AMD_ENABLE_STACK_FAMILY_HOOK
-
- ; Init CPU MSRs for our init routines
- mov ecx, MTRR_SYS_CFG ; SYS_CFG
- _RDMSR
- bts eax, MTRR_FIX_DRAM_MOD_EN ; Turn on modification enable bit
- _WRMSR
-
- mov eax, esi
- bt eax, FLAG_STACK_REENTRY ; Is this a 2nd entry?
- .if (!carry?) ; On a re-entry, do not clear MTRRs or reset TOM; just reset the stack SS:ESP
- bt eax, FLAG_IS_PRIMARY ; Is this core the primary in a compute unit?
- .if (carry?) ; Families using shared groups do not need to clear the MTRRs since that is done at power-on reset
- ; Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores
- ; Clear all variable and Fixed MTRRs for non-shared cores
- mov ecx, AMD_MTRR_VARIABLE_BASE0
- xor eax, eax
- xor edx, edx
- .while (cl != 10h) ; Variable MTRRphysBase[n] and MTRRphysMask[n]
- _WRMSR
- inc cl
- .endw
- mov cx, AMD_MTRR_FIX64k_00000 ; MSR:0000_0250
- _WRMSR
- mov cx, AMD_MTRR_FIX16k_80000 ; MSR:0000_0258
- _WRMSR
- mov cx, AMD_MTRR_FIX16k_A0000 ; MSR:0000_0259
- _WRMSR
- mov cx, AMD_MTRR_FIX4k_C0000 ; Fixed 4Ks: MTRRfix4K_C0000 to MTRRfix4K_F8000
- .while (cl != 70h)
- _WRMSR
- inc cl
- .endw
-
- ; Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init.
- ; - not strictly needed since the FixedMTRRs take presedence.
- mov eax, (16 * 1024 * 1024)
- mov ecx, TOP_MEM ; MSR:C001_001A
- _WRMSR
- .endif ; End Is_Primary
- .endif ; End Stack_ReEntry
-
- ; Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores
- xor eax, eax
- xor edx, edx
- mov ecx, IORR_BASE ; MSR:C001_0016 - 0019
- .while (cl != 1Ah)
- _WRMSR
- inc cl
- .endw
- mov ecx, TOP_MEM2 ; MSR:C001_001D
- _WRMSR
-
- ; setup MTRRs for stacks
- ; A speculative read can be generated by a speculative fetch mis-aligned in a code zone
- ; or due to a data zone being interpreted as code. When a speculative read occurs outside a
- ; controlled region (intentionally used by software), it could cause an unwanted cache eviction.
- ; To prevent speculative reads from causing an eviction, the unused cache ranges are set
- ; to UC type. Only the actively used regions (stack, heap) are reflected in the MTRRs.
- ; Note: some core stack regions will share an MTRR since the control granularity is much
- ; larger than the allocated stack zone. The allocation algorithm must account for this 'extra'
- ; space covered by the MTRR when parseling out cache space for the various uses. In some cases
- ; this could reduce the amount of EXE cache available to a core. see cpuCacheInit.c
- ;
- ; Outcome of this block is that: (Note the MTRR map at the top of the file)
- ; ebp - start address of stack block
- ; ebx - [31:16] - MTRR MSR address
- ; - [15:8] - slot# in MTRR register
- ; - [7:0] - block size in #4K blocks
- ; review: ESI[31:24]=Flags; SI[15,8]= Node#; SI[7,0]= core# (relative to node)
- ;
-
- mov eax, esi ; Load Flags, node, core
- .if (al == 0) ; Is a core 0?
- .if (ah == 0) ; Is Node 0? (BSP)
- ; Is BSP, assign a 64K stack; for F10/F12, foce to a 32K stack
- mov ebx, ((AMD_MTRR_FIX64k_00000 SHL 16) + (3 SHL 8) + (BSP_STACK_SIZE_64K / 1000h))
- bt eax, FLAG_FORCE_32K_STACK
- .if (carry?)
- mov ebx, ((AMD_MTRR_FIX64k_00000 SHL 16) + (3 SHL 8) + (BSP_STACK_SIZE_32K / 1000h))
- .endif
- mov ebp, BSP_STACK_BASE_ADDR
- .else ; node 1 to 7, core0
- ; Is a Core0 of secondary node, assign 16K stacks
- mov bx, AMD_MTRR_FIX16k_80000
- shl ebx, 16 ;
- mov bh, ah ; Node# is used as slot#
- mov bl, (CORE0_STACK_SIZE / 1000h)
- mov al, ah ; Base = (Node# * Size);
- mul bl ;
- movzx eax, ax ;
- shl eax, 12 ; Expand back to full byte count (* 4K)
- add eax, CORE0_STACK_BASE_ADDR
- mov ebp, eax
- .endif
- .else ;core 1 thru core 7
- ; Is core 1-7 of any node, assign 4K stacks
- mov al, 8 ; CoreIndex = ( (Node# * 8) ...
- mul ah ;
- mov bx, si ;
- add al, bl ; ... + Core#);
-
- mov bx, AMD_MTRR_FIX64k_00000
- shl ebx, 16 ;
- mov bh, al ; Slot# = (CoreIndex / 16) + 4;
- shr bh, 4 ;
- add bh, 4 ;
- mov bl, (CORE1_STACK_SIZE / 1000h)
-
- mul bl ; Base = ( (CoreIndex * Size) ...
- movzx eax, ax ;
- shl eax, 12 ; Expand back to full byte count (* 4K)
- add eax, CORE1_STACK_BASE_ADDR ; ... + Base_Addr);
- mov ebp, eax
- .endif
-
- ; Now set the MTRR. Add this to already existing settings (don't clear any MTRR)
- mov edi, WB_DRAM_TYPE ; Load Cache type in 1st slot
- mov cl, bh ; ShiftCount = ((slot# ...
- and cl, 03h ; ... % 4) ...
- shl cl, 3 ; ... * 8);
- shl edi, cl ; Cache type is now in correct position
- ror ebx, 16 ; Get the MTRR address
- movzx ecx, bx ;
- rol ebx, 16 ; Put slot# & size back in BX
- _RDMSR ; Read-modify-write the MSR
- .if (bh < 4) ; Is value in lower or upper half of MSR?
- or eax, edi ;
- .else ;
- or edx, edi ;
- .endif ;
- _WRMSR ;
-
- ; Enable MTRR defaults as UC type
- mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF
- _RDMSR ; Read-modify-write the MSR
- bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn
- bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn
- _WRMSR
-
- ; Close the modification window on the Fixed MTRRs
- mov ecx, MTRR_SYS_CFG ; MSR:0C001_0010
- _RDMSR
- bts eax, MTRR_FIX_DRAM_EN ; MtrrFixDramEn
- bts eax, MTRR_VAR_DRAM_EN ; variable MTRR enable bit
- btr eax, MTRR_FIX_DRAM_MOD_EN ; Turn off modification enable bit
- _WRMSR
-
- ; Enable caching in CR0
- mov eax, CR0 ; Enable WT/WB cache
- btr eax, CR0_PG ; Make sure paging is disabled
- btr eax, CR0_CD ; Clear CR0 NW and CD
- btr eax, CR0_NW
- mov CR0, eax
-
- ; Use the Stack Base & size to calculate SS and ESP values
- ; review:
- ; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
- ; ebp - start address of stack block
- ; ebx - [31:16] - MTRR MSR address
- ; - [15:8] - slot# in MTRR register
- ; - [7:0] - block size in #4K blocks
- ;
- mov esp, ebp ; Initialize the stack pointer
- mov edi, esp ; Copy the stack start to edi
- movzx bx, bl
- movzx ebx, bx ; Clear upper ebx, don't need MSR addr anymore
- shl ebx, 12 ; Make size full byte count (* 4K)
- add esp, ebx ; Set the Stack Pointer as full linear address
- sub esp, 4
- ;
- ; review:
- ; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
- ; edi - 32b start address of stack block
- ; ebx - size of stack block
- ; esp - 32b linear stack pointer
- ;
-
- ; Determine mode for SS base;
- mov ecx, CR0 ; Check for 32-bit protect mode
- bt ecx, CR0_PE ;
- .if (!carry?) ; PE=0 means real mode
- mov cx, cs ;
- .if (cx >= 0D000h) ; If CS >= D000, it's a real mode segment. PM selector would be 08-> 1000
- ; alter SS:ESP for 16b Real Mode:
- mov eax, edi ;
- shr eax, 4 ; Create a Real Mode segment for ss, ds, es
- mov ss, ax ;
- mov ds, ax ;
- mov es, ax ;
- shl eax, 4 ;
- sub edi, eax ; Adjust the clearing pointer for Seg:Offset mode
- mov esp, ebx ; Make SP an offset from SS
- sub esp, 4 ;
- .endif ; endif
- ; else
- ; Default is to use Protected 32b Mode
- .endif
- ;
- ; Clear The Stack
- ; Now that we have set the location and the MTRRs, initialize the cache by
- ; reading then writing to zero all of the stack area.
- ; review:
- ; ss - Stack base
- ; esp - stack pointer
- ; ebx - size of stack block
- ; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
- ; edi - address of start of stack block
- ;
- shr ebx, 2 ;
- mov cx, bx ; set cx for size count of DWORDS
- ; Check our flags - Don't clear an existing stack
- .if ( !(esi & (1 SHL FLAG_STACK_REENTRY)) )
- cld
- mov esi, edi
- rep lods DWORD PTR [esi] ; Pre-load the range
- xor eax, eax
- mov cx, bx
- mov esi, edi ; Preserve base for push on stack
- rep stos DWORD PTR [edi] ; Clear the range
- mov DWORD PTR [esp], 0ABCDDCBAh ; Put marker in top stack dword
- shl ebx, 2 ; Put stack size and base
- push ebx ; in top of stack
- push esi
-
- mov ecx, ebx ; Return size of stack in bytes
- mov eax, AGESA_SUCCESS ; eax = AGESA_SUCCESS : no error return code
- .else
- movzx ecx, cx
- shl ecx, 2 ; Return size of stack, in bytes
- mov edx, CPU_EVENT_STACK_REENTRY
- mov eax, AGESA_WARNING ; eax = AGESA_WARNING (Stack has already been set up)
- .endif
-
-AmdEnableStackExit:
- movd ebx, mm0 ; Restore return address
- movd ebp, mm1
-ENDM
-
-;======================================================================
-; AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine
-; should only be executed on the BSP
-;
-; In:
-; none
-;
-; Out:
-; EAX = AGESA_SUCCESS
-;
-; Preserved:
-; ebx
-; Destroyed:
-; eax, ecx, edx, esp, mmx5
-;======================================================================
-AMD_DISABLE_STACK MACRO
-
- mov esp, ebx ; Save return address
-
- ; get node/core/flags of current executing core
- GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
-
- ; Turn on modification enable bit
- mov ecx, MTRR_SYS_CFG ; MSR:C001_0010
- _RDMSR
- bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable modifications
- _WRMSR
-
- ; Set lower 640K MTRRs for Write-Back memory caching
- mov ecx, AMD_MTRR_FIX64k_00000
- mov eax, 1E1E1E1Eh
- mov edx, eax
- _WRMSR ; 0 - 512K = WB Mem
- mov ecx, AMD_MTRR_FIX16k_80000
- _WRMSR ; 512K - 640K = WB Mem
-
- ; Turn off modification enable bit
- mov ecx, MTRR_SYS_CFG ; MSR:C001_0010
- _RDMSR
- btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable modification
- _WRMSR
-
- AMD_DISABLE_STACK_FAMILY_HOOK ; Re-Enable 'normal' cache operations
-
- mov ebx, esp ; restore return address (ebx)
- xor eax, eax
-
-ENDM
diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/PlatformMemoryConfiguration.inc b/src/vendorcode/amd/agesa/f15tn/Legacy/PlatformMemoryConfiguration.inc
deleted file mode 100644
index 0f32cc6397..0000000000
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/PlatformMemoryConfiguration.inc
+++ /dev/null
@@ -1,688 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * AMD Platform Specific Memory Configuration
-; *
-; * Contains AMD AGESA Memory Configuration Override Interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
-;
-; ****************************************************************************
-; *
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; *
-; **************************************************************************
-IFNDEF PSO_ENTRY
- PSO_ENTRY TEXTEQU <UINT8>; < Platform Configuration Table Entry
-ENDIF
-; *****************************************************************************************
-; *
-; * PLATFORM SPECIFIC MEMORY DEFINITIONS
-; *
-; *****************************************************************************************
-; */
-;
-; < Memory Speed and DIMM Population Masks
-;
-; < DDR Speed Masks
-;
-ANY_SPEED EQU 0FFFFFFFFh
-DDR400 EQU ( 1 SHL (DDR400_FREQUENCY / 66))
-DDR533 EQU ( 1 SHL (DDR533_FREQUENCY / 66))
-DDR667 EQU ( 1 SHL (DDR667_FREQUENCY / 66))
-DDR800 EQU ( 1 SHL (DDR800_FREQUENCY / 66))
-DDR1066 EQU ( 1 SHL (DDR1066_FREQUENCY / 66))
-DDR1333 EQU ( 1 SHL (DDR1333_FREQUENCY / 66))
-DDR1600 EQU ( 1 SHL (DDR1600_FREQUENCY / 66))
-DDR1866 EQU ( 1 SHL (DDR1866_FREQUENCY / 66))
-DDR2133 EQU ( 1 SHL (DDR2133_FREQUENCY / 66))
-DDR2400 EQU ( 1 SHL (DDR2400_FREQUENCY / 66))
-; <
-; < DIMM POPULATION MASKS
-;
-ANY_ EQU 0FFh
-SR_DIMM0 EQU 0001h
-SR_DIMM1 EQU 0010h
-SR_DIMM2 EQU 0100h
-SR_DIMM3 EQU 1000h
-DR_DIMM0 EQU 0002h
-DR_DIMM1 EQU 0020h
-DR_DIMM2 EQU 0200h
-DR_DIMM3 EQU 2000h
-QR_DIMM0 EQU 0004h
-QR_DIMM1 EQU 0040h
-QR_DIMM2 EQU 0400h
-QR_DIMM3 EQU 4000h
-LR_DIMM0 EQU 0001h
-LR_DIMM1 EQU 0010h
-LR_DIMM2 EQU 0100h
-LR_DIMM3 EQU 1000h
-ANY_DIMM0 EQU 000Fh
-ANY_DIMM1 EQU 00F0h
-ANY_DIMM2 EQU 0F00h
-ANY_DIMM3 EQU 0F000h
-; <
-; < CS POPULATION MASKS
-;
-CS_ANY_ EQU 0FFh
-CS0_ EQU 01h
-CS1_ EQU 02h
-CS2_ EQU 04h
-CS3_ EQU 08h
-CS4_ EQU 10h
-CS5_ EQU 20h
-CS6_ EQU 40h
-CS7_ EQU 80h
-;
-; Number of Dimms
-;
-ANY_NUM EQU 0FFh
-NO_DIMM EQU 00h
-ONE_DIMM EQU 01h
-TWO_DIMM EQU 02h
-THREE_DIMM EQU 04h
-FOUR_DIMM EQU 08h
-;
-; DIMM VOLTAGE MASK
-;
-VOLT_ANY_ EQU 0FFh
-VOLT1_5_ EQU 01h
-VOLT1_35_ EQU 02h
-VOLT1_25_ EQU 04h
-;
-; NOT APPLICIABLE
-;
-NA_ EQU 00h
-; *****************************************************************************************
-; *
-; * Platform Specific Override Definitions for Socket, Channel and Dimm
-; * This indicates where a platform override will be applied.
-; *
-; *****************************************************************************************
-;
-; SOCKET MASKS
-;
-ANY_SOCKET EQU 0FFh
-SOCKET0 EQU 01h
-SOCKET1 EQU 02h
-SOCKET2 EQU 04h
-SOCKET3 EQU 08h
-SOCKET4 EQU 10h
-SOCKET5 EQU 20h
-SOCKET6 EQU 40h
-SOCKET7 EQU 80h
-;
-; CHANNEL MASKS
-;
-ANY_CHANNEL EQU 0FFh
-CHANNEL_A EQU 01h
-CHANNEL_B EQU 02h
-CHANNEL_C EQU 04h
-CHANNEL_D EQU 08h
-;
-; DIMM MASKS
-;
-ALL_DIMMS EQU 0FFh
-DIMM0 EQU 01h
-DIMM1 EQU 02h
-DIMM2 EQU 04h
-DIMM3 EQU 08h
-;
-; REGISTER ACCESS MASKS
-;
-ACCESS_NB0 EQU 0h
-ACCESS_NB1 EQU 01h
-ACCESS_NB2 EQU 02h
-ACCESS_NB3 EQU 03h
-ACCESS_NB4 EQU 04h
-ACCESS_PHY EQU 05h
-ACCESS_DCT_XT EQU 06h
-; *****************************************************************************************
-; *
-; * Platform Specific Overriding Table Definitions
-; *
-; *****************************************************************************************
-PSO_END EQU 0 ; < Table End
-PSO_CKE_TRI EQU 1 ; < CKE Tristate Map
-PSO_ODT_TRI EQU 2 ; < ODT Tristate Map
-PSO_CS_TRI EQU 3 ; < CS Tristate Map
-PSO_MAX_DIMMS EQU 4 ; < Max Dimms per channel
-PSO_CLK_SPEED EQU 5 ; < Clock Speed
-PSO_DIMM_TYPE EQU 6 ; < Dimm Type
-PSO_MEMCLK_DIS EQU 7 ; < MEMCLK Disable Map
-PSO_MAX_CHNLS EQU 8 ; < Max Channels per Socket
-PSO_BUS_SPEED EQU 9 ; < Max Memory Bus Speed
-PSO_MAX_CHIPSELS EQU 10 ; < Max Chipsel per Channel
-PSO_MEM_TECH EQU 11 ; < Channel Memory Type
-PSO_WL_SEED EQU 12 ; < DDR3 Write Levelization Seed delay
-PSO_RXEN_SEED EQU 13 ; < Hardwared based RxEn seed
-PSO_NO_LRDIMM_CS67_ROUTING EQU 14 ; < CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
-PSO_SOLDERED_DOWN_SODIMM_TYPE EQU 15 ; < Soldered down SODIMM type
-PSO_LVDIMM_VOLT1_5_SUPPORT EQU 16 ; < Force LvDimm voltage to 1.5V
-PSO_MIN_RD_WR_DATAEYE_WIDTH EQU 17 ; < Min RD/WR dataeye width
-PSO_CPU_FAMILY_TO_OVERRIDE EQU 18 ; < CPU family signature to tell following PSO macros are CPU family dependent
-PSO_MAX_SOLDERED_DOWN_DIMMS EQU 19 ; < Max Soldered-down Dimms per channel
-PSO_MEMORY_POWER_POLICY EQU 20 ; < Memory power policy override
-; **********************************
-; * CONDITIONAL PSO SPECIFIC ENTRIES
-; **********************************
-; Condition Types
-CONDITIONAL_PSO_MIN EQU 100 ; < Start of Conditional Entry Types
-PSO_CONDITION_AND EQU 100 ; < And Block - Start of Conditional block
-PSO_CONDITION_LOC EQU 101 ; < Location - Specify Socket, Channel, Dimms to be affected
-PSO_CONDITION_SPD EQU 102 ; < SPD - Specify a specific SPD value on a Dimm on the channel
-PSO_CONDITION_REG EQU 103 ; Reserved
-PSO_CONDITION_MAX EQU 103 ; < End Of Condition Entry Types
-; Action Types
-PSO_ACTION_MIN EQU 120 ; < Start of Action Entry Types
-PSO_ACTION_ODT EQU 120 ; < ODT values to override
-PSO_ACTION_ADDRTMG EQU 121 ; < Address/Timing values to override
-PSO_ACTION_ODCCONTROL EQU 122 ; < ODC Control values to override
-PSO_ACTION_SLEWRATE EQU 123 ; < Slew Rate value to override
-PSO_ACTION_REG EQU 124 ; Reserved
-PSO_ACTION_SPEEDLIMIT EQU 125 ; < Memory Bus speed Limit based on configuration
-PSO_ACTION_MAX EQU 125 ; < End of Action Entry Types
-CONDITIONAL_PSO_MAX EQU 139 ; < End of Conditional Entry Types
-; **********************************
-; * TABLE DRIVEN PSO SPECIFIC ENTRIES
-; **********************************
-; Condition descriptor
-PSO_TBLDRV_CONFIG EQU 200 ; < Configuration Descriptor
-
-; Overriding entry types
-PSO_TBLDRV_START EQU 210 ; < Start of Table Driven Overriding Entry Types
-PSO_TBLDRV_SPEEDLIMIT EQU 210 ; < Speed Limit
-PSO_TBLDRV_ODT_RTTNOM EQU 211 ; < RttNom
-PSO_TBLDRV_ODT_RTTWR EQU 212 ; < RttWr
-PSO_TBLDRV_ODTPATTERN EQU 213 ; < Odt Patterns
-PSO_TBLDRV_ADDRTMG EQU 214 ; < Address/Timing values
-PSO_TBLDRV_ODCCTRL EQU 215 ; < ODC Control values
-PSO_TBLDRV_SLOWACCMODE EQU 216 ; < Slow Access Mode
-PSO_TBLDRV_MR0_CL EQU 217 ; < MR0[CL]
-PSO_TBLDRV_MR0_WR EQU 218 ; < MR0[WR]
-PSO_TBLDRV_RC2_IBT EQU 219 ; < RC2[IBT]
-PSO_TBLDRV_RC10_OPSPEED EQU 220 ; < RC10[Opearting Speed]
-PSO_TBLDRV_LRDIMM_IBT EQU 221 ; < LrDIMM IBT
-;del PSO_TBLDRV_2D_TRAINING EQU 222 ; < 2D training
-PSO_TBLDRV_INVALID_TYPE EQU 223 ; < Invalid Type
-PSO_TBLDRV_END EQU 223 ; < End of Table Driven Overriding Entry Types
-
-
-; *****************************************************************************************
-; *
-; * CONDITIONAL OVERRIDE TABLE MACROS
-; *
-; *****************************************************************************************
-CPU_FAMILY_TO_OVERRIDE MACRO CpuFamilyRevision:REQ
- DB PSO_CPU_FAMILY_TO_OVERRIDE
- DB 4
- DD CpuFamilyRevision
-ENDM
-
-MEMCLK_DIS_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
- DB PSO_MEMCLK_DIS
- DB 11
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB Bit0Map
- DB Bit1Map
- DB Bit2Map
- DB Bit3Map
- DB Bit4Map
- DB Bit5Map
- DB Bit6Map
- DB Bit7Map
-ENDM
-
-CKE_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ
- DB PSO_CKE_TRI
- DB 5
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB Bit0Map
- DB Bit1Map
-ENDM
-
-ODT_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ
- DB PSO_ODT_TRI
- DB 7
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB Bit0Map
- DB Bit1Map
- DB Bit2Map
- DB Bit3Map
-ENDM
-
-CS_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
- DB PSO_CS_TRI
- DB 11
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB Bit0Map
- DB Bit1Map
- DB Bit2Map
- DB Bit3Map
- DB Bit4Map
- DB Bit5Map
- DB Bit6Map
- DB Bit7Map
-ENDM
-
-NUMBER_OF_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfDimmSlotsPerChannel:REQ
- DB PSO_MAX_DIMMS
- DB 4
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB NumberOfDimmSlotsPerChannel
-ENDM
-
-NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfSolderedDownDimmsPerChannel:REQ
- DB PSO_MAX_SOLDERED_DOWN_DIMMS
- DB 4
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB NumberOfSolderedDownDimmsPerChannel
-ENDM
-
-NUMBER_OF_CHIP_SELECTS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfChipSelectsPerChannel:REQ
- DB PSO_MAX_CHIPSELS
- DB 4
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB NumberOfChipSelectsPerChannel
-ENDM
-
-NUMBER_OF_CHANNELS_SUPPORTED MACRO SocketID:REQ, NumberOfChannelsPerSocket:REQ
- DB PSO_MAX_CHNLS
- DB 4
- DB SocketID
- DB ANY_CHANNEL
- DB ALL_DIMMS
- DB NumberOfChannelsPerSocket
-ENDM
-
-OVERRIDE_DDR_BUS_SPEED MACRO SocketID:REQ, ChannelID:REQ, TimingMode:REQ, BusSpeed:REQ
- PSO_BUS_SPEED
- DB 11
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DD TimingMode
- DD BusSpeed
-ENDM
-
-DRAM_TECHNOLOGY MACRO SocketID:REQ, MemTechType:REQ
- DB PSO_MEM_TECH
- DB 7
- DB SocketID
- DB ANY_CHANNEL
- DB ALL_DIMMS
- DD MemTechType
-ENDM
-
-WRITE_LEVELING_SEED MACRO SocketID:REQ, ChannelID:REQ, DimmID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
-Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
- DB PSO_WL_SEED
- DB 12
- DB SocketID
- DB ChannelID
- DB DimmID
- DB Byte0Seed
- DB Byte1Seed
- DB Byte2Seed
- DB Byte3Seed
- DB Byte4Seed
- DB Byte5Seed
- DB Byte6Seed
- DB Byte7Seed
- DB ByteEccSeed
-ENDM
-
-HW_RXEN_SEED MACRO SocketID:REQ, ChannelID:REQ, DimmID: REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
-Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
- DB PSO_RXEN_SEED
- DB 21
- DB SocketID
- DB ChannelID
- DB DimmID
- DW Byte0Seed
- DW Byte1Seed
- DW Byte2Seed
- DW Byte3Seed
- DW Byte4Seed
- DW Byte5Seed
- DW Byte6Seed
- DW Byte7Seed
- DW ByteEccSeed
-ENDM
-
-NO_LRDIMM_CS67_ROUTING MACRO SocketID:REQ, ChannelID:REQ
- DB PSO_NO_LRDIMM_CS67_ROUTING
- DB 4
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB 1
-ENDM
-
-SOLDERED_DOWN_SODIMM_TYPE MACRO SocketID:REQ, ChannelID:REQ
- DB PSO_SOLDERED_DOWN_SODIMM_TYPE
- DB 4
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB 1
-ENDM
-
-LVDIMM_FORCE_VOLT1_5_FOR_D0 MACRO
- DB PSO_LVDIMM_VOLT1_5_SUPPORT
- DB 4
- DB ANY_SOCKET
- DB ANY_CHANNEL
- DB ALL_DIMMS
- DB 1
-ENDM
-
-MIN_RD_WR_DATAEYE_WIDTH MACRO SocketID:REQ, ChannelID:REQ, MinRdDataeyeWidth:REQ, MinWrDataeyeWidth:REQ
- DB PSO_MIN_RD_WR_DATAEYE_WIDTH
- DB 5
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB MinRdDataeyeWidth
- DB MinWrDataeyeWidth
-ENDM
-
-MEMORY_POWER_POLICY_OVERRIDE MACRO PowerPolicy:REQ
- DB PSO_MEMORY_POWER_POLICY
- DB 4
- DB ANY_SOCKET
- DB ANY_CHANNEL
- DB ALL_DIMMS
- DB PowerPolicy
-ENDM
-; *****************************************************************************************
-; *
-; * CONDITIONAL OVERRIDE TABLE MACROS
-; *
-; *****************************************************************************************
-CONDITION_AND MACRO
- DB PSO_CONDITION_AND
- DB 0
-ENDM
-
-COND_LOC MACRO SocketMsk:REQ, ChannelMsk:REQ, DimmMsk:REQ
- DB PSO_CONDITION_LOC
- DB 3
- DB SocketMsk
- DB ChannelMsk
- DB DimmMsk
-ENDM
-
-COND_SPD MACRO Byte:REQ, Mask:REQ, Value:REQ
- DB PSO_CONDITION_SPD
- DB 3
- DB Byte
- DB Mask
- DB Value
-ENDM
-
-COND_REG MACRO Access:REQ, Offset:REQ, Mask:REQ, Value:REQ
- DB PSO_CONDITION_REG
- DB 11
- DB Access
- DW Offset
- DD Mask
- DD Value
-ENDM
-
-ACTION_ODT MACRO Frequency:REQ, Dimms:REQ, QrDimms:REQ, DramOdt:REQ, QrDramOdt:REQ, DramDynOdt:REQ
- DB PSO_ACTION_ODT
- DB 9
- DD Frequency
- DB Dimms
- DB QrDimms
- DB DramOdt
- DB QrDramOdt
- DB DramDynOdt
-ENDM
-
-ACTION_ADDRTMG MACRO Frequency:REQ, DimmConfig:REQ, AddrTmg:REQ
- DB PSO_ACTION_ADDRTMG
- DB 10
- DD Frequency
- DW DimmConfig
- DD AddrTmg
-ENDM
-
-ACTION_ODCCTRL MACRO Frequency:REQ, DimmConfig:REQ, OdcCtrl:REQ
- DB PSO_ACTION_ODCCONTROL
- DB 10
- DD Frequency
- DW DimmConfig
- DD OdcCtrl
-ENDM
-
-ACTION_SLEWRATE MACRO Frequency:REQ, DimmConfig:REQ, SlewRate:REQ
- DB PSO_ACTION_SLEWRATE
- DB 10
- DD Frequency
- DW DimmConfig
- DD SlewRate
-ENDM
-
-ACTION_SPEEDLIMIT MACRO DimmConfig:REQ, Dimms:REQ, SpeedLimit15:REQ, SpeedLimit135:REQ, SpeedLimit125:REQ
- DB PSO_ACTION_SPEEDLIMIT
- DB 9
- DW DimmConfig
- DB Dimms
- DW SpeedLimit15
- DW SpeedLimit135
- DW SpeedLimit125
-ENDM
-
-; *****************************************************************************************
-; *
-; * END OF CONDITIONAL OVERRIDE TABLE MACROS
-; *
-; *****************************************************************************************
-; *****************************************************************************************
-; *
-; * TABLE DRIVEN OVERRIDE MACROS
-; *
-; *****************************************************************************************
-; Configuration sub-descriptors
-CONFIG_GENERAL EQU 0
-CONFIG_SPEEDLIMIT EQU 1
-CONFIG_RC2IBT EQU 2
-CONFIG_DONT_CARE EQU 3
-Config_Type TEXTEQU <DWORD>
-;
-; Configuration Macros
-;
-TBLDRV_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Frequency:REQ, DimmVolt:REQ, DimmConfig:REQ
- DB PSO_TBLDRV_CONFIG
- DB 9
- DB CONFIG_GENERAL
- DB DimmPerCH
- DB DimmVolt
- DD Frequency
- DW DimmConfig
-ENDM
-
-TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Dimms:REQ, NumOfSR:REQ, NumOfDR:REQ, NumOfQR:REQ, NumOfLRDimm:REQ
- DB PSO_TBLDRV_CONFIG
- DB 7
- DB CONFIG_SPEEDLIMIT
- DB DimmPerCH
- DB Dimms
- DB NumOfSR
- DB NumOfDR
- DB NumOfQR
- DB NumOfLRDimm
-ENDM
-
-TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Frequency:REQ, DimmVolt:REQ, DimmConfig:REQ, NumOfReg:REQ
- DB PSO_TBLDRV_CONFIG
- DB 10
- DB CONFIG_RC2IBT
- DB DimmPerCH
- DB DimmVolt
- DD Frequency
- DW DimmConfig
- DB NumOfReg
-ENDM
-;
-; Overriding Macros
-;
-TBLDRV_CONFIG_ENTRY_SPEEDLIMIT MACRO SpeedLimit1_5:REQ, SpeedLimit1_35:REQ, SpeedLimit1_25:REQ
- DB PSO_TBLDRV_SPEEDLIMIT
- DB 6
- DW SpeedLimit1_5
- DW SpeedLimit1_35
- DW SpeedLimit1_25
-ENDM
-
-TBLDRV_CONFIG_ENTRY_ODT_RTTNOM MACRO TgtCS:REQ, RttNom:REQ
- DB PSO_TBLDRV_ODT_RTTNOM
- DB 2
- DB TgtCS
- DB RttNom
-ENDM
-
-TBLDRV_CONFIG_ENTRY_ODT_RTTWR MACRO TgtCS:REQ, RttWr:REQ
- DB PSO_TBLDRV_ODT_RTTWR
- DB 2
- DB TgtCS
- DB RttWr
-ENDM
-
-TBLDRV_CONFIG_ENTRY_ODTPATTERN MACRO RdODTCSHigh:REQ, RdODTCSLow:REQ, WrODTCSHigh:REQ, WrODTCSLow:REQ
- DB PSO_TBLDRV_ODTPATTERN
- DB 16
- DD RdODTCSHigh
- DD RdODTCSLow
- DD WrODTCSHigh
- DD WrODTCSLow
-ENDM
-
-TBLDRV_CONFIG_ENTRY_ADDRTMG MACRO AddrTmg:REQ
- DB PSO_TBLDRV_ADDRTMG
- DB 4
- DD AddrTmg
-ENDM
-
-TBLDRV_CONFIG_ENTRY_ODCCTRL MACRO OdcCtrl:REQ
- DB PSO_TBLDRV_ODCCTRL
- DB 4
- DD OdcCtrl
-ENDM
-
-TBLDRV_CONFIG_ENTRY_SLOWACCMODE MACRO SlowAccMode:REQ
- DB PSO_TBLDRV_SLOWACCMODE
- DB 1
- DB SlowAccMode
-ENDM
-
-TBLDRV_CONFIG_ENTRY_RC2_IBT MACRO TgtDimm:REQ, IBT:REQ
- DB PSO_TBLDRV_RC2_IBT
- DB 2
- DB TgtDimm
- DB IBT
-ENDM
-
-TBLDRV_OVERRIDE_MR0_CL MACRO RegValOfTcl:REQ, MR0CL13:REQ, MR0CL0:REQ
- DB PSO_TBLDRV_CONFIG
- DB 1
- DB CONFIG_DONT_CARE
- DB PSO_TBLDRV_MR0_CL
- DB 3
- DB RegValOfTcl
- DB MR0CL13
- DB MR0CL0
-ENDM
-
-TBLDRV_OVERRIDE_MR0_WR MACRO RegValOfTwr:REQ, MR0WR:REQ
- DB PSO_TBLDRV_CONFIG
- DB 1
- DB CONFIG_DONT_CARE
- DB PSO_TBLDRV_MR0_WR
- DB 2
- DB RegValOfTcl
- DB MR0WR
-ENDM
-
-TBLDRV_OVERRIDE_RC10_OPSPEED MACRO Frequency:REQ, MR10OPSPEED:REQ
- DB PSO_TBLDRV_CONFIG
- DB 1
- DB CONFIG_DONT_CARE
- DB PSO_TBLDRV_RC10_OPSPEED
- DB 5
- DD Frequency
- DB MR10OPSPEED
-ENDM
-
-TBLDRV_CONFIG_ENTRY_LRDMM_IBT MACRO F0RC8:REQ, F1RC0:REQ, F1RC1:REQ, F1RC2:REQ
- DB PSO_TBLDRV_LRDIMM_IBT
- DB 4
- DB F0RC8
- DB F1RC0
- DB F1RC1
- DB F1RC2
-ENDM
-
-;del TBLDRV_CONFIG_ENTRY_2D_TRAINING MACRO Training2dMode:REQ
-;del DB PSO_TBLDRV_2D_TRAINING
-;del DB 1
-;del DB Training2dMode
-;del ENDM
-
-;
-; Macros for removing entries
-;
-INVALID_CONFIG_FLAG EQU 8000h
-
-TBLDRV_INVALID_CONFIG MACRO
- DB PSO_TBLDRV_INVALID_TYPE
- DB 0
-ENDM
-; *****************************************************************************************
-; *
-; * END OF TABLE DRIVEN OVERRIDE MACROS
-; *
-; *****************************************************************************************
diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/arch2008.asm b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/arch2008.asm
deleted file mode 100644
index a7be499a87..0000000000
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/arch2008.asm
+++ /dev/null
@@ -1,2675 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; Workfile: arch2008.asm $Revision: 63425 $ $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
-;
-; Description: ARCH2008.ASM - AGESA Architecture 2008 Wrapper Template
-;
-;*****************************************************************************
-;
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*****************************************************************************
-
- .XLIST
- INCLUDE agesa.inc
- INCLUDE acwrapg.inc ; Necessary support file as part of wrapper, including but not limited to segment start/end macros.
- INCLUDE acwrap.inc ; IBVs may specify host BIOS-specific include files required when building.
- INCLUDE cpcarmac.inc
- INCLUDE bridge32.inc
- .LIST
- .586p
- .mmx
-
-
-;----------------------------------------------------------------------------
-; Local definitions
-;----------------------------------------------------------------------------
-
-sOemCallout STRUCT
- FuncName DD ? ; Call out function name
- FuncPtr DW ? ; Call out function pointer
-sOemCallout ENDS
-
-sOemEventHandler STRUCT
- ClassCode DD ? ; AGESA event log sub-class code
- FuncPtr DW ? ; Event handler function pointer
-sOemEventHandler ENDS
-
-;; A typical legacy BIOS implementation may require the E000 and F000 segments
-;; to be cached.
-EXE_CACHE_REGION_BASE_0 EQU 0E0000h
-EXE_CACHE_REGION_SIZE_0 EQU 20000h
-
-;; In this sample implementation, the B1 and B2 images are placed next to each
-;; other in the BIOS ROM to help with the maximization of cached code.
-EXE_CACHE_REGION_BASE_1 EQU AGESA_B1_ADDRESS
-EXE_CACHE_REGION_SIZE_1 EQU 40000h
-
-;; The third region is not needed in our example.
-EXE_CACHE_REGION_BASE_2 EQU 0
-EXE_CACHE_REGION_SIZE_2 EQU 0
-
-
-;----------------------------------------------------------------------------
-; PERSISTENT SEGMENT
-; This segment is required to be present throughout all BIOS execution.
-;----------------------------------------------------------------------------
-
-AMD_PERSISTENT_START
-
-
-;----------------------------------------------------------------------------
-; Instantiate the global descriptor table
-;----------------------------------------------------------------------------
-
-AMD_BRIDGE_32_GDT AMD_GDT ; Instantiate the global descriptor table
- ; required by the push-high mechanism.
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the persistent segment
-;----------------------------------------------------------------------------
-
-;+-------------------------------------------------------------------------
-;
-; AmdDfltRet
-;
-; Entry:
-; None
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Near stub procedure. Simply perform a retn instruction.
-;
-EXTERN AmdDfltRet:NEAR
-
-
-;+-------------------------------------------------------------------------
-;
-; AmdDfltRetFar
-;
-; Entry:
-; None
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Far stub procedure. Simply perform a retf instruction.
-;
-EXTERN AmdDfltRetFar:FAR
-
-
-;----------------------------------------------------------------------------
-; Declare the optional external routines in the persistent segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myModuleTypeMismatchHandler (Example)
-;
-; Entry:
-; ESI - Pointer to the EVENT_PARAMS structure of the failure.
-; [ESI].DataParam1 - Socket
-; [ESI].DataParam2 - DCT
-; [ESI].DataParam3 - Channel
-; [ESI].DataParam4 - 0x00000000
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure can be used to react to a memory module type
-; mismatch error discovered by the AGESA code. Actions taken
-; may include, but are not limited to:
-; Logging the event to NV for display later
-; Reset, excluding the mismatch on subsequent reboot
-; Do nothing
-;
-; Dependencies:
-; None
-;
-EXTERN myModuleTypeMismatchHandler(AmdDfltRet):NEAR
-
-;+---------------------------------------------------------------------------
-;
-; oemPlatformConfigInit (Optional)
-;
-; Entry:
-; EDI - 32-bit flat pointer to the PLATFORM_CONFIGURATION to be
-; passed in to the next AGESA entry point.
-;
-; typedef struct {
-; IN PERFORMANCE_PROFILE PlatformProfile;
-; IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList;
-; IN UINT8 CoreLevelingMode;
-; IN PLATFORM_C1E_MODES C1eMode;
-; IN UINT32 C1ePlatformData;
-; IN UINT32 C1ePlatformData1;
-; IN UINT32 C1ePlatformData2;
-; IN UINT32 C1ePlatformData3;
-; IN BOOLEAN UserOptionDmi;
-; IN BOOLEAN UserOptionPState;
-; IN BOOLEAN UserOptionSrat;
-; IN BOOLEAN UserOptionSlit;
-; IN BOOLEAN UserOptionWhea;
-; IN UINT32 PowerCeiling;
-; IN BOOLEAN PstateIndependent;
-; } PLATFORM_CONFIGURATION;
-;
-; typedef struct {
-; IN UINT8 Socket;
-; IN UINT8 Link;
-; IN UINT8 LoFreq;
-; IN UINT8 HighFreq;
-; IN PLATFORM_DEEMPHASIS_LEVEL ReceiverDeemphasis;
-; IN PLATFORM_DEEMPHASIS_LEVEL DcvDeemphasis;
-; } CPU_HT_DEEMPHASIS_LEVEL;
-;
-; typedef struct {
-; IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode;
-; IN BOOLEAN UseHtAssist;
-; IN BOOLEAN UseAtmMode;
-; IN BOOLEAN Use32ByteRefresh;
-; IN BOOLEAN UseVariableMctIsocPriority;
-; } PERFORMANCE_PROFILE;
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Provide a single hook routine to modify the parameters of a
-; PLATFORM_CONFIGURATION structure before any entry point that
-; has such a structure as an input.
-;
-; Dependencies:
-; None
-;
-; Example:
-; If your platform is running in UMA mode, the following code
-; may be added:
-; mov (PLATFORM_CONFIGURATION PTR [edi]).PlatformProfile.PlatformControlFlowMode, UmaDr
-;
-EXTERN oemPlatformConfigInit(AmdDfltRetFar):FAR
-
-;+---------------------------------------------------------------------------
-;
-; oemCallout (Optional)
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The default call out router function which resides in the same
-; segment as the push-high bridge code.
-;
-; Dependencies:
-; None
-;
-EXTERN oemCallout(AmdDfltRet):NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the persistent segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdBridge32
-;
-; Entry:
-; EDX - A Real Mode FAR pointer using seg16:Offset16 format that
-; points to a local host environment call-out router. If
-; this pointer is not equal to zero, then this pointer is
-; used as the call-out router instead of the standard
-; OemCallout. This may be useful when the call-out router
-; is not located in the same segment as the AmdBridge32 and
-; AmdCallout16 routines.
-; ESI - A Flat Mode pointer (32-bit address) that points to the
-; configuration block (AMD_CONFIG_PARAMS) for the AGESA
-; software function.
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; Execute an AGESA software function through the Push-High interface.
-;
-; Dependencies:
-; This procedure requires a stack. The host environment must use the
-; provided service function to establish the stack environment prior
-; to making the call to this procedure.
-;
-AmdBridge32 PROC FAR PUBLIC
- AMD_BRIDGE_32 AMD_GDT ; use the macro for the body
- ret
-AmdBridge32 ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdEnableStack
-;
-; Entry:
-; BX - Return address
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; SS:ESP - Points to the private stack location for this processor core.
-; ECX - Upon success, contains this processor core's stack size in bytes.
-;
-; Modified:
-; EAX, ECX, EDX, EDI, ESI, ESP, DS, ES
-;
-; Purpose:
-; This procedure is used to establish the stack within the host environment.
-;
-; Dependencies:
-; The host environment must use this procedure and not rely on any other
-; sources to create the stack region.
-;
-AmdEnableStack PROC NEAR PUBLIC
- AMD_ENABLE_STACK
- ;; EAX = AGESA_SUCCESS, The stack space has been allocated for this core.
- ;; EAX = AGESA_WARNING, The stack has already been set up. SS:ESP is set
- ;; to stack top, and ECX is the stack size in bytes.
- jmp bx
-AmdEnableStack ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdDisableStack
-;
-; Entry:
-; BX - Return address
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; EAX, ECX, EDX, ESI, ESP
-;
-; Purpose:
-; This procedure is used to remove the pre-memory stack from within the
-; host environment.
-; The exit state for the BSP is described as follows:
-; Memory region 00000-9FFFF MTRRS are set as WB memory.
-; Processor Cache is enabled (CD bit is cleared).
-; MTRRs used for execution cache are kept.
-; Cache content is flushed (invalidated without write-back).
-; Any family-specific clean-up done.
-; The exit state for the APs is described as follows:
-; Memory region 00000-9FFFF MTRRS are set as WB memory.
-; Memory region A0000-DFFFF MTRRS are set as UC IO.
-; Memory region E0000-FFFFF MTRRS are set as UC memory.
-; MTRRs used for execution cache are cleared.
-; Processor Cache is disabled (CD bit is set).
-; Top-of-Memory (TOM) set to the system top of memory as determined
-; by the memory initialization routines.
-; System lock command is enabled.
-; Any family-specific clean-up done.
-;
-; Dependencies:
-; The host environment must use this procedure and not rely on any other
-; sources to break down the stack region.
-; If executing in 16-bit code, the host environment must establish the
-; "Big Real" mode of 32-bit addressing of data.
-;
-AmdDisableStack PROC NEAR PUBLIC
- AMD_DISABLE_STACK
- ;; EAX = AGESA_SUCCESS, The stack space has been disabled for this core.
- jmp bx
-AmdDisableStack ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCallout16
-;
-; Entry:
-; [esp+8] - Func
-; [esp+12] - Data
-; [esp+16] - Configuration Block
-; [esp+4] - Return address to AGESA
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; Execute callback from the push-high interface.
-;
-; Dependencies:
-; None
-;
-AmdCallout16 PROC FAR PUBLIC ; declare the procedure
- AMD_CALLOUT_16 oemCallout ; use the macro for the body
- ret
-AmdCallout16 ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdProcessAgesaErrors (Optional)
-;
-; Entry:
-; AL - Heap status of the AGESA entry point that was just invoked.
-; EBX - AGESA image base address.
-; EDX - Segment / Offset of the appropriate callout router function.
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure is used to handle any errors that may have occurred
-; during an AGESA entry point.
-;
-; Dependencies:
-; None
-;
-AmdProcessAgesaErrors PROC FAR PUBLIC
- LOCAL localCpuInterfaceBlock:EVENT_PARAMS
-
- pushad
- xor edi, edi
- mov di, ss
- shl edi, 4
- lea esi, localCpuInterfaceBlock
- add esi, edi
-
- ; Fill default config block
- mov (EVENT_PARAMS PTR [esi]).StdHeader.Func, AMD_READ_EVENT_LOG
- mov (EVENT_PARAMS PTR [esi]).StdHeader.ImageBasePtr, ebx
- mov (EVENT_PARAMS PTR [esi]).StdHeader.AltImageBasePtr, 0
- mov (EVENT_PARAMS PTR [esi]).StdHeader.HeapStatus, al
- mov edi, SEG AmdCallout16
- shl edi, 4
- add edi, OFFSET AmdCallout16
- mov (EVENT_PARAMS PTR [esi]).StdHeader.CalloutPtr, edi
-
- ; Flush the event log searching for, and handling all monitored events
- xor eax, eax
- .while (eax == 0)
- push edx
- call AmdBridge32
- pop edx
- .if (eax == AGESA_SUCCESS)
- mov eax, (EVENT_PARAMS PTR [esi]).EventInfo
- .if (eax != 0)
- lea di, cs:AgesaEventTable
-
-loopThruTable:
- cmp di, OFFSET cs:AgesaEventTableEnd
- jae unhandledEvent
-
- cmp eax, cs:[di].sOemEventHandler.ClassCode
- je FoundMatch
- add di, SIZEOF sOemEventHandler
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemEventHandler.FuncPtr
- call bx
-
-unhandledEvent:
- xor eax, eax
- .else
- mov al, 1
- .endif
- .endif
- .endw
- popad
- ret
-
-AmdProcessAgesaErrors ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the error handler table
-;----------------------------------------------------------------------------
-
-AgesaEventTable LABEL BYTE
- ;; Add entries as desired
- ;;---------
- ;; EXAMPLE
- ;;---------
- sOemEventHandler <MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, OFFSET myModuleTypeMismatchHandler>
-AgesaEventTableEnd LABEL BYTE
-
-
-AMD_PERSISTENT_END
-
-
-
-
-;----------------------------------------------------------------------------
-; RECOVERY SEGMENT
-; This segment resides in the classic 'boot-block,' and is used
-; for recovery.
-;----------------------------------------------------------------------------
-
-AMD_RECOVERY_START
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the recovery segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myReadSPDRecovery (Required for proper recovery mode operation)
-;
-; Entry:
-; ESI - Pointer to an AGESA_READ_SPD_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT8 SocketId;
-; IN UINT8 MemChannelId;
-; IN UINT8 DimmId;
-; IN OUT UINT8 *Buffer;
-; IN OUT MEM_DATA_STRUCT *MemData;
-; } AGESA_READ_SPD_PARAMS;
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS Indicates the SPD block for the indicated
-; DIMM was read successfully.
-; AGESA_BOUNDS_CHK The specified DIMM is not present.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function and no memory initialized.
-; AGESA_ERROR The DIMM SPD read process has generated
-; communication errors.
-;
-; Modified:
-; None
-;
-; Purpose:
-; This call out reads a block of memory SPD data and places it
-; into the provided buffer.
-;
-; Dependencies:
-; None
-;
-EXTERN myReadSPDRecovery:NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the recovery segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitResetWrapper
-;
-; Entry:
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; A minimal initialization of the processor core is performed. This
-; procedure must be called by all processor cores. The code path
-; separates the BSP from the APs and performs a separate and appropriate
-; list of tasks for each class of core.
-; For the BSP, the following actions are performed:
-; Internal heap sub-system initialization
-; Primary non-coherent HyperTransportT link initialization
-; Return to the host environment to test for Recovery Mode.
-; The AP processor cores do not participate in the recovery process.
-; However, they execute this routine after being released to execute
-; by the BSP during the main boot process. Their actions include the
-; following:
-; Internal heap sub-system initialization
-; Proceed to a wait loop waiting for commands from the BSP
-;
-; For the cache regions, up to three regions of execution cache can be
-; allocated following the following rules:
-; 1. Once a region is allocated, it cannot be de-allocated. However, it
-; can be expanded.
-; 2. At most, two of the three regions can be located above 1 MByte. A
-; region failing this rule is ignored.
-; 3. All region addresses must be at or above the 0x000D0000 linear
-; address. A region failing this rule is ignored.
-; 4. The address is aligned on a 32-KByte boundary. Starting addresses
-; is rounded down to the nearest 32-Kbyte boundary.
-; 5. The execution cache size must be a multiple of 32 KByte. Size is
-; rounded up to the next multiple of 32 KByte.
-; 6. A region must not span either the 1-MByte boundary or the 4-GByte
-; boundary. Allocated size is truncated to not span the boundary.
-; 7. The granted cached execution regions, address, and size are calculated
-; based on the available cache resources of the processor core.
-; Allocations are made up to the limit of cache available on the
-; installed processor.
-; Warning: Enabling instruction cache outside of this interface can cause
-; data corruption.
-;
-; Dependencies:
-; This procedure is expected to be executed soon after a system reset
-; for the main boot path or resume path of execution.
-;
-; This procedure requires a stack.
-;
-; Because the heap system is not yet operational at the point of the
-; interface call, the host environment must allocate the storage for
-; the AMD_RESET_PARAMS structure before making the first call to
-; AmdCreateStruct. This is the ByHost method of allocation.
-;
-AmdInitResetWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
- local localResetParams:AMD_RESET_PARAMS
-
- pushad
-
- ; Prepare for the call to initialize the input parameters for AmdInitReset
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B1_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- ; Use the 'ByHost' allocation method because the heap has not been initialized as of yet.
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RESET
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, ByHost
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, sizeof AMD_RESET_PARAMS
- lea edx, localResetParams
- add edx, eax
- push edx
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr, edx
- mov dx, SEG AmdCalloutRouterRecovery
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterRecovery
- push edx
- call AmdBridge32
- pop edx
- pop esi
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- ; Allocate the execution cache to maximize the amount of code in ROM that is cached.
- ; Placing the B1 and B2 images near one another is a good way to ensure the AGESA code
- ; is cached.
- mov (AMD_RESET_PARAMS ptr [esi]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_0
- mov (AMD_RESET_PARAMS ptr [esi]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_0
- mov (AMD_RESET_PARAMS ptr [esi + sizeof EXECUTION_CACHE_REGION]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_1
- mov (AMD_RESET_PARAMS ptr [esi + sizeof EXECUTION_CACHE_REGION]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_1
- mov (AMD_RESET_PARAMS ptr [esi + (2 * sizeof EXECUTION_CACHE_REGION)]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_2
- mov (AMD_RESET_PARAMS ptr [esi + (2 * sizeof EXECUTION_CACHE_REGION)]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_2
-
- ; Call in to the AmdInitReset entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS Early initialization completed successfully.
- ;; AGESA_WARNING One or more of the execution cache allocation
- ;; rules were violated, but an adjustment was made
- ;; and space was allocated.
- ;; AGESA_ERROR One or more of the execution cache allocation rules
- ;; were violated, which resulted in a requested cache
- ;; region to not be allocated.
- ;; The storage space allocated for the AMD_RESET_PARAMS
- ;; structure is insufficient.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_RESET_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B1_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
-
- ;; Here are what the MTRRs should look like based off of the CacheRegions specified above:
-
- ;; Fixed-Range MTRRs
- ;; Name Address Value
- ;; ---------------- -------- ----------------
- ;; MTRRfix4k_E0000 0000026C 0505050505050505
- ;; MTRRfix4k_E8000 0000026D 0505050505050505
- ;; MTRRfix4k_F0000 0000026E 0505050505050505
- ;; MTRRfix4k_F8000 0000026F 0505050505050505
- ;; MTRRdefType 000002FF 0000000000000C00
- ;;
- ;; Variable-Range MTRRs and IO Range
- ;; MTRRphysBase(n) MTRRphysMask(n)
- ;; ----------------- -----------------
- ;; n=0 0000000000000000 0000000000000000
- ;; n=1 0000000000000000 0000000000000000
- ;; n=2 0000000000000000 0000000000000000
- ;; n=3 0000000000000000 0000000000000000
- ;; n=4 0000000000000000 0000000000000000
- ;; n=5 Heap Base (Varies by core) 0000FFFFFFFF0800
- ;; n=6 AGESA_B1_ADDRESS | 6 0000FFFFFFFC0800
- ;; n=7 0000000000000000 0000000000000000
-
-
- ;; Because the allocation method is 'ByHost,' the call to AMD_RELEASE_STRUCT is
- ;; not necessary. Stack space reclamation is left up to the host BIOS.
-
- popad
- ret
-
-
-AmdInitResetWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitRecoveryWrapper
-;
-; Entry:
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Perform a minimum initialization of the processor and memory to
-; support a recovery mode flash ROM update.
-; For the BSP, the following actions are performed:
-; Configuration of CPU core for recovery process
-; Minimal initialization of some memory
-; The AP processor cores do not participate in the recovery process.
-; No actions or tasks are performed by the AP cores for this time point.
-;
-; Dependencies:
-; This procedure requires a stack. The host environment must use one of
-; the provided service functions to establish the stack environment prior
-; to making the call to this procedure.
-;
-AmdInitRecoveryWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitRecovery
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B1_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RECOVERY
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterRecovery
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterRecovery
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
-
- ; Call in to the AmdInitRecovery entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_WARNING One or more of the allocation rules were violated,
- ;; but an adjustment was made and space was allocated.
- ;; AGESA_ERROR One or more of the allocation rules were violated,
- ;; which resulted in a requested cache region to not be
- ;; allocated.
- ;; AGESA_FATAL No memory was found in the system.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_RECOVERY_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B1_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitRecovery
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-AmdInitRecoveryWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCalloutRouterRecovery
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The call out router function for AmdInitReset and
-; AmdInitRecovery.
-;
-; Dependencies:
-; None
-;
-AmdCalloutRouterRecovery PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
- xor ax, ax
- mov ds, ax
- mov es, ax
- lea di, cs:CalloutRouterTableRecovery
- mov eax, AGESA_UNSUPPORTED
-
-loopThruTable:
- cmp di, OFFSET cs:CalloutRouterTableRecoveryEnd
- jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
- cmp ecx, cs:[di].sOemCallout.FuncName
- je FoundMatch
- add di, SIZEOF sOemCallout
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemCallout.FuncPtr
- call bx
-
-amdCpuCalloutExit:
- ret
-AmdCalloutRouterRecovery ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the callout dispatch table for the recovery segment
-;----------------------------------------------------------------------------
-
-CalloutRouterTableRecovery LABEL BYTE
- ;; Standard B1 implementations only need the SPD reader call out function to be implemented.
- sOemCallout <AGESA_READ_SPD, OFFSET myReadSPDRecovery>
-CalloutRouterTableRecoveryEnd LABEL BYTE
-
-
-AMD_RECOVERY_END
-
-
-
-;----------------------------------------------------------------------------
-; PRE-MEMORY SEGMENT
-; This segment must be uncompressed in the ROM image.
-;----------------------------------------------------------------------------
-
-AMD_PREMEM_START
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the recovery segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myReadSPDPremem (Required)
-;
-; Entry:
-; ESI - Pointer to an AGESA_READ_SPD_PARAMS structure
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT8 SocketId;
-; IN UINT8 MemChannelId;
-; IN UINT8 DimmId;
-; IN OUT UINT8 *Buffer;
-; IN OUT MEM_DATA_STRUCT *MemData;
-; } AGESA_READ_SPD_PARAMS;
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS Indicates the SPD block for the indicated
-; DIMM was read successfully.
-; AGESA_BOUNDS_CHK The specified DIMM is not present.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function and no memory initialized.
-; AGESA_ERROR The DIMM SPD read process has generated
-; communication errors.
-;
-; Modified:
-; None
-;
-; Purpose:
-; This call out reads a block of memory SPD data and places it
-; into the provided buffer.
-;
-; Dependencies:
-; None
-;
-EXTERN myReadSPDPremem:NEAR
-
-;+-------------------------------------------------------------------------
-;
-; AmdDfltRetPremem
-;
-; Entry:
-; None
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Near stub procedure in the prememory segment. Simply perform a
-; retn instruction.
-;
-EXTERN AmdDfltRetPremem:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myDoReset (Required)
-;
-; Entry:
-; EDX - Reset type
-; 1 - Warm reset whenever
-; 2 - Cold reset whenever
-; 3 - Warm reset immediately
-; 4 - Cold reset immediately
-; ESI - Pointer to an AMD_CONFIG_PARAMS structure.
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function.
-;
-; Modified:
-; None
-;
-; Purpose:
-; This host environment function must initiate the specified type
-; of system reset.
-;
-; Implementation of this function by the host environment is
-; REQUIRED. Some host environments may record this as a request
-; allowing other elements in the system to perform some additional
-; tasks before the actual reset is issued.
-;
-; Dependencies:
-; The AMD processor contains 3 bits (BiosRstDet[2:0]) in a PCI
-; register (F0x6C Link Initialization Control Register) that
-; indicate the reset status. These bits are reserved for use by
-; the AGESA software and should not be modified by the host
-; environment.
-;
-EXTERN myDoReset:NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myGetNonVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; None
-;
-; Exit:
-; EBX - Pointer to the non-volatile S3 context block
-; ECX - Size in bytes of the non-volatile S3 context block
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must return the pointer to the data
-; saved during the mySaveNonVolatileS3Context routine.
-;
-; Dependencies:
-; None
-;
-EXTERN myGetNonVolatileS3Context:NEAR
-
-
-;----------------------------------------------------------------------------
-; Declare the optional external routines in the prememory segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myAgesaHookBeforeExitSelfRefresh (Optional)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 44h
-; ESI - Pointer to a data structure containing the memory information
-;
-; Exit:
-; After returning control to AGESA, AGESA will display: - AGESA_TESTPOINT - 45h
-; EAX - Contains the AGESA_STATUS return code
-; AGESA_SUCCESS The function has completed successfully
-; AGESA_UNSUPPORTED This function is not implemented by the host environment
-; AGESA_WARNING A non-critical issue has occued in the host environment
-;
-; Modified:
-; None
-;
-; Purpose:
-; General purpose hook called before the exiting self refresh
-; This procedure is called once per channel
-;
-; Implementation of this function is optional for the host environment
-; This call-out is an opportunity for the host environment to make dynamic
-; modifications to the memory timing settings specific to the board or host
-; environment before exiting self refresh on S3 resume
-;
-; Dependencies:
-; This procedure is called before the exit self refresh bit is set in the resume
-; sequence. The host environment must initiate the OS restart process. This procedure
-; requires a stack. The host environment must establish the stack environment prior
-; to making the call to this procedure
-;
-EXTERN myAgesaHookBeforeExitSelfRefresh(AmdDfltRetPremem):NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myHookBeforeDramInit (Optional)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 40h
-; ESI - Pointer to a data structure containing the memory information
-;
-; Exit:
-; After returning control to AGESA, AGESA will display - AGESA_TESTPOINT - 41h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This function is not implemented by the host environment
-;
-; Modified:
-; None
-;
-; Purpose:
-; General-purpose hook called before the DRAM_Init bit is set. Called
-; once per MCT
-;
-; Implementation of this function is optional for the host environment
-; This call-out is an opportunity for the host environment to make
-; dynamic modifications to the memory timing settings specific to the
-; board or host environment
-;
-; Dependencies:
-; None
-;
-EXTERN myHookBeforeDramInit(AmdDfltRetPremem):NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myHookBeforeDQSTraining (Optional)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 42h
-; ESI - Pointer to a data structure containing the memory information.
-;
-; Exit:
-; After returning control to AGESA, AGESA will display - AGESA_TESTPOINT - 43h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This function is not implemented by the
-; host environment.
-;
-; Modified:
-; None
-;
-; Purpose:
-; General-purpose hook called just before the memory training processes
-; begin. Called once per MCT.
-;
-; Implementation of this function is optional for the host environment.
-; This call-out is an opportunity for the host environment to make
-; dynamic modifications to the memory timing settings specific to the
-; board or host environment.
-;
-; The host environment may also use this call-out for some board-
-; specific features that should be activated at this time point,
-; such as:
-; Low voltage DIMMs-the host environment should set the recommended
-; voltages found in the memory data structure for each memory
-; channel. This needs to occur before training begins.
-;
-; Dependencies:
-; None
-;
-EXTERN myHookBeforeDQSTraining(AmdDfltRetPremem):NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the prememory segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitEarlyWrapper
-;
-; Entry:
-; On Entry to "AmdInitEarly" AGESA will display AGESA_TESTPOINT - C4h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitEarly" AGESA will display AGESA_TESTPOINT - C5h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; A full initialization of the processor is performed. Action details
-; differ for the BSP and AP processor cores.
-; For the BSP, the following actions are performed:
-; Full HyperTransportT link initialization, coherent and non-coherent
-; Processor register loading
-; Microcode patch load
-; Errata workaround processing
-; Launch all processor cores
-; Configure the processor power management capabilities
-; Request a warm reset if needed
-; For the AP, the following actions are performed:
-; Processor register loading
-; Microcode patch load
-; Errata workaround processing
-; Configure the processor power management capabilities
-;
-; Dependencies:
-; This procedure is expected to be called before main memory initialization
-; and before the system warm reset. Prior to this, the basic configuration
-; done by the AmdInitReset routine must be completed.
-;
-; This procedure requires a stack. The host environment must use one of the
-; provided service functions to establish the stack environment prior to
-; making the call to this procedure.
-;
-; The processes performed at this time point require communication between
-; processor cores.
-;
-; The host environment must recognize that all processor cores are running
-; in parallel and avoid activities that might interfere with the core-to-core
-; communication, such as modifying the MTRR settings or writing to the APIC
-; registers.
-;
-AmdInitEarlyWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitEarly
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_EARLY
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPremem
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPremem
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + (3 * (SIZEOF EXECUTION_CACHE_REGION)))
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitEarly entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ALERT An HyperTransportT link CRC error was observed.
- ;; AGESA_WARNING One of more of the allocation rules were violated,
- ;; but an adjustment was made and space was allocated.
- ;; Or a HyperTransport device does not have the expected
- ;; capabilities, or unusable redundant HyperTransport
- ;; links were found.
- ;; AGESA_ERROR One or more of the allocation rules were violated, which
- ;; resulted in a requested cache region to not be allocated.
- ;; Or, a HyperTransport device failed to initialize.
- ;; AGESA_CRITICAL An illegal or unsupported mixture of processor types was
- ;; found, or the processors installed were found to have an
- ;; insufficient MP capability rating for this platform.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_EARLY_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitEarly
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitEarlyWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitPostWrapper
-;
-; Entry:
-; On Entry to "AmdInitPost" AGESA will display AGESA_TESTPOINT - C6h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitPost" AGESA will display AGESA_TESTPOINT - C7h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The main system memory is located, initialized, and brought on-line.
-; The processor(s) are prepared for full operation and control by the
-; host environment. Action details differ for the BSP and AP processor
-; cores.
-; For the BSP, the following actions are performed:
-; Full memory initialization and configuration. BSP is the master for
-; this process and may delegate some tasks to APs.
-; AP collection of data for use later.
-; Transfer the HOBs including the artifact data out of the pre-memory
-; cache storage into a temporary holding buffer in the main memory.
-; Check the BIST status of the BSP
-; Shut down the APs.
-; Prepare for the host environment to begin main boot activity.
-; Disable the pre-memory stack.
-; For the APs, the following actions are performed:
-; Report core identity information.
-; Execute indicated memory initialization processes as directed.
-; Check the BIST status of the AP
-; Disable the pre-memory stack.
-; Prepare to halt, giving control to host environment.
-; The entire range of system memory is enabled for Write-Back cache.
-; The fixed MTRRs and the variable MTRRs[7:6] are not changed in order
-; to leave in place any flash ROM region currently set for Write-Protect
-; execution cache.
-;
-; Dependencies:
-; This procedure is called after the host environment has determined that
-; a normal boot to operating system should be performed after any system
-; warm reset is completed and after the configuration done by AmdInitEarly
-; has completed.
-;
-; This procedure requires a stack. The host environment must use one of the
-; provided service functions to establish the stack environment prior to
-; making the call to this procedure.
-;
-; The processes performed at this time point require communication between
-; processor cores. The host environment must recognize that all processor
-; cores are running in parallel and avoid activities that might interfere
-; with the core-to-core communication, such as modifying the MTRR settings
-; or writing to the APIC registers.
-;
-AmdInitPostWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitPost
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_POST
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPremem
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPremem
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitPost entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ALERT A BIST error was found on one of the cores.
- ;; AGESA_WARNING HT Assist feature is running sub-optimally.
- ;; AGESA_FATAL Memory initialization failed.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_POST_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitPost
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitPostWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitResumeWrapper
-;
-; Entry:
-; On Entry to "AmdInitResume" AGESA will display AGESA_TESTPOINT - D0h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitResume" AGESA will display AGESA_TESTPOINT - D1h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure initializes or re-initializes the silicon components
-; for the resume boot path. For the processor, main memory is brought
-; out of self-refresh mode. This procedure will use the context data
-; in the NvStorage area of the input structure to re-start the main
-; memory. The host environment must fill the AMD_S3_PARAMS NvStorage
-; and VolatileStorage pointers and related size elements to describe
-; the location of the context data. Note that for this procedure, the
-; two data areas do not need to be contained in one buffer zone, they
-; can be anywhere in the accessible memory address space. If the host
-; environment uses a non-volatile storage device accessed on the system
-; address bus such as flashROM, then the context data does not need to
-; be moved prior to this call. If the host environment uses a non-
-; volatile storage device not located on the system address bus (e.g.
-; CMOS or SSEPROM) then the host environment must transfer the context
-; data to a buffer in main memory prior to calling this procedure.
-;
-; Dependencies:
-; The host environment must have determined that the system should take
-; the resume path prior to calling this procedure. The configuration
-; done by AmdInitEarly and any necessary warm reset must be complete.
-; After this procedure, execution proceeds to general system restoration.
-;
-; This procedure requires a stack. The host environment must use one of
-; the provided service functions to establish the stack environment prior
-; to making the call to this procedure.
-;
-AmdInitResumeWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitResume
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RESUME
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPremem
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPremem
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
- call oemPlatformConfigInit
-
- call myGetNonVolatileS3Context
- mov (AMD_RESUME_PARAMS ptr [esi]).S3DataBlock.NvStorage, ebx
- mov (AMD_RESUME_PARAMS ptr [esi]).S3DataBlock.NvStorageSize, ecx
-
- ; Call in to the AmdInitResume entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS Re-initialization has been completed successfully.
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_RESUME_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
-
- ; Allow AGESA to free the space used by AmdInitResume
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitResumeWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCalloutRouterPremem
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The call out router function for AmdInitEarly,
-; AmdInitPost, and AmdInitResume.
-;
-; Dependencies:
-; None
-;
-AmdCalloutRouterPremem PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
- xor ax, ax
- mov ds, ax
- mov es, ax
- lea di, cs:CalloutRouterTablePremem
- mov eax, AGESA_UNSUPPORTED
-
-loopThruTable:
- cmp di, OFFSET cs:CalloutRouterTablePrememEnd
- jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
- cmp ecx, cs:[di].sOemCallout.FuncName
- je FoundMatch
- add di, SIZEOF sOemCallout
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemCallout.FuncPtr
- call bx
-
-amdCpuCalloutExit:
- ret
-AmdCalloutRouterPremem ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the callout dispatch table for the prememory segment
-;----------------------------------------------------------------------------
-
-CalloutRouterTablePremem LABEL BYTE
- ;; Add entries as desired.
- sOemCallout <AGESA_READ_SPD, OFFSET myReadSPDPremem>
- sOemCallout <AGESA_HOOKBEFORE_DRAM_INIT, OFFSET myHookBeforeDramInit>
- sOemCallout <AGESA_HOOKBEFORE_DQS_TRAINING, OFFSET myHookBeforeDQSTraining>
- sOemCallout <AGESA_HOOKBEFORE_EXIT_SELF_REF, OFFSET myAgesaHookBeforeExitSelfRefresh>
- sOemCallout <AGESA_DO_RESET, OFFSET myDoReset>
-;del sOemCallout <AGESA_EXTERNAL_2D_TRAIN_VREF_CHANGE, OFFSET my2DTrainVrefChange>
-CalloutRouterTablePrememEnd LABEL BYTE
-
-
-
-AMD_PREMEM_END
-
-
-;----------------------------------------------------------------------------
-; POST SEGMENT
-; This segment may be decompressed and run from system RAM.
-;----------------------------------------------------------------------------
-
-AMD_POST_START
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the POST segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myAllocateBuffer (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E2h
-; ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 BufferLength;
-; IN UINT32 BufferHandle;
-; OUT VOID *BufferPointer;
-; } AGESA_BUFFER_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E3h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The requested size of memory has been
-; successfully allocated.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function.
-; AGESA_ERROR Less than the requested amount of memory
-; was allocated.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of memory allocation.
-; This function must allocate a buffer of the requested size or
-; larger. This function is required to be implemented by the host
-; environment.
-;
-; Dependencies:
-; The following call-outs must work together in the host system.
-; Parameters of the same name have the same function and must be
-; treated the same in each function:
-; AgesaAllocateBuffer
-; AgesaDeallocateBuffer
-; AgesaLocateBuffer
-; AgesaRunFcnOnAp
-; The host environment may need to reserve a location in the buffer
-; to store any host environment specific value(s). The returned
-; pointer must not include this reserved space. The host environment
-; on the AgesaDeallocateBuffer call needs to account for the reserved
-; space. This reserved space may be an identifier or the "handle"
-; used to identify the specific memory block.
-;
-EXTERN myAllocateBuffer:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myDeallocateBuffer (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E4h
-; ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 BufferLength;
-; IN UINT32 BufferHandle;
-; OUT VOID *BufferPointer;
-; } AGESA_BUFFER_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E5h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_BOUNDS_CHK The BufferHandle is invalid. The AGESA
-; software continues with its function.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of memory allocation.
-; This function releases a valid working buffer. This function is
-; required for the host environment to implement.
-;
-; Dependencies:
-; The following call-outs must work together in the host system.
-; Parameters of the same name have the same function and must be
-; treated the same in each function:
-; AgesaAllocateBuffer
-; AgesaDeallocateBuffer
-; AgesaLocateBuffer
-; AgesaRunFcnOnAp
-;
-EXTERN myDeallocateBuffer:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myLocateBuffer (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E6h
-; ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 BufferLength;
-; IN UINT32 BufferHandle;
-; OUT VOID *BufferPointer;
-; } AGESA_BUFFER_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E7h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_BOUNDS_CHK The presented handle is invalid or the
-; buffer could not be located.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of memory allocation.
-; This function must locate the buffer related to the indicated
-; handle and return the address of the buffer and its length.
-; This function is required to be implemented in the host
-; environment.
-;
-; Dependencies:
-; The following call-outs must work together in the host system.
-; Parameters of the same name have the same function and must be
-; treated the same in each function:
-; AgesaAllocateBuffer
-; AgesaDeallocateBuffer
-; AgesaLocateBuffer
-; AgesaRunFcnOnAp
-;
-EXTERN myLocateBuffer:NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myRunFuncOnAp (Required)
-;
-; Entry:
-; EDX - Local APIC ID of the target core.
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must route execution to the target AP and
-; have that AP call the AmdLateRunApTaskWrapper routine defined
-; above.
-;
-; Dependencies:
-; None
-;
-EXTERN myRunFuncOnAp:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; mySaveNonVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; EBX - Pointer to the non-volatile S3 context block
-; ECX - Size in bytes of the non-volatile S3 context block
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must save the non-volatile data to an area
-; that will not lose context while in the ACPI S3 sleep state, but
-; cannot be placed in system RAM. This data will need to be
-; available during the call to AmdInitResume.
-;
-; Dependencies:
-; None
-;
-EXTERN mySaveNonVolatileS3Context:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; mySaveVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; EBX - Pointer to the volatile S3 context block
-; ECX - Size in bytes of the volatile S3 context block
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must save the volatile data to an area
-; that will not lose context while in the ACPI S3 sleep state.
-; This data will need to be available during the call to
-; AmdS3LateRestore.
-;
-; Dependencies:
-; None
-;
-EXTERN mySaveVolatileS3Context:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myGetVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; None
-;
-; Exit:
-; EBX - Pointer to the volatile S3 context block
-; ECX - Size in bytes of the volatile S3 context block
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must return the pointer to the data
-; saved during the mySaveVolatileS3Context routine.
-;
-; Dependencies:
-; None
-;
-EXTERN myGetVolatileS3Context:NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the POST segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitEnvWrapper
-;
-; Entry:
-; On Entry to "AmdInitEnv" AGESA will display AGESA_TESTPOINT - C8h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitEnv" AGESA will display AGESA_TESTPOINT - C9h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure uses the AgesaAllocateBuffer call-out to acquire
-; permanent buffer space for the UEFI Hand-Off Blocks (HOBs). This
-; is also known as, or includes, artifact data being used by the
-; AGESA software. Upon entry to this procedure, the data is being
-; held in a temporary memory location and it must be moved to a
-; location controlled and protected by the host environment.
-;
-; These actions are performed by the BSP. The APs are not assigned
-; any tasks at this time point.
-;
-; Dependencies:
-; This procedure must be called after full memory is initialized and
-; the host environment has taken control of main memory allocation.
-; This procedure should be called before the PCI enumeration takes
-; place and as soon as possible after the host environment memory
-; allocation sub-system has started.
-;
-; This procedure requires a stack. The host environment must use one
-; of the provided service functions to establish the stack environment
-; prior to making the call to this procedure.
-;
-AmdInitEnvWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitEnv
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_ENV
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitEnv entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ERROR The artifact data could not be found or the host
- ;; environment failed to allocate sufficient buffer space.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_ENV_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitEnv
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitEnvWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitMidWrapper
-;
-; Entry:
-; On Entry to "AmdInitMid" AGESA will display AGESA_TESTPOINT - CAh
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitMid" AGESA will display AGESA_TESTPOINT - CBh
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure call performs special configuration requirements for
-; the graphics display hardware.
-;
-; These actions are performed by the BSP. The APs are not assigned any
-; tasks at this time point.
-;
-; Dependencies:
-; This procedure must be called after PCI enumeration has allocated
-; resources, but before the video BIOS call is performed.
-;
-; This procedure requires a stack. The host environment must use one
-; of the provided service functions to establish the stack environment
-; prior to making the call to this procedure.
-;
-AmdInitMidWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitMid
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_MID
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitMid entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_MID_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitMid
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-
-AmdInitMidWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitLateWrapper
-;
-; Entry:
-; On Entry to "AmdInitLate" AGESA will display AGESA_TESTPOINT - CCh
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitLate" AGESA will display AGESA_TESTPOINT - CDh
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The main purpose of this function is to generate informational
-; data tables used by the operating system. The individual tables
-; can be selected for generation through the user selection entries
-; on the input parameters.
-;
-; This routine uses the Call-Out AgesaAllocateBuffer to allocate a
-; buffer of the proper size to contain the data.
-;
-; The code path separates the BSP from the APs and perform a separate
-; and appropriate list of tasks for each class of core.
-; For the BSP, the following actions are performed:
-; Allocate buffer space for the tables.
-; Generate the table contents.
-; Make sure that the CPU is in a known good power state before
-; proceeding to boot the OS.
-; For the APs, the following actions are performed:
-; Final register settings preparing for entry to OS.
-; Establish the final PState for entry to OS.
-;
-; Dependencies:
-; This routine is expected to be executed late in the boot sequence
-; after main memory has been initialized, after PCI enumeration has
-; completed, after the host environment ACPI sub-system has started,
-; after the host environment has taken control of the APs, but just
-; before the start of OS boot.
-;
-; The host environment must provide the required call-outs listed in
-; the "Required Call-Out Procedures" section of the AGESA interface
-; specification to provide the buffer space in main memory and execute
-; code on the APs. The host environment must register the created ACPI
-; table in the main ACPI pointer tables. This may require moving the
-; generated tables to another location in memory.
-;
-; This procedure requires a stack. The host environment must establish
-; the stack environment prior to making the call to this procedure.
-; Some functions depend upon the preservation of the heap data across
-; the shift from pre-memory environment to a post-memory environment.
-; If that data was not preserved, then those functions cannot complete
-; and an error is returned.
-;
-AmdInitLateWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitLate
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_LATE
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitLate entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ALERT
- ;; AGESA_ERROR The system could not allocate the needed amount of
- ;; buffer space; or could not locate the artifact data block in
- ;; memory. Likely cause: the host environment may not have preserved
- ;; the data properly.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_LATE_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- push es
- mov ax, SEG AmdAcpiSratPointer
- mov es, ax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiSrat
- mov es:AmdAcpiSratPointer, ebx
- mov eax, DWORD PTR [ebx + 4]
- mov es:AmdAcpiSratSize, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiSlit
- mov es:AmdAcpiSlitPointer, ebx
- mov eax, DWORD PTR [ebx + 4]
- mov es:AmdAcpiSlitSize, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiPState
- mov es:AmdAcpiSsdtPointer, ebx
- mov eax, DWORD PTR [ebx + 4]
- mov es:AmdAcpiSsdtSize, eax
-
- xor eax, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiWheaMce
- mov es:AmdAcpiWheaMcePointer, ebx
- mov ax, WORD PTR [ebx]
- mov es:AmdAcpiWheaMceSize, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiWheaMce
- mov es:AmdAcpiWheaCmcPointer, ebx
- mov ax, WORD PTR [ebx]
- mov es:AmdAcpiWheaCmcSize, eax
-
- mov eax, (AMD_LATE_PARAMS ptr [esi]).DmiTable
- mov es:AmdDmiInfoPointer, eax
- pop es
-
-
- ; Allow AGESA to free the space used by AmdInitLate
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-
-AmdInitLateWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdS3SaveWrapper
-;
-; Entry:
-; On Entry to "AmdS3Save" AGESA will display AGESA_TESTPOINT - CEh
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Entry to "AmdS3Save" AGESA will display AGESA_TESTPOINT - CFh
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure saves critical registers and/or configuration
-; information for preservation across a system suspend mode. All
-; actions needed to prepare the processor for suspend mode is
-; performed, however this procedure does NOT initiate the suspend
-; process. The host environment is expected to perform that duty.
-;
-; These actions are performed by the BSP. The APs are not assigned
-; any tasks at this time point.
-;
-; The initializer routine will NULL out the save area pointers and
-; sizes. This procedure will determine the size of storage needed
-; for all the processor context, and make a call out to the environment
-; for allocation of one buffer to store all of the data. Upon exit, the
-; pointers and sizes within the AMD_S3_PARAMS structure will be updated
-; with the appropriate addresses within the buffer that was allocated.
-; The host environment is expected to then transfer the data pointed to
-; by NvStorage to a non-volatile storage area, and the data pointed to
-; by VolatileStorage to either a non-volatile storage area or system
-; RAM that retains its content across suspend.
-;
-; Dependencies:
-; The host environment must initiate the suspend process.
-;
-; This procedure requires a stack. The host environment must establish
-; the stack environment prior to making the call to this procedure.
-;
-AmdS3SaveWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdS3Save
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_S3_SAVE
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
- call oemPlatformConfigInit
-
- ; Call in to the AmdS3Save entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS All suspend duties have been completed successfully.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_S3SAVE_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- mov ecx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.NvStorageSize
- .if (ecx != 0)
- mov ebx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.NvStorage
- call mySaveNonVolatileS3Context
- .endif
-
- mov ecx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.VolatileStorageSize
- .if (ecx != 0)
- mov ebx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.VolatileStorage
- call mySaveVolatileS3Context
- .endif
-
- ; Allow AGESA to free the space used by AmdS3Save
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-
-AmdS3SaveWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdS3LateRestoreWrapper
-;
-; Entry:
-; On Entry to "AmdS3LateRestore" AGESA will display AGESA_TESTPOINT - D2h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdS3LateRestore" AGESA will display AGESA_TESTPOINT - D3h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure restores the processor state, reloads critical
-; silicon component registers, and performs any re-initialization
-; required by the silicon. This procedure will use the context data
-; in the VolatileStorage area of the input structure to restore the
-; processor registers.
-;
-; The host environment must fill the AMD_S3_PARAMS NvStorage and
-; VolatileStorage pointers and related size elements to describe
-; the location of the context data. Note that for this procedure,
-; the two data areas do not need to be contained in one buffer zone,
-; they can be anywhere in the accessible memory address space. If
-; the host environment uses a non-volatile storage device accessed
-; on the system address bus such as flashROM, then the context data
-; does not need to be moved prior to this call. If the host
-; environment uses a non-volatile storage device not located on the
-; system address bus (e.g. CMOS or SSEPROM) then the host environment
-; must transfer the context data to a buffer in main memory prior to
-; calling this procedure.
-;
-; These actions are performed by the BSP. The APs are not assigned
-; any tasks at this time point.
-;
-; Dependencies:
-; This procedure is called late in the resume sequence, after the
-; PCI control space is restored and just before resuming operating
-; system execution.
-;
-; The host environment must initiate the OS restart process.
-;
-; This procedure requires a stack. The host environment must establish
-; the stack environment prior to making the call to this procedure.
-;
-AmdS3LateRestoreWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdS3LateRestore
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_S3LATE_RESTORE
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
- call oemPlatformConfigInit
-
- call myGetVolatileS3Context
- mov (AMD_S3LATE_PARAMS ptr [esi]).S3DataBlock.VolatileStorage, ebx
- mov (AMD_S3LATE_PARAMS ptr [esi]).S3DataBlock.VolatileStorageSize, ecx
-
- ; Call in to the AmdS3LateRestore entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS All resume processes have been completed successfully.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_S3LATE_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdS3LateRestore
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-AmdS3LateRestoreWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdLateRunApTaskWrapper
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - D4h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - D5h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This entry point is tightly connected with the "AgesaRunFcnOnAp"
-; call out. The AGESA software will call the call-out "AgesaRunFcnOnAp";
-; the host environment will then call this entry point to have the AP
-; execute the requested function. This is needed late in the Post and
-; Resume branches for running an AP task since the AGESA software has
-; relinquished control of the APs to the host environment.
-;
-; Dependencies:
-; The host environment must implement the"AgesaRunFcnOnAp" call-out
-; and route execution to the target AP.
-;
-AmdLateRunApTaskWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdLateRunApTask
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_LATE_RUN_AP_TASK
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- push es
- mov ax, SEG AmdRunCodeOnApDataPointer
- mov es, ax
- mov eax, es:AmdRunCodeOnApDataPointer
- mov (AP_EXE_PARAMS PTR [esi]).RelatedDataBlock, eax
- mov eax, es:AmdRunCodeOnApDataSize
- mov (AP_EXE_PARAMS PTR [esi]).RelatedBlockLength, eax
- mov eax, es:AmdRunCodeOnApFunction
- mov (AP_EXE_PARAMS PTR [esi]).FunctionNumber, eax
- pop es
-
- ; Call in to the AmdLateRunApTask dispatcher
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- push es
- mov bx, SEG AmdRunCodeOnApStatus
- mov es, bx
- mov es:AmdRunCodeOnApStatus, eax
- pop es
-
- ; Allow AGESA to free the space used by AmdLateRunApTask
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-
-AmdLateRunApTaskWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdRunFuncOnAp (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E8h
-; EDX - Local APIC ID of the target core.
-; ESI - Pointer to an AP_EXE_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 FunctionNumber;
-; IN VOID *RelatedDataBlock;
-; IN UINT32 RelatedDataBlockLength;
-; } AP_EXE_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E9h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This is a required function, so this value
-; being returned causes a critical error
-; response value from the AGESAT software
-; function and no memory initialized.
-; AGESA_WARNING The AP did not respond.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of AP task dispatching.
-; This function must cause the indicated function code to be executed
-; upon the specified Application Processor. This procedure must be
-; executed in 32-bit mode. This function is required to be implemented
-; in the host environment.
-;
-; Dependencies:
-; The host environment must route execution to the target AP and
-; have that AP call the"AmdLateRunApTask" entry point.
-;
-AmdRunFuncOnAp PROC NEAR PUBLIC
-
- push es
- mov ax, SEG AmdRunCodeOnApDataPointer
- mov es, ax
- mov eax, (AP_EXE_PARAMS PTR [esi]).RelatedDataBlock
- mov es:AmdRunCodeOnApDataPointer, eax
- mov eax, (AP_EXE_PARAMS PTR [esi]).RelatedBlockLength
- mov es:AmdRunCodeOnApDataSize, eax
- mov eax, (AP_EXE_PARAMS PTR [esi]).FunctionNumber
- mov es:AmdRunCodeOnApFunction, eax
- mov eax, AGESA_UNSUPPORTED
- mov es:AmdRunCodeOnApStatus, eax
- pop es
-
- call myRunFuncOnAp
-
- push es
- mov ax, SEG AmdRunCodeOnApStatus
- mov es, ax
- mov eax, es:AmdRunCodeOnApStatus
- pop es
- ret
-AmdRunFuncOnAp ENDP
-
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCalloutRouterPost
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The call out router function for AmdInitEnv,
-; AmdInitMid, AmdInitLate, AmdS3Save, and
-; AmdS3LateRestore.
-;
-; Dependencies:
-; None
-;
-AmdCalloutRouterPost PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
- xor ax, ax
- mov ds, ax
- mov es, ax
- lea di, cs:CalloutRouterTablePost
- mov eax, AGESA_UNSUPPORTED
-
-loopThruTable:
- cmp di, OFFSET cs:CalloutRouterTablePostEnd
- jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
- cmp ecx, cs:[di].sOemCallout.FuncName
- je FoundMatch
- add di, SIZEOF sOemCallout
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemCallout.FuncPtr
- call bx
-
-amdCpuCalloutExit:
- ret
-AmdCalloutRouterPost ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the callout dispatch table for the POST segment
-;----------------------------------------------------------------------------
-
-CalloutRouterTablePost LABEL BYTE
- ;; Add entries as desired.
- sOemCallout <AGESA_ALLOCATE_BUFFER, OFFSET myAllocateBuffer>
- sOemCallout <AGESA_DEALLOCATE_BUFFER, OFFSET myDeallocateBuffer>
- sOemCallout <AGESA_LOCATE_BUFFER, OFFSET myLocateBuffer>
- sOemCallout <AGESA_RUNFUNC_ONAP, OFFSET AmdRunFuncOnAp>
-CalloutRouterTablePostEnd LABEL BYTE
-
-AMD_POST_END
-
-
-;----------------------------------------------------------------------------
-; CPU DATA SEGMENT
-; This segment must be writable, and present at the time that
-; AmdInitLate is run.
-;----------------------------------------------------------------------------
-
-CPU_DATASEG_START
-
- ;; Data used to store pointers for later use by the host environment.
- PUBLIC AmdAcpiSratPointer
- PUBLIC AmdAcpiSratSize
- PUBLIC AmdAcpiSlitPointer
- PUBLIC AmdAcpiSlitSize
- PUBLIC AmdAcpiSsdtPointer
- PUBLIC AmdAcpiSsdtSize
- PUBLIC AmdAcpiWheaMcePointer
- PUBLIC AmdAcpiWheaMceSize
- PUBLIC AmdAcpiWheaCmcPointer
- PUBLIC AmdAcpiWheaCmcSize
- PUBLIC AmdDmiInfoPointer
- AmdAcpiSratPointer DWORD ?
- AmdAcpiSratSize DWORD ?
- AmdAcpiSlitPointer DWORD ?
- AmdAcpiSlitSize DWORD ?
- AmdAcpiSsdtPointer DWORD ?
- AmdAcpiSsdtSize DWORD ?
- AmdAcpiWheaMcePointer DWORD ?
- AmdAcpiWheaMceSize DWORD ?
- AmdAcpiWheaCmcPointer DWORD ?
- AmdAcpiWheaCmcSize DWORD ?
- AmdDmiInfoPointer DWORD ?
-
- ;; Data used for communication between the AP and the BSP.
- PUBLIC AmdRunCodeOnApDataPointer
- PUBLIC AmdRunCodeOnApDataSize
- PUBLIC AmdRunCodeOnApFunction
- PUBLIC AmdRunCodeOnApStatus
- AmdRunCodeOnApDataPointer DWORD ?
- AmdRunCodeOnApDataSize DWORD ?
- AmdRunCodeOnApFunction DWORD ?
- AmdRunCodeOnApStatus DWORD ?
-
-CPU_DATASEG_END
-
-
-END
diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/agesa.inc b/src/vendorcode/amd/agesa/f15tn/Legacy/agesa.inc
deleted file mode 100644
index be8ccf3d4f..0000000000
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/agesa.inc
+++ /dev/null
@@ -1,3089 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * Agesa structures and definitions
-; *
-; * Contains AMD AGESA core interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 64574 $ @e \$Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $
-;
-; ****************************************************************************
-; *
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; *
-; **************************************************************************
-
-INCLUDE amd.inc
-UINT64 TEXTEQU <QWORD>
-UINT32 TEXTEQU <DWORD>
-UINT16 TEXTEQU <WORD>
-UINT8 TEXTEQU <BYTE>
-CHAR8 TEXTEQU <BYTE>
-BOOLEAN TEXTEQU <BYTE>
-POINTER TEXTEQU <DWORD>
-
- ; AGESA Types and Definitions
-
-
-
- ; AGESA BASIC CALLOUTS
- AGESA_MEM_RELEASE EQU 00028000h
-
- ; AGESA ADVANCED CALLOUTS, Processor
- AGESA_CHECK_UMA EQU 00028100h
- AGESA_DO_RESET EQU 00028101h
- AGESA_ALLOCATE_BUFFER EQU 00028102h
- AGESA_DEALLOCATE_BUFFER EQU 00028103h
- AGESA_LOCATE_BUFFER EQU 00028104h
- AGESA_RUNFUNC_ONAP EQU 00028105h
-
- ; AGESA ADVANCED CALLOUTS, HyperTransport
-
- ; AGESA ADVANCED CALLOUTS, Memory
- AGESA_READ_SPD EQU 00028140h
- AGESA_HOOKBEFORE_DRAM_INIT EQU 00028141h
- AGESA_HOOKBEFORE_DQS_TRAINING EQU 00028142h
- AGESA_READ_SPD_RECOVERY EQU 00028143h
- AGESA_HOOKBEFORE_EXIT_SELF_REF EQU 00028144h
- AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY EQU 00028145h
-;del AGESA_EXTERNAL_2D_TRAIN_VREF_CHANGE EQU 00028146h
-
- ; AGESA IDS CALLOUTS
- AGESA_GET_IDS_INIT_DATA EQU 00028200h
-
- ; AGESA GNB CALLOUTS
- AGESA_GNB_PCIE_SLOT_RESET EQU 00028301h
- AGESA_GNB_GFX_GET_VBIOS_IMAGE EQU 00028302h
-
- ; AGESA FCH CALLOUTS
- AGESA_FCH_OEM_CALLOUT EQU 00028401h
-
-; ------------------------------------------------------------------------
-
- ; HyperTransport Interface
-
-
-
-; -----------------------------------------------------------------------------
- ; HT DEFINITIONS AND MACROS
-
-; -----------------------------------------------------------------------------
-
-
- ; Width equates for call backs
- HT_WIDTH_8_BITS EQU 8
- HT_WIDTH_16_BITS EQU 16
- HT_WIDTH_4_BITS EQU 4
- HT_WIDTH_2_BITS EQU 2
- HT_WIDTH_NO_LIMIT EQU HT_WIDTH_16_BITS
-
- ; Frequency Limit equates for call backs which take a frequency supported mask.
- HT_FREQUENCY_LIMIT_200M EQU 1
- HT_FREQUENCY_LIMIT_400M EQU 7
- HT_FREQUENCY_LIMIT_600M EQU 1Fh
- HT_FREQUENCY_LIMIT_800M EQU 3Fh
- HT_FREQUENCY_LIMIT_1000M EQU 7Fh
- HT_FREQUENCY_LIMIT_HT1_ONLY EQU 7Fh
- HT_FREQUENCY_LIMIT_1200M EQU 0FFh
- HT_FREQUENCY_LIMIT_1400M EQU 1FFh
- HT_FREQUENCY_LIMIT_1600M EQU 3FFh
- HT_FREQUENCY_LIMIT_1800M EQU 7FFh
- HT_FREQUENCY_LIMIT_2000M EQU 0FFFh
- HT_FREQUENCY_LIMIT_2200M EQU 1FFFh
- HT_FREQUENCY_LIMIT_2400M EQU 3FFFh
- HT_FREQUENCY_LIMIT_2600M EQU 7FFFh
- HT_FREQUENCY_LIMIT_2800M EQU 27FFFh
- HT_FREQUENCY_LIMIT_3000M EQU 67FFFh
- HT_FREQUENCY_LIMIT_3200M EQU 0E7FFFh
- HT_FREQUENCY_LIMIT_3600M EQU 1E7FFFh
- HT_FREQUENCY_LIMIT_MAX EQU HT_FREQUENCY_LIMIT_3600M
- HT_FREQUENCY_NO_LIMIT EQU 0FFFFFFFFh
-
- ; Unit ID Clumping special values
- HT_CLUMPING_DISABLE EQU 00000000h
- HT_CLUMPING_NO_LIMIT EQU 0FFFFFFFFh
-
- HT_LIST_TERMINAL EQU 0FFh
- HT_LIST_MATCH_ANY EQU 0FEh
- HT_LIST_MATCH_INTERNAL_LINK EQU 0FDh
-
- ; Event Notify definitions
-
- ; Event definitions.
-
- ; Coherent subfunction events
- HT_EVENT_COH_EVENTS EQU 10001000h
- HT_EVENT_COH_NO_TOPOLOGY EQU 10011000h
- HT_EVENT_COH_OBSOLETE000 EQU 10021000h
- HT_EVENT_COH_PROCESSOR_TYPE_MIX EQU 10031000h
- HT_EVENT_COH_NODE_DISCOVERED EQU 10041000h
- HT_EVENT_COH_MPCAP_MISMATCH EQU 10051000h
-
- ; Non-coherent subfunction events
- HT_EVENT_NCOH_EVENTS EQU 10002000h
- HT_EVENT_NCOH_BUID_EXCEED EQU 10012000h
- HT_EVENT_NCOH_OBSOLETE000 EQU 10022000h
- HT_EVENT_NCOH_BUS_MAX_EXCEED EQU 10032000h
- HT_EVENT_NCOH_CFG_MAP_EXCEED EQU 10042000h
- HT_EVENT_NCOH_DEVICE_FAILED EQU 10052000h
- HT_EVENT_NCOH_AUTO_DEPTH EQU 10062000h
-
- ; Optimization subfunction events
- HT_EVENT_OPT_EVENTS EQU 10003000h
- HT_EVENT_OPT_REQUIRED_CAP_RETRY EQU 10013000h
- HT_EVENT_OPT_REQUIRED_CAP_GEN3 EQU 10023000h
- HT_EVENT_OPT_UNUSED_LINKS EQU 10033000h
- HT_EVENT_OPT_LINK_PAIR_EXCEED EQU 10043000h
-
- ; HW Fault events
- HT_EVENT_HW_EVENTS EQU 10004000h
- HT_EVENT_HW_SYNCFLOOD EQU 10014000h
- HT_EVENT_HW_HTCRC EQU 10024000h
-
- ; The Recovery HT component uses 0x10005000 for events.
- ; For consistency, we avoid that range here.
-
- HT_MAX_NC_BUIDS EQU 32
-; ----------------------------------------------------------------------------
- ; HT TYPEDEFS, STRUCTURES, ENUMS
-
-; ----------------------------------------------------------------------------
-MATCHED EQU 0 ; < The link matches the requested customization.
-POWERED_OFF EQU 1 ; < Power the link off.
-UNMATCHED EQU 2 ; < The link should be processed according to normal defaults.
-MaxFinalLinkState EQU 3 ; < Not a final link state, use for limit checking.
-FINAL_LINK_STATE TEXTEQU <DWORD>
-
- ; Swap a device from its current id to a new one.
-
-BUID_SWAP_ITEM STRUCT
- FromId UINT8 ? ; < The device responding to FromId,
- ToId UINT8 ? ; < will be moved to ToId.
-BUID_SWAP_ITEM ENDS
-
-
- ; Each Non-coherent chain may have a list of device swaps. After performing the swaps,
- ; the final in order list of device ids is provided. (There can be more swaps than devices.)
- ; The unused entries in both are filled with 0xFF.
-
-BUID_SWAP_LIST STRUCT
- Swaps BUID_SWAP_ITEM (HT_MAX_NC_BUIDS) DUP ({}) ; < The BUID Swaps to perform
- FinalIds UINT8 (HT_MAX_NC_BUIDS) DUP (?) ; < The ordered final BUIDs, resulting from the swaps
-BUID_SWAP_LIST ENDS
-
-
- ; Control Manual Initialization of Non-Coherent Chains
-
- ; This interface is checked every time a non-coherent chain is
- ; processed. BUID assignment may be controlled explicitly on a
- ; non-coherent chain. Provide a swap list. Swaps controls the
- ; BUID assignment and FinalIds provides the device to device
- ; Linking. Device orientation can be detected automatically, or
- ; explicitly. See interface documentation for more details.
-
- ; If a manual swap list is not supplied,
- ; automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
- ; based on each device's unit count.
-
-MANUAL_BUID_SWAP_LIST STRUCT
- ; Match fields
- Socket UINT8 ? ; < The Socket on which this chain is located
- Link UINT8 ? ; < The Link on the host for this chain
- ; Override fields
- SwapList BUID_SWAP_LIST {} ; < The swap list
-MANUAL_BUID_SWAP_LIST ENDS
-
-
- ; Override options for DEVICE_CAP_OVERRIDE.
-
- ; Specify which override actions should be performed. For Checks, 1 means to check the item
- ; and 0 means to skip the check. For the override options, 1 means to apply the override and
- ; 0 means to ignore the override.
-
-DEVICE_CAP_OVERRIDE_OPTIONS STRUCT
- IsCheckDevVenId UINT32 ?
-; IN UINT32 IsCheckDevVenId:1; ; < Check Match on Device/Vendor id
-; IN UINT32 IsCheckRevision:1; ; < Check Match on device Revision
-; IN UINT32 IsOverrideWidthIn:1; ; < Override Width In
-; IN UINT32 IsOverrideWidthOut:1; ; < Override Width Out
-; IN UINT32 IsOverrideFreq:1; ; < Override Frequency
-; IN UINT32 IsOverrideClumping:1; ; < Override Clumping
-; IN UINT32 IsDoCallout:1; ; < Make the optional callout
-DEVICE_CAP_OVERRIDE_OPTIONS ENDS
-
- ; Override capabilities of a device.
-
- ; This interface is checked once for every Link on every IO device.
- ; Provide the width and frequency capability if needed for this device.
- ; This is used along with device capabilities, the limit interfaces, and northbridge
- ; limits to compute the default settings. The components of the device's PCI config
- ; address are provided, so its settings can be consulted if need be.
- ; The optional callout is a catch all.
-
-DEVICE_CAP_OVERRIDE STRUCT
- ; Match fields
- HostSocket UINT8 ? ; < The Socket on which this chain is located.
- HostLink UINT8 ? ; < The Link on the host for this chain.
- Depth UINT8 ? ; < The Depth in the I/O chain from the Host.
- DevVenId UINT32 ? ; < The Device's PCI Vendor + Device ID (offset 0x00).
- Revision UINT8 ? ; < The Device's PCI Revision field (offset 0x08).
- Link UINT8 ? ; < The Device's Link number (0 or 1).
- Options DEVICE_CAP_OVERRIDE_OPTIONS {} ; < The options for this device override.
- ; Override fields
- LinkWidthIn UINT8 ? ; < modify to change the Link Width In.
- LinkWidthOut UINT8 ? ; < modify to change the Link Width Out.
- FreqCap UINT32 ? ; < modify to change the Link's frequency capability.
- Clumping UINT32 ? ; < modify to change Unit ID clumping support.
- Callout CALLOUT_ENTRY ? ; < optional call for really complex cases, or NULL.
-DEVICE_CAP_OVERRIDE ENDS
-
- ; Callout param struct for override capabilities of a device.
-
- ; If the optional callout is implemented this param struct is passed to it.
-
-DEVICE_CAP_CALLOUT_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < The header
- ; Match fields
- HostSocket UINT8 ? ; < The Socket on which this chain is located.
- HostLink UINT8 ? ; < The Link on the host for this chain.
- Depth UINT8 ? ; < The Depth in the I/O chain from the Host.
- DevVenId UINT32 ? ; < The Device's PCI Vendor + Device ID (offset 0x00).
- Revision UINT8 ? ; < The Device's PCI Revision field (offset 0x08).
- Link UINT8 ? ; < The Device's Link number (0 or 1).
- PciAddress PCI_ADDR {} ; < The Device's PCI Address.
- ; Override fields
- LinkWidthIn POINTER ? ; < modify to change the Link Width In.
- LinkWidthOut POINTER ? ; < modify to change the Link Width Out.
- FreqCap POINTER ? ; < modify to change the Link's frequency capability.
- Clumping POINTER ? ; < modify to change Unit ID clumping support.
-DEVICE_CAP_CALLOUT_PARAMS ENDS
-
- ; Limits for CPU to CPU Links.
-
- ; For each coherent connection this interface is checked once.
- ; Provide the frequency and width if needed for this Link (usually based on board
- ; restriction). This is used with CPU device capabilities and northbridge limits
- ; to compute the default settings.
-
-CPU_TO_CPU_PCB_LIMITS STRUCT
- ; Match fields
- SocketA UINT8 ? ; < One Socket on which this Link is located
- LinkA UINT8 ? ; < The Link on this Node
- SocketB UINT8 ? ; < The other Socket on which this Link is located
- LinkB UINT8 ? ; < The Link on that Node
- ; Limit fields
- ABLinkWidthLimit UINT8 ? ; < modify to change the Link Width A->B
- BALinkWidthLimit UINT8 ? ; < modify to change the Link Width B-<A
- PcbFreqCap UINT32 ? ; < modify to change the Link's frequency capability
-CPU_TO_CPU_PCB_LIMITS ENDS
-
- ; Get limits for non-coherent Links.
-
- ; For each non-coherent connection this interface is checked once.
- ; Provide the frequency and width if needed for this Link (usually based on board
- ; restriction). This is used with device capabilities, device overrides, and northbridge limits
- ; to compute the default settings.
-
-IO_PCB_LIMITS STRUCT
- ; Match fields
- HostSocket UINT8 ? ; < The Socket on which this Link is located
- HostLink UINT8 ? ; < The Link about to be initialized
- Depth UINT8 ? ; < The Depth in the I/O chain from the Host
- ; Limit fields
- DownstreamLinkWidthLimit UINT8 ? ; < modify to change the Link Width going away from processor
- UpstreamLinkWidthLimit UINT8 ? ; < modify to change the Link Width moving toward processor
- PcbFreqCap UINT32 ? ; < modify to change the Link's frequency capability
-IO_PCB_LIMITS ENDS
-
- ; Manually control bus number assignment.
-
- ; This interface is checked every time a non-coherent chain is processed.
- ; If a system can not use the auto Bus numbering feature for non-coherent chain bus
- ; assignments, this interface can provide explicit control. For each chain, provide
- ; the bus number range to use.
-
-OVERRIDE_BUS_NUMBERS STRUCT
- ; Match fields
- Socket UINT8 ? ; < The Socket on which this chain is located
- Link UINT8 ? ; < The Link on the host for this chain
- ; Override fields
- SecBus UINT8 ? ; < Secondary Bus number for this non-coherent chain
- SubBus UINT8 ? ; < Subordinate Bus number
-OVERRIDE_BUS_NUMBERS ENDS
-
-
- ; Ignore a Link.
-
- ; This interface is checked every time a coherent Link is found and then every
- ; time a non-coherent Link from a CPU is found.
- ; Any coherent or non-coherent Link from a CPU can be ignored and not used
- ; for discovery or initialization. Useful for connection based systems.
- ; (Note: not checked for IO device to IO Device Links.)
-
-IGNORE_LINK STRUCT
- ; Match fields
- Socket UINT8 ? ; < The Socket on which this Link is located
- Link UINT8 ? ; < The Link about to be initialized
- ; Customization fields
- LinkState FINAL_LINK_STATE ? ; < The link may be left unitialized, or powered off.
-IGNORE_LINK ENDS
-
-
- ; Skip reganging of subLinks.
-
- ; This interface is checked whenever two subLinks are both connected to the same CPUs.
- ; Normally, unganged sublinks between the same two CPUs are reganged.
- ; Provide a matching structure to leave the Links unganged.
-
-SKIP_REGANG STRUCT
- ; Match fields
- SocketA UINT8 ? ; < One Socket on which this Link is located
- LinkA UINT8 ? ; < The Link on this Node
- SocketB UINT8 ? ; < The other Socket on which this Link is located
- LinkB UINT8 ? ; < The Link on that Node
- ; Customization fields
- LinkState FINAL_LINK_STATE ? ; < The paired sublink may be active, or powered off.
-SKIP_REGANG ENDS
-
- ; The System Socket layout, which sockets are physically connected.
-
- ; The hardware method for Socket naming is preferred. Use this software method only
- ; if required.
-
-SYSTEM_PHYSICAL_SOCKET_MAP STRUCT
- CurrentSocket UINT8 ? ; < The socket from which this connection originates.
- CurrentLink UINT8 ? ; < The Link from the source socket connects to another socket.
- TargetSocket UINT8 ? ; < The target socket which is connected on that link.
-SYSTEM_PHYSICAL_SOCKET_MAP ENDS
-
-; ----------------------------------------------------------------------------
-
- ; This is the input structure for AmdHtInitialize.
-
-AMD_HT_INTERFACE STRUCT
- ; Basic level customization
- AutoBusStart UINT8 ? ; < For automatic bus number assignment, starting bus number usually zero.
- AutoBusMax UINT8 ? ; < For automatic bus number assignment, do not assign above max.
- AutoBusIncrement UINT8 ? ; < For automatic bus number assignment, each chain gets this many busses.
-
- ; Advanced Level Customization
- ManualBuidSwapList POINTER ? ; < Provide Manual Swap List, if any.
- DeviceCapOverrideList POINTER ? ; < Provide Device Overrides, if any.
- CpuToCpuPcbLimitsList POINTER ? ; < Provide CPU PCB Limits, if any.
- IoPcbLimitsList POINTER ? ; < Provide IO PCB Limits, if any.
- OverrideBusNumbersList POINTER ? ; < Provide manual Bus Number assignment, if any.
- ; < Use either auto bus numbering or override bus
- ; < numbers, not both.
-
- IgnoreLinkList POINTER ? ; < Provide links to ignore, if any.
- SkipRegangList POINTER ? ; < Provide links to remain unganged, if any.
-
- ; Expert Level Customization
- Topolist POINTER ? ; < Use this topology list in addition to the built in, if not NULL.
- SystemPhysicalSocketMap POINTER ?
- ; < The hardware socket naming method is preferred,
- ; < If it can't be used, this provides a software method.
-AMD_HT_INTERFACE ENDS
-
-; -----------------------------------------------------------------------------
-
- ; HT Recovery Interface
-
-
-
-; -----------------------------------------------------------------------------
-; * HT Recovery DEFINITIONS AND MACROS
-; *
-; *-----------------------------------------------------------------------------
-;
-
- ; BBHT subfunction events
- HT_EVENT_BB_EVENTS EQU 10005000h
- HT_EVENT_BB_BUID_EXCEED EQU 10015000h
- HT_EVENT_BB_DEVICE_FAILED EQU 10055000h
- HT_EVENT_BB_AUTO_DEPTH EQU 10065000h
-
-; ----------------------------------------------------------------------------
-; * HT Recovery TYPEDEFS, STRUCTURES, ENUMS
-; *
-; *----------------------------------------------------------------------------
-;
-
-
- ; The Interface structure to Recovery HT.
-
-AMD_HT_RESET_INTERFACE STRUCT
- ManualBuidSwapList POINTER ? ; < Option to manually control SB link init
- Depth UINT32 ? ; < If auto init was used this is set to the depth of the chain,
- ; < else, for manual init unmodified.
-AMD_HT_RESET_INTERFACE ENDS
-
-
-;-----------------------------------------------------------------------------
-; FCH DEFINITIONS AND MACROS
-;
-;-----------------------------------------------------------------------------
-
-; Configuration values for SdConfig
- SdDisable EQU 0 ; Disabled
- SdAmda EQU 1 ; AMDA, set 24,18,16, default
- SdDma EQU 2 ; DMA clear 24, 16, set 18
- SdPio EQU 3 ; PIO clear 24,18,16
-SD_MODE TEXTEQU <DWORD>
-
-; Configuration values for SdClockControl
- Sd50MhzTraceCableLengthWithinSixInches EQU 4 ; 50Mhz, default
- Sd40MhzTraceCableLengthSix2ElevenInches EQU 6 ; 40Mhz
- Sd25MhzTraceCableLengthEleven2TwentyfourInches EQU 7 ; 25Mhz
-SD_CLOCK_CONTROL TEXTEQU <DWORD>
-
-;del ; Configuration values for AzaliaController
-;del AzAuto EQU 0 ; Auto - Detect Azalia controller automatically
-;del AzDisable EQU 1 ; Diable - Disable Azalia controller
-;del AzEnable EQU 2 ; Enable - Enable Azalia controller
-HDA_CONFIG TEXTEQU <DWORD>
-
-; Configuration values for IrConfig
- IrDisable EQU 0 ; Disable
- IrRxTx0 EQU 1 ; Rx and Tx0
- IrRxTx1 EQU 2 ; Rx and Tx1
- IrRxTx0Tx1 EQU 3 ; Rx and both Tx0,Tx1
-IR_CONFIG TEXTEQU <DWORD>
-
-; Configuration values for SataClass
- SataNativeIde EQU 0 ; Native IDE mode
- SataRaid EQU 1 ; RAID mode
- SataAhci EQU 2 ; AHCI mode
- SataLegacyIde EQU 3 ; Legacy IDE mode
- SataIde2Ahci EQU 4 ; IDE->AHCI mode
- SataAhci7804 EQU 5 ; AHCI mode as 7804 ID (AMD driver)
- SataIde2Ahci7804 EQU 6 ; IDE->AHCI mode as 7804 ID (AMD driver)
-SATA_CLASS TEXTEQU <DWORD>
-
-; Configuration values for GppLinkConfig
- PortA4 EQU 0 ; 4:0:0:0
- PortA2B2 EQU 2 ; 2:2:0:0
- PortA2B1C1 EQU 3 ; 2:1:1:0
- PortA1B1C1D1 EQU 4 ; 1:1:1:1
-GPP_LINKMODE TEXTEQU <DWORD>
-
-; Configuration values for FchPowerFail
- AlwaysOff EQU 0 ; Always power off after power resumes
- AlwaysOn EQU 1 ; Always power on after power resumes
- UsePrevious EQU 3 ; Resume to same setting when power fails
-POWER_FAIL TEXTEQU <DWORD>
-
-; Configuration values for SATA Link Speed
- Gen1 EQU 1 ; SATA port GEN1 speed
- Gen2 EQU 2 ; SATA port GEN2 speed
- Gen3 EQU 3 ; SATA port GEN3 speed
-SATA_SPEED TEXTEQU <DWORD>
-
-; Configuration values for GPIO function
- Function0 EQU 0 ; GPIO Function 1
- Function1 EQU 1 ; GPIO Function 1
- Function2 EQU 2 ; GPIO Function 2
- Function3 EQU 3 ; GPIO Function 3
-GPIO_FUN TEXTEQU <DWORD>
-
-; Configuration values for GPIO_CFG
- OwnedByEc EQU 1 ; This bit can only be written by EC
- OwnedByHost EQU 2 ; This bit can only be written by host (BIOS)
- Sticky EQU 4 ; If set, [6:3] are sticky
- PullUpB EQU 8 ; 0: Pullup enable; 1: Pullup disabled
- PullDown EQU 16 ; 0: Pulldown disabled; 1: Pulldown enable
- GpioOutEnB EQU 32 ; 0: Output enable; 1: Output disable
- GpioOut EQU 64 ; Output state when GpioOutEnB is 0
- GpioIn EQU 128 ; This bit is read only - current pin state
-CFG_BYTE TEXTEQU <DWORD>
-
-; FCH GPIO CONTROL
-GPIO_CONTROL STRUCT
- GpioPin UINT8 ? ; Gpio Pin, valid range: 0-67, 128-150, 160-228
- PinFunction GPIO_FUN ? ; Multi-function selection
- CfgByte CFG_BYTE ? ; GPIO Register value
-GPIO_CONTROL ENDS
-
-; FCH SCI MAP CONTROL
-SCI_MAP_CONTROL STRUCT
- InputPin UINT8 ? ; Input Pin, valid range 0-63
- GpeMap UINT8 ? ; Gpe Map, valid range 0-31
-SCI_MAP_CONTROL ENDS
-
-; FCH SATA PHY CONTROL
-SATA_PHY_CONTROL STRUCT
- CommonPhy BOOLEAN ? ; Common PHY or not
- Gen SATA_SPEED ? ; SATA speed
- Port UINT8 ? ; Port number, valid range: 0-7
- PhyData UINT32 ? ; SATA PHY data, valid range: 0-0xFFFFFFFF
-SATA_PHY_CONTROL ENDS
-
-;
-; FCH Component Data Structure in InitReset stage
-;
-FCH_RESET_INTERFACE STRUCT
- UmiGen2 BOOLEAN ? ; Enable Gen2 data rate of UMI
- ; FALSE - Disable Gen2
- ; TRUE - Enable Gen2
-
- SataEnable BOOLEAN ? ; SATA controller function
- ; FALSE - SATA controller is disabled
- ; TRUE - SATA controller is enabled
-
- IdeEnable BOOLEAN ? ; SATA IDE controller mode enabled/disabled
- ; FALSE - IDE controller is disabled
- ; TRUE - IDE controller is enabled
-
- GppEnable BOOLEAN ? ; Master switch of GPP function
- ; FALSE - GPP disabled
- ; TRUE - GPP enabled
-
- Xhci0Enable BOOLEAN ? ; XHCI0 controller function
- ; FALSE - XHCI0 controller disabled
- ; TRUE - XHCI0 controller enabled
-
- Xhci1Enable BOOLEAN ? ; XHCI1 controller function
- ; FALSE - XHCI1 controller disabled
- ; TRUE - XHCI1 controller enabled
-
-FCH_RESET_INTERFACE ENDS
-
-
-;
-; FCH Component Data Structure from InitEnv stage
-;
-FCH_INTERFACE STRUCT
- SdConfig SD_MODE ? ; Secure Digital (SD) controller mode
-;del AzaliaController HDA_CONFIG ? ; Azalia HD Audio Controller
- IrConfig IR_CONFIG ? ; Infrared (IR) Configuration
- UmiGen2 BOOLEAN ? ; Enable Gen2 data rate of UMI
- ; FALSE - Disable Gen2
- ; TRUE - Enable Gen2
- SataClass SATA_CLASS ? ; SATA controller mode
- SataEnable BOOLEAN ? ; SATA controller function
- ; FALSE - SATA controller is disabled
- ; TRUE - SATA controller is enabled
- IdeEnable BOOLEAN ? ; SATA IDE controller mode enabled/disabled
- ; FALSE - IDE controller is disabled
- ; TRUE - IDE controller is enabled
- SataIdeMode BOOLEAN ? ; Native mode of SATA IDE controller
- ; FALSE - Legacy IDE mode
- ; TRUE - Native IDE mode
- Ohci1Enable BOOLEAN ? ; OHCI controller #1 Function
- ; FALSE - OHCI1 is disabled
- ; TRUE - OHCI1 is enabled
- Ohci2Enable BOOLEAN ? ; OHCI controller #2 Function
- ; FALSE - OHCI2 is disabled
- ; TRUE - OHCI2 is enabled
- Ohci3Enable BOOLEAN ? ; OHCI controller #3 Function
- ; FALSE - OHCI3 is disabled
- ; TRUE - OHCI3 is enabled
- Ohci4Enable BOOLEAN ? ; OHCI controller #4 Function
- ; FALSE - OHCI4 is disabled
- ; TRUE - OHCI4 is enabled
- XhciSwitch BOOLEAN ? ; XHCI controller Function
- ; FALSE - XHCI is disabled
- ; TRUE - XHCI is enabled
- GppEnable BOOLEAN ? ; Master switch of GPP function
- ; FALSE - GPP disabled
- ; TRUE - GPP enabled
- FchPowerFail POWER_FAIL ? ; FCH power failure option
-FCH_INTERFACE ENDS
-
-
-; ---------------------------------------------------------------------------
-; CPU Feature related info
-; ---------------------------------------------------------------------------
- ; Build Configuration values for BLDCFG_PLATFORM_C1E_MODE
- C1eModeDisabled EQU 0 ; < Disabled
- C1eModeAuto EQU 1 ; < Auto mode enables the best C1e method for the
- ; < currently installed processor
- C1eModeHardware EQU 2 ; < Hardware method
- C1eModeMsgBased EQU 3 ; < Message-based method
- C1eModeSoftwareDeprecated EQU 4 ; < Deprecated software SMI method
- C1eModeHardwareSoftwareDeprecated EQU 5 ; < Hardware or Deprecated software SMI method
- MaxC1eMode EQU 6 ; < Not a valid value, used for verifying input
-PLATFORM_C1E_MODES TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
- CStateModeDisabled EQU 0 ; < Disabled
- CStateModeC6 EQU 1 ; < C6 State
- MaxCStateMode EQU 2 ; < Not a valid value, used for verifying input
-PLATFORM_CSTATE_MODES TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_PLATFORM_CPB_MODE
- CpbModeAuto EQU 0 ; < Auto
- CpbModeDisabled EQU 1 ; < Disabled
- MaxCpbMode EQU 2 ; < Not a valid value, used for verifying input
-PLATFORM_CPB_MODES TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_LOW_POWER_PSTATE_FOR_PROCHOT_MODE
- LOW_POWER_PSTATE_FOR_PROCHOT_AUTO EQU 0 ; < Auto
- LOW_POWER_PSTATE_FOR_PROCHOT_DISABLE EQU 1 ; < Disabled
- MAX_LOW_POWER_PSTATE_FOR_PROCHOT_MODE EQU 2 ; < Not a valid value, used for verifying input
-PLATFORM_LOW_POWER_PSTATE_MODES TEXTEQU <DWORD>
-
-;----------------------------------------------------------------------------
-; GNB PCIe configuration info
-;----------------------------------------------------------------------------
-
-GNB_EVENT_INVALID_CONFIGURATION EQU 20010000h ; User configuration invalid
-GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION EQU 20010001h ; Requested lane allocation for PCIe port can not be supported
-GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION EQU 20010002h ; Requested incorrect PCIe port device address
-GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION EQU 20010003h ; Incorrect parameter in DDI link configuration
-GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION EQU 20010004h ; Invalid with for PCIe port or DDI link
-GNB_EVENT_INVALID_LANES_CONFIGURATION EQU 20010005h ; Lane double subscribe lanes
-GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION EQU 20010006h ; Requested lane allocation for DDI link(s) can not be supported
-GNB_EVENT_LINK_TRAINING_FAIL EQU 20020000h ; PCIe Link training fail
-GNB_EVENT_BROKEN_LANE_RECOVERY EQU 20030000h ; Broken lane workaround applied to recover link training
-GNB_EVENT_GEN2_SUPPORT_RECOVERY EQU 20040000h ; Scale back to GEN1 to recover link training
-
-DESCRIPTOR_TERMINATE_LIST EQU 80000000h
-DESCRIPTOR_IGNORE EQU 40000000h
-
-; PCIe link initialization
-
-EndpointDetect EQU 0 ;Detect endpoint presence
-EndpointNotPresent EQU 1 ;Endpoint not present (or connected). Used in case there is alternative way to determine
- ;if device present on board or in slot. For example GPIO can be used to determine device presence.
-PCIE_ENDPOINT_STATUS TEXTEQU <DWORD>
-
-PCIe_PORT_MISC_CONTROL STRUCT
- LinkComplianceMode UINT8 ?
- ;IN UINT8 LinkComplianceMode :1; ;< Force port into compliance mode (device will not be trained, port output compliance pattern)
-PCIe_PORT_MISC_CONTROL ENDS
-
-APIC_DEVICE_INFO STRUCT
- GroupMap UINT8 ? ; < Group mapping for slot or endpoint device (connected to PCIE port) interrupts .
- ; 0 - IGNORE THIS STRUCTURE and use recommended settings
- ; 1 - mapped to Grp 0 (Interrupts 0..3 of IO APIC redirection table)
- ; 2 - mapped to Grp 1 (Interrupts 4..7 of IO APIC redirection table)
- ; ...
- ; 8 - mapped to Grp 7 (Interrupts 28..31 of IO APIC redirection table)
- Swizzle UINT8 ? ;< Swizzle interrupt in the Group.
- ; 0 - ABCD
- ; 1 - BCDA
- ; 2 - CDAB
- ; 3 - DABC
- BridgeInt UINT8 ? ; < IOAPIC redirection table entry for PCIE bridge interrupt
- ; 0 - Entry 0 of IO APIC redirection table
- ; 1 - Entry 1 of IO APIC redirection table
- ; ...
- ; 31 - Entry 31 of IO APIC redirection table
-APIC_DEVICE_INFO ENDS
-
-PCIe_PORT_DATA STRUCT
- PortPresent UINT8 ? ; < Enable PCIe port for initialization.
- ChannelType UINT8 ? ; < Channel type.
- ; 0 - "lowLoss",
- ; 1 - "highLoss",
- ; 2 - "mob0db",
- ; 3 - "mob3db",
- ; 4 - "extnd6db"
- ; 5 - "extnd8db"
- ;
- DeviceNumber UINT8 ? ; < Device number for port. Available device numbers may very on different CPUs.
- FunctionNumber UINT8 ? ; < Reserved for future use
- LinkSpeedCapability UINT8 ? ; < Advertised Gen Capability
- ; 0 - Maximum supported by silicon
- ; 1 - Gen1
- ; 2 - Gen2
- ; 3 - Gen3
- ;
- LinkAspm UINT8 ? ; < ASPM control. (see OemPcieLinkAspm for additional option to control ASPM)
- ; 0 - Disabled
- ; 1 - L0s only
- ; 2 - L1 only
- ; 2 - L0s and L1
- ;
- LinkHotplug UINT8 ? ; < Hotplug control.
- ; 0 - Disabled
- ; 1 - Basic
- ; 2 - Server
- ; 3 - Enhanced
- ;
- ResetId UINT8 ? ; < Arbitrary number greater than 0 assigned by platform firmware for GPIO
- ; identification which control reset for given port.
- ; Each port with unique GPIO should have unique ResetId assigned.
- ; All ports use same GPIO to control reset should have same ResetId assigned.
- ; see AgesaPcieSlotResetControl
- ;
- MiscControls PCIe_PORT_MISC_CONTROL {} ; < Misc extended controls
- ApicDeviceInfo APIC_DEVICE_INFO {} ; < IOAPIC device programming info
- EndpointStatus PCIE_ENDPOINT_STATUS ? ; < PCIe endpoint status
-PCIe_PORT_DATA ENDS
-
-;DDI channel lane mapping
-
-CHANNEL_MAPPING STRUCT ;
- Lane0 UINT8 ? ;
- ;IN UINT8 Lane0 :2; ;
- ;IN UINT8 Lane1 :2; ///< Lane 1 mapping (see "Lane 0 mapping")
- ;IN UINT8 Lane2 :2; ///< Lane 2 mapping (see "Lane 0 mapping")
- ;IN UINT8 Lane3 :2; ///< Lane 3 mapping (see "Lane 0 mapping")
-CHANNEL_MAPPING ENDS ;
-
-CONN_CHANNEL_MAPPING UNION
- ChannelMappingValue UINT8 ? ; < Raw lane mapping
- ChannelMapping CHANNEL_MAPPING {} ;
-CONN_CHANNEL_MAPPING ENDS ;
-
-; DDI Configuration
-PCIe_DDI_DATA STRUCT
- ConnectorType UINT8 ? ; < Display Connector Type
- ; 0 - DP
- ; 1 - eDP
- ; 2 - Single Link DVI
- ; 3 - Dual Link DVI
- ; 4 - HDMI
- ; 5 - Travis DP-to-VGA
- ; 6 - Travis DP-to-LVDS
- ; 7 - Hudson-2 NutMeg DP-to-VGA
- ; 8 - Single Link DVI-I
- ; 9 - CRT (VGA)
- ; 10 - LVDS
- ; 11 - VBIOS auto detect connector type
- AuxIndex UINT8 ? ; < Indicates which AUX or DDC Line is used
- ; 0 - AUX1
- ; 1 - AUX2
- ; 2 - AUX3
- ; 3 - AUX4
- ; 4 - AUX5
- ; 5 - AUX6
- ;
- HdpIndex UINT8 ? ; < Indicates which HDP pin is used
- ; 0 - HDP1
- ; 1 - HDP2
- ; 2 - HDP3
- ; 3 - HDP4
- ; 4 - HDP5
- ; 5 - HDP6
- Mapping CONN_CHANNEL_MAPPING (2) DUP ({}) ;< Set specific mapping of lanes to connector pins
- ;Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane
- ;Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only
- ;applicable for Dual DDI link)
- ;if Mapping[x] set to 0 than default mapping assumed
- LanePnInversionMask UINT8 ? ; < Specifies whether to invert the state of P and N for each lane. Each bit represents a PCIe lane on the DDI port
- ; 0 - Do not invert (default)
- ; 1 - Invert P and N on this lane
- Flags UINT8 ? ; < Capabilities flags
- ; Flags bit[0] DDI_DATA_FLAGS_DP1_1_ONLY Selects downgrade PHY link to DP1.1
- ; Flags bit[7:1] Reserved
- ;
-PCIe_DDI_DATA ENDS
-
-
-; Engine Configuration
-PCIe_ENGINE_DATA STRUCT
- EngineType UINT8 ? ; < Engine type
- ; 0 - Ignore engine configuration
- ; 1 - PCIe port
- ; 2 - DDI
- StartLane UINT16 ? ; < Start lane number (in reversed configuration StartLane > EndLane).
- EndLane UINT16 ? ; < End lane number (in reversed configuration StartLane > EndLane).
-PCIe_ENGINE_DATA ENDS
-
-; PCIe port descriptor
-PCIe_PORT_DESCRIPTOR STRUCT
- Flags UINT32 ? ; < Descriptor flags
- ; Bit31 - last descriptor in complex
- EngineData PCIe_ENGINE_DATA {} ; < Engine data
- Port PCIe_PORT_DATA {} ; < PCIe port specific configuration info
-PCIe_PORT_DESCRIPTOR ENDS
-
-; DDI descriptor
-PCIe_DDI_DESCRIPTOR STRUCT
- Flags UINT32 ? ; < Descriptor flags
- EngineData PCIe_ENGINE_DATA {} ; < Engine data
- Ddi PCIe_DDI_DATA {} ; < DDI port specific configuration info
-PCIe_DDI_DESCRIPTOR ENDS
-
-; Slot Reset Info
-PCIe_SLOT_RESET_INFO STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < AGESA Standard Header
- ResetId UINT8 ? ; < Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
- ResetControl UINT8 ? ; < Reset control as defined by PCIE_RESET_CONTROL
-PCIe_SLOT_RESET_INFO ENDS
-
-GFX_VBIOS_IMAGE_FLAG_SPECIAL_POST EQU 001h
-
-; VBIOS image info
-GFX_VBIOS_IMAGE_INFO STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard configuration header
- ImagePtr POINTER ? ; < Pointer to VBIOS image
- GfxPciAddress PCI_ADDR {} ; < PCI address of integrated graphics controller
- Flags UINT32 ? ; < BIT[0] - special repost requred
-GFX_VBIOS_IMAGE_INFO ENDS
-
-; PCIe Complex descriptor
-PCIe_COMPLEX_DESCRIPTOR STRUCT
- Flags UINT32 ? ; < Descriptor flags
- ; Bit31 - last descriptor in topology
- ;
- ;
- SocketId UINT32 ? ; < Socket Id
- PciePortList POINTER ? ;< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
- DdiLinkList POINTER ? ;< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
- Reserved POINTER ? ;< Reserved for future use
-PCIe_COMPLEX_DESCRIPTOR ENDS
-
- AssertSlotReset EQU 0
- DeassertSlotReset EQU 1
-PCIE_RESET_CONTROL TEXTEQU <DWORD>
-
- PcieUnusedEngine EQU 0
- PciePortEngine EQU 1
- PcieDdiEngine EQU 2
- MaxPcieEngine EQU 3 ; < Not a valid value, used for verifying input
-PCIE_ENGINE_TYPE TEXTEQU <DWORD>
-
- PcieGenMaxSupported EQU 0
- PcieGen1 EQU 1
- PcieGen2 EQU 2
- PcieGen3 EQU 3
- MaxPcieGen EQU 4 ; < Not a valid value, used for verifying input
-PCIE_LINK_SPEED_CAP TEXTEQU <DWORD>
-
- PsppDisabled EQU 0
- PsppPerformance EQU 1
- PsppBalanceHigh EQU 2
- PsppBalanceLow EQU 3
- PsppPowerSaving EQU 4
- MaxPspp EQU 5 ; < Not a valid value, used for verifying input
-PCIE_PSPP_POLICY TEXTEQU <DWORD>
-
- ConnectorTypeDP EQU 0
- ConnectorTypeEDP EQU 1
- ConnectorTypeSingleLinkDVI EQU 2
- ConnectorTypeDualLinkDVI EQU 3
- ConnectorTypeHDMI EQU 4
- ConnectorTypeTravisDpToVga EQU 5
- ConnectorTypeTravisDpToLvds EQU 6
- ConnectorTypeNutmegDpToVga EQU 7
- ConnectorTypeSingleLinkDviI EQU 8
- ConnectorTypeCrt EQU 9
- ConnectorTypeLvds EQU 10
- ConnectorTypeEDPToLvds EQU 11
- ConnectorTypeEDPToRealtecLvds EQU 12
- ConnectorTypeAutoDetect EQU 13
- MaxConnectorType EQU 14 ; < Not a valid value, used for verifying input
-PCIE_CONNECTOR_TYPE TEXTEQU <DWORD>
-
- ChannelTypeLowLoss EQU 0
- ChannelTypeHighLoss EQU 1
- ChannelTypeMob0db EQU 2
- ChannelTypeMob3db EQU 3
- ChannelTypeExt6db EQU 4
- ChannelTypeExt8db EQU 5
- MaxChannelType EQU 6 ; < Not a valid value, used for verifying input
-PCIE_CHANNEL_TYPE TEXTEQU <DWORD>
-
- AspmDisabled EQU 0
- AspmL0s EQU 1
- AspmL1 EQU 2
- AspmL0sL1 EQU 3
- MaxAspm EQU 4 ; < Not a valid value, used for verifying input
-PCIE_ASPM_TYPE TEXTEQU <DWORD>
-
- HotplugDisabled EQU 0
- HotplugBasic EQU 1
- HotplugServer EQU 2
- HotplugEnhanced EQU 3
- HotplugInboard EQU 4
- MaxHotplug EQU 5 ; < Not a valid value, used for verifying input
-PCIE_HOTPLUG_TYPE TEXTEQU <DWORD>
-
- PortDisabled EQU 0
- PortEnabled EQU 1
-PCIE_PORT_ENABLE TEXTEQU <DWORD>
-
- Aux1 EQU 0
- Aux2 EQU 1
- Aux3 EQU 2
- Aux4 EQU 3
- Aux5 EQU 4
- Aux6 EQU 5
- MaxAux EQU 6 ; < Not a valid value, used for verifying input
-PCIE_AUX_TYPE TEXTEQU <DWORD>
-
- Hdp1 EQU 0
- Hdp2 EQU 1
- Hdp3 EQU 2
- Hdp4 EQU 3
- Hdp5 EQU 4
- Hdp6 EQU 5
- MaxHdp EQU 6 ; < Not a valid value, used for verifying input
-PCIE_HDP_TYPE TEXTEQU <DWORD>
-
-;PCIe_DDI_DATA.Flags definitions
-DDI_DATA_FLAGS_DP1_1_ONLY EQU 01h ; < BIT[0] Selects downgrade PHY link to DP1.1
-
-;IOMMU requestor ID
-IOMMU_REQUESTOR_ID STRUCT
- Bus UINT16 ? ; <[15:8] - Bus number, [7:3] - Device number, [2:0] - Function number
-IOMMU_REQUESTOR_ID ENDS
-
-;IVMD exclusion range descriptor
-IOMMU_EXCLUSION_RANGE_DESCRIPTOR STRUCT
- Flags UINT32 ? ; Descriptor flags
- ; @li @b Flags[31] - Terminate descriptor array.
- ; @li @b Flags[30] - Ignore descriptor.
- RequestorIdStart IOMMU_REQUESTOR_ID {} ; Requestor ID start
- RequestorIdEnd IOMMU_REQUESTOR_ID {} ; Requestor ID end (use same as start for single ID)
- RangeBaseAddress UINT64 ? ; Phisical base address of exclusion range
- RangeLength UINT64 ? ; Length of exclusion range in bytes
-IOMMU_EXCLUSION_RANGE_DESCRIPTOR ENDS
-
-;----------------------------------------------------------------------------
-; GNB configuration info
-;----------------------------------------------------------------------------
-;
-
-; LVDS Misc Control Field
-LVDS_MISC_CONTROL_FIELD STRUCT
- FpdiMode UINT8 ?
- ;IN UINT8 FpdiMode:1;
- ;IN UINT8 DlChSwap:1;
- ;IN UINT8 VsyncActiveLow:1;
- ;IN UINT8 HsyncActiveLow:1;
- ;IN UINT8 BLONActiveLow:1;
- ;IN UINT8 TravisLvdsVolOverwriteEn:1;
- ;IN UINT8 Reserved:2;
-LVDS_MISC_CONTROL_FIELD ENDS
-
-; LVDS Misc Control
-LVDS_MISC_CONTROL UNION
- Field LVDS_MISC_CONTROL_FIELD {}
- Value UINT8 ?
-LVDS_MISC_CONTROL ENDS
-
-; Display Misc Control Field
-DISPLAY_MISC_CONTROL_FIELD STRUCT
- Reserved1 UINT8 ?
- ;IN UINT8 Reserved1:3;
- ;IN UINT8 VbiosFastBootEn:1;
- ;IN UINT8 Reserved2:4;
-DISPLAY_MISC_CONTROL_FIELD ENDS
-
-; Display Misc Control
-DISPLAY_MISC_CONTROL UNION
- Field DISPLAY_MISC_CONTROL_FIELD {}
- Value UINT8 ?
-DISPLAY_MISC_CONTROL ENDS
-
-; Configuration settings for GNB.
-GNB_POST_CONFIGURATION STRUCT
- IgpuEnableDisablePolicy UINT8 ? ; This item defines the iGPU Enable/Disable policy
- ; @li 0 = Auto - use existing default -
- ; @li 1 = Disable iGPU if any PCIe/PCI graphics card present
-GNB_POST_CONFIGURATION ENDS
-
- IGPU_DISABLE_AUTO EQU 0 ; Auto setting - disable iGPU if ANY PCI graphics or non-AMD PCIe graphics
- IGPU_DISABLE_ANY_PCIE EQU 1 ; Disable iGPU if any PCI or PCIE graphics card is present
-
-
-; Configuration settings for GNB.
-GNB_ENV_CONFIGURATION STRUCT
- Gnb3dStereoPinIndex UINT8 ? ;< 3D Stereo Pin ID.
- ; @li 0 = Stereo 3D is disabled (default).
- ; @li 1 = Use processor pin HPD1.
- ; @li 2 = Use processor pin HPD2
- ; @li 3 = Use processor pin HPD3
- ; @li 4 = Use processor pin HPD4
- ; @li 5 = Use processor pin HPD5
- ; @li 6 = Use processor pin HPD6
- IommuSupport BOOLEAN ? ; IOMMU support.
- ; TRUE = Disable and hide IOMMU device.
- ; FLASE = Initialize IOMMU subsystem. Generate ACPI IVRS table.
- LvdsSpreadSpectrum UINT16 ? ; Spread spectrum value in 0.01 %
- LvdsSpreadSpectrumRate UINT16 ? ; Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
- LvdsPowerOnSeqDigonToDe UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqDeToVaryBl UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqDeToDigon UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqVaryBlToDe UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqOnToOffDelay UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqVaryBlToBlon UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqBlonToVaryBl UINT8 ? ; This item configures panel initialization timing.
- LvdsMaxPixelClockFreq UINT16 ? ; This item configures the maximum pixel clock frequency supported.
- LcdBitDepthControlValue UINT32 ? ; This item configures the LCD bit depth control settings.
- Lvds24bbpPanelMode UINT8 ? ; This item configures the LVDS 24 BBP mode.
- LvdsMiscControl LVDS_MISC_CONTROL {} ; This item configures LVDS swap/Hsync/Vsync/BLON
- PcieRefClkSpreadSpectrum UINT16 ? ; Spread spectrum value in 0.01 %
- GnbRemoteDisplaySupport BOOLEAN ? ; This item enables Wireless Display Support
- LvdsMiscVoltAdjustment UINT8 ? ; Travis register LVDS_CTRL_4 to adjust LVDS output voltage
- DisplayMiscControl DISPLAY_MISC_CONTROL {} ; This item configures display misc control
-GNB_ENV_CONFIGURATION ENDS
-
-; Configuration settings for GNB.
-GNB_MID_CONFIGURATION STRUCT
- iGpuVgaMode UINT8 ? ; < VGA resourses decoding configuration for iGPU
- ; < @li 0 = iGPU decode all VGA resourses (must be promary VGA adapter)
- ; < @li 1 = iGPU will not decode any VGA resourses (must be secondary graphics adapter)
-GNB_MID_CONFIGURATION ENDS
-
-; GNB configuration info
-GNB_CONFIGURATION STRUCT
- PcieComplexList POINTER ? ; Pointer to array of PCIe_COMPLEX_DESCRIPTOR structures describe PCIe topology on each processor package or NULL.
- ; Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST
- ;
- ;
- ;
- ; Topology organization definition assume PCIe_COMPLEX_DESCRIPTOR defined first following
- ; PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR for given PCIe_COMPLEX_DESCRIPTOR
- ; defined in arbitrary sequence:
- ; Example of topology definition for single socket system:
- ; PlatfromTopology LABEL DWORD
- ;
- ; Port0_2 PCIe_PORT_DESCRIPTOR <>;
- ; Port0_3 PCIe_PORT_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST> ;
- ; ...
- ; Ddi0_A PCIe_DDI_DESCRIPTOR <>;
- ; Ddi0_B PCIe_DDI_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST,>;
- ; ...
- ; Cpu0 PCIe_COMPLEX_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST, 0, Port0_2, Ddi0_A>
- ;
- ;
- PsppPolicy UINT8 ? ;< PSPP (PCIe Speed Power Policy)
- ; @li @b 0 - Disabled
- ; @li @b 1 - Performance
- ; @li @b 2 - Balance-High
- ; @li @b 3 - Balance-Low
- ; @li @b 4 - Power Saving
- ;
-GNB_CONFIGURATION ENDS
-
-; ---------------------------------------------------------------------------
-
-; MEMORY-SPECIFIC DATA STRUCTURES
-
-; ---------------------------------------------------------------------------
-
-
- ; AGESA MAXIMIUM VALUES
-
- ; These Max values are used to define array sizes and associated loop
- ; counts in the code. They reflect the maximum values that AGESA
- ; currently supports and does not necessarily reflect the hardware
- ; capabilities of configuration.
-
-
- MAX_SOCKETS_SUPPORTED EQU 8 ; < Max number of sockets in system
- MAX_CHANNELS_PER_SOCKET EQU 4 ; < Max Channels per sockets
- MAX_DIMMS_PER_CHANNEL EQU 4 ; < Max DIMMs on a memory channel (independent of platform)
- NUMBER_OF_DELAY_TABLES EQU 9 ; < Number of tables defined in CH_DEF_STRUCT.
- ; < Eg: UINT16 *RcvEnDlys;
- ; < UINT8 *WrDqsDlys;
- ; < UINT8 *RdDqsDlys;
- ; < UINT8 *WrDatDlys;
- ; < UINT8 *RdDqsMinDlys;
- ; < UINT8 *RdDqsMaxDlys;
- ; < UINT8 *WrDatMinDlys;
- ; < UINT8 *WrDatMaxDlys;
- NUMBER_OF_FAILURE_MASK_TABLES EQU 1 ; < Number of failure mask tables
- MAX_PLATFORM_TYPES EQU 16 ; < Platform types per system
-
- MCT_TRNG_KEEPOUT_START EQU 00004000h ; < base [39:8]
- MCT_TRNG_KEEPOUT_END EQU 00007FFFh ; < base [39:8]
-
- UMA_ATTRIBUTE_INTERLEAVE EQU 80000000h ; < Uma Region is interleaved
- UMA_ATTRIBUTE_ON_DCT0 EQU 40000000h ; < UMA resides on memory that belongs to DCT0
- UMA_ATTRIBUTE_ON_DCT1 EQU 20000000h ; < UMA resides on memory that belongs to DCT1
-
- PSO_TABLE TEXTEQU <UINT8>; < Platform Configuration Table
-
- ; AGESA DEFINITIONS
-
- ; Many of these are derived from the platform and hardware specific definitions
-
- ; EccSymbolSize override value
- ECCSYMBOLSIZE_USE_BKDG EQU 0 ; < Use BKDG Recommended Value
- ECCSYMBOLSIZE_FORCE_X4 EQU 4 ; < Force to x4
- ECCSYMBOLSIZE_FORCE_X8 EQU 8 ; < Force to x8
- ; CPU Package Type
- PT_L1 EQU 0 ; < L1 Package type
- PT_M2 EQU 1 ; < AM Package type
- PT_S1 EQU 2 ; < S1 Package type
-
- ; Structures use to pass system Logical CPU-ID
-CPU_LOGICAL_ID STRUCT
- Family UINT64 ? ; < Indicates logical ID Family
- Revision UINT64 ? ; < Indicates logical ID Family
-CPU_LOGICAL_ID ENDS
-
- ; Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
-
- AMD_PLATFORM_SERVER EQU 8000h ; < Server
- AMD_PLATFORM_DESKTOP EQU 10000h ; < Desktop
- AMD_PLATFORM_MOBILE EQU 20000h ; < Mobile
-AMD_PLATFORM_TYPE TEXTEQU <DWORD>
-
- ; Dram technology type
-
- DDR2_TECHNOLOGY EQU 0 ; < DDR2 technology
- DDR3_TECHNOLOGY EQU 1 ; < DDR3 technology
-TECHNOLOGY_TYPE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
-
- DDR400_FREQUENCY EQU 200 ; < DDR 400
- DDR533_FREQUENCY EQU 266 ; < DDR 533
- DDR667_FREQUENCY EQU 333 ; < DDR 667
- DDR800_FREQUENCY EQU 400 ; < DDR 800
- DDR1066_FREQUENCY EQU 533 ; < DDR 1066
- DDR1333_FREQUENCY EQU 667 ; < DDR 1333
- DDR1600_FREQUENCY EQU 800 ; < DDR 1600
- DDR1866_FREQUENCY EQU 933 ; < DDR 1866
- DDR2100_FREQUENCY EQU 1050 ; < DDR 2100
- DDR2133_FREQUENCY EQU 1066 ; < DDR 2133
- DDR2400_FREQUENCY EQU 1200 ; < DDR 2400
- UNSUPPORTED_DDR_FREQUENCY EQU 1201 ; < Highest limit of DDR frequency
-MEMORY_BUS_SPEED TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
-
- QUADRANK_REGISTERED EQU 0
- QUADRANK_UNBUFFERED EQU 1
-QUANDRANK_TYPE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_TIMING_MODE_SELECT
-
- TIMING_MODE_AUTO EQU 0 ; < Use best rate possible
- TIMING_MODE_LIMITED EQU 1 ; < Set user top limit
- TIMING_MODE_SPECIFIC EQU 2 ; < Set user specified speed
-USER_MEMORY_TIMING_MODE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_POWER_DOWN_MODE
-
- POWER_DOWN_BY_CHANNEL EQU 0
- POWER_DOWN_BY_CHIP_SELECT EQU 1
- POWER_DOWN_AUTO EQU 2
-POWER_DOWN_MODE TEXTEQU <DWORD>
-
- ; Low voltage support
-
- VOLT_INITIAL EQU 0 ; < Initial value for VDDIO
- VOLT1_5 EQU 1 ; < 1.5 Volt
- VOLT1_35 EQU 2 ; < 1.35 Volt
- VOLT1_25 EQU 3 ; < 1.25 Volt
- VOLT_UNSUPPORTED EQU 0FFh ; < No common voltage found
-DIMM_VOLTAGE TEXTEQU <DWORD>
-
- ; UMA Mode
-
- UMA_NONE EQU 0 ; < UMA None
- UMA_SPECIFIED EQU 1 ; < UMA Specified
- UMA_AUTO EQU 2 ; < UMA Auto
-UMA_MODE TEXTEQU <DWORD>
-
- ; Force Training Mode
-
-;del FORCE_TRAIN_1D EQU 0 ; < 1D Training only
- FORCE_TRAIN_2D EQU 1 ; < 2D Training only
- FORCE_TRAIN_AUTO EQU 2 ; < Auto - 1D or 2D depending on configuration
-FORCE_TRAIN_MODE TEXTEQU <DWORD>
-
-; The possible DRAM prefetch mode settings.
- DRAM_PREFETCHER_AUTO EQU 0 ; Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
- DISABLE_DRAM_PREFETCH_FOR_IO EQU 1 ; Disable DRAM prefetching for I/O requests only.
- DISABLE_DRAM_PREFETCH_FOR_CPU EQU 2 ; Disable DRAM prefetching for requests from processor cores only.
- DISABLE_DRAM_PREFETCHER EQU 3 ; Disable DRAM prefetching.
- MAX_DRAM_FREFETCH_MODE EQU 4 ; Not a DRAM prefetch mode, use for limit checking.
-DRAM_PREFETCH_MODE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_UMA_ALIGNMENT
-
- NO_UMA_ALIGNED EQU 00FFFFFFh
- UMA_4MB_ALIGNED EQU 00FFFFC0h
- UMA_128MB_ALIGNED EQU 00FFF800h
- UMA_256MB_ALIGNED EQU 00FFF000h
- UMA_512MB_ALIGNED EQU 00FFE000h
-UMA_ALIGNMENT TEXTEQU <DWORD>
- ; ===============================================================================
- ; Global MCT Configuration Status Word (GStatus)
- ; ===============================================================================
-
- GsbMTRRshort EQU 0 ; < Ran out of MTRRs while mapping memory
- GsbAllECCDimms EQU 1 ; < All banks of all Nodes are ECC capable
- GsbDramECCDis EQU 2 ; < Dram ECC requested but not enabled.
- GsbSoftHole EQU 3 ; < A Node Base gap was created
- GsbHWHole EQU 4 ; < A HW dram remap was created
- GsbNodeIntlv EQU 5 ; < Node Memory interleaving was enabled
- GsbSpIntRemapHole EQU 6 ; < Special condition for Node Interleave and HW remapping
- GsbEnDIMMSpareNW EQU 7 ; < Indicates that DIMM Spare can be used without a warm reset
-
- GsbEOL EQU 8 ; < End of list
-GLOBAL_STATUS_FIELD TEXTEQU <DWORD>
-
-; ===============================================================================
- ; Local Error Status (DIE_STRUCT.ErrStatus[31:0])
-; ===============================================================================
-
- EsbNoDimms EQU 0 ; < No DIMMs
- EsbSpdChkSum EQU 1 ; < SPD Checksum fail
- EsbDimmMismatchM EQU 2 ; < dimm module type(buffer) mismatch
- EsbDimmMismatchT EQU 3 ; < dimm CL/T mismatch
- EsbDimmMismatchO EQU 4 ; < dimm organization mismatch (128-bit)
- EsbNoTrcTrfc EQU 5 ; < SPD missing Trc or Trfc info
- EsbNoCycTime EQU 6 ; < SPD missing byte 23 or 25
- EsbBkIntDis EQU 7 ; < Bank interleave requested but not enabled
- EsbDramECCDis EQU 8 ; < Dram ECC requested but not enabled
- EsbSpareDis EQU 9 ; < Online spare requested but not enabled
- EsbMinimumMode EQU 10 ; < Running in Minimum Mode
- EsbNoRcvrEn EQU 11 ; < No DQS Receiver Enable pass window found
- EsbSmallRcvr EQU 12 ; < DQS Rcvr En pass window too small (far right of dynamic range)
- EsbNoDqsPos EQU 13 ; < No DQS-DQ passing positions
- EsbSmallDqs EQU 14 ; < DQS-DQ passing window too small
- EsbDCBKScrubDis EQU 15 ; < DCache scrub requested but not enabled
-
- EsbEMPNotSupported EQU 16 ; < Processor is not capable for EMP.
- EsbEMPConflict EQU 17 ; < EMP requested but cannot be enabled since
- ; < channel interleaving, bank interleaving, or bank swizzle is enabled.
- EsbEMPDis EQU 18 ; < EMP requested but cannot be enabled since
- ; < memory size of each DCT is not a power of two.
-
- EsbEOL EQU 19 ; < End of list
-ERROR_STATUS_FIELD TEXTEQU <DWORD>
-
-; ===============================================================================
- ; Local Configuration Status (DIE_STRUCT.Status[31:0])
-; ===============================================================================
-
- SbRegistered EQU 0 ; < All DIMMs are Registered
- SbEccDimms EQU 1 ; < All banks ECC capable
- SbParDimms EQU 2 ; < All banks Addr/CMD Parity capable
- SbDiagClks EQU 3 ; < Jedec ALL slots clock enable diag mode
- Sb128bitmode EQU 4 ; < DCT in 128-bit mode operation
- Sb64MuxedMode EQU 5 ; < DCT in 64-bit mux'ed mode.
- Sb2TMode EQU 6 ; < 2T CMD timing mode is enabled.
- SbSWNodeHole EQU 7 ; < Remapping of Node Base on this Node to create a gap.
- SbHWHole EQU 8 ; < Memory Hole created on this Node using HW remapping.
- SbOver400Mhz EQU 9 ; < DCT freq greater than or equal to 400MHz flag
- SbDQSPosPass2 EQU 10 ; < Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
- SbDQSRcvLimit EQU 11 ; < Used for DQSRcvEnTrain to know we have reached the upper bound.
- SbExtConfig EQU 12 ; < Indicate the default setting for extended PCI configuration support
- SbLrdimms EQU 13 ; < All DIMMs are LRDIMMs
- SbEOL EQU 14 ; < End of list
-LOCAL_STATUS_FIELD TEXTEQU <DWORD>
-
-
-; < CPU MSR Register definitions ------------------------------------------
- SYS_CFG EQU 0C0010010h
- TOP_MEM EQU 0C001001Ah
- TOP_MEM2 EQU 0C001001Dh
- HWCR EQU 0C0010015h
- NB_CFG EQU 0C001001Fh
-
- FS_BASE EQU 0C0000100h
- IORR0_BASE EQU 0C0010016h
- IORR0_MASK EQU 0C0010017h
- BU_CFG EQU 0C0011023h
- BU_CFG2 EQU 0C001102Ah
- COFVID_STAT EQU 0C0010071h
- TSC EQU 10h
-
-; ===============================================================================
- ; SPD Data for each DIMM
-; ===============================================================================
-SPD_DEF_STRUCT STRUCT
- DimmPresent BOOLEAN ? ; < Indicates that the DIMM is present and Data is valid
- Data UINT8 (256) DUP (?) ; < Buffer for 256 Bytes of SPD data from DIMM
-SPD_DEF_STRUCT ENDS
-
-; ===============================================================================
- ; Channel Definition Structure
- ; This data structure defines entries that are specific to the channel initialization
-; ===============================================================================
-CH_DEF_STRUCT STRUCT
- ChannelID UINT8 ? ; < Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
- TechType TECHNOLOGY_TYPE ? ; < Technology type of this channel
- ChDimmPresent UINT8 ? ; < For each bit n 0..7, 1 = DIMM n is present.
- ; < DIMM# Select Signal
- ; < 0 MA0_CS_L[0, 1]
- ; < 1 MB0_CS_L[0, 1]
- ; < 2 MA1_CS_L[0, 1]
- ; < 3 MB1_CS_L[0, 1]
- ; < 4 MA2_CS_L[0, 1]
- ; < 5 MB2_CS_L[0, 1]
- ; < 6 MA3_CS_L[0, 1]
- ; < 7 MB3_CS_L[0, 1]
-
- DCTPtr POINTER ? ; < Pointer to the DCT data of this channel.
- MCTPtr POINTER ? ; < Pointer to the node data of this channel.
- SpdPtr POINTER ? ; < Pointer to the SPD data for this channel. (Setup by NB Constructor)
- DimmSpdPtr POINTER (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Array of pointers to
- ; < SPD Data for each Dimm. (Setup by Tech Block Constructor)
- ChDimmValid UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved.
- RegDimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved.
- LrDimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
- SODimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is a SO-DIMM where 4..7 are reserved.
- Loads UINT8 ? ; < Number of devices loading bus
- Dimms UINT8 ? ; < Number of DIMMs loading Channel
- Ranks UINT8 ? ; < Number of ranks loading Channel DATA
- SlowMode BOOLEAN ? ; < 1T or 2T CMD mode (slow access mode)
- ; < FALSE = 1T
- ; < TRUE = 2T
- ; < The following pointers will be pointed to dynamically allocated buffers.
- ; < Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
- ; < Example: If DIMM and Byte based training, then
- ; < XX is a value in Hex
- ; < BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
- ; < Row1 - Logical DIMM0 XX XX XX XX XX XX XX XX XX
- ; < Row2 - Logical DIMM1 XX XX XX XX XX XX XX XX XX
- RcvEnDlys POINTER ? ; < DQS Receiver Enable Delays
- WrDqsDlys POINTER ? ; < Write DQS delays (only valid for DDR3)
- RdDqsDlys POINTER ? ; < Read Dqs delays
- WrDatDlys POINTER ? ; < Write Data delays
- RdDqs2dDlys POINTER ? ; < 2d Read DQS data
- RdDqsMinDlys POINTER ? ; < Minimum Window for Read DQS
- RdDqsMaxDlys POINTER ? ; < Maximum Window for Read DQS
- WrDatMinDlys POINTER ? ; < Minimum Window for Write data
- WrDatMaxDlys POINTER ? ; < Maximum Window for Write data
- RcvEnDlysMemPs1 POINTER ? ; < DQS Receiver Enable Delays for Memory Pstate 1
- WrDqsDlysMemPs1 POINTER ? ; < Write DQS delays for Memory Pstate 1 (only valid for DDR3)
- RdDqsDlysMemPs1 POINTER ? ; < Read Dqs delays for Memory Pstate 1
- WrDatDlysMemPs1 POINTER ? ; < Write Data delays for Memory Pstate 1
- RdDqs2dDlysMemPs1 POINTER ? ; < 2d Read DQS data for Memory Pstate 1
- RdDqsMinDlysMemPs1 POINTER ? ; < Minimum Window for Read DQS for Memory Pstate 1
- RdDqsMaxDlysMemPs1 POINTER ? ; < Maximum Window for Read DQS for Memory Pstate 1
- WrDatMinDlysMemPs1 POINTER ? ; < Minimum Window for Write data for Memory Pstate 1
- WrDatMaxDlysMemPs1 POINTER ? ; < Maximum Window for Write data for Memory Pstate 1
- RowCount UINT8 ? ; < Number of rows of the allocated buffer.
- ColumnCount UINT8 ? ; < Number of columns of the allocated buffer.
-
- FailingBitMask POINTER ? ; < Table of masks to Track Failing bits
- FailingBitMaskMemPs1 POINTER ? ; < Table of masks to Track Failing bits for Memory Pstate 1
- DctOdcCtl UINT32 ? ; < Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
- DctAddrTmg UINT32 ? ; < Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
- PhyRODTCSLow UINT32 ? ; < Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h)
- PhyRODTCSHigh UINT32 ? ; < Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h)
- PhyWODTCSLow UINT32 ? ; < Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h)
- PhyWODTCSHigh UINT32 ? ; < Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183)
- PhyWLODT UINT8 (4) DUP (?) ; < Write Levelization ODT Pattern for Dimm 0-3 or CS 0-7(see BKDG FN2:Offset 9Ch, index 0x8[11:8])
- DctEccDqsLike UINT16 ? ; < DCT DQS ECC UINT8 like...
- DctEccDqsScale UINT8 ? ; < DCT DQS ECC UINT8 scale
- PtrPatternBufA UINT16 ? ; < Ptr on stack to aligned DQS testing pattern
- PtrPatternBufB UINT16 ? ; < Ptr on stack to aligned DQS testing pattern
- ByteLane UINT8 ? ; < Current UINT8 Lane (0..7)
- Direction UINT8 ? ; < Current DQS-DQ training write direction (0=read, 1=write)
- Pattern UINT8 ? ; < Current pattern
- DqsDelay UINT8 ? ; < Current DQS delay value
- HostBiosSrvc1 UINT16 ? ; < UINT16 sized general purpose field for use by host BIOS. Scratch space.
- HostBiosSrvc2 UINT32 ? ; < UINT32 sized general purpose field for use by host BIOS. Scratch space.
- DctMaxRdLat UINT16 (4) DUP (?) ; < Max Read Latency (ns) for the DCT
- ; < DctMaxRdLat [i] is for NBPstate i DIMMValidCh UINT8 ? ; < DIMM# in CH
- DIMMValidCh UINT8 ? ; < DIMM# in CH
- MaxCh UINT8 ? ; < Max number of CH in system
- Dct UINT8 ? ; < Dct pointer
- WrDatGrossH UINT8 ? ; < Write Data Gross delay high value
- DqsRcvEnGrossL UINT8 ? ; < DQS Receive Enable Gross Delay low
-
- TrwtWB UINT8 ? ; < Non-SPD timing value for TrwtWB
- CurrRcvrDctADelay UINT8 ? ; < for keep current RcvrEnDly
- T1000 UINT16 ? ; < get the T1000 figure (cycle time (ns) * 1K)
- DqsRcvEnPass UINT8 ? ; < for TrainRcvrEn UINT8 lane pass flag
- DqsRcvEnSaved UINT8 ? ; < for TrainRcvrEn UINT8 lane saved flag
- SeedPass1Remainder UINT8 ? ; < for Phy assisted DQS receiver enable training
-
- ClToNbFlag UINT8 ? ; < is used to restore ClLinesToNbDis bit after memory
- NodeSysBase UINT32 ? ; < for channel interleave usage
- RefRawCard UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Array of rawcards detected
- CtrlWrd02 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 2 values per DIMM
- CtrlWrd03 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 3 values per DIMM
- CtrlWrd04 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 4 values per DIMM
- CtrlWrd05 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 5 values per DIMM
- CtrlWrd08 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 8 values per DIMM
-
- CsPresentDCT UINT16 ? ; < For each bit n 0..7, 1 = Chip-select n is present
- DimmMirrorPresent UINT8 ? ; < For each bit n 0..7, 1 = DIMM n is OnDimmMirror capable
- DimmSpdCse UINT8 ? ; < For each bit n 0..7, 1 = DIMM n SPD checksum error
- DimmExclude UINT8 ? ; < For each bit n 0..7, 1 = DIMM n gets excluded
- DimmYr06 UINT8 ? ; < Bitmap indicating which Dimms have a manufacturer's year code <= 2006
- DimmWk2406 UINT8 ? ; < Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
- DimmPlPresent UINT8 ? ; < Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
- DimmQrPresent UINT8 ? ; < QuadRank DIMM present?
- DimmDrPresent UINT8 ? ; < Bitmap indicating that Dual Rank Dimms are present
- DimmSRPresent UINT8 ? ; < Bitmap indicating that Single Rank Dimms are present
- Dimmx4Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved.
- Dimmx8Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved.
- Dimmx16Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved.
- LrdimmPhysicalRanks UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Number of Physical Ranks for LRDIMMs
- LrDimmLogicalRanks UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Number of LRDIMM Logical ranks in this configuration
- LrDimmRankMult UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Rank Multipication factor per dimm.
- DimmNibbleAccess UINT8 ? ; < For each bit n 0..3, 1 = DIMM n will use nibble signaling. Where 4..7 are reserved.
- MemClkDisMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
- ; < base on this array to disable unused MemClk to save power.
- ; <
- ; < The array must have 8 entries. Each entry, which associates with
- ; < one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
- ; < Example:
- ; < BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package
- ; < is like below:
- ; < Bit AM3/S1g3 pin name
- ; < 0 M[B,A]_CLK_H/L[0]
- ; < 1 M[B,A]_CLK_H/L[1]
- ; < 2 M[B,A]_CLK_H/L[2]
- ; < 3 M[B,A]_CLK_H/L[3]
- ; < 4 M[B,A]_CLK_H/L[4]
- ; < 5 M[B,A]_CLK_H/L[5]
- ; < 6 M[B,A]_CLK_H/L[6]
- ; < 7 M[B,A]_CLK_H/L[7]
- ; < And platform has the following routing:
- ; < CS0 M[B,A]_CLK_H/L[4]
- ; < CS1 M[B,A]_CLK_H/L[2]
- ; < CS2 M[B,A]_CLK_H/L[3]
- ; < CS3 M[B,A]_CLK_H/L[5]
- ; < Then MemClkDisMap should be pointed to the following array:
- ; < CLK_2 CLK_3 CLK_4 CLK_5
- ; < 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00
- ; < Each entry of the array is the bitmask of 8 chip selects.
-
- CKETriMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of CKE pins to the DIMMs' ranks.
- ; < The array must have 2 entries. Each entry, which associates with
- ; < one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
- ; < AGESA will base on this array to disable unused CKE pins to save power.
-
- ODTTriMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of ODT pins to the DIMMs' ranks.
- ; < The array must have 4 entries. Each entry, which associates with
- ; < one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
- ; < AGESA will base on this array to disable unused ODT pins to save power.
-
- ChipSelTriMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of chip select pins to the DIMMs' ranks.
- ; < The array must have 8 entries. Each entry is a bitmap of 8 CS.
- ; < AGESA will base on this array to disable unused Chip select pins to save power.
-
- ExtendTmp BOOLEAN ? ; < If extended temperature is supported on all dimms on a channel.
-
- MaxVref UINT8 ? ; < Maximum Vref Value for channel
-
- Reserved UINT8 (100) DUP (?) ; < Reserved
-CH_DEF_STRUCT ENDS
-
-; ===============================================================================
- ; DCT Channel Timing Parameters
- ; This data structure sets timings that are specific to the channel
-; ===============================================================================
-CH_TIMING_STRUCT STRUCT
- DctDimmValid UINT16 ? ; < For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved.
- DimmMirrorPresent UINT16 ? ; < For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved.
- DimmSpdCse UINT16 ? ; < For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved.
- DimmExclude UINT16 ? ; < For each bit n 0..3, 1 = DIMM n gets excluded because of no common voltage is found
- CsPresent UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is present
- CsEnabled UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is enabled
- CsTestFail UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is present but disabled
- CsTrainFail UINT16 ? ; < Bitmap showing which chipselects failed training
- DIMM1KPage UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved.
- DimmQrPresent UINT16 ? ; < QuadRank DIMM present?
- DimmDrPresent UINT16 ? ; < Bitmap indicating that Dual Rank Dimms are present
- DimmSRPresent UINT8 ? ; < Bitmap indicating that Single Rank Dimms are present
- Dimmx4Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved.
- Dimmx8Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved.
- Dimmx16Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved.
-
- DIMMTrcd UINT16 ? ; < Minimax Trcd*40 (ns) of DIMMs
- DIMMTrp UINT16 ? ; < Minimax Trp*40 (ns) of DIMMs
- DIMMTrtp UINT16 ? ; < Minimax Trtp*40 (ns) of DIMMs
- DIMMTras UINT16 ? ; < Minimax Tras*40 (ns) of DIMMs
- DIMMTrc UINT16 ? ; < Minimax Trc*40 (ns) of DIMMs
- DIMMTwr UINT16 ? ; < Minimax Twr*40 (ns) of DIMMs
- DIMMTrrd UINT16 ? ; < Minimax Trrd*40 (ns) of DIMMs
- DIMMTwtr UINT16 ? ; < Minimax Twtr*40 (ns) of DIMMs
- DIMMTfaw UINT16 ? ; < Minimax Tfaw*40 (ns) of DIMMs
- TargetSpeed UINT16 ? ; < Target DRAM bus speed in MHz
- Speed UINT16 ? ; < DRAM bus speed in MHz
- ; < 400 (MHz)
- ; < 533 (MHz)
- ; < 667 (MHz)
- ; < 800 (MHz)
- ; < and so on...
- CasL UINT8 ? ; < CAS latency DCT setting (busclocks)
- Trcd UINT8 ? ; < DCT Trcd (busclocks)
- Trp UINT8 ? ; < DCT Trp (busclocks)
- Trtp UINT8 ? ; < DCT Trtp (busclocks)
- Tras UINT8 ? ; < DCT Tras (busclocks)
- Trc UINT8 ? ; < DCT Trc (busclocks)
- Twr UINT8 ? ; < DCT Twr (busclocks)
- Trrd UINT8 ? ; < DCT Trrd (busclocks)
- Twtr UINT8 ? ; < DCT Twtr (busclocks)
- Tfaw UINT8 ? ; < DCT Tfaw (busclocks)
- Trfc0 UINT8 ? ; < DCT Logical DIMM0 Trfc
- ; < 0 = 75ns (for 256Mb devs)
- ; < 1 = 105ns (for 512Mb devs)
- ; < 2 = 127.5ns (for 1Gb devs)
- ; < 3 = 195ns (for 2Gb devs)
- ; < 4 = 327.5ns (for 4Gb devs)
- Trfc1 UINT8 ? ; < DCT Logical DIMM1 Trfc (see Trfc0 for format)
- Trfc2 UINT8 ? ; < DCT Logical DIMM2 Trfc (see Trfc0 for format)
- Trfc3 UINT8 ? ; < DCT Logical DIMM3 Trfc (see Trfc0 for format)
- DctMemSize UINT32 ? ; < Base[47:16], total DRAM size controlled by this DCT.
- SlowMode BOOLEAN ? ; < 1T or 2T CMD mode (slow access mode)
- ; < FALSE = 1T
- ; < TRUE = 2T
- TrwtTO UINT8 ? ; < DCT TrwtTO (busclocks)
- Twrrd UINT8 ? ; < DCT Twrrd (busclocks)
- Twrwr UINT8 ? ; < DCT Twrwr (busclocks)
- Trdrd UINT8 ? ; < DCT Trdrd (busclocks)
- TrwtWB UINT8 ? ; < DCT TrwtWB (busclocks)
- TrdrdSD UINT8 ? ; < DCT TrdrdSD (busclocks)
- TwrwrSD UINT8 ? ; < DCT TwrwrSD (busclocks)
- TwrrdSD UINT8 ? ; < DCT TwrrdSD (busclocks)
- MaxRdLat UINT16 ? ; < Max Read Latency
- WrDatGrossH UINT8 ? ; < Temporary variables must be removed
- DqsRcvEnGrossL UINT8 ? ; < Temporary variables must be removed
-CH_TIMING_STRUCT ENDS
-
-; ===============================================================================
- ; Data for each DCT
- ; This data structure defines data used to configure each DRAM controller
-; ===============================================================================
-DCT_STRUCT STRUCT
- Dct UINT8 ? ; < Current Dct
- Timings CH_TIMING_STRUCT {} ; < Channel Timing structure
- TimingsMemPs1 POINTER ? ; < Pointed to channel timing structure for Memory Pstate 1
- ChData POINTER ? ; < Pointed to a dynamically allocated array of Channel structures
- ChannelCount UINT8 ? ; < Number of channel per this DCT
- BkIntDis BOOLEAN ? ; < Bank interleave requested but not enabled on current DCT
-DCT_STRUCT ENDS
-
-
-; ===============================================================================
- ; Data Structure defining each Die
- ; This data structure contains information that is used to configure each Die
-; ===============================================================================
-DIE_STRUCT STRUCT
-
- ; Advanced:
-
- NodeId UINT8 ? ; < Node ID of current controller
- SocketId UINT8 ? ; < Socket ID of this Die
- DieId UINT8 ? ; < ID of this die relative to the socket
- PciAddr PCI_ADDR {} ; < Pci bus and device number of this controller.
- ErrCode AGESA_STATUS ? ; < Current error condition of Node
- ; < 0x0 = AGESA_SUCCESS
- ; < 0x1 = AGESA_UNSUPPORTED
- ; < 0x2 = AGESA_BOUNDS_CHK
- ; < 0x3 = AGESA_ALERT
- ; < 0x4 = AGESA_WARNING
- ; < 0x5 = AGESA_ERROR
- ; < 0x6 = AGESA_CRITICAL
- ; < 0x7 = AGESA_FATAL
- ; <
- ErrStatus BOOLEAN (EsbEOL) DUP (?) ; < Error Status bit Field
- Status BOOLEAN (SbEOL) DUP (?) ; < Status bit Field
- NodeMemSize UINT32 ? ; < Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
- NodeSysBase UINT32 ? ; < Base[47:16] (system address) DRAM base address of this Node.
- NodeHoleBase UINT32 ? ; < If not zero, Base[47:16] (system address) of dram hole for HW remapping. Dram hole exists on this Node
- NodeSysLimit UINT32 ? ; < Base[47:16] (system address) DRAM limit address of this Node.
- DimmPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is present.
- ; < DIMM# Select Signal
- ; < 0 MA0_CS_L[0, 1]
- ; < 1 MB0_CS_L[0, 1]
- ; < 2 MA1_CS_L[0, 1]
- ; < 3 MB1_CS_L[0, 1]
- ; < 4 MA2_CS_L[0, 1]
- ; < 5 MB2_CS_L[0, 1]
- ; < 6 MA3_CS_L[0, 1]
- ; < 7 MB3_CS_L[0, 1]
- DimmValid UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
- RegDimmPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is registered DIMM
- LrDimmPresent UINT32 ? ; < For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
- DimmEccPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is ECC capable.
- DimmParPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
- DimmTrainFail UINT16 ? ; < Bitmap showing which dimms failed training
- ChannelTrainFail UINT16 ? ; < Bitmap showing the channel information about failed Chip Selects
- ; < 0 in any bit field indicates Channel 0
- ; < 1 in any bit field indicates Channel 1
- Dct UINT8 ? ; < Need to be removed
- ; < DCT pointer
- GangedMode BOOLEAN ? ; < Ganged mode
- ; < 0 = disabled
- ; < 1 = enabled
- LogicalCpuid CPU_LOGICAL_ID {} ; < The logical CPUID of the node
- HostBiosSrvc1 UINT16 ? ; < UINT16 sized general purpose field for use by host BIOS. Scratch space.
- HostBiosSrvc2 UINT32 ? ; < UINT32 sized general purpose field for use by host BIOS. Scratch space.
- MLoad UINT8 ? ; < Need to be removed
- ; < Number of devices loading MAA bus
- MaxAsyncLat UINT8 ? ; < Legacy wrapper
- ChbD3Rcvrdly UINT8 ? ; < Legacy wrapper
- ChaMaxRdLat UINT16 ? ; < Max Read Latency (ns) for DCT 0
- ChbD3BcRcvrdly UINT8 ? ; < CHB DIMM 3 Check UINT8 Receiver Enable Delay
-
- DctData POINTER ? ; < Pointed to a dynamically allocated array of DCT_STRUCTs
- DctCount UINT8 ? ; < Number of DCTs per this Die
- Reserved UINT8 (16) DUP (?) ; < Reserved
-DIE_STRUCT ENDS
-
-; *********************************************************************
-; * S3 Support structure
-; *********************************************************************
- ; AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure
-AMD_S3_PARAMS STRUCT
- Signature UINT32 ? ; < "ASTR" for AMD Suspend-To-RAM
- Version UINT16 ? ; < S3 Params version number
- Flags UINT32 ? ; < Indicates operation
- NvStorage POINTER ? ; < Pointer to memory critical save state data
- NvStorageSize UINT32 ? ; < Size in bytes of the NvStorage region
- VolatileStorage POINTER ? ; < Pointer to remaining AMD save state data
- VolatileStorageSize UINT32 ? ; < Size in bytes of the VolatileStorage region
-AMD_S3_PARAMS ENDS
-
-; ===============================================================================
- ; MEM_PARAMETER_STRUCT
- ; This data structure is used to pass wrapper parameters to the memory configuration code
-; ===============================================================================
-MEM_PARAMETER_STRUCT STRUCT
-
- ; Basic (Return parameters)
- ; (This section contains the outbound parameters from the memory init code)
-
- GStatus BOOLEAN (GsbEOL) DUP (?) ; < Global Status bitfield
- HoleBase UINT32 ? ; < If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping.
- Sub4GCacheTop UINT32 ? ; < If not zero, the 32-bit top of cacheable memory.
- Sub1THoleBase UINT32 ? ; < If not zero Base[47:16] (system address) of sub 1TB dram hole.
- SysLimit UINT32 ? ; < Limit[47:16] (system address)
- DDR3Voltage DIMM_VOLTAGE ? ; < Find support voltage and send back to platform BIOS.
-;del ExternalVrefValue UINT8 ? ; < Target reference voltage for external Vref for 2D training
- MemData POINTER ? ; < Pointer to MEM_DATA_STRUCT
- ; Advanced (Optional parameters)
- ; Optional (all defaults values will be initialized by the
- ; 'AmdMemInitDataStructDef' based on AMD defaults. It is up
- ; to the IBV/OEM to change the defaults after initialization
- ; but prior to the main entry to the memory code):
-
- ; Memory Map/Mgt.
-
- BottomIo UINT16 ? ; < Bottom of 32-bit IO space (8-bits)
- ; < NV_BOTTOM_IO[7:0]=Addr[31:24]
- MemHoleRemapping BOOLEAN ? ; < Memory Hole Remapping (1-bit)
- ; < FALSE = disable
- ; < TRUE = enable
- LimitMemoryToBelow1Tb BOOLEAN ? ; < Limit memory address space to below 1 TB
- ; < FALSE = disable
- ; < TRUE = enable
- ; Dram Timing
-
- UserTimingMode USER_MEMORY_TIMING_MODE ? ; < User Memclock Mode
-
- MemClockValue MEMORY_BUS_SPEED ? ; < Memory Clock Value
-
- ; Dram Configuration
-
- EnableBankIntlv BOOLEAN ? ; < Dram Bank (chip-select) Interleaving (1-bit)
- ; < FALSE =disable (AMD default)
- ; < TRUE =enable
- EnableNodeIntlv BOOLEAN ? ; < Node Memory Interleaving (1-bit)
- ; < FALSE = disable (AMD default)
- ; < TRUE = enable
- EnableChannelIntlv BOOLEAN ? ; < Channel Interleaving (1-bit)
- ; < FALSE = disable (AMD default)
- ; < TRUE = enable
- ; ECC
-
- EnableEccFeature BOOLEAN ? ; < enable ECC error to go into MCE
- ; < FALSE = disable (AMD default)
- ; < TRUE = enable
- ; Dram Power
-
- EnablePowerDown BOOLEAN ? ; < CKE based power down mode (1-bit)
- ; < FALSE =disable (AMD default)
- ; < TRUE =enable
- ; Online Spare
-
- EnableOnLineSpareCtl BOOLEAN ? ; < Chip Select Spare Control bit 0:
- ; < FALSE = disable Spare (AMD default)
- ; < TRUE = enable Spare
- TableBasedAlterations POINTER ? ; < Point to an array of data bytes describing desired modifications to register settings.
-
- PlatformMemoryConfiguration POINTER ?
- ; < Points to a table that contains platform specific settings
- ; < (i.e. MemClk routing, the number of DIMM slots per channel,...)
- ; < AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that
- ; < contains default conservative settings. Platform BIOS can either tweak
- ; < DefaultPlatformMemoryConfiguration or reassign this pointer to its own table.
- ; <
- EnableParity BOOLEAN ? ; < Parity control
- ; < TRUE = enable
- ; < FALSE = disable (AMD default)
- EnableBankSwizzle BOOLEAN ? ; < BankSwizzle control
- ; < FALSE = disable
- ; < TRUE = enable (AMD default)
- EnableMemClr BOOLEAN ? ; < Memory Clear functionality control
- ; < FALSE = disable
- ; < TRUE = enable (AMD default)
- ; Uma Configuration
-
- UmaMode UMA_MODE ? ; < Uma Mode
- ; < 0 = None
- ; < 1 = Specified
- ; < 2 = Auto
- UmaSize UINT32 ? ; < The size of shared graphics dram (16-bits)
- ; < NV_UMA_Size[31:0]=Addr[47:16]
- ; <
- UmaBase UINT32 ? ; < The allocated Uma base address (32-bits)
- ; < NV_UMA_Base[31:0]=Addr[47:16]
- ; <
-
- ; Memory Restore Feature
-
- MemRestoreCtl BOOLEAN ? ; < Memory context restore control
- ; < FALSE = perform memory init as normal (AMD default)
- ; < TRUE = restore memory context and skip training. This requires
- ; < MemContext is valid before AmdInitPost
- SaveMemContextCtl BOOLEAN ? ; < Control switch to save memory context at the end of MemAuto
- ; < TRUE = AGESA will setup MemContext block before exit AmdInitPost
- ; < FALSE = AGESA will not setup MemContext block. Platform is
- ; < expected to call S3Save later in POST if it wants to
- ; < use memory context restore feature.
- MemContext AMD_S3_PARAMS {} ; < Memory context block describes the data that platform needs to
- ; < save and restore for memory context restore feature to work.
- ; < It uses the subset of S3Save block to save/restore. Hence platform
- ; < may save only S3 block and uses it for both S3 resume and
- ; < memory context restore.
- ; < - If MemRestoreCtl is TRUE, platform needs to pass in MemContext
- ; < before AmdInitPost.
- ; < - If SaveMemContextCtl is TRUE, platform needs to save MemContext
- ; < right after AmdInitPost.
- ExternalVrefCtl BOOLEAN ? ; < Control the use of external Vref
- ; < TRUE = AGESA will use the function defined in "AGESA_EXTERNAL_2D_TRAIN_VREF_CHANGE" in function list
- ; < to change the vref
- ; < FALSE = AGESA will will use the internal vref control.
- ForceTrainMode FORCE_TRAIN_MODE ? ; < Training Mode
- ; < 0 = Force 1D Training for all configurations
- ; < 1 = Force 2D Training for all configurations
- ; < 2 = Auto - AGESA will control 1D or 2D
-MEM_PARAMETER_STRUCT ENDS
-
-
-; ===============================================================================
- ; Function definition
- ; This data structure passes function pointers to the memory configuration code.
- ; The wrapper can use this structure with customized versions
-; ================================================================================
-MEM_FUNCTION_STRUCT STRUCT
-
- ; PUBLIC required Internal functions
-
- amdMemGetPsCfgU POINTER ? ; < Proc for Unbuffered DIMMs, platform specific
- amdMemGetPsCfgR POINTER ? ; < Proc for Registered DIMMs, platform specific
-
- ; PUBLIC optional functions
-
- amdMemEccInit POINTER ? ; < NB proc for ECC feature
- amdMemChipSelectInterleaveInit POINTER ? ; < NB proc for CS interleave feature
- amdMemDctInterleavingInit POINTER ? ; < NB proc for Channel interleave feature
- amdMemMctInterleavingInit POINTER ? ; < NB proc for Node interleave feature
- amdMemParallelTraining POINTER ? ; < NB proc for parallel training feature
- amdMemEarlySampleSupport POINTER ? ; < NB code for early sample support feature
- amdMemMultiPartInitSupport POINTER ? ; < NB code for 'multi-part'
- amdMemOnlineSpareSupport POINTER ? ; < NB code for On-Line Spare feature
- amdMemUDimmInit POINTER ? ; < NB code for UDIMMs
- amdMemRDimmInit POINTER ? ; < NB code for RDIMMs
- amdMemLrDimmInit POINTER ? ; < NB code for LRDIMMs
- Reserved UINT32 (100) DUP (?) ; < Reserved for later function definition
-MEM_FUNCTION_STRUCT ENDS
-
-; ===============================================================================
- ; Socket Structure
-
-; ===============================================================================
-MEM_SOCKET_STRUCT STRUCT
- ChannelPtr POINTER (MAX_CHANNELS_PER_SOCKET) DUP (?) ; < Pointers to each channels training data
-
- TimingsPtr POINTER (MAX_CHANNELS_PER_SOCKET) DUP (?) ; < Pointers to each channels timing data
-
-MEM_SOCKET_STRUCT ENDS
-
-; ===============================================================================
- ; MEM_DATA_STRUCT
-; ===============================================================================
-MEM_DATA_STRUCT STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < AGESA Standard Header
-
- ParameterListPtr POINTER ? ; < List of input Parameters
-
- FunctionList MEM_FUNCTION_STRUCT {} ; < List of function Pointers
-
- GetPlatformCfg POINTER (MAX_PLATFORM_TYPES) DUP (?) ; < look-up platform info
-
- ErrorHandling POINTER ? ; < Error Handling
-
- ; SocketList is a shortcut for IBVs to retrieve training
- ; and timing data for each channel indexed by socket/channel,
- ; eliminating their need to parse die/dct/channel etc.
- ; It contains pointers to the populated data structures for
- ; each channel and skips the channel structures that are
- ; unpopulated. In the case of channels sharing the same DCT,
- ; the pTimings pointers will point to the same DCT Timing data.
-
- SocketList MEM_SOCKET_STRUCT (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Socket list for memory code
-
- DiesPerSystem POINTER ? ; < Pointed to an array of DIE_STRUCTs
- DieCount UINT8 ? ; < Number of MCTs in the system.
-
- SpdDataStructure POINTER ? ; < Pointer to SPD Data structure
-
- PlatFormConfig POINTER ? ; < Pointer to Platform profile/build option config structure
-
- IsFlowControlSupported BOOLEAN ? ; < Indicates if flow control is supported
-
- TscRate UINT32 ? ; < The rate at which the TSC increments in megahertz.
-
-MEM_DATA_STRUCT ENDS
-
-; ===============================================================================
-; UMA_INFO_STRUCT
-; ===============================================================================
-UMA_INFO STRUCT
- UmaBase UINT64 ? ; < UmaBase[63:0] = Addr[63:0]
- UmaSize UINT32 ? ; < UmaSize[31:0] = Addr[31:0]
- UmaAttributes UINT32 ? ; < Indicate the attribute of Uma
- UmaMode UINT8 ? ; < Indicate the mode of Uma
- MemClock UINT16 ? ; < Indicate memory running speed in MHz
- Reserved UINT8 (3) DUP (?) ; < Reserved for future usage
-UMA_INFO ENDS
-
-; ===============================================================================
-; Bitfield for ID
-; ===============================================================================
-ID_FIELD STRUCT
- SocketId UINT16 ?
-; OUT UINT16 SocketId:8; ; < Socket ID
-; OUT UINT16 ModuleId:8; ; < Module ID
-ID_FIELD ENDS
-
-; ===============================================================================
-; Union for ID of socket and module that will be passed out in call out
-; ===============================================================================
-ID_INFO UNION
- IdField ID_FIELD {} ; < Bitfield for ID
- IdInformation UINT16 ? ; < ID information for call out
-ID_INFO ENDS
-
- ; AGESA MEMORY ERRORS
-
- ; AGESA_ALERT Memory Errors
-MEM_ALERT_USER_TMG_MODE_OVERRULED EQU 04010000h ; < TIMING_MODE_SPECIFIC is requested but
- ; < cannot be applied to current configurations.
-MEM_ALERT_ORG_MISMATCH_DIMM EQU 04010100h ; < DIMM organization miss-match
-MEM_ALERT_BK_INT_DIS EQU 04010200h ; < Bank interleaving disable for internal issue
-
- ; AGESA_ERROR Memory Errors
-MEM_ERROR_NO_DQS_POS_RD_WINDOW EQU 04010300h ; < No DQS Position window for RD DQS
-MEM_ERROR_SMALL_DQS_POS_RD_WINDOW EQU 04020300h ; < Small DQS Position window for RD DQS
-MEM_ERROR_NO_DQS_POS_WR_WINDOW EQU 04030300h ; < No DQS Position window for WR DQS
-MEM_ERROR_SMALL_DQS_POS_WR_WINDOW EQU 04040300h ; < Small DQS Position window for WR DQS
-MEM_ERROR_ECC_DIS EQU 04010400h ; < ECC has been disabled as a result of an internal issue
-MEM_ERROR_DIMM_SPARING_NOT_ENABLED EQU 04010500h ; < DIMM sparing has not been enabled for an internal issues
-MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE EQU 04050300h ; < Receive Enable value is too large
-MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW EQU 04060300h ; < There is no DQS receiver enable window
-MEM_ERROR_DRAM_ENABLED_TIME_OUT EQU 04010600h ; < Time out when polling DramEnabled bit
-MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT EQU 04010700h ; < Time out when polling DctAccessDone bit
-MEM_ERROR_SEND_CTRL_WORD_TIME_OUT EQU 04010800h ; < Time out when polling SendCtrlWord bit
-MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT EQU 04010900h ; < Time out when polling PrefDramTrainMode bit
-MEM_ERROR_ENTER_SELF_REF_TIME_OUT EQU 04010A00h ; < Time out when polling EnterSelfRef bit
-MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT EQU 04010B00h ; < Time out when polling FreqChgInProg bit
-MEM_ERROR_EXIT_SELF_REF_TIME_OUT EQU 04020A00h ; < Time out when polling ExitSelfRef bit
-MEM_ERROR_SEND_MRS_CMD_TIME_OUT EQU 04010C00h ; < Time out when polling SendMrsCmd bit
-MEM_ERROR_SEND_ZQ_CMD_TIME_OUT EQU 04010D00h ; < Time out when polling SendZQCmd bit
-MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT EQU 04010E00h ; < Time out when polling DctExtraAccessDone bit
-MEM_ERROR_MEM_CLR_BUSY_TIME_OUT EQU 04010F00h ; < Time out when polling MemClrBusy bit
-MEM_ERROR_MEM_CLEARED_TIME_OUT EQU 04020F00h ; < Time out when polling MemCleared bit
-MEM_ERROR_FLUSH_WR_TIME_OUT EQU 04011000h ; < Time out when polling FlushWr bit
-MEM_ERROR_NBPSTATE_TRANSITION_TIME_OUT EQU 04012600h ; < Time out when polling CurNBPstate bit
-MEM_ERROR_MAX_LAT_NO_WINDOW EQU 04070300h ; < Fail to find pass during Max Rd Latency training
-MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL EQU 04080300h ; < Fail to launch training code on an AP
-MEM_ERROR_PARALLEL_TRAINING_TIME_OUT EQU 04090300h ; < Fail to finish parallel training
-MEM_ERROR_NO_ADDRESS_MAPPING EQU 04011100h ; < No address mapping found for a dimm
-MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT EQU 040A0300h ; < There is no DQS receiver enable window and the value is equal to the largest value
-MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE EQU 040B0300h ; < Receive Enable value is too large and is 1 less than limit
-MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR EQU 04011200h ; < SPD Checksum error for NV_SPDCHK_RESTRT
-MEM_ERROR_NO_CHIPSELECT EQU 04011300h ; < No chipselects found
-MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM EQU 04011500h ; < Unbuffered dimm is not supported at 333MHz
-MEM_ERROR_WL_PRE_OUT_OF_RANGE EQU 040C0300h ; < Returned PRE value during write levelization was out of range
-MEM_ERROR_NO_2D_RDDQS_WINDOW EQU 040D0300h ; < No 2D RdDqs Window
-MEM_ERROR_NO_2D_RDDQS_HEIGHT EQU 040E0300h ; < No 2D RdDqs Height
-MEM_ERROR_2D_DQS_ERROR EQU 040F0300h ; < 2D RdDqs Error
-MEM_ERROR_INVALID_2D_RDDQS_VALUE EQU 04022400h ; < 2d RdDqs invalid value found
-MEM_ERROR_2D_DQS_VREF_MARGIN_ERROR EQU 04023400h ; < 2d RdDqs Vef Margin error found
-MEM_ERROR_LR_IBT_NOT_FOUND EQU 04013500h ; < No LR dimm IBT value is found
-MEM_ERROR_MR0_NOT_FOUND EQU 04023500h ; < No MR0 value is found
-MEM_ERROR_ODT_PATTERN_NOT_FOUND EQU 04033500h ; < No odt pattern value is found
-MEM_ERROR_RC2_IBT_NOT_FOUND EQU 04043500h ; < No RC2 IBT value is found
-MEM_ERROR_RC10_OP_SPEED_NOT_FOUND EQU 04053500h ; < No RC10 op speed is found
-MEM_ERROR_RTT_NOT_FOUND EQU 04063500h ; < No RTT value is found
-MEM_ERROR_P2D_NOT_FOUND EQU 04073500h ; < No 2D training config value is found
-MEM_ERROR_SAO_NOT_FOUND EQU 04083500h ; < No slow access mode, Address timing and Output driver compensation value is found
-MEM_ERROR_CLK_DIS_MAP_NOT_FOUND EQU 04093500h ; < No CLK disable map is found
-MEM_ERROR_CKE_TRI_MAP_NOT_FOUND EQU 040A3500h ; < No CKE tristate map is found
-MEM_ERROR_ODT_TRI_MAP_NOT_FOUND EQU 040B3500h ; < No ODT tristate map is found
-MEM_ERROR_CS_TRI_MAP_NOT_FOUND EQU 040C3500h ; < No CS tristate map is found
-MEM_ERROR_TRAINING_SEED_NOT_FOUND EQU 040D3500h ; < No training seed is found
-
- ; AGESA_WARNING Memory Errors
- MEM_WARNING_UNSUPPORTED_QRDIMM EQU 04011600h ; < QR DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_UDIMM EQU 04021600h ; < U DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_SODIMM EQU 04031600h ; < SO-DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_X4DIMM EQU 04041600h ; < x4 DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_RDIMM EQU 04051600h ; < R DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_LRDIMM EQU 04061600h ; < LR DIMMs detected but not supported
-
- MEM_WARNING_EMP_NOT_SUPPORTED EQU 04011700h ; < Processor is not capable for EMP
- MEM_WARNING_EMP_CONFLICT EQU 04021700h ; < EMP cannot be enabled if channel interleaving,
- ; < bank interleaving, or bank swizzle is enabled.
- MEM_WARNING_EMP_NOT_ENABLED EQU 04031700h ; < Memory size is not power of two.
- MEM_WARNING_ECC_DIS EQU 04041700h ; < ECC has been disabled as a result of an internal issue
- MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED EQU 04011800h ; < Performance has been enabled, but battery life is preferred.
- MEM_WARNING_NO_SPDTRC_FOUND EQU 04011900h ; < No Trc timing value found in SPD of a dimm.
- MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED EQU 04012000h ; < Node Interleaveing Requested, but could not be enabled
- MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED EQU 04012100h ; < Channel Interleaveing Requested, but could not be enabled
- MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED EQU 04012200h ; < Bank Interleaveing Requested, but could not be enabled
- MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED EQU 04012300h ; < Voltage 1.35 determined, but could not be supported
- MEM_WARNING_INITIAL_DDR3VOLT_NONZERO EQU 04012400h ; < DDR3 voltage initial value is not 0
- MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO EQU 04012500h ; < Cannot find a commonly supported VDDIO
-
- ; AGESA_FATAL Memory Errors
- MEM_ERROR_MINIMUM_MODE EQU 04011A00h ; < Running in minimum mode
- MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM EQU 04011B00h ; < DIMM modules are miss-matched
- MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM EQU 04011C00h ; < No DIMMs have been found on system
- MEM_ERROR_MISMATCH_DIMM_CLOCKS EQU 04011D00h ; < DIMM clocks miss-matched
- MEM_ERROR_NO_CYC_TIME EQU 04011E00h ; < No cycle time found
- MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS EQU 04011F00h ; < Heap allocation error with dynamic storing of trained timings
- MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs EQU 04021F00h ; < Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
- MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV EQU 04031F00h ; < Heap allocation error with REMOTE_TRAINING_ENV
- MEM_ERROR_HEAP_ALLOCATE_FOR_SPD EQU 04041F00h ; < Heap allocation error for SPD data
- MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA EQU 04051F00h ; < Heap allocation error for RECEIVED_DATA during parallel training
- MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS EQU 04061F00h ; < Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
- MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA EQU 04071F00h ; < Heap allocation error for Training Data
- MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK EQU 04081F00h ; < Heap allocation error for DIMM Identify "MEM_NB_BLOCK
- MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM EQU 04022300h ; < No Constructor for DIMM Identify
- MEM_ERROR_VDDIO_UNSUPPORTED EQU 04022500h ; < VDDIO of the dimms on the board is not supported
- MEM_ERROR_HEAP_ALLOCATE_FOR_2D EQU 040B1F00h ; < Heap allocation error for 2D training data
- MEM_ERROR_HEAP_DEALLOCATE_FOR_2D EQU 040C1F00h ; < Heap de-allocation error for 2D training data
-
- ; AGESA_CRITICAL Memory Errors
- MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 EQU 04091F00h ; < Heap allocation error for DMI table for DDR3
- MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 EQU 040A1F00h ; < Heap allocation error for DMI table for DDR2
- MEM_ERROR_UNSUPPORTED_DIMM_CONFIG EQU 04011400h ; < Dimm population is not supported
- MEM_ERROR_HEAP_ALLOCATE_FOR_CRAT_MEM_AFFINITY EQU 040D1F00h ;< Heap allocation error for CRAT memory affinity info
-
-; ----------------------------------------------------------------------------
-; *
-; * END OF MEMORY-SPECIFIC DATA STRUCTURES
-; *
-; *----------------------------------------------------------------------------
-;
-
-
-; ----------------------------------------------------------------------------
-; *
-; * CPU RELATED DEFINITIONS
-; *
-; *----------------------------------------------------------------------------
-;
-
-; CPU Event definitions.
-
-; Defines used to filter CPU events based on functional blocks
-CPU_EVENT_PM_EVENT_MASK EQU 0FF00FF00h
-CPU_EVENT_PM_EVENT_CLASS EQU 008000400h
-
-;================================================================
-; CPU General events
-; Heap allocation (AppFunction = 01h)
-CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT EQU 008000100h
-CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED EQU 008010100h
-CPU_ERROR_HEAP_IS_FULL EQU 008020100h
-CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED EQU 008030100h
-CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT EQU 008040100h
-; BrandId (AppFunction = 02h)
-CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE EQU 008000200h
-; Micro code patch (AppFunction = 03h)
-CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED EQU 008000300h
-; Power management (AppFunction = 04h)
-CPU_EVENT_PM_PSTATE_OVERCURRENT EQU 008000400h
-CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT EQU 008010400h
-CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE EQU 008020400h
-CPU_ERROR_PM_NB_PSTATE_MISMATCH EQU 008030400h
-; Other CPU events (AppFunction = 05h)
-CPU_EVENT_BIST_ERROR EQU 008000500h
-CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY EQU 008010500h
-CPU_EVENT_STACK_REENTRY EQU 008020500h
-CPU_EVENT_CORE_NOT_IDENTIFIED EQU 008030500h
-;=================================================================
-; CPU Feature events
-; Execution cache (AppFunction = 21h)
-; AGESA_CACHE_SIZE_REDUCED 2101
-; AGESA_CACHE_REGIONS_ACROSS_1MB 2102
-; AGESA_CACHE_REGIONS_ACROSS_4GB 2103
-; AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 2104
-; AGESA_CACHE_START_ADDRESS_LESS_D0000 2105
-; AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 2106
-; AGESA_DEALLOCATE_CACHE_REGIONS 2107
-CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR EQU 008002100h
-; Core Leveling (AppFunction = 22h)
-CPU_WARNING_ADJUSTED_LEVELING_MODE EQU 008002200h
-; HT Assist (AppFunction = 23h)
-CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG EQU 008002300h
-
-; CPU Build Configuration structures and definitions
-
-; Build Configuration values for BLDGCFG_AP_MTRR_SETTINGS
-AP_MTRR_SETTINGS STRUCT
- MsrAddr UINT32 ? ; < Fixed-Sized MTRR address
- MsrData UINT64 ? ; < MTRR Settings
-AP_MTRR_SETTINGS ENDS
-
-AMD_AP_MTRR_FIX64k_00000 EQU 000000250h
-AMD_AP_MTRR_FIX16k_80000 EQU 000000258h
-AMD_AP_MTRR_FIX16k_A0000 EQU 000000259h
-AMD_AP_MTRR_FIX4k_C0000 EQU 000000268h
-AMD_AP_MTRR_FIX4k_C8000 EQU 000000269h
-AMD_AP_MTRR_FIX4k_D0000 EQU 00000026Ah
-AMD_AP_MTRR_FIX4k_D8000 EQU 00000026Bh
-AMD_AP_MTRR_FIX4k_E0000 EQU 00000026Ch
-AMD_AP_MTRR_FIX4k_E8000 EQU 00000026Dh
-AMD_AP_MTRR_FIX4k_F0000 EQU 00000026Eh
-AMD_AP_MTRR_FIX4k_F8000 EQU 00000026Fh
-CPU_LIST_TERMINAL EQU 0FFFFFFFFh
-
-; ***********************************************************************
-; *
-; * AGESA interface Call-Out function parameter structures
-; *
-; **********************************************************************
-
- ; Parameters structure for interface call-out AgesaAllocateBuffer
-AGESA_BUFFER_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- BufferLength UINT32 ? ; < Size of buffer to allocate
- BufferHandle UINT32 ? ; < Identifier or name for the buffer
- BufferPointer POINTER ? ; < location of the created buffer
-AGESA_BUFFER_PARAMS ENDS
-
- ; Parameters structure for interface call-out AgesaRunCodeOnAp
-AP_EXE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- FunctionNumber UINT32 ? ; < Index of the procedure to execute
- RelatedDataBlock POINTER ? ; < Location of data structure the procedure will use
- RelatedBlockLength UINT32 ? ; < Size of the related data block
-AP_EXE_PARAMS ENDS
-
- ; Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery
-AGESA_READ_SPD_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < standard header
- SocketId UINT8 ? ; < Address of SPD - socket ID
- MemChannelId UINT8 ? ; < Address of SPD - memory channel ID
- DimmId UINT8 ? ; < Address of SPD - DIMM ID
- Buffer POINTER ? ; < Location where to place the SPD content
- MemData POINTER ? ; < Location of the MemData structure, for reference
-AGESA_READ_SPD_PARAMS ENDS
-
- ; Buffer Handles
- AMD_DMI_INFO_BUFFER_HANDLE EQU 000D000h ; < Assign 0x000D000 buffer handle to DMI function
- AMD_PSTATE_DATA_BUFFER_HANDLE EQU 000D001h ; < Assign 0x000D001 buffer handle to Pstate data
- AMD_PSTATE_ACPI_BUFFER_HANDLE EQU 000D002h ; < Assign 0x000D002 buffer handle to Pstate table
- AMD_BRAND_ID_BUFFER_HANDLE EQU 000D003h ; < Assign 0x000D003 buffer handle to Brand ID
- AMD_ACPI_SLIT_BUFFER_HANDLE EQU 000D004h ; < Assign 0x000D004 buffer handle to SLIT function
- AMD_SRAT_INFO_BUFFER_HANDLE EQU 000D005h ; < Assign 0x000D005 buffer handle to SRAT function
- AMD_WHEA_BUFFER_HANDLE EQU 000D006h ; < Assign 0x000D006 buffer handle to WHEA function
- AMD_S3_INFO_BUFFER_HANDLE EQU 000D007h ; < Assign 0x000D007 buffer handle to S3 function
- AMD_S3_NB_INFO_BUFFER_HANDLE EQU 000D008h ; < Assign 0x000D008 buffer handle to S3 NB device info
- AMD_ACPI_ALIB_BUFFER_HANDLE EQU 000D009h ; < Assign 0x000D009 buffer handle to ALIB SSDT table
- AMD_ACPI_IVRS_BUFFER_HANDLE EQU 000D00Ah ; < Assign 0x000D00A buffer handle to IOMMU IVRS table
- AMD_CRAT_INFO_BUFFER_HANDLE EQU 000D00Bh ; < Assign 0x000D00B buffer handle to CRAT function
- AMD_ACPI_CDIT_BUFFER_HANDLE EQU 000D00Ch ; < Assign 0x000D00C buffer handle to CDIT function
-AMD_BUFFER_HANDLE TEXTEQU <DWORD>
-; ***********************************************************************
-; *
-; * AGESA interface Call-Out function prototypes
-; *
-; **********************************************************************
-
-; ***********************************************************************
-; *
-; * AGESA interface structure definition and function prototypes
-; *
-; **********************************************************************
-
-; *********************************************************************
-; * Platform Configuration: The parameters in boot branch function
-; *********************************************************************
-
-; The possible platform control flow settings.
- Nfcm EQU 0 ; < Normal Flow Control Mode.
- UmaDr EQU 1 ; < UMA using Display Refresh flow control.
- UmaIfcm EQU 2 ; < UMA using Isochronous Flow Control.
- Ifcm EQU 3 ; < Isochronous Flow Control Mode (other than for UMA).
- Iommu EQU 4 ; < An IOMMU is in use in the system.
- MaxControlFlow EQU 5 ; < Not a control flow mode, use for limit checking.
-PLATFORM_CONTROL_FLOW TEXTEQU <DWORD>
-
-; Platform Deemphasis Levels.
- DeemphasisLevelNone EQU 0 ; < No Deemphasis.
- DeemphasisLevelMinus3 EQU 1 ; < Minus 3 db deemphasis.
- DeemphasisLevelMinus6 EQU 2 ; < Minus 6 db deemphasis.
- DeemphasisLevelMinus8 EQU 3 ; < Minus 8 db deemphasis.
- DeemphasisLevelMinus11 EQU 4 ; < Minus 11 db deemphasis.
- DeemphasisLevelMinus11pre8 EQU 5 ; < Minus 11, Minus 8 precursor db deemphasis.
- DcvLevelNone EQU 16 ; < No DCV Deemphasis.
- DcvLevelMinus2 EQU 17 ; < Minus 2 db DCV deemphasis.
- DcvLevelMinus3 EQU 18 ; < Minus 3 db DCV deemphasis.
- DcvLevelMinus5 EQU 19 ; < Minus 5 db DCV deemphasis.
- DcvLevelMinus6 EQU 20 ; < Minus 6 db DCV deemphasis.
- DcvLevelMinus7 EQU 21 ; < Minus 7 db DCV deemphasis.
- DcvLevelMinus8 EQU 22 ; < Minus 8 db DCV deemphasis.
- DcvLevelMinus9 EQU 23 ; < Minus 9 db DCV deemphasis.
- DcvLevelMinus11 EQU 24 ; < Minus 11 db DCV deemphasis.
- MaxPlatformDeemphasisLevel EQU 25 ; < Not a deemphasis level, use for limit checking.
-PLATFORM_DEEMPHASIS_LEVEL TEXTEQU <DWORD>
-
-; Provide Deemphasis Levels for HT Links.
-;
-; For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will
-; be checked for a match. The item matches for a Socket, Link if the link frequency is
-; is in the inclusive range HighFreq:LoFreq.
-; AGESA does not set deemphasis in IO devices, only in processors.
-
-CPU_HT_DEEMPHASIS_LEVEL STRUCT
- ; Match fields
- Socket UINT8 ? ; < One Socket on which this Link is located
- Link UINT8 ? ; < The Link on this Processor.
- LoFreq UINT8 ? ; < If the link is set to this frequency or greater, apply these levels, and
- HighFreq UINT8 ? ; < If the link is set to this frequency or less, apply these levels.
- ; Value fields
- ReceiverDeemphasis PLATFORM_DEEMPHASIS_LEVEL ? ; < The deemphasis level for this link
- DcvDeemphasis PLATFORM_DEEMPHASIS_LEVEL ? ; < The DCV, or far transmitter deemphasis level.
-CPU_HT_DEEMPHASIS_LEVEL ENDS
-
-; The possible hardware prefetch mode settings.
- HARDWARE_PREFETCHER_AUTO EQU 0 ; Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
- DISABLE_L1_PREFETCHER EQU 1 ; Use the recommended settings for the hardware prefetcher, but disable L1 prefetching.
- DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES EQU 2 ; Use the recommended setting for the hardware prefetcher, but disable training on software prefetches.
- DISABLE_L1_PREFETCHER_AND_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES EQU 3 ; Use the recommended settings for the hardware prefetcher, but disable both the L1 prefetcher and training on software prefetches.
- DISABLE_HARDWARE_PREFETCH EQU 4 ; Disable hardware prefetching.
- MAX_HARDWARE_PREFETCH_MODE EQU 5 ; Not a hardware prefetch mode, use for limit checking.
-HARDWARE_PREFETCH_MODE TEXTEQU <DWORD>
-
-; The possible software prefetch mode settings.
- SOFTWARE_PREFETCHES_AUTO EQU 0 ; Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
- DISABLE_SOFTWARE_PREFETCHES EQU 1 ; Disable software prefetches (convert software prefetch instructions to NOP).
- MAX_SOFTWARE_PREFETCH_MODE EQU 2 ; Not a software prefetch mode, use for limit checking.
-SOFTWARE_PREFETCH_MODE TEXTEQU <DWORD>
-
-; Advanced performance tunings, prefetchers.
-; These settings provide for performance tuning to optimize for specific workloads.
-ADVANCED_PERFORMANCE_PROFILE STRUCT
- HardwarePrefetchMode HARDWARE_PREFETCH_MODE ? ; This value provides for advanced performance tuning by controlling the hardware prefetcher setting.
- SoftwarePrefetchMode SOFTWARE_PREFETCH_MODE ? ; This value provides for advanced performance tuning by controlling the software prefetch instructions.
- DramPrefetchMode DRAM_PREFETCH_MODE ? ; This value provides for advanced performance tuning by controlling the DRAM prefetcher setting.
-ADVANCED_PERFORMANCE_PROFILE ENDS
-
-; The possible platform power policy settings.
- Performance EQU 0 ; < Optimize for performance.
- BatteryLife EQU 1 ; < Optimize for battery life.
- MaxPowerPolicy EQU 2 ; < Not a power policy mode, use for limit checking.
-PLATFORM_POWER_POLICY TEXTEQU <DWORD>
-
-; Platform performance settings for optimized settings.
-; Several configuration settings for the processor depend upon other parts and
-; general designer choices for the system. The determination of these data points
-; is not standard for all platforms, so the host environment needs to provide these
-; to specify how the system is to be configured.
-PERFORMANCE_PROFILE STRUCT
- PlatformControlFlowMode PLATFORM_CONTROL_FLOW ? ; < The platform's control flow mode for optimum platform performance.
- UseHtAssist BOOLEAN ? ; < HyperTransport link traffic optimization.
- UseAtmMode BOOLEAN ? ; < HyperTransport link traffic optimization.
- Use32ByteRefresh BOOLEAN ? ; < Display Refresh traffic generates 32 byte requests.
- UseVariableMctIsocPriority BOOLEAN ? ; < The Memory controller will be set to Variable Isoc Priority.
- AdvancedPerformanceProfile ADVANCED_PERFORMANCE_PROFILE {} ; < The advanced platform performance settings.
- PlatformPowerPolicy PLATFORM_POWER_POLICY ? ; < The platform's desired power policy
-PERFORMANCE_PROFILE ENDS
-
-; Platform settings that describe the voltage regulator modules of the system.
-; Many power management settings are dependent upon the characteristics of the
-; on-board voltage regulator module (VRM). The host environment needs to provide
-; these to specify how the system is to be configured.
-PLATFORM_VRM_CONFIGURATION STRUCT
- CurrentLimit UINT32 ? ; < Vrm Current Limit.
- LowPowerThreshold UINT32 ? ; < Vrm Low Power Threshold.
- SlewRate UINT32 ? ; < Vrm Slew Rate.
- AdditionalDelay UINT32 ? ; < Vrm Additional Delay.
- HiSpeedEnable BOOLEAN ? ; < Select high speed VRM.
- InrushCurrentLimit UINT32 ? ; < Vrm Inrush Current Limit.
- SviOcpLevel UINT32 ? ; < Vrm SVI OCP Level.
-PLATFORM_VRM_CONFIGURATION ENDS
-
-; The VRM types to characterize.
- CoreVrm EQU 0 ; < VDD plane.
- NbVrm EQU 1 ; < VDDNB plane.
- MaxVrmType EQU 2 ; < Not a valid VRM type, use for limit checking.
-PLATFORM_VRM_TYPE TEXTEQU <DWORD>
-
-; FCH Platform Configuration Policy
-FCH_PLATFORM_POLICY STRUCT
- CfgSmbus0BaseAddress UINT16 ? ; SMBUS0 Controller Base Address
- CfgSmbus1BaseAddress UINT16 ? ; SMBUS1 Controller Base Address
- CfgSioPmeBaseAddress UINT16 ? ; I/O base address for LPC I/O target range
- CfgAcpiPm1EvtBlkAddr UINT16 ? ; I/O base address of ACPI power management Event Block
- CfgAcpiPm1CntBlkAddr UINT16 ? ; I/O base address of ACPI power management Control Block
- CfgAcpiPmTmrBlkAddr UINT16 ? ; I/O base address of ACPI power management Timer Block
- CfgCpuControlBlkAddr UINT16 ? ; I/O base address of ACPI power management CPU Control Block
- CfgAcpiGpe0BlkAddr UINT16 ? ; I/O base address of ACPI power management General Purpose Event Block
- CfgSmiCmdPortAddr UINT16 ? ; I/O base address of ACPI SMI Command Block
- CfgAcpiPmaCntBlkAddr UINT16 ? ; I/O base address of ACPI power management additional control block
- CfgGecShadowRomBase UINT32 ? ; 32-bit base address to the GEC shadow ROM
- CfgWatchDogTimerBase UINT32 ? ; Watchdog Timer base address
- CfgSpiRomBaseAddress UINT32 ? ; Base address for the SPI ROM controller
- CfgHpetBaseAddress UINT32 ? ; HPET MMIO base address
-;del CfgAzaliaSsid UINT32 ? ; Subsystem ID of HD Audio controller
- CfgSmbusSsid UINT32 ? ; Subsystem ID of SMBUS controller
- CfgIdeSsid UINT32 ? ; Subsystem ID of IDE controller
- CfgSataAhciSsid UINT32 ? ; Subsystem ID of SATA controller in AHCI mode
- CfgSataIdeSsid UINT32 ? ; Subsystem ID of SATA controller in IDE mode
- CfgSataRaid5Ssid UINT32 ? ; Subsystem ID of SATA controller in RAID5 mode
- CfgSataRaidSsid UINT32 ? ; Subsystem ID of SATA controller in RAID mode
- CfgEhciSsid UINT32 ? ; Subsystem ID of EHCI
- CfgOhciSsid UINT32 ? ; Subsystem ID of OHCI
- CfgLpcSsid UINT32 ? ; Subsystem ID of LPC ISA Bridge
- CfgSdSsid UINT32 ? ; Subsystem ID of SecureDigital controller
- CfgXhciSsid UINT32 ? ; Subsystem ID of XHCI
- CfgFchPort80BehindPcib BOOLEAN ? ; Is port80 cycle going to the PCI bridge
- CfgFchEnableAcpiSleepTrap BOOLEAN ? ; ACPI sleep SMI enable/disable
- CfgFchGppLinkConfig GPP_LINKMODE ? ; FCH GPP link configuration
- CfgFchGppPort0Present BOOLEAN ? ; Is FCH GPP port 0 present
- CfgFchGppPort1Present BOOLEAN ? ; Is FCH GPP port 1 present
- CfgFchGppPort2Present BOOLEAN ? ; Is FCH GPP port 2 present
- CfgFchGppPort3Present BOOLEAN ? ; Is FCH GPP port 3 present
- CfgFchGppPort0HotPlug BOOLEAN ? ; Is FCH GPP port 0 hotplug capable
- CfgFchGppPort1HotPlug BOOLEAN ? ; Is FCH GPP port 1 hotplug capable
- CfgFchGppPort2HotPlug BOOLEAN ? ; Is FCH GPP port 2 hotplug capable
- CfgFchGppPort3HotPlug BOOLEAN ? ; Is FCH GPP port 3 hotplug capable
-
- CfgFchEsataPortBitMap UINT8 ? ; ESATA Port definition, eg: [0]=1, means port 0 is ESATA capable
- CfgFchIrPinControl UINT8 ? ; Register bitfield describing Infrared Pin Control:
- CfgFchSdClockControl SD_CLOCK_CONTROL ? ; FCH SD Clock Control
- CfgFchSciMapControl POINTER ? ; FCH SCI Mapping Control
- CfgFchSataPhyControl POINTER ? ; FCH SATA PHY Control
- CfgFchGpioControl POINTER ? ; FCH GPIO Control
-FCH_PLATFORM_POLICY ENDS
-
-
-; Build Option/Configuration Boolean Structure
-BUILD_OPT_CFG STRUCT
- ; Build Option Area
- VersionString AMD_CODE_HEADER {} ; < AMD embedded code version string
- OptionUDimms BOOLEAN ? ; < UDIMMS
- OptionRDimms BOOLEAN ? ; < RDIMMS
- OptionLrDimms BOOLEAN ? ; < LRDIMMS
- OptionEcc BOOLEAN ? ; < ECC
- OptionBankInterleave BOOLEAN ? ; < BANK_INTERLEAVE
- OptionDctInterleave BOOLEAN ? ; < DCT_INTERLEAVE
- OptionNodeInterleave BOOLEAN ? ; < NODE_INTERLEAVE
- OptionParallelTraining BOOLEAN ? ; < PARALLEL_TRAINING
- OptionOnlineSpare BOOLEAN ? ; < ONLINE_SPARE
- OptionMemRestore BOOLEAN ? ; < MEM CONTEXT RESTORE
- OptionMultisocket BOOLEAN ? ; < MULTISOCKET
- OptionAcpiPstates BOOLEAN ? ; < ACPI_PSTATES
- OptionPStatesInHpcMode BOOLEAN ? ; < PSTATES_HPC_MODE
- OptionCrat BOOLEAN ? ; < CRAT
- OptionCdit BOOLEAN ? ; < CDIT
- OptionSrat BOOLEAN ? ; < SRAT
- OptionSlit BOOLEAN ? ; < SLIT
- OptionWhea BOOLEAN ? ; < WHEA
- OptionDmi BOOLEAN ? ; < DMI
- OptionEarlySamples BOOLEAN ? ; < EARLY_SAMPLES
- OptionAddrToCsTranslator BOOLEAN ? ; < ADDR_TO_CS_TRANSLATOR
-
- ; Build Configuration Area
- CfgPciMmioAddress UINT64 ? ; < PciMmioBase
- CfgPciMmioSize UINT32 ? ; < PciMmioSize
- CfgPlatVrmCfg PLATFORM_VRM_CONFIGURATION (MaxVrmType) DUP ({}) ; < Several configuration settings for the voltage regulator modules.
- CfgPlatNumIoApics UINT32 ? ; < PlatformApicIoNumber
- CfgMemInitPstate UINT32 ? ; < MemoryInitPstate
- CfgPlatformC1eMode PLATFORM_C1E_MODES ? ; < PlatformC1eMode
- CfgPlatformC1eOpData UINT32 ? ; < PlatformC1eOpData
- CfgPlatformC1eOpData1 UINT32 ? ; < PlatformC1eOpData1
- CfgPlatformC1eOpData2 UINT32 ? ; < PlatformC1eOpData2
- CfgPlatformC1eOpData3 UINT32 ? ; < PlatformC1eOpData3
- CfgPlatformCStateMode PLATFORM_CSTATE_MODES ? ; < PlatformCStateMode
- CfgPlatformCStateOpData UINT32 ? ; < PlatformCStateOpData
- CfgPlatformCStateIoBaseAddress UINT16 ? ; < PlatformCStateIoBaseAddress
- CfgPlatformCpbMode PLATFORM_CPB_MODES ? ; < PlatformCpbMode
- CfgLowPowerPstateForProcHot PLATFORM_LOW_POWER_PSTATE_MODES ? ; < Low power Pstate for PROCHOT mode
- CfgCoreLevelingMode UINT32 ? ; < CoreLevelingCofig
- CfgPerformanceProfile PERFORMANCE_PROFILE {} ; < The platform's control flow mode and platform performance settings.
- CfgPlatformDeemphasisList POINTER ? ; < HT Deemphasis
- CfgAmdPlatformType UINT32 ? ; < AmdPlatformType
- CfgAmdPstateCapValue UINT32 ? ; < Amd pstate ceiling enabling deck
-
- CfgMemoryBusFrequencyLimit MEMORY_BUS_SPEED ? ; < Memory Bus Frequency Limit
- CfgMemoryModeUnganged BOOLEAN ? ; < Memory Mode Unganged
- CfgMemoryQuadRankCapable BOOLEAN ? ; < Memory Quad Rank Capable
- CfgMemoryQuadrankType QUANDRANK_TYPE ? ; < Memory Quadrank Type
- CfgMemoryRDimmCapable BOOLEAN ? ; < Memory RDIMM Capable
- CfgMemoryLRDimmCapable BOOLEAN ? ; < Memory LRDIMM Capable
- CfgMemoryUDimmCapable BOOLEAN ? ; < Memory UDIMM Capable
- CfgMemorySODimmCapable BOOLEAN ? ; < Memory SODimm Capable
- CfgLimitMemoryToBelow1Tb BOOLEAN ? ; < Limit memory address space to below 1TB
- CfgMemoryEnableBankInterleaving BOOLEAN ? ; < Memory Enable Bank Interleaving
- CfgMemoryEnableNodeInterleaving BOOLEAN ? ; < Memory Enable Node Interleaving
- CfgMemoryChannelInterleaving BOOLEAN ? ; < Memory Channel Interleaving
- CfgMemoryPowerDown BOOLEAN ? ; < Memory Power Down
- CfgPowerDownMode POWER_DOWN_MODE ? ; < Power Down Mode
- CfgOnlineSpare BOOLEAN ? ; < Online Spare
- CfgMemoryParityEnable BOOLEAN ? ; < Memory Parity Enable
- CfgBankSwizzle BOOLEAN ? ; < Bank Swizzle
- CfgTimingModeSelect USER_MEMORY_TIMING_MODE ? ; < Timing Mode Select
- CfgMemoryClockSelect MEMORY_BUS_SPEED ? ; < Memory Clock Select
- CfgDqsTrainingControl BOOLEAN ? ; < Dqs Training Control
- CfgIgnoreSpdChecksum BOOLEAN ? ; < Ignore Spd Checksum
- CfgUseBurstMode BOOLEAN ? ; < Use Burst Mode
- CfgMemoryAllClocksOn BOOLEAN ? ; < Memory All Clocks On
- CfgEnableEccFeature BOOLEAN ? ; < Enable ECC Feature
- CfgEccRedirection BOOLEAN ? ; < ECC Redirection
- CfgScrubDramRate UINT16 ? ; < Scrub Dram Rate
- CfgScrubL2Rate UINT16 ? ; < Scrub L2Rate
- CfgScrubL3Rate UINT16 ? ; < Scrub L3Rate
- CfgScrubIcRate UINT16 ? ; < Scrub Ic Rate
- CfgScrubDcRate UINT16 ? ; < Scrub Dc Rate
- CfgEccSyncFlood BOOLEAN ? ; < ECC Sync Flood
- CfgEccSymbolSize UINT16 ? ; < ECC Symbol Size
- CfgHeapDramAddress UINT64 ? ; < Heap contents will be temporarily stored in this address during the transition
- CfgNodeMem1GBAlign BOOLEAN ? ; < Node Mem 1GB boundary Alignment
- CfgS3LateRestore BOOLEAN ? ; < S3 Late Restore
- CfgAcpiPstateIndependent BOOLEAN ? ; < PSD method dependent/Independent
- CfgApMtrrSettingsList POINTER ? ; < The AP's MTRR settings before final halt
- CfgUmaMode UMA_MODE ? ; < Uma Mode
- CfgUmaSize UINT32 ? ; < Uma Size [31:0]=Addr[47:16]
- CfgUmaAbove4G BOOLEAN ? ; < Uma Above 4G Support
- CfgUmaAlignment UMA_ALIGNMENT ? ; < Uma alignment
- CfgProcessorScopeInSb BOOLEAN ? ; < ACPI Processor Object in \_SB scope
- CfgProcessorScopeName0 CHAR8 ? ; < OEM specific 1st character of processor scope name.
- CfgProcessorScopeName1 CHAR8 ? ; < OEM specific 2nd character of processor scope name.
- CfgGnbHdAudio UINT8 ? ; < Gnb HD Audio Enable
- CfgAbmSupport UINT8 ? ; < ABM support
- CfgDynamicRefreshRate UINT8 ? ; < Dynamic refresh rate
- CfgLcdBackLightControl UINT16 ? ; < Lcd back light control
- CfgGnb3dStereoPinIndex UINT8 ? ; < 3D Stereo Pin ID
- CfgTempPcieMmioBaseAddress UINT32 ? ; < Temp pcie MMIO base address
- CfgGnbIGPUSSID UINT32 ? ; < Gnb internal GPU SSID
- CfgGnbHDAudioSSID UINT32 ? ; < Gnb HD Audio SSID
- CfgGnbPcieSSID UINT32 ? ; < Gnb PCIe SSID
- CfgLvdsSpreadSpectrum UINT16 ? ; < Lvds Spread Spectrum. Build-time customizable only
- CfgLvdsSpreadSpectrumRate UINT16 ? ; < Lvds Spread Spectrum Rate. Build-time customizable only
- FchBldCfg POINTER ? ; < FCH platform build configuration policy
- CfgIommuSupport BOOLEAN ? ; IOMMU support
- CfgLvdsPowerOnSeqDigonToDe UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqDeToVaryBl UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqDeToDigon UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqVaryBlToDe UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqOnToOffDelay UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqVaryBlToBlon UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqBlonToVaryBl UINT8 ? ; Panel initialization timing
- CfgLvdsMaxPixelClockFreq UINT16 ? ; The maximum pixel clock frequency supported
- CfgLcdBitDepthControlValue UINT32 ? ; The LCD bit depth control settings
- CfgLvds24bbpPanelMode UINT8 ? ; The LVDS 24 BBP mode
- CfgLvdsMiscControl LVDS_MISC_CONTROL {}; THe LVDS Misc control
- CfgPcieRefClkSpreadSpectrum UINT16 ? ; PCIe Reference Clock Spread Spectrum
- CfgExternalVrefCtlFeature BOOLEAN ? ; External Vref control
- CfgForceTrainMode FORCE_TRAIN_MODE ? ; < Force Train Mode
- CfgGnbRemoteDisplaySupport BOOLEAN ? ; Wireless Display Support
- CfgIvrsExclusionRangeList POINTER ? ; IOMMU Exclusion Range List
- CfgGnbSyncFloodPinAsNmi BOOLEAN ? ; Define function of NMI_SYNCFLOOD as NMI
- CfgIgpuEnableDisablePolicy UINT8 ? ; This item defines the iGPU Enable/Disable policy
- CfgGnbSwTjOffset UINT8 ? ; Software-writeable TjOffset
- CfgLvdsMiscVoltAdjustment UINT8 ? ; Travis register LVDS_CTRL_4 to adjust LVDS output voltage
- CfgDisplayMiscControl DISPLAY_MISC_CONTROL {}; The Display Misc control
- Reserved BOOLEAN ? ; < reserved...
-BUILD_OPT_CFG ENDS
-
- ; A structure containing platform specific operational characteristics. This
- ; structure is initially populated by the initializer with a copy of the same
- ; structure that was created at build time using the build configuration controls.
-PLATFORM_CONFIGURATION STRUCT
- PlatformProfile PERFORMANCE_PROFILE {} ; < Several configuration settings for the processor.
- PlatformDeemphasisList POINTER ? ; < Deemphasis levels for the platform's HT links.
- CoreLevelingMode UINT8 ? ; < Indicates how to balance the number of cores per processor.
- C1eMode PLATFORM_C1E_MODES ? ; < Specifies the method of C1e enablement - Disabled, HW, or message based.
- C1ePlatformData UINT32 ? ; < If C1eMode is HW, specifies the P_LVL3 I/O port of the platform.
- C1ePlatformData1 UINT32 ? ; < If C1eMode is SW, specifies the address of chipset's SMI command port.
- C1ePlatformData2 UINT32 ? ; < If C1eMode is SW, specifies the unique number used by the SMI handler to identify SMI source.
- C1ePlatformData3 UINT32 ? ; < If C1eMode is Auto, specifies the P_LVL3 I/O port of the platform for HW C1e
- CStateMode PLATFORM_CSTATE_MODES ? ; < Specifies the method of C-State enablement - Disabled, or C6.
- CStatePlatformData UINT32 ? ; < This element specifies some pertinent data needed for the operation of the Cstate feature
- ; < If CStateMode is CStateModeC6, this item is reserved
- CStateIoBaseAddress UINT16 ? ; < This item specifies a free block of 8 consecutive bytes of I/O ports that
- ; < can be used to allow the CPU to enter Cstates.
- CpbMode PLATFORM_CPB_MODES ? ; < Specifies the method of core performance boost enablement - Disabled, or Auto.
- UserOptionDmi BOOLEAN ? ; < When set to TRUE, the DMI data table is generated.
- UserOptionPState BOOLEAN ? ; < When set to TRUE, the PState data tables are generated.
- UserOptionCrat BOOLEAN ? ; < When set to TRUE, the CRAT data table is generated.
- UserOptionCdit BOOLEAN ? ; < When set to TRUE, the CDIT data table is generated.
- UserOptionSrat BOOLEAN ? ; < When set to TRUE, the SRAT data table is generated.
- UserOptionSlit BOOLEAN ? ; < When set to TRUE, the SLIT data table is generated.
- UserOptionWhea BOOLEAN ? ; < When set to TRUE, the WHEA data table is generated.
- LowPowerPstateForProcHot PLATFORM_LOW_POWER_PSTATE_MODES ? ; < Specifies the method of low power Pstate for PROCHOT enablement - Disabled, or Auto.
- PowerCeiling UINT32 ? ; < P-State Ceiling Enabling Deck - Max power milli-watts.
- ForcePstateIndependent BOOLEAN ? ; < P-State _PSD independence or dependence.
- PStatesInHpcMode BOOLEAN ? ; < High performance computing (HPC) mode
- NumberOfIoApics UINT32 ? ; < Number of I/O APICs in the system
- VrmProperties PLATFORM_VRM_CONFIGURATION (MaxVrmType) DUP ({}) ; < Several configuration settings for the voltage regulator modules.
- ProcessorScopeInSb BOOLEAN ? ; < ACPI Processor Object in \_SB scope
- ProcessorScopeName0 CHAR8 ? ; < OEM specific 1st character of processor scope name.
- ProcessorScopeName1 CHAR8 ? ; < OEM specific 2nd character of processor scope name.
- GnbHdAudio UINT8 ? ; < Control GFX HD Audio controller(Used for HDMI and DP display output),
- ; < essentially it enables function 1 of graphics device.
- ; < @li 0 = HD Audio disable
- ; < @li 1 = HD Audio enable
- AbmSupport UINT8 ? ; < Automatic adjust LVDS/eDP Back light level support.It is
- ; < characteristic specific to display panel which used by platform design.
- ; < @li 0 = ABM support disabled
- ; < @li 1 = ABM support enabled
- DynamicRefreshRate UINT8 ? ; < Adjust refresh rate on LVDS/eDP.
- LcdBackLightControl UINT16 ? ; < The PWM frequency to LCD backlight control.
- ; < If equal to 0 backlight not controlled by iGPU.
-PLATFORM_CONFIGURATION ENDS
-
-
-; *********************************************************************
-; * Structures for: AmdInitLate
-; *********************************************************************
- PROC_VERSION_LENGTH EQU 48
- MAX_DIMMS_PER_SOCKET EQU 16
- PROC_MANU_LENGTH EQU 29
-
- ; Interface Parameter Structures
- ; DMI Type4 - Processor ID
-TYPE4_PROC_ID STRUCT
- ProcIdLsd UINT32 ? ; < Lower half of 64b ID
- ProcIdMsd UINT32 ? ; < Upper half of 64b ID
-TYPE4_PROC_ID ENDS
-
- ; DMI Type 4 - Processor information
-TYPE4_DMI_INFO STRUCT
- T4ProcType UINT8 ? ; < CPU Type
- T4ProcFamily UINT8 ? ; < Family 1
- T4ProcId TYPE4_PROC_ID {} ; < Id
- T4Voltage UINT8 ? ; < Voltage
- T4ExternalClock UINT16 ? ; < External clock
- T4MaxSpeed UINT16 ? ; < Max speed
- T4CurrentSpeed UINT16 ? ; < Current speed
- T4Status UINT8 ? ; < Status
- T4ProcUpgrade UINT8 ? ; < Up grade
- T4CoreCount UINT8 ? ; < Core count
- T4CoreEnabled UINT8 ? ; < Core Enable
- T4ThreadCount UINT8 ? ; < Thread count
- T4ProcCharacteristics UINT16 ? ; < Characteristics
- T4ProcFamily2 UINT16 ? ; < Family 2
- T4ProcVersion CHAR8 (PROC_VERSION_LENGTH) DUP (?) ; < Cpu version
- T4ProcManufacturer CHAR8 (PROC_MANU_LENGTH) DUP (?) ; < Manufacturer
-TYPE4_DMI_INFO ENDS
-
- ; DMI Type 7 - Cache information
-TYPE7_DMI_INFO STRUCT
- T7CacheCfg UINT16 ? ; < Cache cfg
- T7MaxCacheSize UINT16 ? ; < Max size
- T7InstallSize UINT16 ? ; < Install size
- T7SupportedSramType UINT16 ? ; < Supported Sram Type
- T7CurrentSramType UINT16 ? ; < Current type
- T7CacheSpeed UINT8 ? ; < Speed
- T7ErrorCorrectionType UINT8 ? ; < ECC type
- T7SystemCacheType UINT8 ? ; < Cache type
- T7Associativity UINT8 ? ; < Associativity
-TYPE7_DMI_INFO ENDS
-
- ; DMI Type 16 offset 04h - Location
-
- OtherLocation EQU 01h ; < Assign 01 to Other
- UnknownLocation EQU 2 ; < Assign 02 to Unknown
- SystemboardOrMotherboard EQU 3 ; < Assign 03 to systemboard or motherboard
- IsaAddonCard EQU 4 ; < Assign 04 to ISA add-on card
- EisaAddonCard EQU 5 ; < Assign 05 to EISA add-on card
- PciAddonCard EQU 6 ; < Assign 06 to PCI add-on card
- McaAddonCard EQU 7 ; < Assign 07 to MCA add-on card
- PcmciaAddonCard EQU 8 ; < Assign 08 to PCMCIA add-on card
- ProprietaryAddonCard EQU 9 ; < Assign 09 to proprietary add-on card
- NuBus EQU 10 ; < Assign 0A to NuBus
- Pc98C20AddonCard EQU 11 ; < Assign 0A0 to PC-98/C20 add-on card
- Pc98C24AddonCard EQU 12 ; < Assign 0A1 to PC-98/C24 add-on card
- Pc98EAddoncard EQU 13 ; < Assign 0A2 to PC-98/E add-on card
- Pc98LocalBusAddonCard EQU 14 ; < Assign 0A3 to PC-98/Local bus add-on card
-DMI_T16_LOCATION TEXTEQU <DWORD> ;} DMI_T16_LOCATION;
-
- ; DMI Type 16 offset 05h - Memory Error Correction
-
- OtherUse EQU 01h ; < Assign 01 to Other
- UnknownUse EQU 2 ; < Assign 02 to Unknown
- SystemMemory EQU 3 ; < Assign 03 to system memory
- VideoMemory EQU 4 ; < Assign 04 to video memory
- FlashMemory EQU 5 ; < Assign 05 to flash memory
- NonvolatileRam EQU 6 ; < Assign 06 to non-volatile RAM
- CacheMemory EQU 7 ; < Assign 07 to cache memory
-DMI_T16_USE TEXTEQU <DWORD> ;} DMI_T16_USE;
-
- ; DMI Type 16 offset 07h - Maximum Capacity
-
- Dmi16OtherErrCorrection EQU 01h ; < Assign 01 to Other
- Dmi16UnknownErrCorrection EQU 2 ; < Assign 02 to Unknown
- Dmi16NoneErrCorrection EQU 3 ; < Assign 03 to None
- Dmi16Parity EQU 4 ; < Assign 04 to parity
- Dmi16SingleBitEcc EQU 5 ; < Assign 05 to Single-bit ECC
- Dmi16MultiBitEcc EQU 6 ; < Assign 06 to Multi-bit ECC
- Dmi16Crc EQU 7 ; < Assign 07 to CRC
-DMI_T16_ERROR_CORRECTION TEXTEQU <DWORD> ;} DMI_T16_ERROR_CORRECTION;
-
- ; DMI Type 16 - Physical Memory Array
-TYPE16_DMI_INFO STRUCT
- Location DMI_T16_LOCATION ? ; < The physical location of the Memory Array,
- ; < whether on the system board or an add-in board.
- Use DMI_T16_USE ? ; < Identifies the function for which the array
- ; < is used.
- MemoryErrorCorrection DMI_T16_ERROR_CORRECTION ? ; < The primary hardware error correction or
- ; < detection method supported by this memory array.
- MaximumCapacity UINT32 ? ; < The maximum memory capacity, in kilobytes,
- ; < for the array.
- NumberOfMemoryDevices UINT16 ? ; < The number of slots or sockets available
- ; < for memory devices in this array.
- ExtMaxCapacity UINT64 ? ; < The maximum memory capacity, in bytes,
- ; < for this array.
-TYPE16_DMI_INFO ENDS
-
- ; DMI Type 17 offset 0Eh - Form Factor
- OtherFormFactor EQU 01h ; < Assign 01 to Other
- UnknowFormFactor EQU 2 ; < Assign 02 to Unknown
- SimmFormFactor EQU 3 ; < Assign 03 to SIMM
- SipFormFactor EQU 4 ; < Assign 04 to SIP
- ChipFormFactor EQU 5 ; < Assign 05 to Chip
- DipFormFactor EQU 6 ; < Assign 06 to DIP
- ZipFormFactor EQU 7 ; < Assign 07 to ZIP
- ProprietaryCardFormFactor EQU 8 ; < Assign 08 to Proprietary Card
- DimmFormFactorFormFactor EQU 9 ; < Assign 09 to DIMM
- TsopFormFactor EQU 10 ; < Assign 10 to TSOP
- RowOfChipsFormFactor EQU 11 ; < Assign 11 to Row of chips
- RimmFormFactor EQU 12 ; < Assign 12 to RIMM
- SodimmFormFactor EQU 13 ; < Assign 13 to SODIMM
- SrimmFormFactor EQU 14 ; < Assign 14 to SRIMM
- FbDimmFormFactor EQU 15 ; < Assign 15 to FB-DIMM
-DMI_T17_FORM_FACTOR TEXTEQU <DWORD>
-
- ; DMI Type 17 offset 12h - Memory Type
- OtherMemType EQU 01h ; < Assign 01 to Other
- UnknownMemType EQU 2 ; < Assign 02 to Unknown
- DramMemType EQU 3 ; < Assign 03 to DRAM
- EdramMemType EQU 4 ; < Assign 04 to EDRAM
- VramMemType EQU 5 ; < Assign 05 to VRAM
- SramMemType EQU 6 ; < Assign 06 to SRAM
- RamMemType EQU 7 ; < Assign 07 to RAM
- RomMemType EQU 8 ; < Assign 08 to ROM
- FlashMemType EQU 9 ; < Assign 09 to Flash
- EepromMemType EQU 10 ; < Assign 10 to EEPROM
- FepromMemType EQU 11 ; < Assign 11 to FEPROM
- EpromMemType EQU 12 ; < Assign 12 to EPROM
- CdramMemType EQU 13 ; < Assign 13 to CDRAM
- ThreeDramMemType EQU 14 ; < Assign 14 to 3DRAM
- SdramMemType EQU 15 ; < Assign 15 to SDRAM
- SgramMemType EQU 16 ; < Assign 16 to SGRAM
- RdramMemType EQU 17 ; < Assign 17 to RDRAM
- DdrMemType EQU 18 ; < Assign 18 to DDR
- Ddr2MemType EQU 19 ; < Assign 19 to DDR2
- Ddr2FbdimmMemType EQU 20 ; < Assign 20 to DDR2 FB-DIMM
- Ddr3MemType EQU 24 ; < Assign 24 to DDR3
- Fbd2MemType EQU 25 ; < Assign 25 to FBD2
-DMI_T17_MEMORY_TYPE TEXTEQU <DWORD>
-
- ; DMI Type 17 offset 13h - Type Detail
-DMI_T17_TYPE_DETAIL STRUCT
- Reserved1 UINT16 ?
-; OUT UINT16 Reserved1:1; ; < Reserved
-; OUT UINT16 Other:1; ; < Other
-; OUT UINT16 Unknown:1; ; < Unknown
-; OUT UINT16 FastPaged:1; ; < Fast-Paged
-; OUT UINT16 StaticColumn:1; ; < Static column
-; OUT UINT16 PseudoStatic:1; ; < Pseudo-static
-; OUT UINT16 Rambus:1; ; < RAMBUS
-; OUT UINT16 Synchronous:1; ; < Synchronous
-; OUT UINT16 Cmos:1; ; < CMOS
-; OUT UINT16 Edo:1; ; < EDO
-; OUT UINT16 WindowDram:1; ; < Window DRAM
-; OUT UINT16 CacheDram:1; ; < Cache Dram
-; OUT UINT16 NonVolatile:1; ; < Non-volatile
-; OUT UINT16 Registered:1; ; < Registered (Buffered)
-; OUT UINT16 Unbuffered:1; ; < Unbuffered (Unregistered)
-; OUT UINT16 Reserved2:1; ; < Reserved
-DMI_T17_TYPE_DETAIL ENDS
-
- ; DMI Type 17 - Memory Device
-TYPE17_DMI_INFO STRUCT
- TotalWidth UINT16 ? ; < Total Width, in bits, of this memory device, including any check or error-correction bits.
- DataWidth UINT16 ? ; < Data Width, in bits, of this memory device.
- MemorySize UINT16 ? ; < The size of the memory device.
- FormFactor DMI_T17_FORM_FACTOR ? ; < The implementation form factor for this memory device.
- DeviceSet UINT8 ? ; < Identifies when the Memory Device is one of a set of
- ; < Memory Devices that must be populated with all devices of
- ; < the same type and size, and the set to which this device belongs.
- DeviceLocator CHAR8 (8) DUP (?) ; < The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
- BankLocator CHAR8 (10) DUP (?) ; < The string number of the string that identifies the physically labeled bank where the memory device is located.
- MemoryType DMI_T17_MEMORY_TYPE ? ; < The type of memory used in this device.
- TypeDetail DMI_T17_TYPE_DETAIL {} ; < Additional detail on the memory device type
- Speed UINT16 ? ; < Identifies the speed of the device, in megahertz (MHz).
- ManufacturerIdCode UINT64 ? ; < Manufacturer ID code.
- SerialNumber CHAR8 (9) DUP (?) ; < Serial Number.
- PartNumber CHAR8 (19) DUP (?) ; < Part Number.
- Attributes UINT8 ? ; < Bits 7-4: Reserved, Bits 3-0: rank.
- ExtSize UINT32 ? ; < Extended Size.
- ConfigSpeed UINT16 ? ; < Configured memory clock speed
-TYPE17_DMI_INFO ENDS
-
- ; Memory DMI Type 17 and 20 - for memory use
-MEM_DMI_INFO STRUCT
- TotalWidth UINT16 ? ; < Total Width, in bits, of this memory device, including any check or error-correction bits.
- DataWidth UINT16 ? ; < Data Width, in bits, of this memory device.
- MemorySize UINT16 ? ; < The size of the memory device.
- FormFactor DMI_T17_FORM_FACTOR ? ; < The implementation form factor for this memory device.
- DeviceLocator UINT8 ? ; < The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
- BankLocator UINT8 ? ; < The string number of the string that identifies the physically labeled bank where the memory device is located.
- Speed UINT16 ? ; < Identifies the speed of the device, in megahertz (MHz).
- ManufacturerIdCode UINT64 ? ; < Manufacturer ID code.
- SerialNumber UINT8 (4) DUP (?) ; < Serial Number.
- PartNumber UINT8 (18) DUP (?) ; < Part Number.
- Attributes UINT8 ? ; < Bits 7-4: Reserved, Bits 3-0: rank.
- ExtSize UINT32 ? ; < Extended Size.
- Socket UINT8 ?
-; OUT UINT8 Socket:3 ; < Socket ID
-; OUT UINT8 Channel:2 ; < Channel ID
-; OUT UINT8 Dimm:2 ; < DIMM ID
-; OUT UINT8 DimmPresent:1 ; < Dimm Present
- StartingAddr UINT32 ? ; < The physical address, in kilobytes, of a range
- ; < of memory mapped to the referenced Memory Device.
- EndingAddr UINT32 ? ; < The handle, or instance number, associated with
- ; < the Memory Device structure to which this address
- ; < range is mapped.
- ConfigSpeed UINT16 ? ; < Configured memory clock speed
- ExtStartingAddr UINT64 ? ; < The physical address, in bytes, of a range of
- ; < memory mapped to the referenced Memory Device.
- ExtEndingAddr UINT64 ? ; < The physical ending address, in bytes, of the last of
- ; < a range of addresses mapped to the referenced Memory Device.
-MEM_DMI_INFO ENDS
-
- ; DMI Type 19 - Memory Array Mapped Address
-TYPE19_DMI_INFO STRUCT
- StartingAddr UINT32 ? ; < The physical address, in kilobytes,
- ; < of a range of memory mapped to the
- ; < specified physical memory array.
- EndingAddr UINT32 ? ; < The physical ending address of the
- ; < last kilobyte of a range of addresses
- ; < mapped to the specified physical memory array.
- MemoryArrayHandle UINT16 ? ; < The handle, or instance number, associated
- ; < with the physical memory array to which this
- ; < address range is mapped.
- PartitionWidth UINT8 ? ; < Identifies the number of memory devices that
- ; < form a single row of memory for the address
- ; < partition defined by this structure.
- ExtStartingAddr UINT64 ? ; < The physical address, in bytes, of a range of
- ; < memory mapped to the specified Physical Memory Array.
- ExtEndingAddr UINT64 ? ; < The physical address, in bytes, of a range of
- ; < memory mapped to the specified Physical Memory Array.
-TYPE19_DMI_INFO ENDS
-
-; DMI Type 20 - Memory Device Mapped Address
-TYPE20_DMI_INFO STRUCT
- StartingAddr UINT32 ? ; < The physical address, in kilobytes, of a range
- ; < of memory mapped to the referenced Memory Device.
- EndingAddr UINT32 ? ; < The handle, or instance number, associated with
- ; < the Memory Device structure to which this address
- ; < range is mapped.
- MemoryDeviceHandle UINT16 ? ; < The handle, or instance number, associated with
- ; < the Memory Device structure to which this address
- ; < range is mapped.
- MemoryArrayMappedAddressHandle UINT16 ? ; < The handle, or instance number, associated
- ; < with the Memory Array Mapped Address structure to
- ; < which this device address range is mapped.
- PartitionRowPosition UINT8 ? ; < Identifies the position of the referenced Memory
- ; < Device in a row of the address partition.
- InterleavePosition UINT8 ? ; < The position of the referenced Memory Device in
- ; < an interleave.
- InterleavedDataDepth UINT8 ? ; < The maximum number of consecutive rows from the
- ; < referenced Memory Device that are accessed in a
- ; < single interleaved transfer.
- ExtStartingAddr UINT64 ? ; < The physical address, in bytes, of a range of
- ; < memory mapped to the referenced Memory Device.
- ExtEndingAddr UINT64 ? ; < The physical ending address, in bytes, of the last of
- ; < a range of addresses mapped to the referenced Memory Device.
-TYPE20_DMI_INFO ENDS
-
- ; Collection of pointers to the DMI records
-DMI_INFO STRUCT
- T4 TYPE4_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 4 struc
- T7L1 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 1
- T7L2 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 2
- T7L3 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 3
- T16 TYPE16_DMI_INFO {} ; < Type 16 struc
- T17 TYPE17_DMI_INFO (MAX_SOCKETS_SUPPORTED * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL) DUP ({}) ; < Type 17 struc
- T19 TYPE19_DMI_INFO {} ; < Type 19 struc
- T20 TYPE20_DMI_INFO (MAX_SOCKETS_SUPPORTED * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL) DUP ({}) ; < Type 20 struc
-DMI_INFO ENDS
-
-
-
-; *********************************************************************
-; * Interface call: AllocateExecutionCache
-; *********************************************************************
- MAX_CACHE_REGIONS EQU 3
-
- ; AllocateExecutionCache sub param structure for cached memory region
-EXECUTION_CACHE_REGION STRUCT
- ExeCacheStartAddr UINT32 ? ; < Start address
- ExeCacheSize UINT32 ? ; < Size
-EXECUTION_CACHE_REGION ENDS
-
-; *********************************************************************
-; * Interface call: AmdGetAvailableExeCacheSize
-; *********************************************************************
- ; Get available Cache remain
-AMD_GET_EXE_SIZE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- AvailableExeCacheSize UINT32 ? ; < Remain size
-AMD_GET_EXE_SIZE_PARAMS ENDS
-
-
-
-
-
-
- ; Selection type for core leveling
- CORE_LEVEL_LOWEST EQU 0 ; < Level to lowest common denominator
- CORE_LEVEL_TWO EQU 1 ; < Level to 2 cores
- CORE_LEVEL_POWER_OF_TWO EQU 2 ; < Level to 1,2,4 or 8
- CORE_LEVEL_NONE EQU 3 ; < Do no leveling
- CORE_LEVEL_COMPUTE_UNIT EQU 4 ; < Level cores to one core per compute unit
- CORE_LEVEL_ONE EQU 5 ; < Level to 1 core
- CORE_LEVEL_THREE EQU 6 ; < Level to 3 cores
- CORE_LEVEL_FOUR EQU 7 ; < Level to 4 cores
- CORE_LEVEL_FIVE EQU 8 ; < Level to 5 cores
- CORE_LEVEL_SIX EQU 9 ; < Level to 6 cores
- CORE_LEVEL_SEVEN EQU 10 ; < Level to 7 cores
- CORE_LEVEL_EIGHT EQU 11 ; < Level to 8 cores
- CORE_LEVEL_NINE EQU 12 ; < Level to 9 cores
- CORE_LEVEL_TEN EQU 13 ; < Level to 10 cores
- CORE_LEVEL_ELEVEN EQU 14 ; < Level to 11 cores
- CORE_LEVEL_TWELVE EQU 15 ; < Level to 12 cores
- CORE_LEVEL_THIRTEEN EQU 16 ; < Level to 13 cores
- CORE_LEVEL_FOURTEEN EQU 17 ; < Level to 14 cores
- CORE_LEVEL_FIFTEEN EQU 18 ; < Level to 15 cores
- CoreLevelModeMax EQU 19 ; < Used for bounds checking
-CORE_LEVELING_TYPE TEXTEQU <DWORD>
-
-
-; ***********************************************************************
-; *
-; * AGESA Basic Level interface structure definition and function prototypes
-; *
-; **********************************************************************
-
-; *********************************************************************
-; * Interface call: AmdCreateStruct
-; *********************************************************************
-
-; *********************************************************************
-; * Interface call: AmdReleaseStruct
-; *********************************************************************
-
-; *********************************************************************
-; * Interface call: AmdInitReset
-; *********************************************************************
- ; AmdInitReset param structure
-AMD_RESET_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < The cached memory region
- HtConfig AMD_HT_RESET_INTERFACE {} ; < The interface for Ht Recovery
- FchInterface FCH_RESET_INTERFACE {} ; Interface for FCH configuration
-AMD_RESET_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitEarly
-; *********************************************************************
- ; InitEarly param structure
-
- ; Provide defaults or customizations to each service performed in AmdInitEarly.
-
-AMD_EARLY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < The standard header
- CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < Execution Map Interface
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- HtConfig AMD_HT_INTERFACE {} ; < HyperTransport Interface
- GnbConfig GNB_CONFIGURATION {} ; < GNB configuration
-AMD_EARLY_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitPost
-; *********************************************************************
- ; AmdInitPost param structure
-AMD_POST_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- MemConfig MEM_PARAMETER_STRUCT {} ; < Memory post param
- GnbPostConfig GNB_POST_CONFIGURATION {}
-AMD_POST_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitEnv
-; *********************************************************************
- ; AmdInitEnv param structure
-AMD_ENV_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- GnbEnvConfiguration GNB_ENV_CONFIGURATION {} ; < GNB configuration
- FchInterface FCH_INTERFACE {} ; FCH configuration
-AMD_ENV_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitMid
-; *********************************************************************
- ; AmdInitMid param structure
-AMD_MID_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics
- GnbMidConfiguration GNB_MID_CONFIGURATION {} ; < GNB configuration
- FchInterface FCH_INTERFACE {} ; FCH configuration
-AMD_MID_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitLate
-; *********************************************************************
- ; AmdInitLate param structure
-AMD_LATE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- IvrsExclusionRangeList POINTER ? ; < IVMD exclusion range descriptor
- DmiTable POINTER ? ; < DMI Interface
- AcpiPState POINTER ? ; < Acpi Pstate SSDT Table
- AcpiSrat POINTER ? ; < SRAT Table
- AcpiSlit POINTER ? ; < SLIT Table
- AcpiWheaMce POINTER ? ; < WHEA MCE Table
- AcpiWheaCmc POINTER ? ; < WHEA CMC Table
- AcpiAlib POINTER ? ; < ALIB Table
- AcpiIvrs POINTER ? ; < IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table
- AcpiCrat POINTER ? ; < Component Resource Affinity Table table
- AcpiCdit POINTER ? ; < Component Locality Distance Information table
-AMD_LATE_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitRecovery
-; *********************************************************************
- ; CPU Recovery Parameters
-AMD_CPU_RECOVERY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard Header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics
-AMD_CPU_RECOVERY_PARAMS ENDS
-
- ; AmdInitRecovery param structure
-AMD_RECOVERY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- MemConfig MEM_PARAMETER_STRUCT {} ; < Memory post param
- CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < The cached memory region. And the max cache region is 3
- CpuRecoveryParams AMD_CPU_RECOVERY_PARAMS {} ; < Params for CPU related recovery init.
-AMD_RECOVERY_PARAMS ENDS
-
-
-; *********************************************************************
-; * Interface call: AmdInitResume
-; *********************************************************************
- ; AmdInitResume param structure
-AMD_RESUME_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < Platform operational characteristics
- S3DataBlock AMD_S3_PARAMS {} ; < Save state data
-AMD_RESUME_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdS3LateRestore
-; *********************************************************************
- ; AmdS3LateRestore param structure
-AMD_S3LATE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- S3DataBlock AMD_S3_PARAMS {} ; < Save state data
-AMD_S3LATE_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdS3Save
-; *********************************************************************
- ; AmdS3Save param structure
-AMD_S3SAVE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- S3DataBlock AMD_S3_PARAMS {} ; < Standard header
- FchInterface FCH_INTERFACE {} ; FCH configuration
-AMD_S3SAVE_PARAMS ENDS
-
- ; General Services API
-
-
-; *********************************************************************
-; * Interface service call: AmdGetApicId
-; *********************************************************************
- ; Request the APIC ID of a particular core.
-
-AMD_APIC_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- Socket UINT8 ? ; < The Core's Socket.
- Core UINT8 ? ; < The Core id.
- IsPresent BOOLEAN ? ; < The Core is present, and ApicAddress is valid.
- ApicAddress UINT8 ? ; < The Core's APIC ID.
-AMD_APIC_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdGetPciAddress
-; *********************************************************************
- ; Request the PCI Address of a Processor Module (that is, its Northbridge)
-
-AMD_GET_PCI_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- Socket UINT8 ? ; < The Processor's socket
- Module UINT8 ? ; < The Module in that Processor
- IsPresent BOOLEAN ? ; < The Core is present, and PciAddress is valid.
- PciAddress PCI_ADDR {} ; < The Processor's PCI Config Space address (Function 0, Register 0)
-AMD_GET_PCI_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdIdentifyCore
-; *********************************************************************
- ; Request the identity (Socket, Module, Core) of the current Processor Core
-
-AMD_IDENTIFY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- Socket UINT8 ? ; < The current Core's Socket
- Module UINT8 ? ; < The current Core's Processor Module
- Core UINT8 ? ; < The current Core's core id.
-AMD_IDENTIFY_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdReadEventLog
-; *********************************************************************
- ; An Event Log Entry.
-EVENT_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- EventClass UINT32 ? ; < The severity of this event, matches AGESA_STATUS.
- EventInfo UINT32 ? ; < The unique event identifier, zero means "no event".
- DataParam1 UINT32 ? ; < Data specific to the Event.
- DataParam2 UINT32 ? ; < Data specific to the Event.
- DataParam3 UINT32 ? ; < Data specific to the Event.
- DataParam4 UINT32 ? ; < Data specific to the Event.
-EVENT_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdIdentifyDimm
-; *********************************************************************
- ; Request the identity of dimm from system address
-
-AMD_IDENTIFY_DIMM STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- MemoryAddress UINT64 ? ; < System Address that needs to be translated to dimm identification.
- SocketId UINT8 ? ; < The socket on which the targeted address locates.
- MemChannelId UINT8 ? ; < The channel on which the targeted address locates.
- DimmId UINT8 ? ; < The dimm on which the targeted address locates.
-AMD_IDENTIFY_DIMM ENDS
-
- ; Data structure for the Mapping Item between Unified ID for IDS Setup Option
- ; and the option value.
-
-IDS_NV_ITEM STRUCT
- IdsNvId UINT16 ? ; < Unified ID for IDS Setup Option.
- IdsNvValue UINT16 ? ; < The value of IDS Setup Option.
-IDS_NV_ITEM ENDS
-
- ; Data Structure for IDS CallOut Function
-IDS_CALLOUT_STRUCT STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < The Standard Header for AGESA Service
- IdsNvPtr POINTER ? ; < Memory Pointer of IDS NV Table
- Reserved UINT32 ? ; < reserved
-IDS_CALLOUT_STRUCT ENDS
-
- AGESA_IDS_DFT_VAL EQU 0FFFFh; < Default value of every uninitlized NV item, the action for it will be ignored
- AGESA_IDS_NV_END EQU 0FFFFh; < Flag specify end of option structure
-; WARNING: Don't change the comment below, it used as signature for script
-; AGESA IDS NV ID Definitions
- AGESA_IDS_EXT_ID_START EQU 0000h; < specify the start of external NV id
-
- AGESA_IDS_NV_UCODE EQU 0001h; < Enable or disable microcode patching
-
- AGESA_IDS_NV_TARGET_PSTATE EQU 0002h; < Set the P-state required to be activated
- AGESA_IDS_NV_POSTPSTATE EQU 0003h; < Set the P-state required to be activated through POST
-
- AGESA_IDS_NV_BANK_INTERLEAVE EQU 0004h; < Enable or disable Bank Interleave
- AGESA_IDS_NV_CHANNEL_INTERLEAVE EQU 0005h; < Enable or disable Channel Interleave
- AGESA_IDS_NV_NODE_INTERLEAVE EQU 0006h; < Enable or disable Node Interleave
- AGESA_IDS_NV_MEMHOLE EQU 0007h; < Enables or disable memory hole
-
- AGESA_IDS_NV_SCRUB_REDIRECTION EQU 0008h; < Enable or disable a write to dram with corrected data
- AGESA_IDS_NV_DRAM_SCRUB EQU 0009h; < Set the rate of background scrubbing for DRAM
- AGESA_IDS_NV_DCACHE_SCRUB EQU 000Ah; < Set the rate of background scrubbing for the DCache.
- AGESA_IDS_NV_L2_SCRUB EQU 000Bh; < Set the rate of background scrubbing for the L2 cache
- AGESA_IDS_NV_L3_SCRUB EQU 000Ch; < Set the rate of background scrubbing for the L3 cache
- AGESA_IDS_NV_ICACHE_SCRUB EQU 000Dh; < Set the rate of background scrubbing for the Icache
- AGESA_IDS_NV_SYNC_ON_ECC_ERROR EQU 000Eh; < Enable or disable the sync flood on un-correctable ECC error
- AGESA_IDS_NV_ECC_SYMBOL_SIZE EQU 000Fh; < Set ECC symbol size
-
- AGESA_IDS_NV_ALL_MEMCLKS EQU 0010h; < Enable or disable all memory clocks enable
- AGESA_IDS_NV_DCT_GANGING_MODE EQU 0011h; < Set the Ganged mode
- AGESA_IDS_NV_DRAM_BURST_LENGTH32 EQU 0012h; < Set the DRAM Burst Length 32
- AGESA_IDS_NV_MEMORY_POWER_DOWN EQU 0013h; < Enable or disable Memory power down mode
- AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE EQU 0014h; < Set the Memory power down mode
- AGESA_IDS_NV_DLL_SHUT_DOWN EQU 0015h; < Enable or disable DLLShutdown
- AGESA_IDS_NV_ONLINE_SPARE EQU 0016h; < Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap
-
- AGESA_IDS_NV_HT_ASSIST EQU 0017h; < Enable or Disable HT Assist
- AGESA_IDS_NV_ATMMODE EQU 0018h; < Enable or Disable ATM mode
-
- AGESA_IDS_NV_HDTOUT EQU 0019h; < Enable or disable HDTOUT feature
-
- AGESA_IDS_NV_HTLINKSOCKET EQU 001Ah; < HT Link Socket
- AGESA_IDS_NV_HTLINKPORT EQU 001Bh; < HT Link Port
- AGESA_IDS_NV_HTLINKFREQ EQU 001Ch; < HT Link Frequency
- AGESA_IDS_NV_HTLINKWIDTHIN EQU 001Dh; < HT Link In Width
- AGESA_IDS_NV_HTLINKWIDTHOUT EQU 001Eh; < HT Link Out Width
-
- AGESA_IDS_NV_GNBHDAUDIOEN EQU 001Fh; < Enable or disable GNB HD Audio
-
- AGESA_IDS_NV_CPB_EN EQU 0020h; < Core Performance Boost
-
- AGESA_IDS_NV_HTC_EN EQU 0021h; < HTC Enable
- AGESA_IDS_NV_HTC_OVERRIDE EQU 0022h; < HTC Override
- AGESA_IDS_NV_HTC_PSTATE_LIMIT EQU 0023h; < HTC P-state limit select
- AGESA_IDS_NV_HTC_TEMP_HYS EQU 0024h; < HTC Temperature Hysteresis
- AGESA_IDS_NV_HTC_ACT_TEMP EQU 0025h; < HTC Activation Temp
-
- AGESA_IDS_NV_POWER_POLICY EQU 0026h; < Select Platform Power Policy
- AGESA_IDS_EXT_ID_END EQU 0027h; < specify the end of external NV ID
-
- IDS_EX_NV_ID TEXTEQU <DWORD>
diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/amd.inc b/src/vendorcode/amd/agesa/f15tn/Legacy/amd.inc
deleted file mode 100644
index 550475a04a..0000000000
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/amd.inc
+++ /dev/null
@@ -1,461 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * Agesa structures and definitions
-; *
-; * Contains AMD AGESA core interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
-;
-; ****************************************************************************
-; *
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; *
-; **************************************************************************
-
-
-UINT64 TEXTEQU <QWORD>
-UINT32 TEXTEQU <DWORD>
-UINT16 TEXTEQU <WORD>
-UINT8 TEXTEQU <BYTE>
-CHAR8 TEXTEQU <BYTE>
-BOOLEAN TEXTEQU <BYTE>
-POINTER TEXTEQU <DWORD>
-
- ; AGESA Types and Definitions
-
- AGESA_REVISION EQU "Arch2008"
- AGESA_ID EQU "AGESA"
-
- LAST_ENTRY EQU 0FFFFFFFFh
- IMAGE_SIGNATURE EQU 'DMA$'
- IOCF8 EQU 0CF8h
- IOCFC EQU 0CFCh
-
- ; The return status for all AGESA public services.
-
- ; Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
- ; will have log entries with more detail.
-
- AGESA_SUCCESS EQU 0 ; < The service completed normally. Info may be logged.
- AGESA_UNSUPPORTED EQU 1 ; < The dispatcher or create struct had an unimplemented function requested.
- ; < Not logged.
- AGESA_BOUNDS_CHK EQU 2 ; < A dynamic parameter was out of range and the service was not provided.
- ; < Example, memory address not installed, heap buffer handle not found.
- ; < Not Logged.
- ; AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
- AGESA_ALERT EQU 3 ; < An observed condition, but no loss of function.
- ; < See log. Example, HT CRC.
- AGESA_WARNING EQU 4 ; < Possible or minor loss of function. See Log.
- AGESA_ERROR EQU 5 ; < Significant loss of function, boot may be possible. See Log.
- AGESA_CRITICAL EQU 6 ; < Continue boot only to notify user. See Log.
- AGESA_FATAL EQU 7 ; < Halt booting. See Log.
- AgesaStatusMax EQU 8 ; < Not a status, use for limit checking.
-AGESA_STATUS TEXTEQU <DWORD>
-
-; For checking whether a status is at or above the mandatory log level.
-AGESA_STATUS_LOG_LEVEL EQU AGESA_ALERT
-
- CALLOUT_ENTRY TEXTEQU <POINTER>
- IMAGE_ENTRY TEXTEQU <POINTER>
- MODULE_ENTRY TEXTEQU <POINTER>
-
-; This allocation type is used by the AmdCreateStruct entry point
- PreMemHeap EQU 0 ; < Create heap in cache.
- PostMemDram EQU 1 ; < Create heap in memory.
- ByHost EQU 2 ; < Create heap by Host.
-ALLOCATION_METHOD TEXTEQU <DWORD>
-
- ; These width descriptors are used by the library function, and others, to specify the data size
- AccessWidth8 EQU 1 ; < Access width is 8 bits.
- AccessWidth16 EQU 2 ; < Access width is 16 bits.
- AccessWidth32 EQU 3 ; < Access width is 32 bits.
- AccessWidth64 EQU 4 ; < Access width is 64 bits.
-
- AccessS3SaveWidth8 EQU 81h ; < Save 8 bits data.
- AccessS3SaveWidth16 EQU 130 ; < Save 16 bits data.
- AccessS3SaveWidth32 EQU 131 ; < Save 32 bits data.
- AccessS3SaveWidth64 EQU 132 ; < Save 64 bits data.
-ACCESS_WIDTH TEXTEQU <DWORD>
-
- ; AGESA struct name
-
- ; AGESA BASIC FUNCTIONS
- AMD_INIT_RECOVERY EQU 00020000h
- AMD_CREATE_STRUCT EQU 00020001h
- AMD_INIT_EARLY EQU 00020002h
- AMD_INIT_ENV EQU 00020003h
- AMD_INIT_LATE EQU 00020004h
- AMD_INIT_MID EQU 00020005h
- AMD_INIT_POST EQU 00020006h
- AMD_INIT_RESET EQU 00020007h
- AMD_INIT_RESUME EQU 00020008h
- AMD_RELEASE_STRUCT EQU 00020009h
- AMD_S3LATE_RESTORE EQU 0002000Ah
- AMD_S3_SAVE EQU 0002000Bh
- AMD_GET_APIC_ID EQU 0002000Ch
- AMD_GET_PCI_ADDRESS EQU 0002000Dh
- AMD_IDENTIFY_CORE EQU 0002000Eh
- AMD_READ_EVENT_LOG EQU 0002000Fh
- AMD_GET_EXECACHE_SIZE EQU 00020010h
- AMD_LATE_RUN_AP_TASK EQU 00020011h
- AMD_IDENTIFY_DIMMS EQU 00020012h
-AGESA_STRUCT_NAME TEXTEQU <DWORD>
-
-
- ; ResetType constant values
- WARM_RESET_WHENEVER EQU 1
- COLD_RESET_WHENEVER EQU 2
- WARM_RESET_IMMEDIATELY EQU 3
- COLD_RESET_IMMEDIATELY EQU 4
-
-
- ; AGESA Structures
-
- ; The standard header for all AGESA services.
-AMD_CONFIG_PARAMS STRUCT
- ImageBasePtr UINT32 ? ; < The AGESA Image base address.
- Func UINT32 ? ; < The service desired, @sa dispatch.h.
- AltImageBasePtr UINT32 ? ; < Alternate Image location
- CalloutPtr CALLOUT_ENTRY ? ; < For Callout from AGESA
- HeapStatus UINT8 ? ; < For heap status from boot time slide.
- HeapBasePtr UINT64 ? ; < Location of the heap
- Reserved UINT8 (7) DUP (?) ; < This space is reserved for future use.
-AMD_CONFIG_PARAMS ENDS
-
-
- ; Create Struct Interface.
-AMD_INTERFACE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Config header
- AgesaFunctionName AGESA_STRUCT_NAME ? ; < The service to init, @sa dispatch.h
- AllocationMethod ALLOCATION_METHOD ? ; < How to handle buffer allocation
- NewStructSize UINT32 ? ; < The size of the allocated data, in for ByHost, else out only.
- NewStructPtr POINTER ? ; < The struct for the service.
- ; < The struct to init for ByHost allocation,
- ; < the initialized struct on return.
-AMD_INTERFACE_PARAMS ENDS
-
- FUNC_0 EQU 0 ; bit-placed for PCI address creation
- FUNC_1 EQU 1
- FUNC_2 EQU 2
- FUNC_3 EQU 3
- FUNC_4 EQU 4
- FUNC_5 EQU 5
- FUNC_6 EQU 6
- FUNC_7 EQU 7
-
- ; AGESA Binary module header structure
-AMD_IMAGE_HEADER STRUCT
- Signature UINT32 ? ; < Binary Signature
- CreatorID CHAR8 (8) DUP (?) ; < 8 characters ID
- Version CHAR8 (12) DUP (?) ; < 12 characters version
- ModuleInfoOffset UINT32 ? ; < Offset of module
- EntryPointAddress UINT32 ? ; < Entry address
- ImageBase UINT32 ? ; < Image base
- RelocTableOffset UINT32 ? ; < Relocate Table offset
- ImageSize UINT32 ? ; < Size
- Checksum UINT16 ? ; < Checksum
- ImageType UINT8 ? ; < Type
- V_Reserved UINT8 ? ; < Reserved
-AMD_IMAGE_HEADER ENDS
- ; AGESA Binary module header structure
-AMD_MODULE_HEADER STRUCT
- ModuleHeaderSignature UINT32 ? ; < Module signature
- ModuleIdentifier CHAR8 (8) DUP (?) ; < 8 characters ID
- ModuleVersion CHAR8 (12) DUP (?) ; < 12 characters version
- ModuleDispatcher POINTER ? ; < A pointer point to dispatcher
- NextBlock POINTER ? ; < Next module header link
-AMD_MODULE_HEADER ENDS
-
-; AMD_CODE_HEADER Signatures.
-AGESA_CODE_SIGNATURE TEXTEQU <'!', '!', 'A', 'G', 'E', 'S', 'A', ' '>
-CIMXNB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'>
-CIMXSB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'>
-
-; AGESA_CODE_SIGNATURE
-AMD_CODE_HEADER STRUCT
- Signature CHAR8 (8) DUP (?) ; < code header Signature
- ComponentName CHAR8 (8) DUP (?) ; < 8 character name of the code module
- Version CHAR8 (12) DUP (?) ; < 12 character version string
- TerminatorNull CHAR8 ? ; < null terminated string
- VerReserved CHAR8 (7) DUP (?) ; < reserved space
-AMD_CODE_HEADER ENDS
-
- ; Extended PCI address format
-EXT_PCI_ADDR STRUCT
- Register UINT32 ?
-; IN OUT UINT32 Register:12; ; < Register offset
-; IN OUT UINT32 Function:3; ; < Function number
-; IN OUT UINT32 Device:5; ; < Device number
-; IN OUT UINT32 Bus:8; ; < Bus number
-; IN OUT UINT32 Segment:4; ; < Segment
-EXT_PCI_ADDR ENDS
-
- ; Union type for PCI address
-PCI_ADDR UNION
- AddressValue UINT32 ? ; < Formal address
- Address EXT_PCI_ADDR {} ; < Extended address
-PCI_ADDR ENDS
-
- ; SBDFO - Segment Bus Device Function Offset
- ; 31:28 Segment (4-bits)
- ; 27:20 Bus (8-bits)
- ; 19:15 Device (5-bits)
- ; 14:12 Function(3-bits)
- ; 11:00 Offset (12-bits)
-
-
-
- ILLEGAL_SBDFO EQU 0FFFFFFFFh
-
- ; CPUID data received registers format
-CPUID_DATA STRUCT
- EAX_Reg UINT32 ? ; < CPUID instruction result in EAX
- EBX_Reg UINT32 ? ; < CPUID instruction result in EBX
- ECX_Reg UINT32 ? ; < CPUID instruction result in ECX
- EDX_Reg UINT32 ? ; < CPUID instruction result in EDX
-CPUID_DATA ENDS
-
- ; HT frequency for external callbacks
-;typedef enum {
- HT_FREQUENCY_200M EQU 0 ; < HT speed 200 for external callbacks
- HT_FREQUENCY_400M EQU 2 ; < HT speed 400 for external callbacks
- HT_FREQUENCY_600M EQU 4 ; < HT speed 600 for external callbacks
- HT_FREQUENCY_800M EQU 5 ; < HT speed 800 for external callbacks
- HT_FREQUENCY_1000M EQU 6 ; < HT speed 1000 for external callbacks
- HT_FREQUENCY_1200M EQU 7 ; < HT speed 1200 for external callbacks
- HT_FREQUENCY_1400M EQU 8 ; < HT speed 1400 for external callbacks
- HT_FREQUENCY_1600M EQU 9 ; < HT speed 1600 for external callbacks
- HT_FREQUENCY_1800M EQU 10 ; < HT speed 1800 for external callbacks
- HT_FREQUENCY_2000M EQU 11 ; < HT speed 2000 for external callbacks
- HT_FREQUENCY_2200M EQU 12 ; < HT speed 2200 for external callbacks
- HT_FREQUENCY_2400M EQU 13 ; < HT speed 2400 for external callbacks
- HT_FREQUENCY_2600M EQU 14 ; < HT speed 2600 for external callbacks
- HT_FREQUENCY_2800M EQU 17 ; < HT speed 2800 for external callbacks
- HT_FREQUENCY_3000M EQU 18 ; < HT speed 3000 for external callbacks
- HT_FREQUENCY_3200M EQU 19 ; < HT speed 3200 for external callbacks
- HT_FREQUENCY_MAX EQU 20 ; < Limit Check.
-HT_FREQUENCIES TEXTEQU <DWORD> ;} HT_FREQUENCIES;
-
-HT3_FREQUENCY_MIN EQU HT_FREQUENCY_1200M
-
-IFNDEF BIT0
- BIT0 EQU 0000000000000001h
-ENDIF
-IFNDEF BIT1
- BIT1 EQU 0000000000000002h
-ENDIF
-IFNDEF BIT2
- BIT2 EQU 0000000000000004h
-ENDIF
-IFNDEF BIT3
- BIT3 EQU 0000000000000008h
-ENDIF
-IFNDEF BIT4
- BIT4 EQU 0000000000000010h
-ENDIF
-IFNDEF BIT5
- BIT5 EQU 0000000000000020h
-ENDIF
-IFNDEF BIT6
- BIT6 EQU 0000000000000040h
-ENDIF
-IFNDEF BIT7
- BIT7 EQU 0000000000000080h
-ENDIF
-IFNDEF BIT8
- BIT8 EQU 0000000000000100h
-ENDIF
-IFNDEF BIT9
- BIT9 EQU 0000000000000200h
-ENDIF
-IFNDEF BIT10
- BIT10 EQU 0000000000000400h
-ENDIF
-IFNDEF BIT11
- BIT11 EQU 0000000000000800h
-ENDIF
-IFNDEF BIT12
- BIT12 EQU 0000000000001000h
-ENDIF
-IFNDEF BIT13
- BIT13 EQU 0000000000002000h
-ENDIF
-IFNDEF BIT14
- BIT14 EQU 0000000000004000h
-ENDIF
-IFNDEF BIT15
- BIT15 EQU 0000000000008000h
-ENDIF
-IFNDEF BIT16
- BIT16 EQU 0000000000010000h
-ENDIF
-IFNDEF BIT17
- BIT17 EQU 0000000000020000h
-ENDIF
-IFNDEF BIT18
- BIT18 EQU 0000000000040000h
-ENDIF
-IFNDEF BIT19
- BIT19 EQU 0000000000080000h
-ENDIF
-IFNDEF BIT20
- BIT20 EQU 0000000000100000h
-ENDIF
-IFNDEF BIT21
- BIT21 EQU 0000000000200000h
-ENDIF
-IFNDEF BIT22
- BIT22 EQU 0000000000400000h
-ENDIF
-IFNDEF BIT23
- BIT23 EQU 0000000000800000h
-ENDIF
-IFNDEF BIT24
- BIT24 EQU 0000000001000000h
-ENDIF
-IFNDEF BIT25
- BIT25 EQU 0000000002000000h
-ENDIF
-IFNDEF BIT26
- BIT26 EQU 0000000004000000h
-ENDIF
-IFNDEF BIT27
- BIT27 EQU 0000000008000000h
-ENDIF
-IFNDEF BIT28
- BIT28 EQU 0000000010000000h
-ENDIF
-IFNDEF BIT29
- BIT29 EQU 0000000020000000h
-ENDIF
-IFNDEF BIT30
- BIT30 EQU 0000000040000000h
-ENDIF
-IFNDEF BIT31
- BIT31 EQU 0000000080000000h
-ENDIF
-IFNDEF BIT32
- BIT32 EQU 0000000100000000h
-ENDIF
-IFNDEF BIT33
- BIT33 EQU 0000000200000000h
-ENDIF
-IFNDEF BIT34
- BIT34 EQU 0000000400000000h
-ENDIF
-IFNDEF BIT35
- BIT35 EQU 0000000800000000h
-ENDIF
-IFNDEF BIT36
- BIT36 EQU 0000001000000000h
-ENDIF
-IFNDEF BIT37
- BIT37 EQU 0000002000000000h
-ENDIF
-IFNDEF BIT38
- BIT38 EQU 0000004000000000h
-ENDIF
-IFNDEF BIT39
- BIT39 EQU 0000008000000000h
-ENDIF
-IFNDEF BIT40
- BIT40 EQU 0000010000000000h
-ENDIF
-IFNDEF BIT41
- BIT41 EQU 0000020000000000h
-ENDIF
-IFNDEF BIT42
- BIT42 EQU 0000040000000000h
-ENDIF
-IFNDEF BIT43
- BIT43 EQU 0000080000000000h
-ENDIF
-IFNDEF BIT44
- BIT44 EQU 0000100000000000h
-ENDIF
-IFNDEF BIT45
- BIT45 EQU 0000200000000000h
-ENDIF
-IFNDEF BIT46
- BIT46 EQU 0000400000000000h
-ENDIF
-IFNDEF BIT47
- BIT47 EQU 0000800000000000h
-ENDIF
-IFNDEF BIT48
- BIT48 EQU 0001000000000000h
-ENDIF
-IFNDEF BIT49
- BIT49 EQU 0002000000000000h
-ENDIF
-IFNDEF BIT50
- BIT50 EQU 0004000000000000h
-ENDIF
-IFNDEF BIT51
- BIT51 EQU 0008000000000000h
-ENDIF
-IFNDEF BIT52
- BIT52 EQU 0010000000000000h
-ENDIF
-IFNDEF BIT53
- BIT53 EQU 0020000000000000h
-ENDIF
-IFNDEF BIT54
- BIT54 EQU 0040000000000000h
-ENDIF
-IFNDEF BIT55
- BIT55 EQU 0080000000000000h
-ENDIF
-IFNDEF BIT56
- BIT56 EQU 0100000000000000h
-ENDIF
-IFNDEF BIT57
- BIT57 EQU 0200000000000000h
-ENDIF
-IFNDEF BIT58
- BIT58 EQU 0400000000000000h
-ENDIF
-IFNDEF BIT59
- BIT59 EQU 0800000000000000h
-ENDIF
-IFNDEF BIT60
- BIT60 EQU 1000000000000000h
-ENDIF
-IFNDEF BIT61
- BIT61 EQU 2000000000000000h
-ENDIF
-IFNDEF BIT62
- BIT62 EQU 4000000000000000h
-ENDIF
-IFNDEF BIT63
- BIT63 EQU 8000000000000000h
-ENDIF
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/bridge32.inc b/src/vendorcode/amd/agesa/f15tn/Legacy/bridge32.inc
deleted file mode 100644
index dbcbf186dc..0000000000
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/bridge32.inc
+++ /dev/null
@@ -1,576 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * Agesa structures and definitions
-; *
-; * Contains AMD AGESA core interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
-;
-; ****************************************************************************
-;
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*****************************************************************************
-
-PARAM1 textequ <[bp+8]>
-PARAM2 textequ <[bp+12]>
-PARAM3 textequ <[bp+16]>
-RETAddress textequ <[bp+4]>
-
-AMD_PRIVATE_PARAMS STRUCT
- Gate16_CS DW ? ; Segment of AMD_BRIDGE_32 and AMD_CALLOUT_16
- Gate16_SS DW ? ; RM stack segment
- Router_Seg DW ? ; Segment of oem router
- Router_Off DW ? ; Offset of oem router
-AMD_PRIVATE_PARAMS ENDS
-
-; OEM may pre-define the GDT and selector offsets. If they do not, use our defaults.
-IFNDEF AGESA_SELECTOR_GDT
- AGESA_SELECTOR_GDT EQU 00h
-ENDIF
-IFNDEF AGESA_SELECTOR_CODE16
- AGESA_SELECTOR_CODE16 EQU 08h
-ENDIF
-IFNDEF AGESA_SELECTOR_DATA16
- AGESA_SELECTOR_DATA16 EQU 10h
-ENDIF
-IFNDEF AGESA_SELECTOR_CODE32
- AGESA_SELECTOR_CODE32 EQU 18h
-ENDIF
-IFNDEF AGESA_SELECTOR_DATA32
- AGESA_SELECTOR_DATA32 EQU 20h
-ENDIF
-
-
-AMD_BRIDGE_32_GDT MACRO GDT_Name:REQ
-
- GDT_Name LABEL BYTE
- DD 000000000h, 000000000h ; NULL descriptor
- DD 00000ffffh, 000009b00h ; 16-bit code, fixed up
- DD 00000ffffh, 000009300h ; 16-bit data, fixed up
- DD 00000ffffh, 000CF9B00h ; 32-bit protected mode code
- DD 00000ffffh, 000CF9300h ; 32-bit protected mode data
- GDT_Length EQU ($-GDT_Name)
-
-ENDM
-
-;+-------------------------------------------------------------------------
-;
-; AMD_BRIDGE_32 - Execute Agesa through Pushhigh interface
-;
-; Processing:
-; The following steps are taken:
-; 1) Enter 32bit Protected Mode (PM32)
-; 2) Run AGESA code
-; 3) Restore Real Mode (RM)
-;
-; Entry:
-; [big real mode] : ds, es set to base 0 limit 4G segment
-; EDX - if not 0, provides a FAR PTR to oem router (Seg | Offset)
-; ESI - configuration block pointer
-;
-; Exit:
-; EAX - return value
-; ESI - configuration block pointer
-; ds, es, fs, gs - Set to 4GB segment limit for Big Real Mode
-;
-; Modified:
-; None
-;
-
-AMD_BRIDGE_32 MACRO GDT_Name
-
- local copyGDT
- local flushTo16PM
- local agesaReturnAddress
- local leave32bitPM
- local flush2RM
-
- push gs
- push fs
- push ebx
- push ecx
- push edi
- mov eax, esp
- push eax
- movzx esp, sp
-;
-; Do not use any locals here, BP will be changed frequently during RM->PM32->RM
-;
- pushf
- cli ; Disable interrupts during AGESA
- cld ; Need known direction flag during AGESA
-
-;
-; Save the FAR PTR input parameter
-;
- mov gs, dx ; Offset
- shr edx, 16
- mov fs, dx ; Segment
-;
-; Determine where our binary file is and get entry point
-;
- mov edx, (AMD_CONFIG_PARAMS PTR [esi]).ImageBasePtr
- add edx, (AMD_IMAGE_HEADER PTR [edx]).EntryPointAddress
-;
-; Figure out the return address we will use after calling AGESA
-; and store it in ebx until we have our stack set up properly
-;
- mov ebx, cs
- shl ebx, 4
- add ebx, OFFSET agesaReturnAddress
-;
-; Save our current RM stack AND entry EBP
-;
- push ebp
-; push esp
- push ss
-
-;
-; BEGIN --- STACK MUST BE BALANCED AT THIS POINT --- BEGIN
-;
-; Copy the GDT onto the stack for modification
-;
- mov cx, GDT_Length
- sub sp, cx
- mov bp, sp
- lea di, GDT_Name
-copyGDT:
- mov al, cs:[di]
- mov [bp], al
- inc di
- inc bp
- loop copyGDT
-;
-; Patch 16-bit code and data descriptors on stack. We will
-; fix up CS and SS for PM16 during the callout if applicable.
-;
- mov bp, sp
-
- mov eax, cs
- shl eax, 4
- mov [bp+AGESA_SELECTOR_CODE16+2], ax
- shr eax, 16
- mov [bp+AGESA_SELECTOR_CODE16+4], al
-
- mov eax, ss
- shl eax, 4
- mov [bp+AGESA_SELECTOR_DATA16+2], ax
- shr eax, 16
- mov [bp+AGESA_SELECTOR_DATA16+4], al
-;
-; Need to place Length and Address on GDT
-;
- mov eax, ss
- shl eax, 4
- add eax, esp
- push eax
- push WORD PTR (GDT_Length-1)
-;
-; Load the GDT
-;
- mov bp, sp
- lgdt FWORD PTR [bp]
-;
-; TABLE 1
-;
-; Place PRIVATE DATA on stack DIRECTLY following GDT
-; During this routine, stack data is critical. If
-; order is changed or additional added, bad things
-; will happen!
-;
-; HIGHEST PHYSICAL ADDRESS
-;
-; | ... |
-; ------------------------
-; | old RM SP |
-; | old RM SS |
-; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS + (SIZEOF GDT_LENGTH + 6 {size, address})
-; | GDT_DATA32 |
-; | ... |
-; | GDT_NULL |
-; | GDT Addr, Length |
-; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS
-; | Priv.Gate16_SS |
-; | Priv.Gate16_CS |
-; ------------------------ sp
-; ------ THEN PUSH -------
-; | Return to 16-bit CS |
-; | Return to 16-bit Off |
-; | ... |
-;
-; LOWEST PHYSICAL ADDRESS
-;
- mov edi, esp
- sub edi, SIZEOF AMD_PRIVATE_PARAMS
- mov ax, cs
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS, ax
- mov ax, ss
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS, ax
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off, gs
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg, fs
-
- mov esp, edi
-;
-; Save an address for returning to 16 bit real mode on stack,
-; we'll use it in a far ret after turning off CR0.PE so that
-; we can take our address off and force a far jump. Be sure
-; no unexpected data is on the stack after this!
-;
- mov ax, cs
- push cs
- lea ax, flush2RM
- push ax
-;
-; Convert ss:esp to "flat"
-;
-
- mov ax, sp
- push ax
- mov eax, ss
- shl eax, 4
- add eax, esp
- mov esp, eax ; Load the zero based ESP
-
-;
-; Set CR0.PE
-;
- mov eax, CR0 ; Get CPU control word 0
- or al, 01 ; Enable CPU protected mode
- mov CR0, eax ; Write back to CPU control word 0
- jmp flushTo16PM
-
-flushTo16PM:
-;
-; 16-bit protected mode
-;
- mov ax, AGESA_SELECTOR_DATA32
- mov ds, ax
- mov es, ax
- mov fs, ax
- mov gs, ax
- mov ss, ax
-;
-; Push our parameters RIGHT TO LEFT, and then return address
-;
- push esi ; AGESA configuration block pointer (data)
- push ebx ; after AGESA return offset (32PM flat) - consumed by dispatcher ret
- pushd AGESA_SELECTOR_CODE32 ; AGESA entry selector (32PM flat)
- push edx ; AGESA entry point (32PM flat)
-
- DB 066h
- retf ; <><><> Enter AGESA 32-bit code!!! <><><>
-
-agesaReturnAddress:
-;
-; Returns from the Agesa 32-bit code still PM32
-;
- DB 0EAh
- DD OFFSET leave32bitPM
- DW AGESA_SELECTOR_CODE16
-
-leave32bitPM:
-;
-; Now in 16-bit PM
-;
- add esp, 4 ; +4 to remove our config block pointer
-;
-; Eax reserve AGESA_STATUS return code, save it
-;
- mov ebx, eax
-;
-; Turn off CR0.PE, restore 64K stack limit
-;
- pop ax
- mov sp, ax
- mov ax, AGESA_SELECTOR_DATA16
- mov ss, ax
-
- mov eax, CR0
- and al, NOT 1 ; Disable protected mode
- mov CR0, eax ; Write back CR0.PE
-;
-; Jump far to enter RM, we saved this address on the stack
-; already. Hopefully stack is balanced through AGESA
-; nor were any params added by pushing them on the stack and
-; not removing them between BEGIN-END comments.
-;
- retf
-
-flush2RM:
-;
-; Set segments registers for big real mode before returning
-;
- xor ax, ax
- mov ds, ax
- mov es, ax
- mov fs, ax
- mov gs, ax
-;
-; Discard GDT, +6 for GDT pointer/size, privates
-;
- add esp, GDT_Length + 6 + SIZEOF AMD_PRIVATE_PARAMS
-;
-; Restore real mode stack and entry EBP
-;
- pop cx
-; mov esp, [esp]
- mov ss, cx
- pop ebp
-;
-; Restore AGESA_STATUS return code to eax
-;
- mov eax, ebx
-;
-; END --- STACK MUST BE BALANCED TO THIS POINT --- END
-;
-
- popf
- pop ebx
- mov esp, ebx
- pop edi
- pop ecx
- pop ebx
- pop fs
- pop gs
- ; EXIT AMD_BRIDGE_32
-ENDM
-;+-------------------------------------------------------------------------
-;
-; AMD_CALLOUT_16 - Execute Callback from Pushhigh interface
-;
-; Processing:
-; The following steps are taken:
-; 1) Enter PM16
-; 2) Setup stack, get private params
-; 3) Enter RM
-; 4) Get 3 params
-; 5) Call oemCallout OR oem router
-; 6) Enter PM32
-; 7) Return to Agesa PH
-;
-; Entry:
-; [32-bit protected mode]
-; [esp+8] Func
-; [esp+12] Data
-; [esp+16] Configuration Block
-; [esp+4] return address to Agesa
-;
-; Exit:
-; [32-bit protected mode]
-;
-; Modified:
-; None
-;
-AMD_CALLOUT_16 MACRO LocalOemCalloutRouter
-;
-; Note that we are still PM32, so MASM may work strangely
-;
-
- push bp ; Save our original SP to access params
- mov bp, sp
- push bx
- push si
- push di
- push cx
- push dx
- push di
-
- DB 066h, 0EAh
- DW OFFSET PM16Entry
- DW AGESA_SELECTOR_CODE16
-
-PM16Entry:
-;
-; PM16 CS, but still PM32 SS, as we need to access our private params
-; before we enter RM.
-;
-; Note: we are working below the stack temporarily, and and it will
-; not affect our ability to get entry params
-;
- xor ecx, ecx
- xor edx, edx
-;
-; SGDT will give us the original location of the GDT on our CAS stack.
-; We need this value because our private parameters are located just
-; below the GDT.
-;
- mov edi, esp
- sub edi, GDT_Length + 6
- sgdt FWORD PTR [edi] ; [edi] = word size, dword address
- mov edi, DWORD PTR [edi+2] ; Get the PM32 address only
- sub edi, SIZEOF AMD_PRIVATE_PARAMS + 6
-;
-; cx = code segment of this code in RM
-; dx = stack segment of CAS in RM
-; fs = code segment of oem router (save for later)
-; gs = offset of oem router (save for later)
-; fs and gs are loaded after switch to real mode because we can't
-; use them as scratch pad registers in protected mode
-;
- mov cx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS
- mov dx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS
-
- mov eax, edi ; Save edi in eax for after RM switch
- mov edi, esp ; Save our current ESP for RM
-
- movzx ebx, dx
- shl ebx, 4
- sub esp, ebx
-
-;
-; We had been accessing the stack in PM32, we will now change to PM16 so we
-; will make the stack segment 64KB limit so SP needs to be fixed made PM16
-; compatible.
-;
- mov bx, AGESA_SELECTOR_DATA16
- mov ss, bx
-
-;
-; Save the RM segment and RM offset of the jump we will need to make in
-; order to enter RM so that code in this segment is relocatable.
-;
-; BEGIN --- Don't unbalance the stack --- BEGIN
-;
- push cx
- pushw OFFSET RMEntry
-
- mov ebx, CR0
- and bl, NOT 1
- mov CR0, ebx ; CR0.PE cleared
-;
-; Far jump to clear segment descriptor cache and enter RM
-;
- retf
-
-RMEntry:
-;
-; We are in RM, setup RM stack
-;
- movzx ebx, dx ; Get RM SS in ebx
- shl ebx, 4 ; Get our stack top on entry in EBP to
- sub ebp, ebx ; access our entry parameters
- sub eax, ebx ; save copy of parameters address
- mov ss, dx ; Set stack segment
-;
-; We are going to figure out the address to use when we return
-; and have to go back into PM32 while we have access to it
-;
- movzx ebx, cx ; Get original CS in ebx
- shl ebx, 4
- add ebx, OFFSET PM32Entry
-;
-; Now we put our data, func, block params into calling convention
-; for our hook
-;
-; ECX = Func
-; EDX = Data
-; ESI = config pointer
-;
- mov ecx, PARAM1 ; Func
- mov edx, PARAM2 ; Data
- mov esi, PARAM3 ; pointer
-
- push ebx ; Save PM32 mode switch address
- push edi ; Save PM32 stack pointer
- pushf
-;
-; Get Router Function Address
-;
- mov edi, eax
- mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg
- mov fs, ax
- mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off
- mov gs, ax
-
- mov eax, AGESA_UNSUPPORTED ; Default return value
-;
-; If AMD_BRIDGE_32 EDX == 0 call oemCallout
-; otherwise call FAR PTR EDX
-;
-; Critical:
-; sp+2 - EDI aka PM32 stack address
-; sp+4 - address of PM32Entry in PM32
-;
- mov bx, fs
- shl ebx, 16
- mov bx, gs
-
- .if (ebx == 0)
- call LocalOemCalloutRouter
- .else
-;
-; Make far call to Router function
-;
- push cs
- push offset CalloutReturn
- push ebx
- retf
-CalloutReturn:
- .endif
-;
-; Restore PM32 esp from RM stack
-;
- popf
- pop edi ; Our PM32 stack pointer
- pop edx ; Our PM32 mode switch address
-
- mov ebx, CR0
- or bl, 1 ; CR0.PE set
- mov CR0, ebx
-
- mov ebx, AGESA_SELECTOR_DATA32
- pushd AGESA_SELECTOR_CODE32 ; PM32 selector
- push edx ; PM32 entry point
-
- DB 066h
- retf ; Far jump to enter PM32
-
-PM32Entry:
-;
-; END --- Don't unbalance the stack --- END
-; We are now PM32, so remember MASM is assembling in 16-bit again
-;
- mov ss, bx
- mov ds, bx
- mov es, bx
- mov fs, bx
- mov gs, bx
-
- mov sp, di
- pop di
- pop dx
- pop cx
- pop di
- pop si
- pop bx
- pop bp
- ; EXIT AMD_CALLOUT_16
-ENDM
diff --git a/src/vendorcode/amd/agesa/f15tn/Lib/x64/amdlib64.asm b/src/vendorcode/amd/agesa/f15tn/Lib/x64/amdlib64.asm
deleted file mode 100644
index c528a750aa..0000000000
--- a/src/vendorcode/amd/agesa/f15tn/Lib/x64/amdlib64.asm
+++ /dev/null
@@ -1,602 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa library 64bit
-; *
-; * Contains AMD AGESA Library
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Lib
-; * @e \$Revision: 17071 $ @e \$Date: 2009-07-30 10:13:11 -0700 (Thu, 30 Jul 2009) $
-; */
-;*****************************************************************************
-;
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*****************************************************************************
-
-.code
-;/*++
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write IO byte
-; *
-; * @param[in] CX IO port address
-; * @param[in] DL IO port Value
-; */
-
-PUBLIC WriteIo8
-WriteIo8 PROC
- mov al, dl
- mov dx, cx
- out dx, al
- ret
-WriteIo8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write IO word
-; *
-; * @param[in] CX IO port address
-; * @param[in] DX IO port Value
-; */
-PUBLIC WriteIo16
-WriteIo16 PROC
- mov ax, dx
- mov dx, cx
- out dx, ax
- ret
-WriteIo16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write IO dword
-; *
-; * @param[in] CX IO port address
-; * @param[in] EDX IO port Value
-; */
-
-PUBLIC WriteIo32
-WriteIo32 PROC
- mov eax, edx
- mov dx, cx
- out dx, eax
- ret
-WriteIo32 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read IO byte
-; *
-; * @param[in] CX IO port address
-; * @retval AL IO port Value
-; */
-PUBLIC ReadIo8
-ReadIo8 PROC
- mov dx, cx
- in al, dx
- ret
-ReadIo8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read IO word
-; *
-; * @param[in] CX IO port address
-; * @retval AX IO port Value
-; */
-PUBLIC ReadIo16
-ReadIo16 PROC
- mov dx, cx
- in ax, dx
- ret
-ReadIo16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read IO dword
-; *
-; * @param[in] CX IO port address
-; * @retval EAX IO port Value
-; */
-PUBLIC ReadIo32
-ReadIo32 PROC
- mov dx, cx
- in eax, dx
- ret
-ReadIo32 ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read MSR
-; *
-; * @param[in] RCX MSR Address
-; * @param[in] RDX Pointer to data
-; * @param[in] R8D ConfigPtr (Optional)
-; */
-PUBLIC LibAmdMsrRead
-LibAmdMsrRead PROC
- push rsi
- mov rsi, rdx
- rdmsr
- mov [rsi], eax
- mov [rsi+4], edx
- pop rsi
- ret
-LibAmdMsrRead ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write MSR
-; *
-; * @param[in] RCX MSR Address
-; * @param[in] RDX Pointer to data
-; * @param[in] R8D ConfigPtr (Optional)
-; */
-PUBLIC LibAmdMsrWrite
-LibAmdMsrWrite PROC
- push rsi
- mov rsi, rdx
- mov eax, [rsi]
- and rax, 0ffffffffh
- mov edx, [rsi+4]
- and rdx, 0ffffffffh
- wrmsr
- pop rsi
- ret
-LibAmdMsrWrite ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read CPUID
-; *
-; * @param[in] RCX CPUID function
-; * @param[in] RDX Pointer to CPUID_DATA to save cpuid data
-; * @param[in] R8D ConfigPtr (Optional)
-; */
-PUBLIC LibAmdCpuidRead
-LibAmdCpuidRead PROC
-
- push rbx
- push rsi
- mov rsi, rdx
- mov rax, rcx
- cpuid
- mov [rsi], eax
- mov [rsi+4], ebx
- mov [rsi+8], ecx
- mov [rsi+12],edx
- pop rsi
- pop rbx
- ret
-
-LibAmdCpuidRead ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read TSC
-; *
-; *
-; * @retval RAX Time stamp counter value
-; */
-
-PUBLIC ReadTSC
-ReadTSC PROC
- rdtsc
- and rax, 0ffffffffh
- shl rdx, 32
- or rax, rdx
- ret
-ReadTSC ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read memory/MMIO byte
-; *
-; * @param[in] RCX - Memory Address
-; * @retval Memory byte at given address
-; */
-PUBLIC Read64Mem8
-Read64Mem8 PROC
-
- xor rax, rax
- mov al, [rcx]
- ret
-
-Read64Mem8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read memory/MMIO word
-; *
-; * @param[in] RCX - Memory Address
-; * @retval Memory word at given address
-; */
-PUBLIC Read64Mem16
-Read64Mem16 PROC
-
- xor rax, rax
- mov ax, [rcx]
- ret
-
-Read64Mem16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read memory/MMIO dword
-; *
-; * @param[in] RCX - Memory Address
-; * @retval Memory dword at given address
-; */
-PUBLIC Read64Mem32
-Read64Mem32 PROC
-
- xor rax, rax
- mov eax, [rcx]
- ret
-
-Read64Mem32 ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write memory/MMIO byte
-; *
-; * @param[in] RCX Memory Address
-; * @param[in] DL Value to write
-; */
-
-PUBLIC Write64Mem8
-Write64Mem8 PROC
-
- xor rax, rax
- mov rax, rdx
- mov [rcx], al
- ret
-
-Write64Mem8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write memory/MMIO word
-; *
-; * @param[in] RCX Memory Address
-; * @param[in] DX Value to write
-; */
-PUBLIC Write64Mem16
-Write64Mem16 PROC
-
- xor rax, rax
- mov rax, rdx
- mov [rcx], ax
- ret
-
-Write64Mem16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write memory/MMIO dword
-; *
-; * @param[in] RCX Memory Address
-; * @param[in] EDX Value to write
-; */
-PUBLIC Write64Mem32
-Write64Mem32 PROC
-
- xor rax, rax
- mov rax, rdx
- mov [rcx], eax
- ret
-
-Write64Mem32 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read various CPU registers
-; *
-; * @param[in] CL Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
-; * @param[in] RDX Pointer to value
-; */
-
-PUBLIC LibAmdReadCpuReg
-LibAmdReadCpuReg PROC
-
- push rax
- xor rax, rax
-Reg00h:
- cmp cl, 00h
- jne Reg04h
- mov rax, cr0
- jmp RegRead
-Reg04h:
- cmp cl, 04h
- jne Reg10h
- mov rax, cr4
- jmp RegRead
-Reg10h:
- cmp cl, 10h
- jne Reg11h
- mov rax, dr0
- jmp RegRead
-Reg11h:
- cmp cl, 11h
- jne Reg12h
- mov rax, dr1
- jmp RegRead
-Reg12h:
- cmp cl, 12h
- jne Reg13h
- mov rax, dr2
- jmp RegRead
-Reg13h:
- cmp cl, 13h
- jne Reg17h
- mov rax, dr3
- jmp RegRead
-Reg17h:
- cmp cl, 17h
- jne RegRead
- mov rax, dr7
-RegRead:
- mov [rdx], eax
- pop rax
- ret
-LibAmdReadCpuReg ENDP
-
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write various CPU registers
-; *
-; * @param[in] CL Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
-; * @param[in] RDX Value to write
-; */
-
-PUBLIC LibAmdWriteCpuReg
-LibAmdWriteCpuReg PROC
-
- push rax
-Reg00h:
- cmp cl, 00h
- jne Reg04h
- mov rax, cr0
- mov eax, edx
- mov cr0, rax
- jmp Done
-Reg04h:
- cmp cl, 04h
- jne Reg10h
- mov rax, cr4
- mov eax, edx
- mov cr4, rax
- jmp Done
-Reg10h:
- cmp cl, 10h
- jne Reg11h
- mov rax, dr0
- mov eax, edx
- mov dr0, rax
- jmp Done
-Reg11h:
- cmp cl, 11h
- jne Reg12h
- mov rax, dr1
- mov eax, edx
- mov dr1, rax
- jmp Done
-Reg12h:
- cmp cl, 12h
- jne Reg13h
- mov rax, dr2
- mov eax, edx
- mov dr2, rax
- jmp Done
-Reg13h:
- cmp cl, 13h
- jne Reg17h
- mov rax, dr3
- mov eax, edx
- mov dr3, rax
- jmp Done
-Reg17h:
- cmp cl, 17h
- jne Done
- mov rax, dr7
- mov eax, edx
- mov dr7, rax
-Done:
- pop rax
- ret
-LibAmdWriteCpuReg ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write back invalidate caches using wbinvd.
-; *
-; *
-; *
-; */
-
-PUBLIC LibAmdWriteBackInvalidateCache
-LibAmdWriteBackInvalidateCache PROC
- wbinvd
- ret
-LibAmdWriteBackInvalidateCache ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Stop CPU
-; *
-; *
-; *
-; */
-
-PUBLIC StopHere
-StopHere PROC
-@@:
- jmp short @b
-StopHere ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Enter debugger on SimNow
-; *
-; *
-; *
-; */
-PUBLIC LibAmdSimNowEnterDebugger
-LibAmdSimNowEnterDebugger PROC
- pushfq
- mov rax, 0BACCD00Bh ; Backdoor in SimNow
- mov rbx, 2 ; Select breakpoint feature
- cpuid
-@@:
- jmp short @b
- popfq
- ret
-LibAmdSimNowEnterDebugger ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * IDS IO port write
-; *
-; * @param[in] ECX IO Port Address
-; * @param[in] EDX Value to write
-; * @param[in] R8D IDS flags
-; *
-; */
-
-PUBLIC IdsOutPort
-IdsOutPort PROC
- push rbx
- push rax
-
- mov ebx, r8d
- mov eax, edx
- mov edx, ecx
- out dx, eax
-
- pop rax
- pop rbx
- ret
-IdsOutPort ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Force breakpoint on HDT
-; *
-; *
-; */
-PUBLIC LibAmdHDTBreakPoint
-LibAmdHDTBreakPoint PROC
-
- push rbx
-
- mov rcx, 0C001100Ah ;bit 0 = HDT redirect
- mov rdi, 09C5A203Ah ;Password
- rdmsr
- and rax, 0ffffffffh
- or rax, 1
-
- wrmsr
-
- mov rax, 0B2h ;Marker = B2
- db 0F1h ;ICEBP
-
- pop rbx
- ret
-
-LibAmdHDTBreakPoint ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Find the most right hand side non-zero bit with
-; *
-; * @param[in] ECX Value
-; */
-PUBLIC LibAmdBitScanForward
-LibAmdBitScanForward PROC
- bsf eax, ecx
- jnz nonZeroSource
- mov al,32
-nonZeroSource:
- ret
-LibAmdBitScanForward ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Find the most left hand side non-zero bit.
-; *
-; * @param[in] ECX Value
-; */
-PUBLIC LibAmdBitScanReverse
-LibAmdBitScanReverse PROC
- bsr eax, ecx
- jnz nonZeroSource
- mov al,0FFh
-nonZeroSource:
- ret
-LibAmdBitScanReverse ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Flush specified number of cache line
-; *
-; * @param[in] RCX Physical address to be flushed
-; * @param[in] DL number of cachelines to be flushed
-; */
-PUBLIC LibAmdCLFlush
-LibAmdCLFlush PROC
- push rax
- mov rax, rcx
- movzx rcx, dl
- @@:
- mfence
- clflush [rax]
- mfence
- add rax,64
- loop @B
- pop rax
- ret
-LibAmdCLFlush ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * FPU init
-; *
-; *
-; */
-PUBLIC LibAmdFinit
-LibAmdFinit PROC
- finit
- ret
-LibAmdFinit ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt.asm b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt.asm
deleted file mode 100644
index a409f8ed62..0000000000
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt.asm
+++ /dev/null
@@ -1,361 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa pre-memory miscellaneous support, including ap halt loop.
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: CPU
-; */
-;*****************************************************************************
-;
-; Copyright (C) 2012 Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- .XLIST
- INCLUDE agesa.inc
- INCLUDE cpcarmac.inc
- .LIST
-
- .586P
-
-;===============================================
-;===============================================
-;==
-;== M E M O R Y A B S E N T S E G M E N T
-;==
-;===============================================
-;===============================================
- .MODEL flat
- .CODE
-;======================================================================
-; ExecuteFinalHltInstruction: Disables the stack and performs
-; a hlt instruction on an AP.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; eax, ebx, ecx, edx, esp
-;
-;======================================================================
-PUBLIC ExecuteFinalHltInstruction
-ExecuteFinalHltInstruction PROC NEAR C USES ESI EDI HaltFlags:DWORD, ApMtrrSettingList:PTR, StandardHeader:PTR
-
- mov esi, StandardHeader ; The code must reference all parameters to avoid a build warning
- mov esi, HaltFlags
- mov edi, ApMtrrSettingList
- ; Do these special steps in case if the core is part of a compute unit
- ; Note: The following bits are family specific flags, that gets set during build time,
- ; and indicates things like "family cache control methodology", etc.
- ; esi bit0 = 0 -> not a Primary core
- ; esi bit0 = 1 -> Primary core
- ; esi bit1 = 0 -> Cache disable
- ; esi bit1 = 1 -> Cache enable
- .if (esi & 2h)
- ; Set CombineCr0Cd bit
- mov ecx, CU_CFG3
- _RDMSR
- bts edx, (COMBINE_CR0_CD - 32)
- _WRMSR
- ; Clear the CR0.CD bit
- mov eax, CR0 ; Make sure cache is enabled for all APs
- btr eax, CR0_CD
- btr eax, CR0_NW
- mov CR0, eax ; Write back to CR0
- .else
- mov eax, CR0 ; Make sure cache is disabled for all APs
- bts eax, CR0_CD ; Disable cache
- bts eax, CR0_NW
- mov CR0, eax ; Write back to CR0
- .endif
-
- .if (esi & 1h)
- ; This core is a primary core and needs to do all the MTRRs, including shared MTRRs.
- mov esi, edi ; Get ApMtrrSettingList
-
- ; Configure the MTRRs on the AP so
- ; when it runs remote code it will execute
- ; out of RAM instead of ROM.
-
- ; Disable MTRRs and turn on modification enable bit
- mov ecx, MTRR_SYS_CFG
- _RDMSR
- btr eax, MTRR_VAR_DRAM_EN ; Disable
- bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable
- btr eax, MTRR_FIX_DRAM_EN ; Disable
- bts eax, SYS_UC_LOCK_EN
- _WRMSR
-
- ; Setup default values for Fixed-Sized MTRRs
- ; Set 7FFFh-00000h as WB
- mov ecx, AMD_AP_MTRR_FIX64k_00000
- mov eax, 1E1E1E1Eh
- mov edx, eax
- _WRMSR
-
- ; Set 9FFFFh-80000h also as WB
- mov ecx, AMD_AP_MTRR_FIX16k_80000
- _WRMSR
-
- ; Set BFFFFh-A0000h as Uncacheable Memory-mapped IO
- mov ecx, AMD_AP_MTRR_FIX16k_A0000
- xor eax, eax
- xor edx, edx
- _WRMSR
-
- ; Set DFFFFh-C0000h as Uncacheable Memory-mapped IO
- xor eax, eax
- xor edx, edx
- mov ecx, AMD_AP_MTRR_FIX4k_C0000
-
-CDLoop:
- _WRMSR
- inc ecx
- cmp ecx, AMD_AP_MTRR_FIX4k_D8000
- jbe CDLoop
-
- ; Set FFFFFh-E0000h as Uncacheable Memory
- mov eax, 18181818h
- mov edx, eax
-
- mov ecx, AMD_AP_MTRR_FIX4k_E0000
-
-EFLoop:
- _WRMSR
- inc ecx
- cmp ecx, AMD_AP_MTRR_FIX4k_F8000
- jbe EFLoop
-
- ; If IBV provided settings for Fixed-Sized MTRRs,
- ; overwrite the default settings.
- .if ((esi != 0) && (esi != 0FFFFFFFFh))
- mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
- ; While we are not at the end of the list
- .while (ecx != CPU_LIST_TERMINAL)
- ; Ensure that the MSR address is valid for Fixed-Sized MTRRs
- .if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \
- (ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || (ecx == AMD_AP_MTRR_FIX16k_A0000))
- mov eax, dword ptr (AP_MTRR_SETTINGS ptr [esi]).MsrData
- mov edx, dword ptr (AP_MTRR_SETTINGS ptr [esi+4]).MsrData
- _WRMSR
- .endif
- add esi, sizeof (AP_MTRR_SETTINGS)
- mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
- .endw
- .endif
-
- ; Enable fixed-range and variable-range MTRRs
- mov ecx, AMD_MTRR_DEFTYPE
- _RDMSR
- bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn
- bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn
- _WRMSR
-
- ; Enable Top-of-Memory setting
- ; Enable use of RdMem/WrMem bits attributes
- mov ecx, MTRR_SYS_CFG
- _RDMSR
- bts eax, MTRR_VAR_DRAM_EN ; Enable
- btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable
- bts eax, MTRR_FIX_DRAM_EN ; Enable
- _WRMSR
-
- mov esi, (1 SHL FLAG_IS_PRIMARY)
- .else ; end if primary core
- xor esi, esi
- .endif
- ; Make sure not to touch any Shared MSR from this point on
-
- AMD_DISABLE_STACK_FAMILY_HOOK
-
- bt esi, FLAG_IS_PRIMARY
- .if (carry?)
- ; restore variable MTRR6 and MTRR7 to default states
- mov ecx, AMD_MTRR_VARIABLE_MASK7 ; clear MTRRPhysBase6 MTRRPhysMask6
- xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7
- xor edx, edx
- .while (cx >= AMD_MTRR_VARIABLE_BASE6)
- _WRMSR
- dec cx
- .endw
- .endif
-
-@@:
- cli
- hlt
- jmp @B ;ExecuteHltInstruction
- ret
-ExecuteFinalHltInstruction ENDP
-
-;======================================================================
-; ExecuteHltInstruction: Performs a hlt instruction.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; eax, ebx, ecx, edx, esp
-;
-;======================================================================
-PUBLIC ExecuteHltInstruction
-ExecuteHltInstruction PROC NEAR C
- cli
- hlt
- ret
-ExecuteHltInstruction ENDP
-
-;======================================================================
-; NmiHandler: Simply performs an IRET.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-PUBLIC NmiHandler
-NmiHandler PROC NEAR C
- iretd
-NmiHandler ENDP
-
-;======================================================================
-; GetCsSelector: Returns the current protected mode CS selector.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-PUBLIC GetCsSelector
-GetCsSelector PROC NEAR C, CsSelector:PTR
- push ax
- push ebx
-
- call FarCallGetCs
- mov ebx, CsSelector
- mov [ebx], ax
- pop ebx
- pop ax
- ret
-GetCsSelector ENDP
-
-;======================================================================
-; FarCallGetCs:
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; none
-;
-;======================================================================
-FarCallGetCs PROC FAR PRIVATE
-
- mov ax, ss:[esp + 4]
- retf
-
-FarCallGetCs ENDP
-
-;======================================================================
-; SetIdtr:
-;
-; In:
-; @param[in] IdtPtr Points to IDT table
-;
-; Out:
-; None
-;
-; Destroyed:
-; none
-;
-;======================================================================
-PUBLIC SetIdtr
-SetIdtr PROC NEAR C USES EBX, IdtPtr:PTR
- mov ebx, IdtPtr
- lidt fword ptr ss:[ebx]
- ret
-SetIdtr ENDP
-
-;======================================================================
-; GetIdtr:
-;
-; In:
-; @param[in] IdtPtr Points to IDT table
-;
-; Out:
-; None
-;
-; Destroyed:
-; none
-;
-;======================================================================
-PUBLIC GetIdtr
-GetIdtr PROC NEAR C USES EBX, IdtPtr:PTR
- mov ebx, IdtPtr
- sidt fword ptr ss:[ebx]
- ret
-GetIdtr ENDP
-
-;======================================================================
-; ExecuteWbinvdInstruction: Performs a wbinvd instruction.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-PUBLIC ExecuteWbinvdInstruction
-ExecuteWbinvdInstruction PROC NEAR C
- wbinvd ; Write back the cache tag RAMs
- ret
-ExecuteWbinvdInstruction ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt64.asm b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt64.asm
deleted file mode 100644
index b2736c507c..0000000000
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt64.asm
+++ /dev/null
@@ -1,173 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa pre-memory miscellaneous support, including ap halt loop.
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: CPU
-; */
-;*****************************************************************************
-;
-; Copyright (C) 2012 Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- text SEGMENT
-
-
-;======================================================================
-; ExecuteFinalHltInstruction: Performs a hlt instruction.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; eax, ebx, ecx, edx, esp
-;
-;======================================================================
-ExecuteFinalHltInstruction PROC PUBLIC
-@@:
- cli
- hlt
- jmp @B ;ExecuteHltInstruction
-ExecuteFinalHltInstruction ENDP
-
-;======================================================================
-; ExecuteHltInstruction: Performs a hlt instruction.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; eax, ebx, ecx, edx, esp
-;
-;======================================================================
-ExecuteHltInstruction PROC PUBLIC
- cli
- hlt
- ret
-ExecuteHltInstruction ENDP
-
-;======================================================================
-; NmiHandler: Simply performs an IRET.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-NmiHandler PROC PUBLIC
- iretq
-NmiHandler ENDP
-
-;======================================================================
-; GetCsSelector: Returns the current protected mode CS selector.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-GetCsSelector PROC PUBLIC
- ; This stub function is here to avoid compilation errors.
- ; At this time, there is no need to provide a 64 bit function.
- ret
-GetCsSelector ENDP
-
-;======================================================================
-; SetIdtr:
-;
-; In:
-; @param[in] IdtPtr Points to IDT table
-;
-; Out:
-; None
-;
-; Destroyed:
-; none
-;
-;======================================================================
-SetIdtr PROC PUBLIC
- ; This stub function is here to avoid compilation errors.
- ; At this time, there is no need to provide a 64 bit function.
- ret
-SetIdtr ENDP
-
-;======================================================================
-; GetIdtr:
-;
-; In:
-; @param[in] IdtPtr Points to IDT table
-;
-; Out:
-; None
-;
-; Destroyed:
-; none
-;
-;======================================================================
-GetIdtr PROC PUBLIC
- ; This stub function is here to avoid compilation errors.
- ; At this time, there is no need to provide a 64 bit function.
- ret
-GetIdtr ENDP
-
-;======================================================================
-; ExecuteWbinvdInstruction: Performs a wbinvd instruction.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-ExecuteWbinvdInstruction PROC PUBLIC
- wbinvd ; Write back the cache tag RAMs
- ret
-ExecuteWbinvdInstruction ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib32.asm b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib32.asm
deleted file mode 100644
index 4cf423c46a..0000000000
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib32.asm
+++ /dev/null
@@ -1,335 +0,0 @@
-;/**
-; * @file
-; *
-; * Ids Assembly library 32bit
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: IDS
-; * @e \$Revision: 14305 $ @e \$Date: 2009-05-24 02:20:55 +0800 (Sun, 24 May 2009) $
-; */
-;*****************************************************************************
-;
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*****************************************************************************
-
-.586p
-.model flat
-ASSUME FS:NOTHING
-.code
-public IdsDelay
-IdsDelay PROC NEAR C USES EAX EDX
-Local targetedx:dword, targeteax:dword
- rdtsc
-;set target time
- add eax,1500000000
- adc edx,0
- mov targetedx,edx
- mov targeteax,eax
-
- rdtsc
-;set "Si!=0" skip below loop
- .while(1)
- .if(si != 0)
- jmp delay_exit
- .endif
- .if(edx > targetedx)
- jmp delay_exit
- .elseif (edx == targetedx)
- .if(eax > targeteax)
- jmp delay_exit
- .endif
- .endif
- rdtsc
- .endw
-delay_exit:
- ret
-IdsDelay ENDP
-;/*++
-;
-;Routine Description:
-;
-; IdsErrorStop -- Function for Assert
-;
-;Arguments:
-; Filecode
-;
-;Returns:
-;
-; None
-;
-;--*/
-public IdsErrorStop
-IdsErrorStop PROC NEAR C filecode:dword
-local tmpebx:dword,tmpedx:dword
- pushad
-
- mov si,0 ; Si is used as control flag, "Si!=0" skip postcode loop
-; send debug port 1st, then fire SimNow breakpoint
- mov ax, 0deadh
- out 0e0h, ax
- mov eax, filecode
- out 84h, eax
- mov eax, 0BACCD00Bh ; Backdoor in SimNow
- mov ebx, 2 ; Select breakpoint feature
- cpuid
-
- mov ebx,0dead0000h
- mov edx,filecode
- ror edx,16
- mov bx,dx
- mov dx,0
-;ebx:edx = deadxxxxyyyy0000 xxxx is the filecode yyyy is the line num
- mov tmpebx,ebx
- mov tmpedx,edx
-
- xor eax,eax
- mov cl,6
-
- .while((cl != 0) && (si == 0))
- .if(cl <= 2)
- shld eax,edx,8
- shl edx,8
- .else
- shld eax,ebx,8
- shl ebx,8
- .endif
-
- out 80h,eax
- call IdsDelay
- dec cl
- .if(cl == 0)
- mov cl,6
- mov ebx,tmpebx
- mov edx,tmpedx
- .endif
- .endw
-
- popad
- xor eax,eax
- ret
-IdsErrorStop endp
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Stop CPU
-; *
-; *
-; *
-; */
-IDS_STOP_HERE MACRO
-@@:
- jmp short @b
-ENDM
-
-;======================================================================
-; IdsExceptionHandler: Simply performs a jmp $ and IRET.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-PUBLIC _IdsExceptionHandler
-PUBLIC _SizeIdtDescriptor
-PUBLIC _SizeTotalIdtDescriptors
-
-; Size of each exception MUST be the same
-Exception00:
- push eax
- mov al, 00h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception01:
- push eax
- mov al, 01h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception02:
- push eax
- mov al, 02h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception03:
- push eax
- mov al, 03h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception04:
- push eax
- mov al, 04h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception05:
- push eax
- mov al, 05h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception06:
- push eax
- mov al, 06h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception07:
- push eax
- mov al, 07h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception08:
- push eax
- mov al, 08h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception09:
- push eax
- mov al, 09h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception10:
- push eax
- mov al, 10h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception11:
- push eax
- mov al, 11h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception12:
- push eax
- mov al, 12h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception13:
- push eax
- mov al, 13h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception14:
- push eax
- mov al, 14h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception15:
- push eax
- mov al, 15h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception16:
- push eax
- mov al, 16h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception17:
- push eax
- mov al, 17h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception18:
- push eax
- mov al, 18h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception19:
- push eax
- mov al, 19h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception20:
- push eax
- mov al, 20h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception21:
- push eax
- mov al, 21h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception22:
- push eax
- mov al, 22h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception23:
- push eax
- mov al, 23h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception24:
- push eax
- mov al, 24h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception25:
- push eax
- mov al, 25h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception26:
- push eax
- mov al, 26
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception27:
- push eax
- mov al, 27h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception28:
- push eax
- mov al, 28h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception29:
- push eax
- mov al, 29h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception30:
- push eax
- mov al, 30h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception31:
- push eax
- mov al, 31h
- jmp near ptr CommonHandler
-CommonHandler:
- out 80h, al
- pop eax
- IDS_STOP_HERE
- iretd
-
-_IdsExceptionHandler dq offset Exception00
-_SizeIdtDescriptor dd (offset Exception01 - offset Exception00)
-_SizeTotalIdtDescriptors dd (offset CommonHandler - offset Exception00)
-
-END
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib64.asm b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib64.asm
deleted file mode 100644
index fc00e674b7..0000000000
--- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib64.asm
+++ /dev/null
@@ -1,342 +0,0 @@
-;/**
-; * @file
-; *
-; * Ids Assembly library 64bit
-; *
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: IDS
-; * @e \$Revision: 14126 $ @e \$Date: 2009-05-21 23:02:32 +0800 (Thu, 21 May 2009) $
-; */
-;*****************************************************************************
-;
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*****************************************************************************
-
-.code
-IdsDelay PROC
- push rax
- push rdx
- push rbx
- xor rax,rax
- xor rdx,rdx
- rdtsc
-;set target time
- add eax,1500000000
- adc edx,0
- shl rdx,32
- add rdx,rax
- mov rbx,rdx
-;rbx store the target
-;set "Si!=0" skip below loop
-__loop:
- cmp si,0
- jnz __loopexit
- rdtsc
- shl rdx,32
- add rdx,rax
- cmp rdx,rbx
- jae __loopexit
- jmp __loop
-__loopexit:
- pop rbx
- pop rdx
- pop rax
- ret
-IdsDelay ENDP
-;/*++
-;
-;Routine Description:
-;
-; IdsErrorStop -- Function for Assert
-;
-;Arguments:
-; Filecode
-;
-;Returns:
-;
-; None
-;
-;--*/
-public IdsErrorStop
-IdsErrorStop PROC
-;As x64 calling convention RCX is used as input parameters
- push rcx
- push rbx
- push si
- push dx
- push rbx
-
- mov si,0 ; Si is used as control flag, "Si!=0" skip postcode loop
-; send debug port 1st, then fire SimNow breakpoint
- mov ax, 0deadh
- out 0e0h, ax
- mov eax, ecx
- out 84h, eax
- mov eax, 0BACCD00Bh ; Backdoor in SimNow
- mov ebx, 2 ; Select breakpoint feature
- cpuid
-
- mov rax,0dead00000000h
- or rcx,rax
-;rcx= 0dead__FILECODE
- shl rcx,16
-;rcx= 0dead__FILECODE__0000
- mov rbx,rcx
-
- xor rax,rax
- mov dl,6
-
-IdsErrorStopLoop:
- cmp dl,0
- jz IdsErrorStopExit
- cmp si,0
- jnz IdsErrorStopExit
-
- shld rax,rcx,8
- shl rcx,8
- out 80h,eax
- call IdsDelay
-
- dec dl
- cmp dl,0
- jnz _nextloop
- mov dl,6
- mov rcx,rbx
-_nextloop:
- jmp IdsErrorStopLoop
-IdsErrorStopExit:
- pop rbx
- pop dx
- pop si
- pop rbx
- pop rcx
- xor rax,rax
- ret
-IdsErrorStop endp
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Stop CPU
-; *
-; *
-; *
-; */
-IDS_STOP_HERE MACRO
-@@:
- jmp short @b
-ENDM
-
-;======================================================================
-; IdsExceptionHandler: Simply performs a jmp $ and IRET.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-PUBLIC IdsExceptionHandler
-PUBLIC SizeIdtDescriptor
-PUBLIC SizeTotalIdtDescriptors
-
-; Size of each exception MUST be the same
-Exception00:
- push rax
- mov al, 00h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception01:
- push rax
- mov al, 01h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception02:
- push rax
- mov al, 02h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception03:
- push rax
- mov al, 03h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception04:
- push rax
- mov al, 04h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception05:
- push rax
- mov al, 05h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception06:
- push rax
- mov al, 06h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception07:
- push rax
- mov al, 07h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception08:
- push rax
- mov al, 08h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception09:
- push rax
- mov al, 09h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception10:
- push rax
- mov al, 10h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception11:
- push rax
- mov al, 11h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception12:
- push rax
- mov al, 12h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception13:
- push rax
- mov al, 13h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception14:
- push rax
- mov al, 14h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception15:
- push rax
- mov al, 15h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception16:
- push rax
- mov al, 16h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception17:
- push rax
- mov al, 17h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception18:
- push rax
- mov al, 18h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception19:
- push rax
- mov al, 19h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception20:
- push rax
- mov al, 20h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception21:
- push rax
- mov al, 21h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception22:
- push rax
- mov al, 22h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception23:
- push rax
- mov al, 23h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception24:
- push rax
- mov al, 24h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception25:
- push rax
- mov al, 25h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception26:
- push rax
- mov al, 26
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception27:
- push rax
- mov al, 27h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception28:
- push rax
- mov al, 28h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception29:
- push rax
- mov al, 29h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception30:
- push rax
- mov al, 30h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception31:
- push rax
- mov al, 31h
- jmp near ptr CommonHandler
-CommonHandler:
- out 80h, al
- pop rax
- IDS_STOP_HERE
- iretq
-
-IdsExceptionHandler dq offset Exception00
-SizeIdtDescriptor dd (offset Exception01 - offset Exception00)
-SizeTotalIdtDescriptors dd (offset CommonHandler - offset Exception00)
-
-END
-
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mu.asm b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mu.asm
deleted file mode 100644
index 8289f44b64..0000000000
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mu.asm
+++ /dev/null
@@ -1,496 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; Description: Main memory controller system configuration for AGESA
-;
-;
-;*****************************************************************************
-;
-; Copyright (C) 2012 Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-;============================================================================
-
-
- .XLIST
- .LIST
-
- .686p
- .MODEL FLAT
- .CODE
- ASSUME FS: NOTHING
-
-; Define the calling convention used for the C library modules
-;@attention - This should be in a central include file
-CALLCONV EQU NEAR C
-
-
-;===============================================================================
-;memUOutPort:
-;
-; Do a 32 Bit IO Out operation using edx.
-; NOTE: This function will be obsolete in the future.
-;
-; In: Port - port number
-; Value - value to be written
-;
-; Out:
-;
-; All registers preserved.
-;===============================================================================
-MemUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD
- pushad
- mov edx,Port
- mov eax,Value
- out dx,al
- popad
- ret
-MemUOutPort ENDP
-
-
-;----------------------------------------------------------------------------
-; _SFENCE();
-;
-_SFENCE macro
- db 0Fh,0AEh,0F8h
- endm
-
-;----------------------------------------------------------------------------
-; _MFENCE();
-;
-_MFENCE macro
- db 0Fh,0AEh,0F0h
- endm
-
-;----------------------------------------------------------------------------
-; _EXECFENCE();
-;
-_EXECFENCE macro
- out 0EDh,al ;prevent speculative execution of following instructions
- endm
-
-;===============================================================================
-;MemUWriteCachelines:
-; Write a test pattern to DRAM
-;
-; In: Pattern - pointer to the write pattern
-; Address - Physical address to be read
-; ClCount - number of cachelines to be read
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUWriteCachelines PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD, ClCount:WORD
- pushad
- push ds
-
- mov eax,Address
- push ss
- pop ds
- xor edx,edx
- mov edx, DWORD PTR Pattern
- mov esi,edx
- mov edx,16
- _EXECFENCE
- xor ecx, ecx
- mov cx,ClCount
- shl ecx,2
- @@:
- db 66h, 0Fh,6Fh,06 ;MOVDQA xmm0,[esi]
- db 64h, 66h, 0Fh,0E7h,00 ;MOVNTDQ fs:[eax],xmm0 (xmm0 is 128 bits)
- add eax,edx
- add esi,edx
- loop @B
-
- pop ds
- popad
- ret
-MemUWriteCachelines ENDP
-
-;===============================================================================
-;MemUReadCachelines:
-;
-; Read a pattern of 72 bit times (per DQ), to test dram functionality. The
-;pattern is a stress pattern which exercises both ISI and crosstalk. The number
-;of cache lines to fill is dependent on DCT width mode and burstlength.
-;
-; In: Buffer - pointer to a buffer where read data will be stored
-; Address - Physical address to be read
-; ClCount - number of cachelines to be read
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUReadCachelines PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
-LOCAL Count:BYTE
- pushad
- ; First, issue continuous dummy reads to fill up the cache
- mov eax,Address
- .if (ClCount > 18)
- mov cx,ClCount
- shr cx,4
- mov Count,cl
- .while (Count != 0)
- push eax
- mov edi,eax
- add edi,128 ;bias value (to account for signed displacement)
- ;clflush opcode=0F AE /7
- mov esi,edi
- mov ebx,esi
- mov ecx,esi
- mov edx,esi
- add edi,4*64 ;TestAddr+4 cache lines
- add ebx,8*64 ;TestAddr+8 cache lines
- add ecx,12*64 ;TestAddr+12 cache lines
- add edx,16*64 ;TestAddr+16 cache lines
- sub edx,128
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- mov eax,fs:[edi] ;TestAddr+6 cache lines
- _MFENCE
- mov eax,fs:[edi+64] ;TestAddr+7 cache lines
- _MFENCE
- mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
- _MFENCE
- mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
- _MFENCE
- mov eax,fs:[ebx] ;TestAddr+10 cache lines
- _MFENCE
- mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
- _MFENCE
- mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
- _MFENCE
- mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
- _MFENCE
- mov eax,fs:[ecx] ;TestAddr+14 cache lines
- _MFENCE
- mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
- _MFENCE
- pop eax
- add eax,(16*64) ;Next 16CL
- dec Count
- .endw
- .else
- mov edi,eax
- add edi,128 ;bias value (to account for signed displacement)
- ;clflush opcode=0F AE /7
- mov esi,edi
- mov ebx,esi
- mov ecx,esi
- mov edx,esi
- add edi,4*64 ;TestAddr+4 cache lines
- add ebx,8*64 ;TestAddr+8 cache lines
- add ecx,12*64 ;TestAddr+12 cache lines
- add edx,16*64 ;TestAddr+16 cache lines
- sub edx,128
- .if(ClCount == 1)
- _MFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- .elseif(ClCount == 3)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- .elseif(ClCount == 6)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- .elseif(ClCount == 9)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- mov eax,fs:[edi] ;TestAddr+6 cache lines
- _MFENCE
- mov eax,fs:[edi+64] ;TestAddr+7 cache lines
- _MFENCE
- mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
- _MFENCE
- .elseif(ClCount == 18)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- mov eax,fs:[edi] ;TestAddr+6 cache lines
- _MFENCE
- mov eax,fs:[edi+64] ;TestAddr+7 cache lines
- _MFENCE
- mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
- _MFENCE
- mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
- _MFENCE
- mov eax,fs:[ebx] ;TestAddr+10 cache lines
- _MFENCE
- mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
- _MFENCE
- mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
- _MFENCE
- mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
- _MFENCE
- mov eax,fs:[ecx] ;TestAddr+14 cache lines
- _MFENCE
- mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
- _MFENCE
- mov eax,fs:[edx] ;TestAddr+16 cache lines
- _MFENCE
- mov eax,fs:[edx+64] ;TestAddr+17 cache lines
- _MFENCE
- .endif
- .endif
- _MFENCE
-
- ; Then, copy data to buffer
- mov esi,Address
- xor edx,edx
- mov edx,DWORD PTR Buffer
- mov edi,edx
- xor ecx, ecx
- mov cx,ClCount
- shl ecx,6
- @@:
- mov al,fs:[esi]
- mov ss:[edi],al
- inc esi
- inc edi
- loop @B
-
- popad
- ret
-MemUReadCachelines ENDP
-
-;===============================================================================
-;MemUDummyCLRead:
-;
-; Perform a single cache line read from a given physical address.
-;
-; In: Address - Physical address to be read
-; ClCount - number of cachelines to be read
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUDummyCLRead PROC CALLCONV PUBLIC Address:DWORD
- _SFENCE
- pushad
- mov eax,Address
- mov dl,fs:[eax]
- popad
- ret
-MemUDummyCLRead ENDP
-
-;===============================================================================
-;MemUFlushPattern:
-;
-; Flush a pattern of 72 bit times (per DQ) from cache. This procedure is used
-;to ensure cache miss on the next read training.
-;
-; In: Address - Physical address to be flushed
-; ClCount - number of cachelines to be flushed
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUFlushPattern PROC CALLCONV PUBLIC Address:DWORD, ClCount:WORD
- pushad
- mov edi,Address
- movzx ecx,ClCount
- @@:
- _MFENCE ; Force strong ordering of clflush
- db 64h,0Fh,0AEh,3Fh ; MemUClFlush fs:[edi]
- _MFENCE
- add edi,64
- loop @B
- popad
- ret
-MemUFlushPattern ENDP
-
-
-;===============================================================================
-;MemUGetWrLvNblErr:
-; Read ClCount number of cachelines then return the bitmap that indicates
-; the write leveling result of each byte lane.
-;
-; IN: ErrBitmap - pointer to a DWORD that will be assigned with WL result
-; Address - Physical address to be sampled
-; ClCount - number of cachelines to be read
-;
-; OUT: ErrBitmap - WL result
-;
-;All registers preserved
-;===============================================================================
-MemUGetWrLvNblErr PROC CALLCONV PUBLIC ErrBitmap:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
-LOCAL ZeroCount[32]:WORD
-
- pushad
- mov esi,Address
- _EXECFENCE
- ;Cache fill
- movzx ecx,ClCount
- @@:
- mov eax,fs:[esi]
- add esi,64
- loop @B
- _MFENCE
-
- ; Then, count the number of 0's
- ;push es
- ;push ss
- ;pop es
- lea edi,ZeroCount
- mov cx,SIZEOF ZeroCount
- mov al,0
- rep stosb
- ;pop es
-
- mov esi,Address
- lea edi,ZeroCount
- mov cx,ClCount
- shl cx,6
- .while(cx > 0)
- mov al,fs:[esi]
- test al,00Fh ;check lower nibble
- .if(ZERO?)
- inc WORD PTR [edi]
- .endif
- add edi,2
- test al,0F0h ;check upper nibble
- .if(ZERO?)
- inc WORD PTR [edi]
- .endif
- add edi,2
- inc esi
- dec cx
- test cx,07h
- .if(ZERO?)
- sub edi,(16*2)
- sub cx,8
- add esi,8
- .endif
- .endw
-
- ; Then, average and compress data to error bits
- lea esi,ZeroCount
- mov dx,ClCount
- shl dx,1
- xor eax,eax
- xor ecx,ecx
- mov cl,0
- .while(cl<16)
- .if(WORD PTR [esi] < dx)
- bts eax,ecx
- .endif
- add esi,2
- inc cl
- .endw
- xor edx,edx
- mov dx,WORD PTR ErrBitmap
- mov [edx], ax
-
- popad
- ret
-MemUGetWrLvNblErr ENDP
-
-;===============================================================================
-;AlignPointerTo16Byte:
-; Modifies BufferPtr to be 16 byte aligned
-;
-; In: BufferPtrPtr - Pointer to buffer pointer
-; Out: BufferPtrPtr - Pointer to buffer pointer that has been 16 byte aligned
-;
-;All registers preserved.
-;===============================================================================
-AlignPointerTo16Byte PROC CALLCONV PUBLIC BufferPtrPtr:NEAR PTR DWORD
- push edx
- push eax
- mov edx, BufferPtrPtr
- mov eax, [edx]
- add eax, 16
- and ax, 0FFF0h
- mov [edx], eax
- pop eax
- pop edx
- ret
-AlignPointerTo16Byte ENDP
-
-;===============================================================================
-;MemUMFenceInstr:
-; Serialize instruction
-;
-; In:
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUMFenceInstr PROC CALLCONV PUBLIC
- _MFENCE
- ret
-MemUMFenceInstr ENDP
-
- END
-
diff --git a/src/vendorcode/amd/agesa/f15tn/cpcarmac.inc b/src/vendorcode/amd/agesa/f15tn/cpcarmac.inc
deleted file mode 100644
index a3d9f0f73b..0000000000
--- a/src/vendorcode/amd/agesa/f15tn/cpcarmac.inc
+++ /dev/null
@@ -1,456 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-;
-; Description: Code to setup and break down cache-as-stack
-;
-;*****************************************************************************
-;
-; Copyright (C) 2012 Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- .XLIST
- INCLUDE cpcar.inc
- .LIST
- .586P
- .mmx
-
-;======================================================================
-; AMD_ENABLE_STACK: Setup a stack
-;
-; In:
-; EBX = Return address (preserved)
-;
-; Out:
-; SS:ESP - Our new private stack location
-;
-; EAX = AGESA_STATUS
-; EDX = Return status code if EAX contains a return code of higher
-; severity than AGESA_SUCCESS
-; ECX = Stack size in bytes
-;
-; Requirements:
-; * This routine presently is limited to a max of 64 processor cores
-; Preserved:
-; ebx ebp
-; Destroyed:
-; eax, ecx, edx, edi, esi, ds, es, ss, esp
-; mmx0, mmx1, mmx5
-;
-; Description:
-; Fixed MTRR address allocation to cores:
-; The BSP gets 64K of stack, Core0 of each node gets 16K of stack, all other cores get 4K.
-; There is a max of 1 BSP, 7 core0s and 56 other cores.
-; Although each core has it's own cache storage, they share the address space. Each core must
-; be assigned a private and unique address space for its stack. To support legacy systems,
-; the stack needs to be within the legacy address space (1st 1Meg). Room must also be reserved
-; for the other legacy elements (Interrupt vectors, BIOS ROM, video buffer, etc.)
-;
-; 80000h 40000h 00000h
-; +----------+----------+----------+----------+----------+----------+----------+----------+
-; 64K | | | | | | | | | 64K ea
-; ea +----------+----------+----------+----------+----------+----------+----------+----------+
-; | MTRR 0000_0250 MTRRfix64K_00000 |
-; +----------+----------+----------+----------+----------+----------+----------+----------+
-; | 7 , 6 | 5 , 4 | 3 , 2 | 1 , 0 | 0 | | | | <-node
-; |7..1,7..1 |7..1,7..1 |7..1,7..1 |7..1,7..1 | 0 | | | | <-core
-; +----------+----------+----------+----------+----------+----------+----------+----------+
-;
-; C0000h B0000h A0000h 90000h 80000h
-; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
-;16K | | | | | | | | | | | | | | | | |
-; ea +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
-; | MTRR 0259 MTRRfix16K_A0000 | MTRR 0258 MTRRfix16K_80000 |
-; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
-; | > Dis|play B|uffer | < | | | | | 7 | 6 | 5 | 4 | 3 | 2 | 1 | | <-node
-; | > T| e m |p o r |a r y | B u |f f e |r A |r e a<| 0 | 0 | 0 | 0 | 0 | 0 | 0 | | <-core
-; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
-;
-; E0000h D0000h C0000h
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; 4K | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
-; ea +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | 026B MTRRfix4K_D8000 | 026A MTRRfix4K_D0000 | 0269 MTRRfix4K_C8000 | 0268 MTRRfix4K_C0000 |
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | | | | | | | | | | | | | | | | | >| V| I| D| E| O| |B |I |O |S | |A |r |e |a<|
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-;
-; 100000h F0000h E0000h
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | 026F MTRRfix4K_F8000 | 026E MTRRfix4K_F0000 | 026D MTRRfix4K_E8000 | 026C MTRRfix4K_E0000 |
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< |
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-;======================================================================
-AMD_ENABLE_STACK MACRO
- local AmdEnableStackExit
-
-; Note that SS:ESP will be default stack. Note that this stack
-; routine will not be used after memory has been initialized. Because
-; of its limited lifetime, it will not conflict with typical PCI devices.
- movd mm0, ebx ; Put return address in a safe place
- movd mm1, ebp ; Save some other user registers
-
- ; get node id and core id of current executing core
- GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
- ; Note: ESI[31:24] are used for flags: Unrecognized Family, Is_Primary core, Stack already established
-
- ; If we detected an unknown processor family or core combination, return AGESA_FATAL.
- .if (esi & (1 SHL FLAG_UNKNOWN_FAMILY))
- mov edx, CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY
- mov eax, AGESA_FATAL
- jmp AmdEnableStackExit
- .elseif (esi & (1 SHL FLAG_CORE_NOT_IDENTIFIED))
- mov edx, CPU_EVENT_CORE_NOT_IDENTIFIED
- mov eax, AGESA_FATAL
- jmp AmdEnableStackExit
- .endif
-
- ; determine if stack is already enabled. We are using the DefType MSR for this determination.
- ; It is =0 after reset; CAR setup sets it to enable the MTRRs
- mov eax, cr0 ; Is cache enabled? (CD or NW bit set)
- CR0_MASK TEXTEQU %((1 SHL CR0_CD) OR (1 SHL CR0_NW))
- .if (!(eax & CR0_MASK))
- mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF
- _RDMSR ; Are either of the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)
- MSR_MASK TEXTEQU %((1 SHL MTRR_DEF_TYPE_EN)+(1 SHL MTRR_DEF_TYPE_FIX_EN))
- .if (eax & MSR_MASK)
- bts esi, FLAG_STACK_REENTRY ; indicate stack has already been initialized
- .endif
- .endif
-
- ; Set node to map the first 16MB to node 0; 0000_0000 to 00FF_FFFF as DRAM
- mov ebx, esi ; Get my Node/Core info
- xor bl, bl
- shl bh, 3 ; Isolate my node#, match alignment for PCI Dev#
- mov eax, 8000C144h ; D18F1x44:DRAM Base/Limit; N is Base, N+4 is Limit
- add ah, bh
- mov ebx, eax ; Save PCI address for Base/Limit pair
-
- mov dx, 0CF8h
- out dx, eax
- add dx, 4
- xor eax, eax ; Least Significant bit is AD24 so 0 sets mask of 00FF_FFFF (16MB)
- out dx, eax ; DRAM Limit = node0, no interleave
-
- mov eax, ebx
- sub eax, 4 ; Now point to the Base register
- mov dx, 0CF8h
- out dx, eax
- add dx, 4
- mov eax, 00000003h ; Set the read and write enable bits
- out dx, eax ; DRAM Base = 0x0000, R/W
-
- AMD_ENABLE_STACK_FAMILY_HOOK
-
- ; Init CPU MSRs for our init routines
- mov ecx, MTRR_SYS_CFG ; SYS_CFG
- _RDMSR
- bts eax, MTRR_FIX_DRAM_MOD_EN ; Turn on modification enable bit
- _WRMSR
-
- mov eax, esi
- bt eax, FLAG_STACK_REENTRY ; Is this a 2nd entry?
- .if (!carry?) ; On a re-entry, do not clear MTRRs or reset TOM; just reset the stack SS:ESP
- bt eax, FLAG_IS_PRIMARY ; Is this core the primary in a compute unit?
- .if (carry?) ; Families using shared groups do not need to clear the MTRRs since that is done at power-on reset
- ; Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores
- ; Clear all variable and Fixed MTRRs for non-shared cores
- mov ecx, AMD_MTRR_VARIABLE_BASE0
- xor eax, eax
- xor edx, edx
- .while (cl != 10h) ; Variable MTRRphysBase[n] and MTRRphysMask[n]
- _WRMSR
- inc cl
- .endw
- mov cx, AMD_MTRR_FIX64k_00000 ; MSR:0000_0250
- _WRMSR
- mov cx, AMD_MTRR_FIX16k_80000 ; MSR:0000_0258
- _WRMSR
- mov cx, AMD_MTRR_FIX16k_A0000 ; MSR:0000_0259
- _WRMSR
- mov cx, AMD_MTRR_FIX4k_C0000 ; Fixed 4Ks: MTRRfix4K_C0000 to MTRRfix4K_F8000
- .while (cl != 70h)
- _WRMSR
- inc cl
- .endw
-
- ; Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init.
- ; - not strictly needed since the FixedMTRRs take presedence.
- mov eax, (16 * 1024 * 1024)
- mov ecx, TOP_MEM ; MSR:C001_001A
- _WRMSR
- .endif ; End Is_Primary
- .endif ; End Stack_ReEntry
-
- ; Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores
- xor eax, eax
- xor edx, edx
- mov ecx, IORR_BASE ; MSR:C001_0016 - 0019
- .while (cl != 1Ah)
- _WRMSR
- inc cl
- .endw
- mov ecx, TOP_MEM2 ; MSR:C001_001D
- _WRMSR
-
- ; setup MTRRs for stacks
- ; A speculative read can be generated by a speculative fetch mis-aligned in a code zone
- ; or due to a data zone being interpreted as code. When a speculative read occurs outside a
- ; controlled region (intentionally used by software), it could cause an unwanted cache eviction.
- ; To prevent speculative reads from causing an eviction, the unused cache ranges are set
- ; to UC type. Only the actively used regions (stack, heap) are reflected in the MTRRs.
- ; Note: some core stack regions will share an MTRR since the control granularity is much
- ; larger than the allocated stack zone. The allocation algorithm must account for this 'extra'
- ; space covered by the MTRR when parseling out cache space for the various uses. In some cases
- ; this could reduce the amount of EXE cache available to a core. see cpuCacheInit.c
- ;
- ; Outcome of this block is that: (Note the MTRR map at the top of the file)
- ; ebp - start address of stack block
- ; ebx - [31:16] - MTRR MSR address
- ; - [15:8] - slot# in MTRR register
- ; - [7:0] - block size in #4K blocks
- ; review: ESI[31:24]=Flags; SI[15,8]= Node#; SI[7,0]= core# (relative to node)
- ;
-
- mov eax, esi ; Load Flags, node, core
- .if (al == 0) ; Is a core 0?
- .if (ah == 0) ; Is Node 0? (BSP)
- ; Is BSP, assign a 64K stack; for F10/F12, foce to a 32K stack
- mov ebx, ((AMD_MTRR_FIX64k_00000 SHL 16) + (3 SHL 8) + (BSP_STACK_SIZE_64K / 1000h))
- bt eax, FLAG_FORCE_32K_STACK
- .if (carry?)
- mov ebx, ((AMD_MTRR_FIX64k_00000 SHL 16) + (3 SHL 8) + (BSP_STACK_SIZE_32K / 1000h))
- .endif
- mov ebp, BSP_STACK_BASE_ADDR
- .else ; node 1 to 7, core0
- ; Is a Core0 of secondary node, assign 16K stacks
- mov bx, AMD_MTRR_FIX16k_80000
- shl ebx, 16 ;
- mov bh, ah ; Node# is used as slot#
- mov bl, (CORE0_STACK_SIZE / 1000h)
- mov al, ah ; Base = (Node# * Size);
- mul bl ;
- movzx eax, ax ;
- shl eax, 12 ; Expand back to full byte count (* 4K)
- add eax, CORE0_STACK_BASE_ADDR
- mov ebp, eax
- .endif
- .else ;core 1 thru core 7
- ; Is core 1-7 of any node, assign 4K stacks
- mov al, 8 ; CoreIndex = ( (Node# * 8) ...
- mul ah ;
- mov bx, si ;
- add al, bl ; ... + Core#);
-
- mov bx, AMD_MTRR_FIX64k_00000
- shl ebx, 16 ;
- mov bh, al ; Slot# = (CoreIndex / 16) + 4;
- shr bh, 4 ;
- add bh, 4 ;
- mov bl, (CORE1_STACK_SIZE / 1000h)
-
- mul bl ; Base = ( (CoreIndex * Size) ...
- movzx eax, ax ;
- shl eax, 12 ; Expand back to full byte count (* 4K)
- add eax, CORE1_STACK_BASE_ADDR ; ... + Base_Addr);
- mov ebp, eax
- .endif
-
- ; Now set the MTRR. Add this to already existing settings (don't clear any MTRR)
- mov edi, WB_DRAM_TYPE ; Load Cache type in 1st slot
- mov cl, bh ; ShiftCount = ((slot# ...
- and cl, 03h ; ... % 4) ...
- shl cl, 3 ; ... * 8);
- shl edi, cl ; Cache type is now in correct position
- ror ebx, 16 ; Get the MTRR address
- movzx ecx, bx ;
- rol ebx, 16 ; Put slot# & size back in BX
- _RDMSR ; Read-modify-write the MSR
- .if (bh < 4) ; Is value in lower or upper half of MSR?
- or eax, edi ;
- .else ;
- or edx, edi ;
- .endif ;
- _WRMSR ;
-
- ; Enable MTRR defaults as UC type
- mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF
- _RDMSR ; Read-modify-write the MSR
- bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn
- bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn
- _WRMSR
-
- ; Close the modification window on the Fixed MTRRs
- mov ecx, MTRR_SYS_CFG ; MSR:0C001_0010
- _RDMSR
- bts eax, MTRR_FIX_DRAM_EN ; MtrrFixDramEn
- bts eax, MTRR_VAR_DRAM_EN ; variable MTRR enable bit
- btr eax, MTRR_FIX_DRAM_MOD_EN ; Turn off modification enable bit
- _WRMSR
-
- ; Enable caching in CR0
- mov eax, CR0 ; Enable WT/WB cache
- btr eax, CR0_PG ; Make sure paging is disabled
- btr eax, CR0_CD ; Clear CR0 NW and CD
- btr eax, CR0_NW
- mov CR0, eax
-
- ; Use the Stack Base & size to calculate SS and ESP values
- ; review:
- ; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
- ; ebp - start address of stack block
- ; ebx - [31:16] - MTRR MSR address
- ; - [15:8] - slot# in MTRR register
- ; - [7:0] - block size in #4K blocks
- ;
- mov esp, ebp ; Initialize the stack pointer
- mov edi, esp ; Copy the stack start to edi
- movzx bx, bl
- movzx ebx, bx ; Clear upper ebx, don't need MSR addr anymore
- shl ebx, 12 ; Make size full byte count (* 4K)
- add esp, ebx ; Set the Stack Pointer as full linear address
- sub esp, 4
- ;
- ; review:
- ; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
- ; edi - 32b start address of stack block
- ; ebx - size of stack block
- ; esp - 32b linear stack pointer
- ;
-
- ; Determine mode for SS base;
- mov ecx, CR0 ; Check for 32-bit protect mode
- bt ecx, CR0_PE ;
- .if (!carry?) ; PE=0 means real mode
- mov cx, cs ;
- .if (cx >= 0D000h) ; If CS >= D000, it's a real mode segment. PM selector would be 08-> 1000
- ; alter SS:ESP for 16b Real Mode:
- mov eax, edi ;
- shr eax, 4 ; Create a Real Mode segment for ss, ds, es
- mov ss, ax ;
- mov ds, ax ;
- mov es, ax ;
- shl eax, 4 ;
- sub edi, eax ; Adjust the clearing pointer for Seg:Offset mode
- mov esp, ebx ; Make SP an offset from SS
- sub esp, 4 ;
- .endif ; endif
- ; else
- ; Default is to use Protected 32b Mode
- .endif
- ;
- ; Clear The Stack
- ; Now that we have set the location and the MTRRs, initialize the cache by
- ; reading then writing to zero all of the stack area.
- ; review:
- ; ss - Stack base
- ; esp - stack pointer
- ; ebx - size of stack block
- ; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
- ; edi - address of start of stack block
- ;
- shr ebx, 2 ;
- mov cx, bx ; set cx for size count of DWORDS
- ; Check our flags - Don't clear an existing stack
- .if ( !(esi & (1 SHL FLAG_STACK_REENTRY)) )
- cld
- mov esi, edi
- rep lods DWORD PTR [esi] ; Pre-load the range
- xor eax, eax
- mov cx, bx
- mov esi, edi ; Preserve base for push on stack
- rep stos DWORD PTR [edi] ; Clear the range
- mov DWORD PTR [esp], 0ABCDDCBAh ; Put marker in top stack dword
- shl ebx, 2 ; Put stack size and base
- push ebx ; in top of stack
- push esi
-
- mov ecx, ebx ; Return size of stack in bytes
- mov eax, AGESA_SUCCESS ; eax = AGESA_SUCCESS : no error return code
- .else
- movzx ecx, cx
- shl ecx, 2 ; Return size of stack, in bytes
- mov edx, CPU_EVENT_STACK_REENTRY
- mov eax, AGESA_WARNING ; eax = AGESA_WARNING (Stack has already been set up)
- .endif
-
-AmdEnableStackExit:
- movd ebx, mm0 ; Restore return address
- movd ebp, mm1
-ENDM
-
-;======================================================================
-; AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine
-; should only be executed on the BSP
-;
-; In:
-; none
-;
-; Out:
-; EAX = AGESA_SUCCESS
-;
-; Preserved:
-; ebx
-; Destroyed:
-; eax, ecx, edx, esp, mmx5
-;======================================================================
-AMD_DISABLE_STACK MACRO
-
- mov esp, ebx ; Save return address
-
- ; get node/core/flags of current executing core
- GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
-
- ; Turn on modification enable bit
- mov ecx, MTRR_SYS_CFG ; MSR:C001_0010
- _RDMSR
- bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable modifications
- _WRMSR
-
- ; Set lower 640K MTRRs for Write-Back memory caching
- mov ecx, AMD_MTRR_FIX64k_00000
- mov eax, 1E1E1E1Eh
- mov edx, eax
- _WRMSR ; 0 - 512K = WB Mem
- mov ecx, AMD_MTRR_FIX16k_80000
- _WRMSR ; 512K - 640K = WB Mem
-
- ; Turn off modification enable bit
- mov ecx, MTRR_SYS_CFG ; MSR:C001_0010
- _RDMSR
- btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable modification
- _WRMSR
-
- AMD_DISABLE_STACK_FAMILY_HOOK ; Re-Enable 'normal' cache operations
-
- mov ebx, esp ; restore return address (ebx)
- xor eax, eax
-
-ENDM
diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/PlatformMemoryConfiguration.inc b/src/vendorcode/amd/agesa/f16kb/Legacy/PlatformMemoryConfiguration.inc
deleted file mode 100644
index 872f973585..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Legacy/PlatformMemoryConfiguration.inc
+++ /dev/null
@@ -1,701 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * AMD Platform Specific Memory Configuration
-; *
-; * Contains AMD AGESA Memory Configuration Override Interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
-;
-; ****************************************************************************
-; *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; *
-; **************************************************************************
-IFNDEF PSO_ENTRY
- PSO_ENTRY TEXTEQU <UINT8>; < Platform Configuration Table Entry
-ENDIF
-; *****************************************************************************************
-; *
-; * PLATFORM SPECIFIC MEMORY DEFINITIONS
-; *
-; *****************************************************************************************
-; */
-;
-; < Memory Speed and DIMM Population Masks
-;
-; < DDR Speed Masks
-;
-ANY_SPEED EQU 0FFFFFFFFh
-DDR400 EQU ( 1 SHL (DDR400_FREQUENCY / 66))
-DDR533 EQU ( 1 SHL (DDR533_FREQUENCY / 66))
-DDR667 EQU ( 1 SHL (DDR667_FREQUENCY / 66))
-DDR800 EQU ( 1 SHL (DDR800_FREQUENCY / 66))
-DDR1066 EQU ( 1 SHL (DDR1066_FREQUENCY / 66))
-DDR1333 EQU ( 1 SHL (DDR1333_FREQUENCY / 66))
-DDR1600 EQU ( 1 SHL (DDR1600_FREQUENCY / 66))
-DDR1866 EQU ( 1 SHL (DDR1866_FREQUENCY / 66))
-DDR2133 EQU ( 1 SHL (DDR2133_FREQUENCY / 66))
-DDR2400 EQU ( 1 SHL (DDR2400_FREQUENCY / 66))
-; <
-; < DIMM POPULATION MASKS
-;
-ANY_ EQU 0FFh
-SR_DIMM0 EQU 0001h
-SR_DIMM1 EQU 0010h
-SR_DIMM2 EQU 0100h
-SR_DIMM3 EQU 1000h
-DR_DIMM0 EQU 0002h
-DR_DIMM1 EQU 0020h
-DR_DIMM2 EQU 0200h
-DR_DIMM3 EQU 2000h
-QR_DIMM0 EQU 0004h
-QR_DIMM1 EQU 0040h
-QR_DIMM2 EQU 0400h
-QR_DIMM3 EQU 4000h
-LR_DIMM0 EQU 0001h
-LR_DIMM1 EQU 0010h
-LR_DIMM2 EQU 0100h
-LR_DIMM3 EQU 1000h
-ANY_DIMM0 EQU 000Fh
-ANY_DIMM1 EQU 00F0h
-ANY_DIMM2 EQU 0F00h
-ANY_DIMM3 EQU 0F000h
-; <
-; < CS POPULATION MASKS
-;
-CS_ANY_ EQU 0FFh
-CS0_ EQU 01h
-CS1_ EQU 02h
-CS2_ EQU 04h
-CS3_ EQU 08h
-CS4_ EQU 10h
-CS5_ EQU 20h
-CS6_ EQU 40h
-CS7_ EQU 80h
-;
-; Number of Dimms
-;
-ANY_NUM EQU 0FFh
-NO_DIMM EQU 00h
-ONE_DIMM EQU 01h
-TWO_DIMM EQU 02h
-THREE_DIMM EQU 04h
-FOUR_DIMM EQU 08h
-;
-; DIMM VOLTAGE MASK
-;
-VOLT_ANY_ EQU 0FFh
-VOLT1_5_ EQU 01h
-VOLT1_35_ EQU 02h
-VOLT1_25_ EQU 04h
-;
-; NOT APPLICIABLE
-;
-NA_ EQU 00h
-; *****************************************************************************************
-; *
-; * Platform Specific Override Definitions for Socket, Channel and Dimm
-; * This indicates where a platform override will be applied.
-; *
-; *****************************************************************************************
-;
-; SOCKET MASKS
-;
-ANY_SOCKET EQU 0FFh
-SOCKET0 EQU 01h
-SOCKET1 EQU 02h
-SOCKET2 EQU 04h
-SOCKET3 EQU 08h
-SOCKET4 EQU 10h
-SOCKET5 EQU 20h
-SOCKET6 EQU 40h
-SOCKET7 EQU 80h
-;
-; CHANNEL MASKS
-;
-ANY_CHANNEL EQU 0FFh
-CHANNEL_A EQU 01h
-CHANNEL_B EQU 02h
-CHANNEL_C EQU 04h
-CHANNEL_D EQU 08h
-;
-; DIMM MASKS
-;
-ALL_DIMMS EQU 0FFh
-DIMM0 EQU 01h
-DIMM1 EQU 02h
-DIMM2 EQU 04h
-DIMM3 EQU 08h
-;
-; REGISTER ACCESS MASKS
-;
-ACCESS_NB0 EQU 0h
-ACCESS_NB1 EQU 01h
-ACCESS_NB2 EQU 02h
-ACCESS_NB3 EQU 03h
-ACCESS_NB4 EQU 04h
-ACCESS_PHY EQU 05h
-ACCESS_DCT_XT EQU 06h
-;
-; MOTHER BOARD DESIGN LAYERS MASKS
-; Indicates the layer design of mother board
-;
-LAYERS_4 EQU 0h
-LAYERS_6 EQU 01h
-; *****************************************************************************************
-; *
-; * Platform Specific Overriding Table Definitions
-; *
-; *****************************************************************************************
-PSO_END EQU 0 ; < Table End
-PSO_CKE_TRI EQU 1 ; < CKE Tristate Map
-PSO_ODT_TRI EQU 2 ; < ODT Tristate Map
-PSO_CS_TRI EQU 3 ; < CS Tristate Map
-PSO_MAX_DIMMS EQU 4 ; < Max Dimms per channel
-PSO_CLK_SPEED EQU 5 ; < Clock Speed
-PSO_DIMM_TYPE EQU 6 ; < Dimm Type
-PSO_MEMCLK_DIS EQU 7 ; < MEMCLK Disable Map
-PSO_MAX_CHNLS EQU 8 ; < Max Channels per Socket
-PSO_BUS_SPEED EQU 9 ; < Max Memory Bus Speed
-PSO_MAX_CHIPSELS EQU 10 ; < Max Chipsel per Channel
-PSO_MEM_TECH EQU 11 ; < Channel Memory Type
-PSO_WL_SEED EQU 12 ; < DDR3 Write Levelization Seed delay
-PSO_RXEN_SEED EQU 13 ; < Hardwared based RxEn seed
-PSO_NO_LRDIMM_CS67_ROUTING EQU 14 ; < CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
-PSO_SOLDERED_DOWN_SODIMM_TYPE EQU 15 ; < Soldered down SODIMM type
-PSO_LVDIMM_VOLT1_5_SUPPORT EQU 16 ; < Force LvDimm voltage to 1.5V
-PSO_MIN_RD_WR_DATAEYE_WIDTH EQU 17 ; < Min RD/WR dataeye width
-PSO_CPU_FAMILY_TO_OVERRIDE EQU 18 ; < CPU family signature to tell following PSO macros are CPU family dependent
-PSO_MAX_SOLDERED_DOWN_DIMMS EQU 19 ; < Max Soldered-down Dimms per channel
-PSO_MEMORY_POWER_POLICY EQU 20 ; < Memory power policy override
-PSO_MOTHER_BOARD_LAYERS EQU 21 ; < Mother board layer design
-; **********************************
-; * CONDITIONAL PSO SPECIFIC ENTRIES
-; **********************************
-; Condition Types
-CONDITIONAL_PSO_MIN EQU 100 ; < Start of Conditional Entry Types
-PSO_CONDITION_AND EQU 100 ; < And Block - Start of Conditional block
-PSO_CONDITION_LOC EQU 101 ; < Location - Specify Socket, Channel, Dimms to be affected
-PSO_CONDITION_SPD EQU 102 ; < SPD - Specify a specific SPD value on a Dimm on the channel
-PSO_CONDITION_REG EQU 103 ; Reserved
-PSO_CONDITION_MAX EQU 103 ; < End Of Condition Entry Types
-; Action Types
-PSO_ACTION_MIN EQU 120 ; < Start of Action Entry Types
-PSO_ACTION_ODT EQU 120 ; < ODT values to override
-PSO_ACTION_ADDRTMG EQU 121 ; < Address/Timing values to override
-PSO_ACTION_ODCCONTROL EQU 122 ; < ODC Control values to override
-PSO_ACTION_SLEWRATE EQU 123 ; < Slew Rate value to override
-PSO_ACTION_REG EQU 124 ; Reserved
-PSO_ACTION_SPEEDLIMIT EQU 125 ; < Memory Bus speed Limit based on configuration
-PSO_ACTION_MAX EQU 125 ; < End of Action Entry Types
-CONDITIONAL_PSO_MAX EQU 139 ; < End of Conditional Entry Types
-; **********************************
-; * TABLE DRIVEN PSO SPECIFIC ENTRIES
-; **********************************
-; Condition descriptor
-PSO_TBLDRV_CONFIG EQU 200 ; < Configuration Descriptor
-
-; Overriding entry types
-PSO_TBLDRV_START EQU 210 ; < Start of Table Driven Overriding Entry Types
-PSO_TBLDRV_SPEEDLIMIT EQU 210 ; < Speed Limit
-PSO_TBLDRV_ODT_RTTNOM EQU 211 ; < RttNom
-PSO_TBLDRV_ODT_RTTWR EQU 212 ; < RttWr
-PSO_TBLDRV_ODTPATTERN EQU 213 ; < Odt Patterns
-PSO_TBLDRV_ADDRTMG EQU 214 ; < Address/Timing values
-PSO_TBLDRV_ODCCTRL EQU 215 ; < ODC Control values
-PSO_TBLDRV_SLOWACCMODE EQU 216 ; < Slow Access Mode
-PSO_TBLDRV_MR0_CL EQU 217 ; < MR0[CL]
-PSO_TBLDRV_MR0_WR EQU 218 ; < MR0[WR]
-PSO_TBLDRV_RC2_IBT EQU 219 ; < RC2[IBT]
-PSO_TBLDRV_RC10_OPSPEED EQU 220 ; < RC10[Opearting Speed]
-PSO_TBLDRV_LRDIMM_IBT EQU 221 ; < LrDIMM IBT
-PSO_TBLDRV_2D_TRAINING EQU 222 ; < 2D training
-PSO_TBLDRV_INVALID_TYPE EQU 223 ; < Invalid Type
-PSO_TBLDRV_END EQU 223 ; < End of Table Driven Overriding Entry Types
-
-
-; *****************************************************************************************
-; *
-; * CONDITIONAL OVERRIDE TABLE MACROS
-; *
-; *****************************************************************************************
-CPU_FAMILY_TO_OVERRIDE MACRO CpuFamilyRevision:REQ
- DB PSO_CPU_FAMILY_TO_OVERRIDE
- DB 4
- DD CpuFamilyRevision
-ENDM
-
-MEMCLK_DIS_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
- DB PSO_MEMCLK_DIS
- DB 11
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB Bit0Map
- DB Bit1Map
- DB Bit2Map
- DB Bit3Map
- DB Bit4Map
- DB Bit5Map
- DB Bit6Map
- DB Bit7Map
-ENDM
-
-CKE_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ
- DB PSO_CKE_TRI
- DB 5
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB Bit0Map
- DB Bit1Map
-ENDM
-
-ODT_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ
- DB PSO_ODT_TRI
- DB 7
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB Bit0Map
- DB Bit1Map
- DB Bit2Map
- DB Bit3Map
-ENDM
-
-CS_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
- DB PSO_CS_TRI
- DB 11
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB Bit0Map
- DB Bit1Map
- DB Bit2Map
- DB Bit3Map
- DB Bit4Map
- DB Bit5Map
- DB Bit6Map
- DB Bit7Map
-ENDM
-
-NUMBER_OF_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfDimmSlotsPerChannel:REQ
- DB PSO_MAX_DIMMS
- DB 4
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB NumberOfDimmSlotsPerChannel
-ENDM
-
-NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfSolderedDownDimmsPerChannel:REQ
- DB PSO_MAX_SOLDERED_DOWN_DIMMS
- DB 4
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB NumberOfSolderedDownDimmsPerChannel
-ENDM
-
-NUMBER_OF_CHIP_SELECTS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfChipSelectsPerChannel:REQ
- DB PSO_MAX_CHIPSELS
- DB 4
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB NumberOfChipSelectsPerChannel
-ENDM
-
-NUMBER_OF_CHANNELS_SUPPORTED MACRO SocketID:REQ, NumberOfChannelsPerSocket:REQ
- DB PSO_MAX_CHNLS
- DB 4
- DB SocketID
- DB ANY_CHANNEL
- DB ALL_DIMMS
- DB NumberOfChannelsPerSocket
-ENDM
-
-OVERRIDE_DDR_BUS_SPEED MACRO SocketID:REQ, ChannelID:REQ, TimingMode:REQ, BusSpeed:REQ
- PSO_BUS_SPEED
- DB 11
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DD TimingMode
- DD BusSpeed
-ENDM
-
-DRAM_TECHNOLOGY MACRO SocketID:REQ, MemTechType:REQ
- DB PSO_MEM_TECH
- DB 7
- DB SocketID
- DB ANY_CHANNEL
- DB ALL_DIMMS
- DD MemTechType
-ENDM
-
-WRITE_LEVELING_SEED MACRO SocketID:REQ, ChannelID:REQ, DimmID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
-Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
- DB PSO_WL_SEED
- DB 12
- DB SocketID
- DB ChannelID
- DB DimmID
- DB Byte0Seed
- DB Byte1Seed
- DB Byte2Seed
- DB Byte3Seed
- DB Byte4Seed
- DB Byte5Seed
- DB Byte6Seed
- DB Byte7Seed
- DB ByteEccSeed
-ENDM
-
-HW_RXEN_SEED MACRO SocketID:REQ, ChannelID:REQ, DimmID: REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
-Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
- DB PSO_RXEN_SEED
- DB 21
- DB SocketID
- DB ChannelID
- DB DimmID
- DW Byte0Seed
- DW Byte1Seed
- DW Byte2Seed
- DW Byte3Seed
- DW Byte4Seed
- DW Byte5Seed
- DW Byte6Seed
- DW Byte7Seed
- DW ByteEccSeed
-ENDM
-
-NO_LRDIMM_CS67_ROUTING MACRO SocketID:REQ, ChannelID:REQ
- DB PSO_NO_LRDIMM_CS67_ROUTING
- DB 4
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB 1
-ENDM
-
-SOLDERED_DOWN_SODIMM_TYPE MACRO SocketID:REQ, ChannelID:REQ
- DB PSO_SOLDERED_DOWN_SODIMM_TYPE
- DB 4
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB 1
-ENDM
-
-LVDIMM_FORCE_VOLT1_5_FOR_D0 MACRO
- DB PSO_LVDIMM_VOLT1_5_SUPPORT
- DB 4
- DB ANY_SOCKET
- DB ANY_CHANNEL
- DB ALL_DIMMS
- DB 1
-ENDM
-
-MIN_RD_WR_DATAEYE_WIDTH MACRO SocketID:REQ, ChannelID:REQ, MinRdDataeyeWidth:REQ, MinWrDataeyeWidth:REQ
- DB PSO_MIN_RD_WR_DATAEYE_WIDTH
- DB 5
- DB SocketID
- DB ChannelID
- DB ALL_DIMMS
- DB MinRdDataeyeWidth
- DB MinWrDataeyeWidth
-ENDM
-
-MEMORY_POWER_POLICY_OVERRIDE MACRO PowerPolicy:REQ
- DB PSO_MEMORY_POWER_POLICY
- DB 4
- DB ANY_SOCKET
- DB ANY_CHANNEL
- DB ALL_DIMMS
- DB PowerPolicy
-ENDM
-
-MOTHER_BOARD_LAYERS MACRO Layers:REQ
- DB PSO_MOTHER_BOARD_LAYERS
- DB 1
- DB Layers
-ENDM
-; *****************************************************************************************
-; *
-; * CONDITIONAL OVERRIDE TABLE MACROS
-; *
-; *****************************************************************************************
-CONDITION_AND MACRO
- DB PSO_CONDITION_AND
- DB 0
-ENDM
-
-COND_LOC MACRO SocketMsk:REQ, ChannelMsk:REQ, DimmMsk:REQ
- DB PSO_CONDITION_LOC
- DB 3
- DB SocketMsk
- DB ChannelMsk
- DB DimmMsk
-ENDM
-
-COND_SPD MACRO Byte:REQ, Mask:REQ, Value:REQ
- DB PSO_CONDITION_SPD
- DB 3
- DB Byte
- DB Mask
- DB Value
-ENDM
-
-COND_REG MACRO Access:REQ, Offset:REQ, Mask:REQ, Value:REQ
- DB PSO_CONDITION_REG
- DB 11
- DB Access
- DW Offset
- DD Mask
- DD Value
-ENDM
-
-ACTION_ODT MACRO Frequency:REQ, Dimms:REQ, QrDimms:REQ, DramOdt:REQ, QrDramOdt:REQ, DramDynOdt:REQ
- DB PSO_ACTION_ODT
- DB 9
- DD Frequency
- DB Dimms
- DB QrDimms
- DB DramOdt
- DB QrDramOdt
- DB DramDynOdt
-ENDM
-
-ACTION_ADDRTMG MACRO Frequency:REQ, DimmConfig:REQ, AddrTmg:REQ
- DB PSO_ACTION_ADDRTMG
- DB 10
- DD Frequency
- DW DimmConfig
- DD AddrTmg
-ENDM
-
-ACTION_ODCCTRL MACRO Frequency:REQ, DimmConfig:REQ, OdcCtrl:REQ
- DB PSO_ACTION_ODCCONTROL
- DB 10
- DD Frequency
- DW DimmConfig
- DD OdcCtrl
-ENDM
-
-ACTION_SLEWRATE MACRO Frequency:REQ, DimmConfig:REQ, SlewRate:REQ
- DB PSO_ACTION_SLEWRATE
- DB 10
- DD Frequency
- DW DimmConfig
- DD SlewRate
-ENDM
-
-ACTION_SPEEDLIMIT MACRO DimmConfig:REQ, Dimms:REQ, SpeedLimit15:REQ, SpeedLimit135:REQ, SpeedLimit125:REQ
- DB PSO_ACTION_SPEEDLIMIT
- DB 9
- DW DimmConfig
- DB Dimms
- DW SpeedLimit15
- DW SpeedLimit135
- DW SpeedLimit125
-ENDM
-
-; *****************************************************************************************
-; *
-; * END OF CONDITIONAL OVERRIDE TABLE MACROS
-; *
-; *****************************************************************************************
-; *****************************************************************************************
-; *
-; * TABLE DRIVEN OVERRIDE MACROS
-; *
-; *****************************************************************************************
-; Configuration sub-descriptors
-CONFIG_GENERAL EQU 0
-CONFIG_SPEEDLIMIT EQU 1
-CONFIG_RC2IBT EQU 2
-CONFIG_DONT_CARE EQU 3
-Config_Type TEXTEQU <DWORD>
-;
-; Configuration Macros
-;
-TBLDRV_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Frequency:REQ, DimmVolt:REQ, DimmConfig:REQ
- DB PSO_TBLDRV_CONFIG
- DB 9
- DB CONFIG_GENERAL
- DB DimmPerCH
- DB DimmVolt
- DD Frequency
- DW DimmConfig
-ENDM
-
-TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Dimms:REQ, NumOfSR:REQ, NumOfDR:REQ, NumOfQR:REQ, NumOfLRDimm:REQ
- DB PSO_TBLDRV_CONFIG
- DB 7
- DB CONFIG_SPEEDLIMIT
- DB DimmPerCH
- DB Dimms
- DB NumOfSR
- DB NumOfDR
- DB NumOfQR
- DB NumOfLRDimm
-ENDM
-
-TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Frequency:REQ, DimmVolt:REQ, DimmConfig:REQ, NumOfReg:REQ
- DB PSO_TBLDRV_CONFIG
- DB 10
- DB CONFIG_RC2IBT
- DB DimmPerCH
- DB DimmVolt
- DD Frequency
- DW DimmConfig
- DB NumOfReg
-ENDM
-;
-; Overriding Macros
-;
-TBLDRV_CONFIG_ENTRY_SPEEDLIMIT MACRO SpeedLimit1_5:REQ, SpeedLimit1_35:REQ, SpeedLimit1_25:REQ
- DB PSO_TBLDRV_SPEEDLIMIT
- DB 6
- DW SpeedLimit1_5
- DW SpeedLimit1_35
- DW SpeedLimit1_25
-ENDM
-
-TBLDRV_CONFIG_ENTRY_ODT_RTTNOM MACRO TgtCS:REQ, RttNom:REQ
- DB PSO_TBLDRV_ODT_RTTNOM
- DB 2
- DB TgtCS
- DB RttNom
-ENDM
-
-TBLDRV_CONFIG_ENTRY_ODT_RTTWR MACRO TgtCS:REQ, RttWr:REQ
- DB PSO_TBLDRV_ODT_RTTWR
- DB 2
- DB TgtCS
- DB RttWr
-ENDM
-
-TBLDRV_CONFIG_ENTRY_ODTPATTERN MACRO RdODTCSHigh:REQ, RdODTCSLow:REQ, WrODTCSHigh:REQ, WrODTCSLow:REQ
- DB PSO_TBLDRV_ODTPATTERN
- DB 16
- DD RdODTCSHigh
- DD RdODTCSLow
- DD WrODTCSHigh
- DD WrODTCSLow
-ENDM
-
-TBLDRV_CONFIG_ENTRY_ADDRTMG MACRO AddrTmg:REQ
- DB PSO_TBLDRV_ADDRTMG
- DB 4
- DD AddrTmg
-ENDM
-
-TBLDRV_CONFIG_ENTRY_ODCCTRL MACRO OdcCtrl:REQ
- DB PSO_TBLDRV_ODCCTRL
- DB 4
- DD OdcCtrl
-ENDM
-
-TBLDRV_CONFIG_ENTRY_SLOWACCMODE MACRO SlowAccMode:REQ
- DB PSO_TBLDRV_SLOWACCMODE
- DB 1
- DB SlowAccMode
-ENDM
-
-TBLDRV_CONFIG_ENTRY_RC2_IBT MACRO TgtDimm:REQ, IBT:REQ
- DB PSO_TBLDRV_RC2_IBT
- DB 2
- DB TgtDimm
- DB IBT
-ENDM
-
-TBLDRV_OVERRIDE_MR0_CL MACRO RegValOfTcl:REQ, MR0CL13:REQ, MR0CL0:REQ
- DB PSO_TBLDRV_CONFIG
- DB 1
- DB CONFIG_DONT_CARE
- DB PSO_TBLDRV_MR0_CL
- DB 3
- DB RegValOfTcl
- DB MR0CL13
- DB MR0CL0
-ENDM
-
-TBLDRV_OVERRIDE_MR0_WR MACRO RegValOfTwr:REQ, MR0WR:REQ
- DB PSO_TBLDRV_CONFIG
- DB 1
- DB CONFIG_DONT_CARE
- DB PSO_TBLDRV_MR0_WR
- DB 2
- DB RegValOfTcl
- DB MR0WR
-ENDM
-
-TBLDRV_OVERRIDE_RC10_OPSPEED MACRO Frequency:REQ, MR10OPSPEED:REQ
- DB PSO_TBLDRV_CONFIG
- DB 1
- DB CONFIG_DONT_CARE
- DB PSO_TBLDRV_RC10_OPSPEED
- DB 5
- DD Frequency
- DB MR10OPSPEED
-ENDM
-
-TBLDRV_CONFIG_ENTRY_LRDMM_IBT MACRO F0RC8:REQ, F1RC0:REQ, F1RC1:REQ, F1RC2:REQ
- DB PSO_TBLDRV_LRDIMM_IBT
- DB 4
- DB F0RC8
- DB F1RC0
- DB F1RC1
- DB F1RC2
-ENDM
-
-TBLDRV_CONFIG_ENTRY_2D_TRAINING MACRO Training2dMode:REQ
- DB PSO_TBLDRV_2D_TRAINING
- DB 1
- DB Training2dMode
-ENDM
-
-;
-; Macros for removing entries
-;
-INVALID_CONFIG_FLAG EQU 8000h
-
-TBLDRV_INVALID_CONFIG MACRO
- DB PSO_TBLDRV_INVALID_TYPE
- DB 0
-ENDM
-; *****************************************************************************************
-; *
-; * END OF TABLE DRIVEN OVERRIDE MACROS
-; *
-; ***************************************************************************************** \ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/arch2008.asm b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/arch2008.asm
deleted file mode 100644
index a3932c19c1..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/arch2008.asm
+++ /dev/null
@@ -1,2676 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; Workfile: arch2008.asm $Revision: 84150 $ $Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
-;
-; Description: ARCH2008.ASM - AGESA Architecture 2008 Wrapper Template
-;
-;*****************************************************************************
-;
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*****************************************************************************
-
- .XLIST
- INCLUDE agesa.inc
- INCLUDE acwrapg.inc ; Necessary support file as part of wrapper, including but not limited to segment start/end macros.
- INCLUDE acwrap.inc ; IBVs may specify host BIOS-specific include files required when building.
- INCLUDE cpcarmac.inc
- INCLUDE bridge32.inc
- .LIST
- .586p
- .mmx
-
-
-;----------------------------------------------------------------------------
-; Local definitions
-;----------------------------------------------------------------------------
-
-sOemCallout STRUCT
- FuncName DD ? ; Call out function name
- FuncPtr DW ? ; Call out function pointer
-sOemCallout ENDS
-
-sOemEventHandler STRUCT
- ClassCode DD ? ; AGESA event log sub-class code
- FuncPtr DW ? ; Event handler function pointer
-sOemEventHandler ENDS
-
-;; A typical legacy BIOS implementation may require the E000 and F000 segments
-;; to be cached.
-EXE_CACHE_REGION_BASE_0 EQU 0E0000h
-EXE_CACHE_REGION_SIZE_0 EQU 20000h
-
-;; In this sample implementation, the B1 and B2 images are placed next to each
-;; other in the BIOS ROM to help with the maximization of cached code.
-EXE_CACHE_REGION_BASE_1 EQU AGESA_B1_ADDRESS
-EXE_CACHE_REGION_SIZE_1 EQU 40000h
-
-;; The third region is not needed in our example.
-EXE_CACHE_REGION_BASE_2 EQU 0
-EXE_CACHE_REGION_SIZE_2 EQU 0
-
-
-;----------------------------------------------------------------------------
-; PERSISTENT SEGMENT
-; This segment is required to be present throughout all BIOS execution.
-;----------------------------------------------------------------------------
-
-AMD_PERSISTENT_START
-
-
-;----------------------------------------------------------------------------
-; Instantiate the global descriptor table
-;----------------------------------------------------------------------------
-
-AMD_BRIDGE_32_GDT AMD_GDT ; Instantiate the global descriptor table
- ; required by the push-high mechanism.
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the persistent segment
-;----------------------------------------------------------------------------
-
-;+-------------------------------------------------------------------------
-;
-; AmdDfltRet
-;
-; Entry:
-; None
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Near stub procedure. Simply perform a retn instruction.
-;
-EXTERN AmdDfltRet:NEAR
-
-
-;+-------------------------------------------------------------------------
-;
-; AmdDfltRetFar
-;
-; Entry:
-; None
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Far stub procedure. Simply perform a retf instruction.
-;
-EXTERN AmdDfltRetFar:FAR
-
-
-;----------------------------------------------------------------------------
-; Declare the optional external routines in the persistent segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myModuleTypeMismatchHandler (Example)
-;
-; Entry:
-; ESI - Pointer to the EVENT_PARAMS structure of the failure.
-; [ESI].DataParam1 - Socket
-; [ESI].DataParam2 - DCT
-; [ESI].DataParam3 - Channel
-; [ESI].DataParam4 - 0x00000000
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure can be used to react to a memory module type
-; mismatch error discovered by the AGESA code. Actions taken
-; may include, but are not limited to:
-; Logging the event to NV for display later
-; Reset, excluding the mismatch on subsequent reboot
-; Do nothing
-;
-; Dependencies:
-; None
-;
-EXTERN myModuleTypeMismatchHandler(AmdDfltRet):NEAR
-
-;+---------------------------------------------------------------------------
-;
-; oemPlatformConfigInit (Optional)
-;
-; Entry:
-; EDI - 32-bit flat pointer to the PLATFORM_CONFIGURATION to be
-; passed in to the next AGESA entry point.
-;
-; typedef struct {
-; IN PERFORMANCE_PROFILE PlatformProfile;
-; IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList;
-; IN UINT8 CoreLevelingMode;
-; IN PLATFORM_C1E_MODES C1eMode;
-; IN UINT32 C1ePlatformData;
-; IN UINT32 C1ePlatformData1;
-; IN UINT32 C1ePlatformData2;
-; IN UINT32 C1ePlatformData3;
-; IN BOOLEAN UserOptionDmi;
-; IN BOOLEAN UserOptionPState;
-; IN BOOLEAN UserOptionSrat;
-; IN BOOLEAN UserOptionSlit;
-; IN BOOLEAN UserOptionWhea;
-; IN UINT32 PowerCeiling;
-; IN BOOLEAN PstateIndependent;
-; } PLATFORM_CONFIGURATION;
-;
-; typedef struct {
-; IN UINT8 Socket;
-; IN UINT8 Link;
-; IN UINT8 LoFreq;
-; IN UINT8 HighFreq;
-; IN PLATFORM_DEEMPHASIS_LEVEL ReceiverDeemphasis;
-; IN PLATFORM_DEEMPHASIS_LEVEL DcvDeemphasis;
-; } CPU_HT_DEEMPHASIS_LEVEL;
-;
-; typedef struct {
-; IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode;
-; IN BOOLEAN UseHtAssist;
-; IN BOOLEAN UseAtmMode;
-; IN BOOLEAN UseNbrCache;
-; IN BOOLEAN Use32ByteRefresh;
-; IN BOOLEAN UseVariableMctIsocPriority;
-; } PERFORMANCE_PROFILE;
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Provide a single hook routine to modify the parameters of a
-; PLATFORM_CONFIGURATION structure before any entry point that
-; has such a structure as an input.
-;
-; Dependencies:
-; None
-;
-; Example:
-; If your platform is running in UMA mode, the following code
-; may be added:
-; mov (PLATFORM_CONFIGURATION PTR [edi]).PlatformProfile.PlatformControlFlowMode, UmaDr
-;
-EXTERN oemPlatformConfigInit(AmdDfltRetFar):FAR
-
-;+---------------------------------------------------------------------------
-;
-; oemCallout (Optional)
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The default call out router function which resides in the same
-; segment as the push-high bridge code.
-;
-; Dependencies:
-; None
-;
-EXTERN oemCallout(AmdDfltRet):NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the persistent segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdBridge32
-;
-; Entry:
-; EDX - A Real Mode FAR pointer using seg16:Offset16 format that
-; points to a local host environment call-out router. If
-; this pointer is not equal to zero, then this pointer is
-; used as the call-out router instead of the standard
-; OemCallout. This may be useful when the call-out router
-; is not located in the same segment as the AmdBridge32 and
-; AmdCallout16 routines.
-; ESI - A Flat Mode pointer (32-bit address) that points to the
-; configuration block (AMD_CONFIG_PARAMS) for the AGESA
-; software function.
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; Execute an AGESA software function through the Push-High interface.
-;
-; Dependencies:
-; This procedure requires a stack. The host environment must use the
-; provided service function to establish the stack environment prior
-; to making the call to this procedure.
-;
-AmdBridge32 PROC FAR PUBLIC
- AMD_BRIDGE_32 AMD_GDT ; use the macro for the body
- ret
-AmdBridge32 ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdEnableStack
-;
-; Entry:
-; BX - Return address
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; SS:ESP - Points to the private stack location for this processor core.
-; ECX - Upon success, contains this processor core's stack size in bytes.
-;
-; Modified:
-; EAX, ECX, EDX, EDI, ESI, ESP, DS, ES
-;
-; Purpose:
-; This procedure is used to establish the stack within the host environment.
-;
-; Dependencies:
-; The host environment must use this procedure and not rely on any other
-; sources to create the stack region.
-;
-AmdEnableStack PROC NEAR PUBLIC
- AMD_ENABLE_STACK
- ;; EAX = AGESA_SUCCESS, The stack space has been allocated for this core.
- ;; EAX = AGESA_WARNING, The stack has already been set up. SS:ESP is set
- ;; to stack top, and ECX is the stack size in bytes.
- jmp bx
-AmdEnableStack ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdDisableStack
-;
-; Entry:
-; BX - Return address
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; EAX, ECX, EDX, ESI, ESP
-;
-; Purpose:
-; This procedure is used to remove the pre-memory stack from within the
-; host environment.
-; The exit state for the BSP is described as follows:
-; Memory region 00000-9FFFF MTRRS are set as WB memory.
-; Processor Cache is enabled (CD bit is cleared).
-; MTRRs used for execution cache are kept.
-; Cache content is flushed (invalidated without write-back).
-; Any family-specific clean-up done.
-; The exit state for the APs is described as follows:
-; Memory region 00000-9FFFF MTRRS are set as WB memory.
-; Memory region A0000-DFFFF MTRRS are set as UC IO.
-; Memory region E0000-FFFFF MTRRS are set as UC memory.
-; MTRRs used for execution cache are cleared.
-; Processor Cache is disabled (CD bit is set).
-; Top-of-Memory (TOM) set to the system top of memory as determined
-; by the memory initialization routines.
-; System lock command is enabled.
-; Any family-specific clean-up done.
-;
-; Dependencies:
-; The host environment must use this procedure and not rely on any other
-; sources to break down the stack region.
-; If executing in 16-bit code, the host environment must establish the
-; "Big Real" mode of 32-bit addressing of data.
-;
-AmdDisableStack PROC NEAR PUBLIC
- AMD_DISABLE_STACK
- ;; EAX = AGESA_SUCCESS, The stack space has been disabled for this core.
- jmp bx
-AmdDisableStack ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCallout16
-;
-; Entry:
-; [esp+8] - Func
-; [esp+12] - Data
-; [esp+16] - Configuration Block
-; [esp+4] - Return address to AGESA
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; Execute callback from the push-high interface.
-;
-; Dependencies:
-; None
-;
-AmdCallout16 PROC FAR PUBLIC ; declare the procedure
- AMD_CALLOUT_16 oemCallout ; use the macro for the body
- ret
-AmdCallout16 ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdProcessAgesaErrors (Optional)
-;
-; Entry:
-; AL - Heap status of the AGESA entry point that was just invoked.
-; EBX - AGESA image base address.
-; EDX - Segment / Offset of the appropriate callout router function.
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure is used to handle any errors that may have occurred
-; during an AGESA entry point.
-;
-; Dependencies:
-; None
-;
-AmdProcessAgesaErrors PROC FAR PUBLIC
- LOCAL localCpuInterfaceBlock:EVENT_PARAMS
-
- pushad
- xor edi, edi
- mov di, ss
- shl edi, 4
- lea esi, localCpuInterfaceBlock
- add esi, edi
-
- ; Fill default config block
- mov (EVENT_PARAMS PTR [esi]).StdHeader.Func, AMD_READ_EVENT_LOG
- mov (EVENT_PARAMS PTR [esi]).StdHeader.ImageBasePtr, ebx
- mov (EVENT_PARAMS PTR [esi]).StdHeader.AltImageBasePtr, 0
- mov (EVENT_PARAMS PTR [esi]).StdHeader.HeapStatus, al
- mov edi, SEG AmdCallout16
- shl edi, 4
- add edi, OFFSET AmdCallout16
- mov (EVENT_PARAMS PTR [esi]).StdHeader.CalloutPtr, edi
-
- ; Flush the event log searching for, and handling all monitored events
- xor eax, eax
- .while (eax == 0)
- push edx
- call AmdBridge32
- pop edx
- .if (eax == AGESA_SUCCESS)
- mov eax, (EVENT_PARAMS PTR [esi]).EventInfo
- .if (eax != 0)
- lea di, cs:AgesaEventTable
-
-loopThruTable:
- cmp di, OFFSET cs:AgesaEventTableEnd
- jae unhandledEvent
-
- cmp eax, cs:[di].sOemEventHandler.ClassCode
- je FoundMatch
- add di, SIZEOF sOemEventHandler
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemEventHandler.FuncPtr
- call bx
-
-unhandledEvent:
- xor eax, eax
- .else
- mov al, 1
- .endif
- .endif
- .endw
- popad
- ret
-
-AmdProcessAgesaErrors ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the error handler table
-;----------------------------------------------------------------------------
-
-AgesaEventTable LABEL BYTE
- ;; Add entries as desired
- ;;---------
- ;; EXAMPLE
- ;;---------
- sOemEventHandler <MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, OFFSET myModuleTypeMismatchHandler>
-AgesaEventTableEnd LABEL BYTE
-
-
-AMD_PERSISTENT_END
-
-
-
-
-;----------------------------------------------------------------------------
-; RECOVERY SEGMENT
-; This segment resides in the classic 'boot-block,' and is used
-; for recovery.
-;----------------------------------------------------------------------------
-
-AMD_RECOVERY_START
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the recovery segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myReadSPDRecovery (Required for proper recovery mode operation)
-;
-; Entry:
-; ESI - Pointer to an AGESA_READ_SPD_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT8 SocketId;
-; IN UINT8 MemChannelId;
-; IN UINT8 DimmId;
-; IN OUT UINT8 *Buffer;
-; IN OUT MEM_DATA_STRUCT *MemData;
-; } AGESA_READ_SPD_PARAMS;
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS Indicates the SPD block for the indicated
-; DIMM was read successfully.
-; AGESA_BOUNDS_CHK The specified DIMM is not present.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function and no memory initialized.
-; AGESA_ERROR The DIMM SPD read process has generated
-; communication errors.
-;
-; Modified:
-; None
-;
-; Purpose:
-; This call out reads a block of memory SPD data and places it
-; into the provided buffer.
-;
-; Dependencies:
-; None
-;
-EXTERN myReadSPDRecovery:NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the recovery segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitResetWrapper
-;
-; Entry:
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; A minimal initialization of the processor core is performed. This
-; procedure must be called by all processor cores. The code path
-; separates the BSP from the APs and performs a separate and appropriate
-; list of tasks for each class of core.
-; For the BSP, the following actions are performed:
-; Internal heap sub-system initialization
-; Primary non-coherent HyperTransportT link initialization
-; Return to the host environment to test for Recovery Mode.
-; The AP processor cores do not participate in the recovery process.
-; However, they execute this routine after being released to execute
-; by the BSP during the main boot process. Their actions include the
-; following:
-; Internal heap sub-system initialization
-; Proceed to a wait loop waiting for commands from the BSP
-;
-; For the cache regions, up to three regions of execution cache can be
-; allocated following the following rules:
-; 1. Once a region is allocated, it cannot be de-allocated. However, it
-; can be expanded.
-; 2. At most, two of the three regions can be located above 1 MByte. A
-; region failing this rule is ignored.
-; 3. All region addresses must be at or above the 0x000D0000 linear
-; address. A region failing this rule is ignored.
-; 4. The address is aligned on a 32-KByte boundary. Starting addresses
-; is rounded down to the nearest 32-Kbyte boundary.
-; 5. The execution cache size must be a multiple of 32 KByte. Size is
-; rounded up to the next multiple of 32 KByte.
-; 6. A region must not span either the 1-MByte boundary or the 4-GByte
-; boundary. Allocated size is truncated to not span the boundary.
-; 7. The granted cached execution regions, address, and size are calculated
-; based on the available cache resources of the processor core.
-; Allocations are made up to the limit of cache available on the
-; installed processor.
-; Warning: Enabling instruction cache outside of this interface can cause
-; data corruption.
-;
-; Dependencies:
-; This procedure is expected to be executed soon after a system reset
-; for the main boot path or resume path of execution.
-;
-; This procedure requires a stack.
-;
-; Because the heap system is not yet operational at the point of the
-; interface call, the host environment must allocate the storage for
-; the AMD_RESET_PARAMS structure before making the first call to
-; AmdCreateStruct. This is the ByHost method of allocation.
-;
-AmdInitResetWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
- local localResetParams:AMD_RESET_PARAMS
-
- pushad
-
- ; Prepare for the call to initialize the input parameters for AmdInitReset
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B1_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- ; Use the 'ByHost' allocation method because the heap has not been initialized as of yet.
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RESET
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, ByHost
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, sizeof AMD_RESET_PARAMS
- lea edx, localResetParams
- add edx, eax
- push edx
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr, edx
- mov dx, SEG AmdCalloutRouterRecovery
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterRecovery
- push edx
- call AmdBridge32
- pop edx
- pop esi
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- ; Allocate the execution cache to maximize the amount of code in ROM that is cached.
- ; Placing the B1 and B2 images near one another is a good way to ensure the AGESA code
- ; is cached.
- mov (AMD_RESET_PARAMS ptr [esi]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_0
- mov (AMD_RESET_PARAMS ptr [esi]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_0
- mov (AMD_RESET_PARAMS ptr [esi + sizeof EXECUTION_CACHE_REGION]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_1
- mov (AMD_RESET_PARAMS ptr [esi + sizeof EXECUTION_CACHE_REGION]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_1
- mov (AMD_RESET_PARAMS ptr [esi + (2 * sizeof EXECUTION_CACHE_REGION)]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_2
- mov (AMD_RESET_PARAMS ptr [esi + (2 * sizeof EXECUTION_CACHE_REGION)]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_2
-
- ; Call in to the AmdInitReset entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS Early initialization completed successfully.
- ;; AGESA_WARNING One or more of the execution cache allocation
- ;; rules were violated, but an adjustment was made
- ;; and space was allocated.
- ;; AGESA_ERROR One or more of the execution cache allocation rules
- ;; were violated, which resulted in a requested cache
- ;; region to not be allocated.
- ;; The storage space allocated for the AMD_RESET_PARAMS
- ;; structure is insufficient.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_RESET_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B1_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
-
- ;; Here are what the MTRRs should look like based off of the CacheRegions specified above:
-
- ;; Fixed-Range MTRRs
- ;; Name Address Value
- ;; ---------------- -------- ----------------
- ;; MTRRfix4k_E0000 0000026C 0505050505050505
- ;; MTRRfix4k_E8000 0000026D 0505050505050505
- ;; MTRRfix4k_F0000 0000026E 0505050505050505
- ;; MTRRfix4k_F8000 0000026F 0505050505050505
- ;; MTRRdefType 000002FF 0000000000000C00
- ;;
- ;; Variable-Range MTRRs and IO Range
- ;; MTRRphysBase(n) MTRRphysMask(n)
- ;; ----------------- -----------------
- ;; n=0 0000000000000000 0000000000000000
- ;; n=1 0000000000000000 0000000000000000
- ;; n=2 0000000000000000 0000000000000000
- ;; n=3 0000000000000000 0000000000000000
- ;; n=4 0000000000000000 0000000000000000
- ;; n=5 Heap Base (Varies by core) 0000FFFFFFFF0800
- ;; n=6 AGESA_B1_ADDRESS | 6 0000FFFFFFFC0800
- ;; n=7 0000000000000000 0000000000000000
-
-
- ;; Because the allocation method is 'ByHost,' the call to AMD_RELEASE_STRUCT is
- ;; not necessary. Stack space reclamation is left up to the host BIOS.
-
- popad
- ret
-
-
-AmdInitResetWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitRecoveryWrapper
-;
-; Entry:
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Perform a minimum initialization of the processor and memory to
-; support a recovery mode flash ROM update.
-; For the BSP, the following actions are performed:
-; Configuration of CPU core for recovery process
-; Minimal initialization of some memory
-; The AP processor cores do not participate in the recovery process.
-; No actions or tasks are performed by the AP cores for this time point.
-;
-; Dependencies:
-; This procedure requires a stack. The host environment must use one of
-; the provided service functions to establish the stack environment prior
-; to making the call to this procedure.
-;
-AmdInitRecoveryWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitRecovery
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B1_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RECOVERY
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterRecovery
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterRecovery
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
-
- ; Call in to the AmdInitRecovery entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_WARNING One or more of the allocation rules were violated,
- ;; but an adjustment was made and space was allocated.
- ;; AGESA_ERROR One or more of the allocation rules were violated,
- ;; which resulted in a requested cache region to not be
- ;; allocated.
- ;; AGESA_FATAL No memory was found in the system.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_RECOVERY_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B1_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitRecovery
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-AmdInitRecoveryWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCalloutRouterRecovery
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The call out router function for AmdInitReset and
-; AmdInitRecovery.
-;
-; Dependencies:
-; None
-;
-AmdCalloutRouterRecovery PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
- xor ax, ax
- mov ds, ax
- mov es, ax
- lea di, cs:CalloutRouterTableRecovery
- mov eax, AGESA_UNSUPPORTED
-
-loopThruTable:
- cmp di, OFFSET cs:CalloutRouterTableRecoveryEnd
- jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
- cmp ecx, cs:[di].sOemCallout.FuncName
- je FoundMatch
- add di, SIZEOF sOemCallout
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemCallout.FuncPtr
- call bx
-
-amdCpuCalloutExit:
- ret
-AmdCalloutRouterRecovery ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the callout dispatch table for the recovery segment
-;----------------------------------------------------------------------------
-
-CalloutRouterTableRecovery LABEL BYTE
- ;; Standard B1 implementations only need the SPD reader call out function to be implemented.
- sOemCallout <AGESA_READ_SPD, OFFSET myReadSPDRecovery>
-CalloutRouterTableRecoveryEnd LABEL BYTE
-
-
-AMD_RECOVERY_END
-
-
-
-;----------------------------------------------------------------------------
-; PRE-MEMORY SEGMENT
-; This segment must be uncompressed in the ROM image.
-;----------------------------------------------------------------------------
-
-AMD_PREMEM_START
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the recovery segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myReadSPDPremem (Required)
-;
-; Entry:
-; ESI - Pointer to an AGESA_READ_SPD_PARAMS structure
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT8 SocketId;
-; IN UINT8 MemChannelId;
-; IN UINT8 DimmId;
-; IN OUT UINT8 *Buffer;
-; IN OUT MEM_DATA_STRUCT *MemData;
-; } AGESA_READ_SPD_PARAMS;
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS Indicates the SPD block for the indicated
-; DIMM was read successfully.
-; AGESA_BOUNDS_CHK The specified DIMM is not present.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function and no memory initialized.
-; AGESA_ERROR The DIMM SPD read process has generated
-; communication errors.
-;
-; Modified:
-; None
-;
-; Purpose:
-; This call out reads a block of memory SPD data and places it
-; into the provided buffer.
-;
-; Dependencies:
-; None
-;
-EXTERN myReadSPDPremem:NEAR
-
-;+-------------------------------------------------------------------------
-;
-; AmdDfltRetPremem
-;
-; Entry:
-; None
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Near stub procedure in the prememory segment. Simply perform a
-; retn instruction.
-;
-EXTERN AmdDfltRetPremem:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myDoReset (Required)
-;
-; Entry:
-; EDX - Reset type
-; 1 - Warm reset whenever
-; 2 - Cold reset whenever
-; 3 - Warm reset immediately
-; 4 - Cold reset immediately
-; ESI - Pointer to an AMD_CONFIG_PARAMS structure.
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function.
-;
-; Modified:
-; None
-;
-; Purpose:
-; This host environment function must initiate the specified type
-; of system reset.
-;
-; Implementation of this function by the host environment is
-; REQUIRED. Some host environments may record this as a request
-; allowing other elements in the system to perform some additional
-; tasks before the actual reset is issued.
-;
-; Dependencies:
-; The AMD processor contains 3 bits (BiosRstDet[2:0]) in a PCI
-; register (F0x6C Link Initialization Control Register) that
-; indicate the reset status. These bits are reserved for use by
-; the AGESA software and should not be modified by the host
-; environment.
-;
-EXTERN myDoReset:NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myGetNonVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; None
-;
-; Exit:
-; EBX - Pointer to the non-volatile S3 context block
-; ECX - Size in bytes of the non-volatile S3 context block
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must return the pointer to the data
-; saved during the mySaveNonVolatileS3Context routine.
-;
-; Dependencies:
-; None
-;
-EXTERN myGetNonVolatileS3Context:NEAR
-
-
-;----------------------------------------------------------------------------
-; Declare the optional external routines in the prememory segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myAgesaHookBeforeExitSelfRefresh (Optional)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 44h
-; ESI - Pointer to a data structure containing the memory information
-;
-; Exit:
-; After returning control to AGESA, AGESA will display: - AGESA_TESTPOINT - 45h
-; EAX - Contains the AGESA_STATUS return code
-; AGESA_SUCCESS The function has completed successfully
-; AGESA_UNSUPPORTED This function is not implemented by the host environment
-; AGESA_WARNING A non-critical issue has occued in the host environment
-;
-; Modified:
-; None
-;
-; Purpose:
-; General purpose hook called before the exiting self refresh
-; This procedure is called once per channel
-;
-; Implementation of this function is optional for the host environment
-; This call-out is an opportunity for the host environment to make dynamic
-; modifications to the memory timing settings specific to the board or host
-; environment before exiting self refresh on S3 resume
-;
-; Dependencies:
-; This procedure is called before the exit self refresh bit is set in the resume
-; sequence. The host environment must initiate the OS restart process. This procedure
-; requires a stack. The host environment must establish the stack environment prior
-; to making the call to this procedure
-;
-EXTERN myAgesaHookBeforeExitSelfRefresh(AmdDfltRetPremem):NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myHookBeforeDramInit (Optional)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 40h
-; ESI - Pointer to a data structure containing the memory information
-;
-; Exit:
-; After returning control to AGESA, AGESA will display - AGESA_TESTPOINT - 41h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This function is not implemented by the host environment
-;
-; Modified:
-; None
-;
-; Purpose:
-; General-purpose hook called before the DRAM_Init bit is set. Called
-; once per MCT
-;
-; Implementation of this function is optional for the host environment
-; This call-out is an opportunity for the host environment to make
-; dynamic modifications to the memory timing settings specific to the
-; board or host environment
-;
-; Dependencies:
-; None
-;
-EXTERN myHookBeforeDramInit(AmdDfltRetPremem):NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myHookBeforeDQSTraining (Optional)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 42h
-; ESI - Pointer to a data structure containing the memory information.
-;
-; Exit:
-; After returning control to AGESA, AGESA will display - AGESA_TESTPOINT - 43h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This function is not implemented by the
-; host environment.
-;
-; Modified:
-; None
-;
-; Purpose:
-; General-purpose hook called just before the memory training processes
-; begin. Called once per MCT.
-;
-; Implementation of this function is optional for the host environment.
-; This call-out is an opportunity for the host environment to make
-; dynamic modifications to the memory timing settings specific to the
-; board or host environment.
-;
-; The host environment may also use this call-out for some board-
-; specific features that should be activated at this time point,
-; such as:
-; Low voltage DIMMs-the host environment should set the recommended
-; voltages found in the memory data structure for each memory
-; channel. This needs to occur before training begins.
-;
-; Dependencies:
-; None
-;
-EXTERN myHookBeforeDQSTraining(AmdDfltRetPremem):NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the prememory segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitEarlyWrapper
-;
-; Entry:
-; On Entry to "AmdInitEarly" AGESA will display AGESA_TESTPOINT - C4h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitEarly" AGESA will display AGESA_TESTPOINT - C5h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; A full initialization of the processor is performed. Action details
-; differ for the BSP and AP processor cores.
-; For the BSP, the following actions are performed:
-; Full HyperTransportT link initialization, coherent and non-coherent
-; Processor register loading
-; Microcode patch load
-; Errata workaround processing
-; Launch all processor cores
-; Configure the processor power management capabilities
-; Request a warm reset if needed
-; For the AP, the following actions are performed:
-; Processor register loading
-; Microcode patch load
-; Errata workaround processing
-; Configure the processor power management capabilities
-;
-; Dependencies:
-; This procedure is expected to be called before main memory initialization
-; and before the system warm reset. Prior to this, the basic configuration
-; done by the AmdInitReset routine must be completed.
-;
-; This procedure requires a stack. The host environment must use one of the
-; provided service functions to establish the stack environment prior to
-; making the call to this procedure.
-;
-; The processes performed at this time point require communication between
-; processor cores.
-;
-; The host environment must recognize that all processor cores are running
-; in parallel and avoid activities that might interfere with the core-to-core
-; communication, such as modifying the MTRR settings or writing to the APIC
-; registers.
-;
-AmdInitEarlyWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitEarly
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_EARLY
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPremem
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPremem
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + (3 * (SIZEOF EXECUTION_CACHE_REGION)))
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitEarly entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ALERT An HyperTransportT link CRC error was observed.
- ;; AGESA_WARNING One of more of the allocation rules were violated,
- ;; but an adjustment was made and space was allocated.
- ;; Or a HyperTransport device does not have the expected
- ;; capabilities, or unusable redundant HyperTransport
- ;; links were found.
- ;; AGESA_ERROR One or more of the allocation rules were violated, which
- ;; resulted in a requested cache region to not be allocated.
- ;; Or, a HyperTransport device failed to initialize.
- ;; AGESA_CRITICAL An illegal or unsupported mixture of processor types was
- ;; found, or the processors installed were found to have an
- ;; insufficient MP capability rating for this platform.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_EARLY_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitEarly
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitEarlyWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitPostWrapper
-;
-; Entry:
-; On Entry to "AmdInitPost" AGESA will display AGESA_TESTPOINT - C6h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitPost" AGESA will display AGESA_TESTPOINT - C7h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The main system memory is located, initialized, and brought on-line.
-; The processor(s) are prepared for full operation and control by the
-; host environment. Action details differ for the BSP and AP processor
-; cores.
-; For the BSP, the following actions are performed:
-; Full memory initialization and configuration. BSP is the master for
-; this process and may delegate some tasks to APs.
-; AP collection of data for use later.
-; Transfer the HOBs including the artifact data out of the pre-memory
-; cache storage into a temporary holding buffer in the main memory.
-; Check the BIST status of the BSP
-; Shut down the APs.
-; Prepare for the host environment to begin main boot activity.
-; Disable the pre-memory stack.
-; For the APs, the following actions are performed:
-; Report core identity information.
-; Execute indicated memory initialization processes as directed.
-; Check the BIST status of the AP
-; Disable the pre-memory stack.
-; Prepare to halt, giving control to host environment.
-; The entire range of system memory is enabled for Write-Back cache.
-; The fixed MTRRs and the variable MTRRs[7:6] are not changed in order
-; to leave in place any flash ROM region currently set for Write-Protect
-; execution cache.
-;
-; Dependencies:
-; This procedure is called after the host environment has determined that
-; a normal boot to operating system should be performed after any system
-; warm reset is completed and after the configuration done by AmdInitEarly
-; has completed.
-;
-; This procedure requires a stack. The host environment must use one of the
-; provided service functions to establish the stack environment prior to
-; making the call to this procedure.
-;
-; The processes performed at this time point require communication between
-; processor cores. The host environment must recognize that all processor
-; cores are running in parallel and avoid activities that might interfere
-; with the core-to-core communication, such as modifying the MTRR settings
-; or writing to the APIC registers.
-;
-AmdInitPostWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitPost
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_POST
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPremem
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPremem
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitPost entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ALERT A BIST error was found on one of the cores.
- ;; AGESA_WARNING HT Assist feature is running sub-optimally.
- ;; AGESA_FATAL Memory initialization failed.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_POST_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitPost
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitPostWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitResumeWrapper
-;
-; Entry:
-; On Entry to "AmdInitResume" AGESA will display AGESA_TESTPOINT - D0h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitResume" AGESA will display AGESA_TESTPOINT - D1h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure initializes or re-initializes the silicon components
-; for the resume boot path. For the processor, main memory is brought
-; out of self-refresh mode. This procedure will use the context data
-; in the NvStorage area of the input structure to re-start the main
-; memory. The host environment must fill the AMD_S3_PARAMS NvStorage
-; and VolatileStorage pointers and related size elements to describe
-; the location of the context data. Note that for this procedure, the
-; two data areas do not need to be contained in one buffer zone, they
-; can be anywhere in the accessible memory address space. If the host
-; environment uses a non-volatile storage device accessed on the system
-; address bus such as flashROM, then the context data does not need to
-; be moved prior to this call. If the host environment uses a non-
-; volatile storage device not located on the system address bus (e.g.
-; CMOS or SSEPROM) then the host environment must transfer the context
-; data to a buffer in main memory prior to calling this procedure.
-;
-; Dependencies:
-; The host environment must have determined that the system should take
-; the resume path prior to calling this procedure. The configuration
-; done by AmdInitEarly and any necessary warm reset must be complete.
-; After this procedure, execution proceeds to general system restoration.
-;
-; This procedure requires a stack. The host environment must use one of
-; the provided service functions to establish the stack environment prior
-; to making the call to this procedure.
-;
-AmdInitResumeWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitResume
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RESUME
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPremem
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPremem
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
- call oemPlatformConfigInit
-
- call myGetNonVolatileS3Context
- mov (AMD_RESUME_PARAMS ptr [esi]).S3DataBlock.NvStorage, ebx
- mov (AMD_RESUME_PARAMS ptr [esi]).S3DataBlock.NvStorageSize, ecx
-
- ; Call in to the AmdInitResume entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS Re-initialization has been completed successfully.
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_RESUME_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
-
- ; Allow AGESA to free the space used by AmdInitResume
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitResumeWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCalloutRouterPremem
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The call out router function for AmdInitEarly,
-; AmdInitPost, and AmdInitResume.
-;
-; Dependencies:
-; None
-;
-AmdCalloutRouterPremem PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
- xor ax, ax
- mov ds, ax
- mov es, ax
- lea di, cs:CalloutRouterTablePremem
- mov eax, AGESA_UNSUPPORTED
-
-loopThruTable:
- cmp di, OFFSET cs:CalloutRouterTablePrememEnd
- jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
- cmp ecx, cs:[di].sOemCallout.FuncName
- je FoundMatch
- add di, SIZEOF sOemCallout
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemCallout.FuncPtr
- call bx
-
-amdCpuCalloutExit:
- ret
-AmdCalloutRouterPremem ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the callout dispatch table for the prememory segment
-;----------------------------------------------------------------------------
-
-CalloutRouterTablePremem LABEL BYTE
- ;; Add entries as desired.
- sOemCallout <AGESA_READ_SPD, OFFSET myReadSPDPremem>
- sOemCallout <AGESA_HOOKBEFORE_DRAM_INIT, OFFSET myHookBeforeDramInit>
- sOemCallout <AGESA_HOOKBEFORE_DQS_TRAINING, OFFSET myHookBeforeDQSTraining>
- sOemCallout <AGESA_HOOKBEFORE_EXIT_SELF_REF, OFFSET myAgesaHookBeforeExitSelfRefresh>
- sOemCallout <AGESA_DO_RESET, OFFSET myDoReset>
- sOemCallout <AGESA_EXTERNAL_2D_TRAIN_VREF_CHANGE, OFFSET my2DTrainVrefChange>
-CalloutRouterTablePrememEnd LABEL BYTE
-
-
-
-AMD_PREMEM_END
-
-
-;----------------------------------------------------------------------------
-; POST SEGMENT
-; This segment may be decompressed and run from system RAM.
-;----------------------------------------------------------------------------
-
-AMD_POST_START
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the POST segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myAllocateBuffer (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E2h
-; ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 BufferLength;
-; IN UINT32 BufferHandle;
-; OUT VOID *BufferPointer;
-; } AGESA_BUFFER_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E3h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The requested size of memory has been
-; successfully allocated.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function.
-; AGESA_ERROR Less than the requested amount of memory
-; was allocated.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of memory allocation.
-; This function must allocate a buffer of the requested size or
-; larger. This function is required to be implemented by the host
-; environment.
-;
-; Dependencies:
-; The following call-outs must work together in the host system.
-; Parameters of the same name have the same function and must be
-; treated the same in each function:
-; AgesaAllocateBuffer
-; AgesaDeallocateBuffer
-; AgesaLocateBuffer
-; AgesaRunFcnOnAp
-; The host environment may need to reserve a location in the buffer
-; to store any host environment specific value(s). The returned
-; pointer must not include this reserved space. The host environment
-; on the AgesaDeallocateBuffer call needs to account for the reserved
-; space. This reserved space may be an identifier or the "handle"
-; used to identify the specific memory block.
-;
-EXTERN myAllocateBuffer:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myDeallocateBuffer (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E4h
-; ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 BufferLength;
-; IN UINT32 BufferHandle;
-; OUT VOID *BufferPointer;
-; } AGESA_BUFFER_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E5h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_BOUNDS_CHK The BufferHandle is invalid. The AGESA
-; software continues with its function.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of memory allocation.
-; This function releases a valid working buffer. This function is
-; required for the host environment to implement.
-;
-; Dependencies:
-; The following call-outs must work together in the host system.
-; Parameters of the same name have the same function and must be
-; treated the same in each function:
-; AgesaAllocateBuffer
-; AgesaDeallocateBuffer
-; AgesaLocateBuffer
-; AgesaRunFcnOnAp
-;
-EXTERN myDeallocateBuffer:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myLocateBuffer (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E6h
-; ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 BufferLength;
-; IN UINT32 BufferHandle;
-; OUT VOID *BufferPointer;
-; } AGESA_BUFFER_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E7h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_BOUNDS_CHK The presented handle is invalid or the
-; buffer could not be located.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of memory allocation.
-; This function must locate the buffer related to the indicated
-; handle and return the address of the buffer and its length.
-; This function is required to be implemented in the host
-; environment.
-;
-; Dependencies:
-; The following call-outs must work together in the host system.
-; Parameters of the same name have the same function and must be
-; treated the same in each function:
-; AgesaAllocateBuffer
-; AgesaDeallocateBuffer
-; AgesaLocateBuffer
-; AgesaRunFcnOnAp
-;
-EXTERN myLocateBuffer:NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myRunFuncOnAp (Required)
-;
-; Entry:
-; EDX - Local APIC ID of the target core.
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must route execution to the target AP and
-; have that AP call the AmdLateRunApTaskWrapper routine defined
-; above.
-;
-; Dependencies:
-; None
-;
-EXTERN myRunFuncOnAp:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; mySaveNonVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; EBX - Pointer to the non-volatile S3 context block
-; ECX - Size in bytes of the non-volatile S3 context block
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must save the non-volatile data to an area
-; that will not lose context while in the ACPI S3 sleep state, but
-; cannot be placed in system RAM. This data will need to be
-; available during the call to AmdInitResume.
-;
-; Dependencies:
-; None
-;
-EXTERN mySaveNonVolatileS3Context:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; mySaveVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; EBX - Pointer to the volatile S3 context block
-; ECX - Size in bytes of the volatile S3 context block
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must save the volatile data to an area
-; that will not lose context while in the ACPI S3 sleep state.
-; This data will need to be available during the call to
-; AmdS3LateRestore.
-;
-; Dependencies:
-; None
-;
-EXTERN mySaveVolatileS3Context:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myGetVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; None
-;
-; Exit:
-; EBX - Pointer to the volatile S3 context block
-; ECX - Size in bytes of the volatile S3 context block
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must return the pointer to the data
-; saved during the mySaveVolatileS3Context routine.
-;
-; Dependencies:
-; None
-;
-EXTERN myGetVolatileS3Context:NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the POST segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitEnvWrapper
-;
-; Entry:
-; On Entry to "AmdInitEnv" AGESA will display AGESA_TESTPOINT - C8h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitEnv" AGESA will display AGESA_TESTPOINT - C9h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure uses the AgesaAllocateBuffer call-out to acquire
-; permanent buffer space for the UEFI Hand-Off Blocks (HOBs). This
-; is also known as, or includes, artifact data being used by the
-; AGESA software. Upon entry to this procedure, the data is being
-; held in a temporary memory location and it must be moved to a
-; location controlled and protected by the host environment.
-;
-; These actions are performed by the BSP. The APs are not assigned
-; any tasks at this time point.
-;
-; Dependencies:
-; This procedure must be called after full memory is initialized and
-; the host environment has taken control of main memory allocation.
-; This procedure should be called before the PCI enumeration takes
-; place and as soon as possible after the host environment memory
-; allocation sub-system has started.
-;
-; This procedure requires a stack. The host environment must use one
-; of the provided service functions to establish the stack environment
-; prior to making the call to this procedure.
-;
-AmdInitEnvWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitEnv
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_ENV
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitEnv entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ERROR The artifact data could not be found or the host
- ;; environment failed to allocate sufficient buffer space.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_ENV_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitEnv
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitEnvWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitMidWrapper
-;
-; Entry:
-; On Entry to "AmdInitMid" AGESA will display AGESA_TESTPOINT - CAh
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitMid" AGESA will display AGESA_TESTPOINT - CBh
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure call performs special configuration requirements for
-; the graphics display hardware.
-;
-; These actions are performed by the BSP. The APs are not assigned any
-; tasks at this time point.
-;
-; Dependencies:
-; This procedure must be called after PCI enumeration has allocated
-; resources, but before the video BIOS call is performed.
-;
-; This procedure requires a stack. The host environment must use one
-; of the provided service functions to establish the stack environment
-; prior to making the call to this procedure.
-;
-AmdInitMidWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitMid
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_MID
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitMid entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_MID_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitMid
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-
-AmdInitMidWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitLateWrapper
-;
-; Entry:
-; On Entry to "AmdInitLate" AGESA will display AGESA_TESTPOINT - CCh
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitLate" AGESA will display AGESA_TESTPOINT - CDh
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The main purpose of this function is to generate informational
-; data tables used by the operating system. The individual tables
-; can be selected for generation through the user selection entries
-; on the input parameters.
-;
-; This routine uses the Call-Out AgesaAllocateBuffer to allocate a
-; buffer of the proper size to contain the data.
-;
-; The code path separates the BSP from the APs and perform a separate
-; and appropriate list of tasks for each class of core.
-; For the BSP, the following actions are performed:
-; Allocate buffer space for the tables.
-; Generate the table contents.
-; Make sure that the CPU is in a known good power state before
-; proceeding to boot the OS.
-; For the APs, the following actions are performed:
-; Final register settings preparing for entry to OS.
-; Establish the final PState for entry to OS.
-;
-; Dependencies:
-; This routine is expected to be executed late in the boot sequence
-; after main memory has been initialized, after PCI enumeration has
-; completed, after the host environment ACPI sub-system has started,
-; after the host environment has taken control of the APs, but just
-; before the start of OS boot.
-;
-; The host environment must provide the required call-outs listed in
-; the "Required Call-Out Procedures" section of the AGESA interface
-; specification to provide the buffer space in main memory and execute
-; code on the APs. The host environment must register the created ACPI
-; table in the main ACPI pointer tables. This may require moving the
-; generated tables to another location in memory.
-;
-; This procedure requires a stack. The host environment must establish
-; the stack environment prior to making the call to this procedure.
-; Some functions depend upon the preservation of the heap data across
-; the shift from pre-memory environment to a post-memory environment.
-; If that data was not preserved, then those functions cannot complete
-; and an error is returned.
-;
-AmdInitLateWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitLate
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_LATE
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitLate entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ALERT
- ;; AGESA_ERROR The system could not allocate the needed amount of
- ;; buffer space; or could not locate the artifact data block in
- ;; memory. Likely cause: the host environment may not have preserved
- ;; the data properly.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_LATE_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- push es
- mov ax, SEG AmdAcpiSratPointer
- mov es, ax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiSrat
- mov es:AmdAcpiSratPointer, ebx
- mov eax, DWORD PTR [ebx + 4]
- mov es:AmdAcpiSratSize, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiSlit
- mov es:AmdAcpiSlitPointer, ebx
- mov eax, DWORD PTR [ebx + 4]
- mov es:AmdAcpiSlitSize, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiPState
- mov es:AmdAcpiSsdtPointer, ebx
- mov eax, DWORD PTR [ebx + 4]
- mov es:AmdAcpiSsdtSize, eax
-
- xor eax, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiWheaMce
- mov es:AmdAcpiWheaMcePointer, ebx
- mov ax, WORD PTR [ebx]
- mov es:AmdAcpiWheaMceSize, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiWheaMce
- mov es:AmdAcpiWheaCmcPointer, ebx
- mov ax, WORD PTR [ebx]
- mov es:AmdAcpiWheaCmcSize, eax
-
- mov eax, (AMD_LATE_PARAMS ptr [esi]).DmiTable
- mov es:AmdDmiInfoPointer, eax
- pop es
-
-
- ; Allow AGESA to free the space used by AmdInitLate
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-
-AmdInitLateWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdS3SaveWrapper
-;
-; Entry:
-; On Entry to "AmdS3Save" AGESA will display AGESA_TESTPOINT - CEh
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Entry to "AmdS3Save" AGESA will display AGESA_TESTPOINT - CFh
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure saves critical registers and/or configuration
-; information for preservation across a system suspend mode. All
-; actions needed to prepare the processor for suspend mode is
-; performed, however this procedure does NOT initiate the suspend
-; process. The host environment is expected to perform that duty.
-;
-; These actions are performed by the BSP. The APs are not assigned
-; any tasks at this time point.
-;
-; The initializer routine will NULL out the save area pointers and
-; sizes. This procedure will determine the size of storage needed
-; for all the processor context, and make a call out to the environment
-; for allocation of one buffer to store all of the data. Upon exit, the
-; pointers and sizes within the AMD_S3_PARAMS structure will be updated
-; with the appropriate addresses within the buffer that was allocated.
-; The host environment is expected to then transfer the data pointed to
-; by NvStorage to a non-volatile storage area, and the data pointed to
-; by VolatileStorage to either a non-volatile storage area or system
-; RAM that retains its content across suspend.
-;
-; Dependencies:
-; The host environment must initiate the suspend process.
-;
-; This procedure requires a stack. The host environment must establish
-; the stack environment prior to making the call to this procedure.
-;
-AmdS3SaveWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdS3Save
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_S3_SAVE
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
- call oemPlatformConfigInit
-
- ; Call in to the AmdS3Save entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS All suspend duties have been completed successfully.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_S3SAVE_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- mov ecx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.NvStorageSize
- .if (ecx != 0)
- mov ebx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.NvStorage
- call mySaveNonVolatileS3Context
- .endif
-
- mov ecx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.VolatileStorageSize
- .if (ecx != 0)
- mov ebx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.VolatileStorage
- call mySaveVolatileS3Context
- .endif
-
- ; Allow AGESA to free the space used by AmdS3Save
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-
-AmdS3SaveWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdS3LateRestoreWrapper
-;
-; Entry:
-; On Entry to "AmdS3LateRestore" AGESA will display AGESA_TESTPOINT - D2h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdS3LateRestore" AGESA will display AGESA_TESTPOINT - D3h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure restores the processor state, reloads critical
-; silicon component registers, and performs any re-initialization
-; required by the silicon. This procedure will use the context data
-; in the VolatileStorage area of the input structure to restore the
-; processor registers.
-;
-; The host environment must fill the AMD_S3_PARAMS NvStorage and
-; VolatileStorage pointers and related size elements to describe
-; the location of the context data. Note that for this procedure,
-; the two data areas do not need to be contained in one buffer zone,
-; they can be anywhere in the accessible memory address space. If
-; the host environment uses a non-volatile storage device accessed
-; on the system address bus such as flashROM, then the context data
-; does not need to be moved prior to this call. If the host
-; environment uses a non-volatile storage device not located on the
-; system address bus (e.g. CMOS or SSEPROM) then the host environment
-; must transfer the context data to a buffer in main memory prior to
-; calling this procedure.
-;
-; These actions are performed by the BSP. The APs are not assigned
-; any tasks at this time point.
-;
-; Dependencies:
-; This procedure is called late in the resume sequence, after the
-; PCI control space is restored and just before resuming operating
-; system execution.
-;
-; The host environment must initiate the OS restart process.
-;
-; This procedure requires a stack. The host environment must establish
-; the stack environment prior to making the call to this procedure.
-;
-AmdS3LateRestoreWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdS3LateRestore
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_S3LATE_RESTORE
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
- call oemPlatformConfigInit
-
- call myGetVolatileS3Context
- mov (AMD_S3LATE_PARAMS ptr [esi]).S3DataBlock.VolatileStorage, ebx
- mov (AMD_S3LATE_PARAMS ptr [esi]).S3DataBlock.VolatileStorageSize, ecx
-
- ; Call in to the AmdS3LateRestore entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS All resume processes have been completed successfully.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_S3LATE_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdS3LateRestore
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-AmdS3LateRestoreWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdLateRunApTaskWrapper
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - D4h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - D5h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This entry point is tightly connected with the "AgesaRunFcnOnAp"
-; call out. The AGESA software will call the call-out "AgesaRunFcnOnAp";
-; the host environment will then call this entry point to have the AP
-; execute the requested function. This is needed late in the Post and
-; Resume branches for running an AP task since the AGESA software has
-; relinquished control of the APs to the host environment.
-;
-; Dependencies:
-; The host environment must implement the"AgesaRunFcnOnAp" call-out
-; and route execution to the target AP.
-;
-AmdLateRunApTaskWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdLateRunApTask
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_LATE_RUN_AP_TASK
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- push es
- mov ax, SEG AmdRunCodeOnApDataPointer
- mov es, ax
- mov eax, es:AmdRunCodeOnApDataPointer
- mov (AP_EXE_PARAMS PTR [esi]).RelatedDataBlock, eax
- mov eax, es:AmdRunCodeOnApDataSize
- mov (AP_EXE_PARAMS PTR [esi]).RelatedBlockLength, eax
- mov eax, es:AmdRunCodeOnApFunction
- mov (AP_EXE_PARAMS PTR [esi]).FunctionNumber, eax
- pop es
-
- ; Call in to the AmdLateRunApTask dispatcher
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- push es
- mov bx, SEG AmdRunCodeOnApStatus
- mov es, bx
- mov es:AmdRunCodeOnApStatus, eax
- pop es
-
- ; Allow AGESA to free the space used by AmdLateRunApTask
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-
-AmdLateRunApTaskWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdRunFuncOnAp (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E8h
-; EDX - Local APIC ID of the target core.
-; ESI - Pointer to an AP_EXE_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 FunctionNumber;
-; IN VOID *RelatedDataBlock;
-; IN UINT32 RelatedDataBlockLength;
-; } AP_EXE_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E9h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This is a required function, so this value
-; being returned causes a critical error
-; response value from the AGESAT software
-; function and no memory initialized.
-; AGESA_WARNING The AP did not respond.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of AP task dispatching.
-; This function must cause the indicated function code to be executed
-; upon the specified Application Processor. This procedure must be
-; executed in 32-bit mode. This function is required to be implemented
-; in the host environment.
-;
-; Dependencies:
-; The host environment must route execution to the target AP and
-; have that AP call the"AmdLateRunApTask" entry point.
-;
-AmdRunFuncOnAp PROC NEAR PUBLIC
-
- push es
- mov ax, SEG AmdRunCodeOnApDataPointer
- mov es, ax
- mov eax, (AP_EXE_PARAMS PTR [esi]).RelatedDataBlock
- mov es:AmdRunCodeOnApDataPointer, eax
- mov eax, (AP_EXE_PARAMS PTR [esi]).RelatedBlockLength
- mov es:AmdRunCodeOnApDataSize, eax
- mov eax, (AP_EXE_PARAMS PTR [esi]).FunctionNumber
- mov es:AmdRunCodeOnApFunction, eax
- mov eax, AGESA_UNSUPPORTED
- mov es:AmdRunCodeOnApStatus, eax
- pop es
-
- call myRunFuncOnAp
-
- push es
- mov ax, SEG AmdRunCodeOnApStatus
- mov es, ax
- mov eax, es:AmdRunCodeOnApStatus
- pop es
- ret
-AmdRunFuncOnAp ENDP
-
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCalloutRouterPost
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The call out router function for AmdInitEnv,
-; AmdInitMid, AmdInitLate, AmdS3Save, and
-; AmdS3LateRestore.
-;
-; Dependencies:
-; None
-;
-AmdCalloutRouterPost PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
- xor ax, ax
- mov ds, ax
- mov es, ax
- lea di, cs:CalloutRouterTablePost
- mov eax, AGESA_UNSUPPORTED
-
-loopThruTable:
- cmp di, OFFSET cs:CalloutRouterTablePostEnd
- jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
- cmp ecx, cs:[di].sOemCallout.FuncName
- je FoundMatch
- add di, SIZEOF sOemCallout
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemCallout.FuncPtr
- call bx
-
-amdCpuCalloutExit:
- ret
-AmdCalloutRouterPost ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the callout dispatch table for the POST segment
-;----------------------------------------------------------------------------
-
-CalloutRouterTablePost LABEL BYTE
- ;; Add entries as desired.
- sOemCallout <AGESA_ALLOCATE_BUFFER, OFFSET myAllocateBuffer>
- sOemCallout <AGESA_DEALLOCATE_BUFFER, OFFSET myDeallocateBuffer>
- sOemCallout <AGESA_LOCATE_BUFFER, OFFSET myLocateBuffer>
- sOemCallout <AGESA_RUNFUNC_ONAP, OFFSET AmdRunFuncOnAp>
-CalloutRouterTablePostEnd LABEL BYTE
-
-AMD_POST_END
-
-
-;----------------------------------------------------------------------------
-; CPU DATA SEGMENT
-; This segment must be writable, and present at the time that
-; AmdInitLate is run.
-;----------------------------------------------------------------------------
-
-CPU_DATASEG_START
-
- ;; Data used to store pointers for later use by the host environment.
- PUBLIC AmdAcpiSratPointer
- PUBLIC AmdAcpiSratSize
- PUBLIC AmdAcpiSlitPointer
- PUBLIC AmdAcpiSlitSize
- PUBLIC AmdAcpiSsdtPointer
- PUBLIC AmdAcpiSsdtSize
- PUBLIC AmdAcpiWheaMcePointer
- PUBLIC AmdAcpiWheaMceSize
- PUBLIC AmdAcpiWheaCmcPointer
- PUBLIC AmdAcpiWheaCmcSize
- PUBLIC AmdDmiInfoPointer
- AmdAcpiSratPointer DWORD ?
- AmdAcpiSratSize DWORD ?
- AmdAcpiSlitPointer DWORD ?
- AmdAcpiSlitSize DWORD ?
- AmdAcpiSsdtPointer DWORD ?
- AmdAcpiSsdtSize DWORD ?
- AmdAcpiWheaMcePointer DWORD ?
- AmdAcpiWheaMceSize DWORD ?
- AmdAcpiWheaCmcPointer DWORD ?
- AmdAcpiWheaCmcSize DWORD ?
- AmdDmiInfoPointer DWORD ?
-
- ;; Data used for communication between the AP and the BSP.
- PUBLIC AmdRunCodeOnApDataPointer
- PUBLIC AmdRunCodeOnApDataSize
- PUBLIC AmdRunCodeOnApFunction
- PUBLIC AmdRunCodeOnApStatus
- AmdRunCodeOnApDataPointer DWORD ?
- AmdRunCodeOnApDataSize DWORD ?
- AmdRunCodeOnApFunction DWORD ?
- AmdRunCodeOnApStatus DWORD ?
-
-CPU_DATASEG_END
-
-
-END
diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/agesa.inc b/src/vendorcode/amd/agesa/f16kb/Legacy/agesa.inc
deleted file mode 100644
index 7683b15596..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Legacy/agesa.inc
+++ /dev/null
@@ -1,3300 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * Agesa structures and definitions
-; *
-; * Contains AMD AGESA core interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 85818 $ @e \$Date: 2013-01-11 17:04:21 -0600 (Fri, 11 Jan 2013) $
-;
-; ****************************************************************************
-; *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; *
-; **************************************************************************
-
-INCLUDE amd.inc
-UINT64 TEXTEQU <QWORD>
-UINT32 TEXTEQU <DWORD>
-UINT16 TEXTEQU <WORD>
-UINT8 TEXTEQU <BYTE>
-INT8 TEXTEQU <BYTE>
-CHAR8 TEXTEQU <BYTE>
-BOOLEAN TEXTEQU <BYTE>
-POINTER TEXTEQU <DWORD>
-
- ; AGESA Types and Definitions
-
-
-
- ; AGESA BASIC CALLOUTS
- AGESA_MEM_RELEASE EQU 00028000h
-
- ; AGESA ADVANCED CALLOUTS, Processor
- AGESA_CHECK_UMA EQU 00028100h
- AGESA_DO_RESET EQU 00028101h
- AGESA_ALLOCATE_BUFFER EQU 00028102h
- AGESA_DEALLOCATE_BUFFER EQU 00028103h
- AGESA_LOCATE_BUFFER EQU 00028104h
- AGESA_RUNFUNC_ONAP EQU 00028105h
-
- ; AGESA ADVANCED CALLOUTS, HyperTransport
-
- ; AGESA ADVANCED CALLOUTS, Memory
- AGESA_READ_SPD EQU 00028140h
- AGESA_HOOKBEFORE_DRAM_INIT EQU 00028141h
- AGESA_HOOKBEFORE_DQS_TRAINING EQU 00028142h
- AGESA_READ_SPD_RECOVERY EQU 00028143h
- AGESA_HOOKBEFORE_EXIT_SELF_REF EQU 00028144h
- AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY EQU 00028145h
- AGESA_EXTERNAL_2D_TRAIN_VREF_CHANGE EQU 00028146h
- AGESA_EXTERNAL_VOLTAGE_ADJUST EQU 00028147h
-
- ; AGESA IDS CALLOUTS
- AGESA_GET_IDS_INIT_DATA EQU 00028200h
-
- ; AGESA GNB CALLOUTS
- AGESA_GNB_PCIE_SLOT_RESET EQU 00028301h
- AGESA_GNB_GFX_GET_VBIOS_IMAGE EQU 00028302h
-
- ; AGESA FCH CALLOUTS
- AGESA_FCH_OEM_CALLOUT EQU 00028401h
-
-; ------------------------------------------------------------------------
-
- ; HyperTransport Interface
-
-
-
-; -----------------------------------------------------------------------------
- ; HT DEFINITIONS AND MACROS
-
-; -----------------------------------------------------------------------------
-
-
- ; Width equates for call backs
- HT_WIDTH_8_BITS EQU 8
- HT_WIDTH_16_BITS EQU 16
- HT_WIDTH_4_BITS EQU 4
- HT_WIDTH_2_BITS EQU 2
- HT_WIDTH_NO_LIMIT EQU HT_WIDTH_16_BITS
-
- ; Frequency Limit equates for call backs which take a frequency supported mask.
- HT_FREQUENCY_LIMIT_200M EQU 1
- HT_FREQUENCY_LIMIT_400M EQU 7
- HT_FREQUENCY_LIMIT_600M EQU 1Fh
- HT_FREQUENCY_LIMIT_800M EQU 3Fh
- HT_FREQUENCY_LIMIT_1000M EQU 7Fh
- HT_FREQUENCY_LIMIT_HT1_ONLY EQU 7Fh
- HT_FREQUENCY_LIMIT_1200M EQU 0FFh
- HT_FREQUENCY_LIMIT_1400M EQU 1FFh
- HT_FREQUENCY_LIMIT_1600M EQU 3FFh
- HT_FREQUENCY_LIMIT_1800M EQU 7FFh
- HT_FREQUENCY_LIMIT_2000M EQU 0FFFh
- HT_FREQUENCY_LIMIT_2200M EQU 1FFFh
- HT_FREQUENCY_LIMIT_2400M EQU 3FFFh
- HT_FREQUENCY_LIMIT_2600M EQU 7FFFh
- HT_FREQUENCY_LIMIT_2800M EQU 27FFFh
- HT_FREQUENCY_LIMIT_3000M EQU 67FFFh
- HT_FREQUENCY_LIMIT_3200M EQU 0E7FFFh
- HT_FREQUENCY_LIMIT_3600M EQU 1E7FFFh
- HT_FREQUENCY_LIMIT_MAX EQU HT_FREQUENCY_LIMIT_3600M
- HT_FREQUENCY_NO_LIMIT EQU 0FFFFFFFFh
-
- ; Unit ID Clumping special values
- HT_CLUMPING_DISABLE EQU 00000000h
- HT_CLUMPING_NO_LIMIT EQU 0FFFFFFFFh
-
- HT_LIST_TERMINAL EQU 0FFh
- HT_LIST_MATCH_ANY EQU 0FEh
- HT_LIST_MATCH_INTERNAL_LINK EQU 0FDh
-
- ; Event Notify definitions
-
- ; Event definitions.
-
- ; Coherent subfunction events
- HT_EVENT_COH_EVENTS EQU 10001000h
- HT_EVENT_COH_NO_TOPOLOGY EQU 10011000h
- HT_EVENT_COH_OBSOLETE000 EQU 10021000h
- HT_EVENT_COH_PROCESSOR_TYPE_MIX EQU 10031000h
- HT_EVENT_COH_NODE_DISCOVERED EQU 10041000h
- HT_EVENT_COH_MPCAP_MISMATCH EQU 10051000h
-
- ; Non-coherent subfunction events
- HT_EVENT_NCOH_EVENTS EQU 10002000h
- HT_EVENT_NCOH_BUID_EXCEED EQU 10012000h
- HT_EVENT_NCOH_OBSOLETE000 EQU 10022000h
- HT_EVENT_NCOH_BUS_MAX_EXCEED EQU 10032000h
- HT_EVENT_NCOH_CFG_MAP_EXCEED EQU 10042000h
- HT_EVENT_NCOH_DEVICE_FAILED EQU 10052000h
- HT_EVENT_NCOH_AUTO_DEPTH EQU 10062000h
-
- ; Optimization subfunction events
- HT_EVENT_OPT_EVENTS EQU 10003000h
- HT_EVENT_OPT_REQUIRED_CAP_RETRY EQU 10013000h
- HT_EVENT_OPT_REQUIRED_CAP_GEN3 EQU 10023000h
- HT_EVENT_OPT_UNUSED_LINKS EQU 10033000h
- HT_EVENT_OPT_LINK_PAIR_EXCEED EQU 10043000h
-
- ; HW Fault events
- HT_EVENT_HW_EVENTS EQU 10004000h
- HT_EVENT_HW_SYNCFLOOD EQU 10014000h
- HT_EVENT_HW_HTCRC EQU 10024000h
-
- ; The Recovery HT component uses 0x10005000 for events.
- ; For consistency, we avoid that range here.
-
- HT_MAX_NC_BUIDS EQU 32
-; ----------------------------------------------------------------------------
- ; HT TYPEDEFS, STRUCTURES, ENUMS
-
-; ----------------------------------------------------------------------------
-MATCHED EQU 0 ; < The link matches the requested customization.
-POWERED_OFF EQU 1 ; < Power the link off.
-UNMATCHED EQU 2 ; < The link should be processed according to normal defaults.
-MaxFinalLinkState EQU 3 ; < Not a final link state, use for limit checking.
-FINAL_LINK_STATE TEXTEQU <DWORD>
-
- ; Swap a device from its current id to a new one.
-
-BUID_SWAP_ITEM STRUCT
- FromId UINT8 ? ; < The device responding to FromId,
- ToId UINT8 ? ; < will be moved to ToId.
-BUID_SWAP_ITEM ENDS
-
-
- ; Each Non-coherent chain may have a list of device swaps. After performing the swaps,
- ; the final in order list of device ids is provided. (There can be more swaps than devices.)
- ; The unused entries in both are filled with 0xFF.
-
-BUID_SWAP_LIST STRUCT
- Swaps BUID_SWAP_ITEM (HT_MAX_NC_BUIDS) DUP ({}) ; < The BUID Swaps to perform
- FinalIds UINT8 (HT_MAX_NC_BUIDS) DUP (?) ; < The ordered final BUIDs, resulting from the swaps
-BUID_SWAP_LIST ENDS
-
-
- ; Control Manual Initialization of Non-Coherent Chains
-
- ; This interface is checked every time a non-coherent chain is
- ; processed. BUID assignment may be controlled explicitly on a
- ; non-coherent chain. Provide a swap list. Swaps controls the
- ; BUID assignment and FinalIds provides the device to device
- ; Linking. Device orientation can be detected automatically, or
- ; explicitly. See interface documentation for more details.
-
- ; If a manual swap list is not supplied,
- ; automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
- ; based on each device's unit count.
-
-MANUAL_BUID_SWAP_LIST STRUCT
- ; Match fields
- Socket UINT8 ? ; < The Socket on which this chain is located
- Link UINT8 ? ; < The Link on the host for this chain
- ; Override fields
- SwapList BUID_SWAP_LIST {} ; < The swap list
-MANUAL_BUID_SWAP_LIST ENDS
-
-
- ; Override options for DEVICE_CAP_OVERRIDE.
-
- ; Specify which override actions should be performed. For Checks, 1 means to check the item
- ; and 0 means to skip the check. For the override options, 1 means to apply the override and
- ; 0 means to ignore the override.
-
-DEVICE_CAP_OVERRIDE_OPTIONS STRUCT
- IsCheckDevVenId UINT32 ?
-; IN UINT32 IsCheckDevVenId:1; ; < Check Match on Device/Vendor id
-; IN UINT32 IsCheckRevision:1; ; < Check Match on device Revision
-; IN UINT32 IsOverrideWidthIn:1; ; < Override Width In
-; IN UINT32 IsOverrideWidthOut:1; ; < Override Width Out
-; IN UINT32 IsOverrideFreq:1; ; < Override Frequency
-; IN UINT32 IsOverrideClumping:1; ; < Override Clumping
-; IN UINT32 IsDoCallout:1; ; < Make the optional callout
-DEVICE_CAP_OVERRIDE_OPTIONS ENDS
-
- ; Override capabilities of a device.
-
- ; This interface is checked once for every Link on every IO device.
- ; Provide the width and frequency capability if needed for this device.
- ; This is used along with device capabilities, the limit interfaces, and northbridge
- ; limits to compute the default settings. The components of the device's PCI config
- ; address are provided, so its settings can be consulted if need be.
- ; The optional callout is a catch all.
-
-DEVICE_CAP_OVERRIDE STRUCT
- ; Match fields
- HostSocket UINT8 ? ; < The Socket on which this chain is located.
- HostLink UINT8 ? ; < The Link on the host for this chain.
- Depth UINT8 ? ; < The Depth in the I/O chain from the Host.
- DevVenId UINT32 ? ; < The Device's PCI Vendor + Device ID (offset 0x00).
- Revision UINT8 ? ; < The Device's PCI Revision field (offset 0x08).
- Link UINT8 ? ; < The Device's Link number (0 or 1).
- Options DEVICE_CAP_OVERRIDE_OPTIONS {} ; < The options for this device override.
- ; Override fields
- LinkWidthIn UINT8 ? ; < modify to change the Link Width In.
- LinkWidthOut UINT8 ? ; < modify to change the Link Width Out.
- FreqCap UINT32 ? ; < modify to change the Link's frequency capability.
- Clumping UINT32 ? ; < modify to change Unit ID clumping support.
- Callout CALLOUT_ENTRY ? ; < optional call for really complex cases, or NULL.
-DEVICE_CAP_OVERRIDE ENDS
-
- ; Callout param struct for override capabilities of a device.
-
- ; If the optional callout is implemented this param struct is passed to it.
-
-DEVICE_CAP_CALLOUT_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < The header
- ; Match fields
- HostSocket UINT8 ? ; < The Socket on which this chain is located.
- HostLink UINT8 ? ; < The Link on the host for this chain.
- Depth UINT8 ? ; < The Depth in the I/O chain from the Host.
- DevVenId UINT32 ? ; < The Device's PCI Vendor + Device ID (offset 0x00).
- Revision UINT8 ? ; < The Device's PCI Revision field (offset 0x08).
- Link UINT8 ? ; < The Device's Link number (0 or 1).
- PciAddress PCI_ADDR {} ; < The Device's PCI Address.
- ; Override fields
- LinkWidthIn POINTER ? ; < modify to change the Link Width In.
- LinkWidthOut POINTER ? ; < modify to change the Link Width Out.
- FreqCap POINTER ? ; < modify to change the Link's frequency capability.
- Clumping POINTER ? ; < modify to change Unit ID clumping support.
-DEVICE_CAP_CALLOUT_PARAMS ENDS
-
- ; Limits for CPU to CPU Links.
-
- ; For each coherent connection this interface is checked once.
- ; Provide the frequency and width if needed for this Link (usually based on board
- ; restriction). This is used with CPU device capabilities and northbridge limits
- ; to compute the default settings.
-
-CPU_TO_CPU_PCB_LIMITS STRUCT
- ; Match fields
- SocketA UINT8 ? ; < One Socket on which this Link is located
- LinkA UINT8 ? ; < The Link on this Node
- SocketB UINT8 ? ; < The other Socket on which this Link is located
- LinkB UINT8 ? ; < The Link on that Node
- ; Limit fields
- ABLinkWidthLimit UINT8 ? ; < modify to change the Link Width A->B
- BALinkWidthLimit UINT8 ? ; < modify to change the Link Width B-<A
- PcbFreqCap UINT32 ? ; < modify to change the Link's frequency capability
-CPU_TO_CPU_PCB_LIMITS ENDS
-
- ; Get limits for non-coherent Links.
-
- ; For each non-coherent connection this interface is checked once.
- ; Provide the frequency and width if needed for this Link (usually based on board
- ; restriction). This is used with device capabilities, device overrides, and northbridge limits
- ; to compute the default settings.
-
-IO_PCB_LIMITS STRUCT
- ; Match fields
- HostSocket UINT8 ? ; < The Socket on which this Link is located
- HostLink UINT8 ? ; < The Link about to be initialized
- Depth UINT8 ? ; < The Depth in the I/O chain from the Host
- ; Limit fields
- DownstreamLinkWidthLimit UINT8 ? ; < modify to change the Link Width going away from processor
- UpstreamLinkWidthLimit UINT8 ? ; < modify to change the Link Width moving toward processor
- PcbFreqCap UINT32 ? ; < modify to change the Link's frequency capability
-IO_PCB_LIMITS ENDS
-
- ; Manually control bus number assignment.
-
- ; This interface is checked every time a non-coherent chain is processed.
- ; If a system can not use the auto Bus numbering feature for non-coherent chain bus
- ; assignments, this interface can provide explicit control. For each chain, provide
- ; the bus number range to use.
-
-OVERRIDE_BUS_NUMBERS STRUCT
- ; Match fields
- Socket UINT8 ? ; < The Socket on which this chain is located
- Link UINT8 ? ; < The Link on the host for this chain
- ; Override fields
- SecBus UINT8 ? ; < Secondary Bus number for this non-coherent chain
- SubBus UINT8 ? ; < Subordinate Bus number
-OVERRIDE_BUS_NUMBERS ENDS
-
-
- ; Ignore a Link.
-
- ; This interface is checked every time a coherent Link is found and then every
- ; time a non-coherent Link from a CPU is found.
- ; Any coherent or non-coherent Link from a CPU can be ignored and not used
- ; for discovery or initialization. Useful for connection based systems.
- ; (Note: not checked for IO device to IO Device Links.)
-
-IGNORE_LINK STRUCT
- ; Match fields
- Socket UINT8 ? ; < The Socket on which this Link is located
- Link UINT8 ? ; < The Link about to be initialized
- ; Customization fields
- LinkState FINAL_LINK_STATE ? ; < The link may be left unitialized, or powered off.
-IGNORE_LINK ENDS
-
-
- ; Skip reganging of subLinks.
-
- ; This interface is checked whenever two subLinks are both connected to the same CPUs.
- ; Normally, unganged sublinks between the same two CPUs are reganged.
- ; Provide a matching structure to leave the Links unganged.
-
-SKIP_REGANG STRUCT
- ; Match fields
- SocketA UINT8 ? ; < One Socket on which this Link is located
- LinkA UINT8 ? ; < The Link on this Node
- SocketB UINT8 ? ; < The other Socket on which this Link is located
- LinkB UINT8 ? ; < The Link on that Node
- ; Customization fields
- LinkState FINAL_LINK_STATE ? ; < The paired sublink may be active, or powered off.
-SKIP_REGANG ENDS
-
- ; The System Socket layout, which sockets are physically connected.
-
- ; The hardware method for Socket naming is preferred. Use this software method only
- ; if required.
-
-SYSTEM_PHYSICAL_SOCKET_MAP STRUCT
- CurrentSocket UINT8 ? ; < The socket from which this connection originates.
- CurrentLink UINT8 ? ; < The Link from the source socket connects to another socket.
- TargetSocket UINT8 ? ; < The target socket which is connected on that link.
-SYSTEM_PHYSICAL_SOCKET_MAP ENDS
-
-; ----------------------------------------------------------------------------
-
- ; This is the input structure for AmdHtInitialize.
-
-AMD_HT_INTERFACE STRUCT
- ; Basic level customization
- AutoBusStart UINT8 ? ; < For automatic bus number assignment, starting bus number usually zero.
- AutoBusMax UINT8 ? ; < For automatic bus number assignment, do not assign above max.
- AutoBusIncrement UINT8 ? ; < For automatic bus number assignment, each chain gets this many busses.
-
- ; Advanced Level Customization
- ManualBuidSwapList POINTER ? ; < Provide Manual Swap List, if any.
- DeviceCapOverrideList POINTER ? ; < Provide Device Overrides, if any.
- CpuToCpuPcbLimitsList POINTER ? ; < Provide CPU PCB Limits, if any.
- IoPcbLimitsList POINTER ? ; < Provide IO PCB Limits, if any.
- OverrideBusNumbersList POINTER ? ; < Provide manual Bus Number assignment, if any.
- ; < Use either auto bus numbering or override bus
- ; < numbers, not both.
-
- IgnoreLinkList POINTER ? ; < Provide links to ignore, if any.
- SkipRegangList POINTER ? ; < Provide links to remain unganged, if any.
-
- ; Expert Level Customization
- Topolist POINTER ? ; < Use this topology list in addition to the built in, if not NULL.
- SystemPhysicalSocketMap POINTER ?
- ; < The hardware socket naming method is preferred,
- ; < If it can't be used, this provides a software method.
-AMD_HT_INTERFACE ENDS
-
-; -----------------------------------------------------------------------------
-
- ; HT Recovery Interface
-
-
-
-; -----------------------------------------------------------------------------
-; * HT Recovery DEFINITIONS AND MACROS
-; *
-; *-----------------------------------------------------------------------------
-;
-
- ; BBHT subfunction events
- HT_EVENT_BB_EVENTS EQU 10005000h
- HT_EVENT_BB_BUID_EXCEED EQU 10015000h
- HT_EVENT_BB_DEVICE_FAILED EQU 10055000h
- HT_EVENT_BB_AUTO_DEPTH EQU 10065000h
-
-; ----------------------------------------------------------------------------
-; * HT Recovery TYPEDEFS, STRUCTURES, ENUMS
-; *
-; *----------------------------------------------------------------------------
-;
-
-
- ; The Interface structure to Recovery HT.
-
-AMD_HT_RESET_INTERFACE STRUCT
- ManualBuidSwapList POINTER ? ; < Option to manually control SB link init
- Depth UINT32 ? ; < If auto init was used this is set to the depth of the chain,
- ; < else, for manual init unmodified.
-AMD_HT_RESET_INTERFACE ENDS
-
-
-;-----------------------------------------------------------------------------
-; FCH DEFINITIONS AND MACROS
-;
-;-----------------------------------------------------------------------------
-
-; Configuration values for SdConfig
- SdDisable EQU 0 ; Disabled
- SdAmda EQU 1 ; AMDA, set 24,18,16, default
- SdDma EQU 2 ; DMA clear 24, 16, set 18
- SdPio EQU 3 ; PIO clear 24,18,16
-SD_MODE TEXTEQU <DWORD>
-
-; Configuration values for SdClockControl
- Sd50MhzTraceCableLengthWithinSixInches EQU 4 ; 50Mhz, default
- Sd40MhzTraceCableLengthSix2ElevenInches EQU 6 ; 40Mhz
- Sd25MhzTraceCableLengthEleven2TwentyfourInches EQU 7 ; 25Mhz
-SD_CLOCK_CONTROL TEXTEQU <DWORD>
-
-; Configuration values for AzaliaController
- AzAuto EQU 0 ; Auto - Detect Azalia controller automatically
- AzDisable EQU 1 ; Diable - Disable Azalia controller
- AzEnable EQU 2 ; Enable - Enable Azalia controller
-HDA_CONFIG TEXTEQU <DWORD>
-
-; Configuration values for IrConfig
- IrDisable EQU 0 ; Disable
- IrRxTx0 EQU 1 ; Rx and Tx0
- IrRxTx1 EQU 2 ; Rx and Tx1
- IrRxTx0Tx1 EQU 3 ; Rx and both Tx0,Tx1
-IR_CONFIG TEXTEQU <DWORD>
-
-; Configuration values for SataClass
- SataNativeIde EQU 0 ; Native IDE mode
- SataRaid EQU 1 ; RAID mode
- SataAhci EQU 2 ; AHCI mode
- SataLegacyIde EQU 3 ; Legacy IDE mode
- SataIde2Ahci EQU 4 ; IDE->AHCI mode
- SataAhci7804 EQU 5 ; AHCI mode as 7804 ID (AMD driver)
- SataIde2Ahci7804 EQU 6 ; IDE->AHCI mode as 7804 ID (AMD driver)
-SATA_CLASS TEXTEQU <DWORD>
-
-; Configuration values for GppLinkConfig
- PortA4 EQU 0 ; 4:0:0:0
- PortA2B2 EQU 2 ; 2:2:0:0
- PortA2B1C1 EQU 3 ; 2:1:1:0
- PortA1B1C1D1 EQU 4 ; 1:1:1:1
-GPP_LINKMODE TEXTEQU <DWORD>
-
-; Configuration values for FchPowerFail
- AlwaysOff EQU 0 ; Always power off after power resumes
- AlwaysOn EQU 1 ; Always power on after power resumes
- UsePrevious EQU 3 ; Resume to same setting when power fails
-POWER_FAIL TEXTEQU <DWORD>
-
-; Configuration values for SATA Link Speed
- Gen1 EQU 1 ; SATA port GEN1 speed
- Gen2 EQU 2 ; SATA port GEN2 speed
- Gen3 EQU 3 ; SATA port GEN3 speed
-SATA_SPEED TEXTEQU <DWORD>
-
-; Configuration values for GPIO function
- Function0 EQU 0 ; GPIO Function 1
- Function1 EQU 1 ; GPIO Function 1
- Function2 EQU 2 ; GPIO Function 2
- Function3 EQU 3 ; GPIO Function 3
-GPIO_FUN TEXTEQU <DWORD>
-
-; Configuration values for GPIO_CFG
- OwnedByEc EQU 1 ; This bit can only be written by EC
- OwnedByHost EQU 2 ; This bit can only be written by host (BIOS)
- Sticky EQU 4 ; If set, [6:3] are sticky
- PullUpB EQU 8 ; 0: Pullup enable; 1: Pullup disabled
- PullDown EQU 16 ; 0: Pulldown disabled; 1: Pulldown enable
- GpioOutEnB EQU 32 ; 0: Output enable; 1: Output disable
- GpioOut EQU 64 ; Output state when GpioOutEnB is 0
- GpioIn EQU 128 ; This bit is read only - current pin state
-CFG_BYTE TEXTEQU <DWORD>
-
-; FCH GPIO CONTROL
-GPIO_CONTROL STRUCT
- GpioPin UINT8 ? ; Gpio Pin, valid range: 0-67, 128-150, 160-228
- PinFunction GPIO_FUN ? ; Multi-function selection
- CfgByte CFG_BYTE ? ; GPIO Register value
-GPIO_CONTROL ENDS
-
-; FCH SCI MAP CONTROL
-SCI_MAP_CONTROL STRUCT
- InputPin UINT8 ? ; Input Pin, valid range 0-63
- GpeMap UINT8 ? ; Gpe Map, valid range 0-31
-SCI_MAP_CONTROL ENDS
-
-; FCH SATA PHY CONTROL
-SATA_PHY_CONTROL STRUCT
- CommonPhy BOOLEAN ? ; Common PHY or not
- Gen SATA_SPEED ? ; SATA speed
- Port UINT8 ? ; Port number, valid range: 0-7
- PhyData UINT32 ? ; SATA PHY data, valid range: 0-0xFFFFFFFF
-SATA_PHY_CONTROL ENDS
-
-;
-; FCH Component Data Structure in InitReset stage
-;
-FCH_RESET_INTERFACE STRUCT
- UmiGen2 BOOLEAN ? ; Enable Gen2 data rate of UMI
- ; FALSE - Disable Gen2
- ; TRUE - Enable Gen2
-
- SataEnable BOOLEAN ? ; SATA controller function
- ; FALSE - SATA controller is disabled
- ; TRUE - SATA controller is enabled
-
- IdeEnable BOOLEAN ? ; SATA IDE controller mode enabled/disabled
- ; FALSE - IDE controller is disabled
- ; TRUE - IDE controller is enabled
-
- GppEnable BOOLEAN ? ; Master switch of GPP function
- ; FALSE - GPP disabled
- ; TRUE - GPP enabled
-
- Xhci0Enable BOOLEAN ? ; XHCI0 controller function
- ; FALSE - XHCI0 controller disabled
- ; TRUE - XHCI0 controller enabled
-
- Xhci1Enable BOOLEAN ? ; XHCI1 controller function
- ; FALSE - XHCI1 controller disabled
- ; TRUE - XHCI1 controller enabled
-
-FCH_RESET_INTERFACE ENDS
-
-
-;
-; FCH Component Data Structure from InitEnv stage
-;
-FCH_INTERFACE STRUCT
- SdConfig SD_MODE ? ; Secure Digital (SD) controller mode
- AzaliaController HDA_CONFIG ? ; Azalia HD Audio Controller
- IrConfig IR_CONFIG ? ; Infrared (IR) Configuration
- UmiGen2 BOOLEAN ? ; Enable Gen2 data rate of UMI
- ; FALSE - Disable Gen2
- ; TRUE - Enable Gen2
- SataClass SATA_CLASS ? ; SATA controller mode
- SataEnable BOOLEAN ? ; SATA controller function
- ; FALSE - SATA controller is disabled
- ; TRUE - SATA controller is enabled
- IdeEnable BOOLEAN ? ; SATA IDE controller mode enabled/disabled
- ; FALSE - IDE controller is disabled
- ; TRUE - IDE controller is enabled
- SataIdeMode BOOLEAN ? ; Native mode of SATA IDE controller
- ; FALSE - Legacy IDE mode
- ; TRUE - Native IDE mode
- Ohci1Enable BOOLEAN ? ; OHCI controller #1 Function
- ; FALSE - OHCI1 is disabled
- ; TRUE - OHCI1 is enabled
- Ohci2Enable BOOLEAN ? ; OHCI controller #2 Function
- ; FALSE - OHCI2 is disabled
- ; TRUE - OHCI2 is enabled
- Ohci3Enable BOOLEAN ? ; OHCI controller #3 Function
- ; FALSE - OHCI3 is disabled
- ; TRUE - OHCI3 is enabled
- Ohci4Enable BOOLEAN ? ; OHCI controller #4 Function
- ; FALSE - OHCI4 is disabled
- ; TRUE - OHCI4 is enabled
- XhciSwitch BOOLEAN ? ; XHCI controller Function
- ; FALSE - XHCI is disabled
- ; TRUE - XHCI is enabled
- GppEnable BOOLEAN ? ; Master switch of GPP function
- ; FALSE - GPP disabled
- ; TRUE - GPP enabled
- FchPowerFail POWER_FAIL ? ; FCH power failure option
-FCH_INTERFACE ENDS
-
-
-; ---------------------------------------------------------------------------
-; CPU Feature related info
-; ---------------------------------------------------------------------------
- ; Build Configuration values for BLDCFG_PLATFORM_C1E_MODE
- C1eModeDisabled EQU 0 ; < Disabled
- C1eModeAuto EQU 1 ; < Auto mode enables the best C1e method for the
- ; < currently installed processor
- C1eModeHardware EQU 2 ; < Hardware method
- C1eModeMsgBased EQU 3 ; < Message-based method
- C1eModeSoftwareDeprecated EQU 4 ; < Deprecated software SMI method
- C1eModeHardwareSoftwareDeprecated EQU 5 ; < Hardware or Deprecated software SMI method
- MaxC1eMode EQU 6 ; < Not a valid value, used for verifying input
-PLATFORM_C1E_MODES TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
- CStateModeDisabled EQU 0 ; < Disabled
- CStateModeC6 EQU 1 ; < C6 State
- MaxCStateMode EQU 2 ; < Not a valid value, used for verifying input
-PLATFORM_CSTATE_MODES TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_PLATFORM_CPB_MODE
- CpbModeAuto EQU 0 ; < Auto
- CpbModeDisabled EQU 1 ; < Disabled
- MaxCpbMode EQU 2 ; < Not a valid value, used for verifying input
-PLATFORM_CPB_MODES TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_LOW_POWER_PSTATE_FOR_PROCHOT_MODE
- LOW_POWER_PSTATE_FOR_PROCHOT_AUTO EQU 0 ; < Auto
- LOW_POWER_PSTATE_FOR_PROCHOT_DISABLE EQU 1 ; < Disabled
- MAX_LOW_POWER_PSTATE_FOR_PROCHOT_MODE EQU 2 ; < Not a valid value, used for verifying input
-PLATFORM_LOW_POWER_PSTATE_MODES TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_ACPI_PSTATES_PSD_POLICY
- PsdPolicyProcessorDefault EQU 0 ; PSD is dependent or independent per processor default
- PsdPolicyDependent EQU 1 ; PSD is forced dependent
- PsdPolicyIndependent EQU 2 ; PSD is forced independent
- PsdPolicyMax EQU 3 ; Not a valid value, used for verifying input
-
-
-;----------------------------------------------------------------------------
-; GNB PCIe configuration info
-;----------------------------------------------------------------------------
-
-GNB_EVENT_INVALID_CONFIGURATION EQU 20010000h ; User configuration invalid
-GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION EQU 20010001h ; Requested lane allocation for PCIe port can not be supported
-GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION EQU 20010002h ; Requested incorrect PCIe port device address
-GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION EQU 20010003h ; Incorrect parameter in DDI link configuration
-GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION EQU 20010004h ; Invalid with for PCIe port or DDI link
-GNB_EVENT_INVALID_LANES_CONFIGURATION EQU 20010005h ; Lane double subscribe lanes
-GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION EQU 20010006h ; Requested lane allocation for DDI link(s) can not be supported
-GNB_EVENT_LINK_TRAINING_FAIL EQU 20020000h ; PCIe Link training fail
-GNB_EVENT_BROKEN_LANE_RECOVERY EQU 20030000h ; Broken lane workaround applied to recover link training
-GNB_EVENT_GEN2_SUPPORT_RECOVERY EQU 20040000h ; Scale back to GEN1 to recover link training
-
-DESCRIPTOR_TERMINATE_LIST EQU 80000000h
-DESCRIPTOR_IGNORE EQU 40000000h
-
-; PCIe link initialization
-
-EndpointDetect EQU 0 ;Detect endpoint presence
-EndpointNotPresent EQU 1 ;Endpoint not present (or connected). Used in case there is alternative way to determine
- ;if device present on board or in slot. For example GPIO can be used to determine device presence.
-PCIE_ENDPOINT_STATUS TEXTEQU <DWORD>
-
-PCIe_PORT_MISC_CONTROL STRUCT
- LinkComplianceMode UINT8 ?
- ;IN UINT8 LinkComplianceMode :1; ;< Force port into compliance mode (device will not be trained, port output compliance pattern)
-PCIe_PORT_MISC_CONTROL ENDS
-
-APIC_DEVICE_INFO STRUCT
- GroupMap UINT8 ? ; < Group mapping for slot or endpoint device (connected to PCIE port) interrupts .
- ; 0 - IGNORE THIS STRUCTURE and use recommended settings
- ; 1 - mapped to Grp 0 (Interrupts 0..3 of IO APIC redirection table)
- ; 2 - mapped to Grp 1 (Interrupts 4..7 of IO APIC redirection table)
- ; ...
- ; 8 - mapped to Grp 7 (Interrupts 28..31 of IO APIC redirection table)
- Swizzle UINT8 ? ;< Swizzle interrupt in the Group.
- ; 0 - ABCD
- ; 1 - BCDA
- ; 2 - CDAB
- ; 3 - DABC
- BridgeInt UINT8 ? ; < IOAPIC redirection table entry for PCIE bridge interrupt
- ; 0 - Entry 0 of IO APIC redirection table
- ; 1 - Entry 1 of IO APIC redirection table
- ; ...
- ; 31 - Entry 31 of IO APIC redirection table
-APIC_DEVICE_INFO ENDS
-
-PCIe_PORT_DATA STRUCT
- PortPresent UINT8 ? ; < Enable PCIe port for initialization.
- ChannelType UINT8 ? ; < Channel type.
- ; 0 - "lowLoss",
- ; 1 - "highLoss",
- ; 2 - "mob0db",
- ; 3 - "mob3db",
- ; 4 - "extnd6db"
- ; 5 - "extnd8db"
- ;
- DeviceNumber UINT8 ? ; < Device number for port. Available device numbers may very on different CPUs.
- FunctionNumber UINT8 ? ; < Reserved for future use
- LinkSpeedCapability UINT8 ? ; < Advertised Gen Capability
- ; 0 - Maximum supported by silicon
- ; 1 - Gen1
- ; 2 - Gen2
- ; 3 - Gen3
- ;
- LinkAspm UINT8 ? ; < ASPM control. (see OemPcieLinkAspm for additional option to control ASPM)
- ; 0 - Disabled
- ; 1 - L0s only
- ; 2 - L1 only
- ; 2 - L0s and L1
- ;
- LinkHotplug UINT8 ? ; < Hotplug control.
- ; 0 - Disabled
- ; 1 - Basic
- ; 2 - Server
- ; 3 - Enhanced
- ;
- ResetId UINT8 ? ; < Arbitrary number greater than 0 assigned by platform firmware for GPIO
- ; identification which control reset for given port.
- ; Each port with unique GPIO should have unique ResetId assigned.
- ; All ports use same GPIO to control reset should have same ResetId assigned.
- ; see AgesaPcieSlotResetControl
- ;
- MiscControls PCIe_PORT_MISC_CONTROL {} ; < Misc extended controls
- ApicDeviceInfo APIC_DEVICE_INFO {} ; < IOAPIC device programming info
- EndpointStatus PCIE_ENDPOINT_STATUS ? ; < PCIe endpoint status
-PCIe_PORT_DATA ENDS
-
-;DDI channel lane mapping
-
-CHANNEL_MAPPING STRUCT ;
- Lane0 UINT8 ? ;
- ;IN UINT8 Lane0 :2; ;
- ;IN UINT8 Lane1 :2; ///< Lane 1 mapping (see "Lane 0 mapping")
- ;IN UINT8 Lane2 :2; ///< Lane 2 mapping (see "Lane 0 mapping")
- ;IN UINT8 Lane3 :2; ///< Lane 3 mapping (see "Lane 0 mapping")
-CHANNEL_MAPPING ENDS ;
-
-CONN_CHANNEL_MAPPING UNION
- ChannelMappingValue UINT8 ? ; < Raw lane mapping
- ChannelMapping CHANNEL_MAPPING {} ;
-CONN_CHANNEL_MAPPING ENDS ;
-
-; DDI Configuration
-PCIe_DDI_DATA STRUCT
- ConnectorType UINT8 ? ; < Display Connector Type
- ; 0 - DP
- ; 1 - eDP
- ; 2 - Single Link DVI
- ; 3 - Dual Link DVI
- ; 4 - HDMI
- ; 5 - DP-to-VGA
- ; 6 - DP-to-LVDS
- ; 7 - Hudson-2 NutMeg DP-to-VGA
- ; 8 - Single Link DVI-I
- ; 9 - CRT (VGA)
- ; 10 - LVDS
- ; 11 - VBIOS auto detect connector type
- AuxIndex UINT8 ? ; < Indicates which AUX or DDC Line is used
- ; 0 - AUX1
- ; 1 - AUX2
- ; 2 - AUX3
- ; 3 - AUX4
- ; 4 - AUX5
- ; 5 - AUX6
- ;
- HdpIndex UINT8 ? ; < Indicates which HDP pin is used
- ; 0 - HDP1
- ; 1 - HDP2
- ; 2 - HDP3
- ; 3 - HDP4
- ; 4 - HDP5
- ; 5 - HDP6
- Mapping CONN_CHANNEL_MAPPING (2) DUP ({}) ;< Set specific mapping of lanes to connector pins
- ;Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane
- ;Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only
- ;applicable for Dual DDI link)
- ;if Mapping[x] set to 0 than default mapping assumed
- LanePnInversionMask UINT8 ? ; < Specifies whether to invert the state of P and N for each lane. Each bit represents a PCIe lane on the DDI port
- ; 0 - Do not invert (default)
- ; 1 - Invert P and N on this lane
- Flags UINT8 ? ; < Capabilities flags
- ; Flags bit[0] DDI_DATA_FLAGS_DP1_1_ONLY Selects downgrade PHY link to DP1.1
- ; Flags bit[7:1] Reserved
- ;
-PCIe_DDI_DATA ENDS
-
-
-; Engine Configuration
-PCIe_ENGINE_DATA STRUCT
- EngineType UINT8 ? ; < Engine type
- ; 0 - Ignore engine configuration
- ; 1 - PCIe port
- ; 2 - DDI
- StartLane UINT16 ? ; < Start lane number (in reversed configuration StartLane > EndLane).
- EndLane UINT16 ? ; < End lane number (in reversed configuration StartLane > EndLane).
-PCIe_ENGINE_DATA ENDS
-
-; PCIe port descriptor
-PCIe_PORT_DESCRIPTOR STRUCT
- Flags UINT32 ? ; < Descriptor flags
- ; Bit31 - last descriptor in complex
- EngineData PCIe_ENGINE_DATA {} ; < Engine data
- Port PCIe_PORT_DATA {} ; < PCIe port specific configuration info
-PCIe_PORT_DESCRIPTOR ENDS
-
-; DDI descriptor
-PCIe_DDI_DESCRIPTOR STRUCT
- Flags UINT32 ? ; < Descriptor flags
- EngineData PCIe_ENGINE_DATA {} ; < Engine data
- Ddi PCIe_DDI_DATA {} ; < DDI port specific configuration info
-PCIe_DDI_DESCRIPTOR ENDS
-
-; Slot Reset Info
-PCIe_SLOT_RESET_INFO STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < AGESA Standard Header
- ResetId UINT8 ? ; < Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
- ResetControl UINT8 ? ; < Reset control as defined by PCIE_RESET_CONTROL
-PCIe_SLOT_RESET_INFO ENDS
-
-GFX_VBIOS_IMAGE_FLAG_SPECIAL_POST EQU 001h
-
-; VBIOS image info
-GFX_VBIOS_IMAGE_INFO STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard configuration header
- ImagePtr POINTER ? ; < Pointer to VBIOS image
- GfxPciAddress PCI_ADDR {} ; < PCI address of integrated graphics controller
- Flags UINT32 ? ; < BIT[0] - special repost requred
-GFX_VBIOS_IMAGE_INFO ENDS
-
-; PCIe Complex descriptor
-PCIe_COMPLEX_DESCRIPTOR STRUCT
- Flags UINT32 ? ; < Descriptor flags
- ; Bit31 - last descriptor in topology
- ;
- ;
- SocketId UINT32 ? ; < Socket Id
- PciePortList POINTER ? ;< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
- DdiLinkList POINTER ? ;< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
- Reserved POINTER ? ;< Reserved for future use
-PCIe_COMPLEX_DESCRIPTOR ENDS
-
- AssertSlotReset EQU 0
- DeassertSlotReset EQU 1
-PCIE_RESET_CONTROL TEXTEQU <DWORD>
-
- PcieUnusedEngine EQU 0
- PciePortEngine EQU 1
- PcieDdiEngine EQU 2
- MaxPcieEngine EQU 3 ; < Not a valid value, used for verifying input
-PCIE_ENGINE_TYPE TEXTEQU <DWORD>
-
- PcieGenMaxSupported EQU 0
- PcieGen1 EQU 1
- PcieGen2 EQU 2
- PcieGen3 EQU 3
- MaxPcieGen EQU 4 ; < Not a valid value, used for verifying input
-PCIE_LINK_SPEED_CAP TEXTEQU <DWORD>
-
- PsppDisabled EQU 0
- PsppPerformance EQU 1
- PsppBalanceHigh EQU 2
- PsppBalanceLow EQU 3
- PsppPowerSaving EQU 4
- MaxPspp EQU 5 ; < Not a valid value, used for verifying input
-PCIE_PSPP_POLICY TEXTEQU <DWORD>
-
- ConnectorTypeDP EQU 0
- ConnectorTypeEDP EQU 1
- ConnectorTypeSingleLinkDVI EQU 2
- ConnectorTypeDualLinkDVI EQU 3
- ConnectorTypeHDMI EQU 4
- ConnectorTypeDpToVga EQU 5
- ConnectorTypeDpToLvds EQU 6
- ConnectorTypeNutmegDpToVga EQU 7
- ConnectorTypeSingleLinkDviI EQU 8
- ConnectorTypeCrt EQU 9
- ConnectorTypeLvds EQU 10
- ConnectorTypeEDPToLvds EQU 11
- ConnectorTypeEDPToLvdsSwInit EQU 12
- ConnectorTypeAutoDetect EQU 13
- MaxConnectorType EQU 14 ; < Not a valid value, used for verifying input
-PCIE_CONNECTOR_TYPE TEXTEQU <DWORD>
-
- ChannelTypeLowLoss EQU 0
- ChannelTypeHighLoss EQU 1
- ChannelTypeMob0db EQU 2
- ChannelTypeMob3db EQU 3
- ChannelTypeExt6db EQU 4
- ChannelTypeExt8db EQU 5
- MaxChannelType EQU 6 ; < Not a valid value, used for verifying input
-PCIE_CHANNEL_TYPE TEXTEQU <DWORD>
-
- AspmDisabled EQU 0
- AspmL0s EQU 1
- AspmL1 EQU 2
- AspmL0sL1 EQU 3
- MaxAspm EQU 4 ; < Not a valid value, used for verifying input
-PCIE_ASPM_TYPE TEXTEQU <DWORD>
-
- HotplugDisabled EQU 0
- HotplugBasic EQU 1
- HotplugServer EQU 2
- HotplugEnhanced EQU 3
- HotplugInboard EQU 4
- MaxHotplug EQU 5 ; < Not a valid value, used for verifying input
-PCIE_HOTPLUG_TYPE TEXTEQU <DWORD>
-
- PortDisabled EQU 0
- PortEnabled EQU 1
-PCIE_PORT_ENABLE TEXTEQU <DWORD>
-
- PcieAcsDisabled EQU 0
- PcieAcsEnabled EQU 1
-PCIE_ACS_CAP TEXTEQU <DWORD>
-
- ClkPmSupportDisabled EQU 0
- ClkPmSupportEnabled EQU 1
-CLKPM_SUPPORT_ENABLE TEXTEQU <DWORD>
-
- Aux1 EQU 0
- Aux2 EQU 1
- Aux3 EQU 2
- Aux4 EQU 3
- Aux5 EQU 4
- Aux6 EQU 5
- MaxAux EQU 6 ; < Not a valid value, used for verifying input
-PCIE_AUX_TYPE TEXTEQU <DWORD>
-
- Hdp1 EQU 0
- Hdp2 EQU 1
- Hdp3 EQU 2
- Hdp4 EQU 3
- Hdp5 EQU 4
- Hdp6 EQU 5
- MaxHdp EQU 6 ; < Not a valid value, used for verifying input
-PCIE_HDP_TYPE TEXTEQU <DWORD>
-
-;PCIe_DDI_DATA.Flags definitions
-DDI_DATA_FLAGS_DP1_1_ONLY EQU 01h ; < BIT[0] Selects downgrade PHY link to DP1.1
-EXT_DISPLAY_PATH_CAPS_DP_FIXED_VS_EN EQU 02h ; < BIT[1] VBIOS will always output fixed voltage swing during DP link training
-
-;DP receiver definitions with fixed voltage swing
-DP_VS_0_4V_0DB EQU 00h ; < 0x00
-DP_VS_0_6V_0DB EQU 01h ; < 0x01
-DP_VS_0_8V_0DB EQU 02h ; < 0x02
-DP_VS_1_2V_0DB EQU 03h ; < 0x03
-DP_VS_0_4V_3_5DB EQU 08h ; < 0x08
-DP_VS_0_6V_3_5DB EQU 09h ; < 0x09
-DP_VS_0_8V_3_5DB EQU 0Ah ; < 0x0a
-DP_VS_0_4V_6DB EQU 10h ; < 0x10
-DP_VS_0_6V_6DB EQU 11h ; < 0x11
-DP_VS_0_4V_9_5DB EQU 18h ; < 0x18
-DP_FIXED_VOLT_SWING_TYPE TEXTEQU <DWORD>
-
-;IOMMU requestor ID
-IOMMU_REQUESTOR_ID STRUCT
- Bus UINT16 ? ; <[15:8] - Bus number, [7:3] - Device number, [2:0] - Function number
-IOMMU_REQUESTOR_ID ENDS
-
-;IVMD exclusion range descriptor
-IOMMU_EXCLUSION_RANGE_DESCRIPTOR STRUCT
- Flags UINT32 ? ; Descriptor flags
- ; @li @b Flags[31] - Terminate descriptor array.
- ; @li @b Flags[30] - Ignore descriptor.
- RequestorIdStart IOMMU_REQUESTOR_ID {} ; Requestor ID start
- RequestorIdEnd IOMMU_REQUESTOR_ID {} ; Requestor ID end (use same as start for single ID)
- RangeBaseAddress UINT64 ? ; Phisical base address of exclusion range
- RangeLength UINT64 ? ; Length of exclusion range in bytes
-IOMMU_EXCLUSION_RANGE_DESCRIPTOR ENDS
-
-;----------------------------------------------------------------------------
-; GNB configuration info
-;----------------------------------------------------------------------------
-;
-
-; LVDS Misc Control Field
-LVDS_MISC_CONTROL_FIELD STRUCT
- FpdiMode UINT8 ?
- ;IN UINT8 FpdiMode:1;
- ;IN UINT8 DlChSwap:1;
- ;IN UINT8 VsyncActiveLow:1;
- ;IN UINT8 HsyncActiveLow:1;
- ;IN UINT8 BLONActiveLow:1;
- ;IN UINT8 LvdsVolOverwriteEn:1;
- ;IN UINT8 Reserved:2;
-LVDS_MISC_CONTROL_FIELD ENDS
-
-; LVDS Misc Control
-LVDS_MISC_CONTROL UNION
- Field LVDS_MISC_CONTROL_FIELD {}
- Value UINT8 ?
-LVDS_MISC_CONTROL ENDS
-
-; Display Misc Control Field
-DISPLAY_MISC_CONTROL_FIELD STRUCT
- Reserved1 UINT8 ?
- ;IN UINT8 Reserved1:3;
- ;IN UINT8 VbiosFastBootEn:1;
- ;IN UINT8 Reserved2:4;
-DISPLAY_MISC_CONTROL_FIELD ENDS
-
-; Display Misc Control
-DISPLAY_MISC_CONTROL UNION
- Field DISPLAY_MISC_CONTROL_FIELD {}
- Value UINT8 ?
-DISPLAY_MISC_CONTROL ENDS
-
-; Configuration settings for GNB.
-GNB_POST_CONFIGURATION STRUCT
- IgpuEnableDisablePolicy UINT8 ? ; This item defines the iGPU Enable/Disable policy
- ; @li 0 = Auto - use existing default -
- ; @li 1 = Disable iGPU if any PCIe/PCI graphics card present
-GNB_POST_CONFIGURATION ENDS
-
- IGPU_DISABLE_AUTO EQU 0 ; Auto setting - disable iGPU if ANY PCI graphics or non-AMD PCIe graphics
- IGPU_DISABLE_ANY_PCIE EQU 1 ; Disable iGPU if any PCI or PCIE graphics card is present
-
-
-; Configuration settings for GNB.
-GNB_ENV_CONFIGURATION STRUCT
- Gnb3dStereoPinIndex UINT8 ? ;< 3D Stereo Pin ID.
- ; @li 0 = Stereo 3D is disabled (default).
- ; @li 1 = Use processor pin HPD1.
- ; @li 2 = Use processor pin HPD2
- ; @li 3 = Use processor pin HPD3
- ; @li 4 = Use processor pin HPD4
- ; @li 5 = Use processor pin HPD5
- ; @li 6 = Use processor pin HPD6
- IommuSupport BOOLEAN ? ; IOMMU support.
- ; TRUE = Disable and hide IOMMU device.
- ; FLASE = Initialize IOMMU subsystem. Generate ACPI IVRS table.
- LvdsSpreadSpectrum UINT16 ? ; Spread spectrum value in 0.01 %
- LvdsSpreadSpectrumRate UINT16 ? ; Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
- LvdsPowerOnSeqDigonToDe UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqDeToVaryBl UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqDeToDigon UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqVaryBlToDe UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqOnToOffDelay UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqVaryBlToBlon UINT8 ? ; This item configures panel initialization timing.
- LvdsPowerOnSeqBlonToVaryBl UINT8 ? ; This item configures panel initialization timing.
- LvdsMaxPixelClockFreq UINT16 ? ; This item configures the maximum pixel clock frequency supported.
- LcdBitDepthControlValue UINT32 ? ; This item configures the LCD bit depth control settings.
- Lvds24bbpPanelMode UINT8 ? ; This item configures the LVDS 24 BBP mode.
- LvdsMiscControl LVDS_MISC_CONTROL {} ; This item configures LVDS swap/Hsync/Vsync/BLON
- PcieRefClkSpreadSpectrum UINT16 ? ; Spread spectrum value in 0.01 %
- GnbRemoteDisplaySupport BOOLEAN ? ; This item enables Wireless Display Support
- LvdsMiscVoltAdjustment UINT8 ? ; Register LVDS_CTRL_4 to adjust LVDS output voltage
- DisplayMiscControl DISPLAY_MISC_CONTROL {} ; This item configures display misc control
- DpFixedVoltSwingType DP_FIXED_VOLT_SWING_TYPE ? ; To indicate fixed voltage swing value
-GNB_ENV_CONFIGURATION ENDS
-
-; Configuration settings for GNB.
-GNB_MID_CONFIGURATION STRUCT
- iGpuVgaMode UINT8 ? ; < VGA resources decoding configuration for iGPU
- ; < @li 0 = iGPU decode all VGA resources (must be promary VGA adapter)
- ; < @li 1 = iGPU will not decode any VGA resources (must be secondary graphics adapter)
- PcieAcsCapability UINT8 ? ; < Pcie ACS Capability support
- ; < @li 0 = Disabled
- ; < @li 1 = Enabled
- GnbIoapicAddress UINT64 ? ; < GNB IOAPIC Base Address(NULL if platform configured)
-GNB_MID_CONFIGURATION ENDS
-
-; GNB configuration info
-GNB_CONFIGURATION STRUCT
- PcieComplexList POINTER ? ; Pointer to array of PCIe_COMPLEX_DESCRIPTOR structures describe PCIe topology on each processor package or NULL.
- ; Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST
- ;
- ;
- ;
- ; Topology organization definition assume PCIe_COMPLEX_DESCRIPTOR defined first following
- ; PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR for given PCIe_COMPLEX_DESCRIPTOR
- ; defined in arbitrary sequence:
- ; Example of topology definition for single socket system:
- ; platformTopology LABEL DWORD
- ;
- ; Port0_2 PCIe_PORT_DESCRIPTOR <>;
- ; Port0_3 PCIe_PORT_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST> ;
- ; ...
- ; Ddi0_A PCIe_DDI_DESCRIPTOR <>;
- ; Ddi0_B PCIe_DDI_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST,>;
- ; ...
- ; Cpu0 PCIe_COMPLEX_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST, 0, Port0_2, Ddi0_A>
- ;
- ;
- PsppPolicy UINT8 ? ;< PSPP (PCIe Speed Power Policy)
- ; @li @b 0 - Disabled
- ; @li @b 1 - Performance
- ; @li @b 2 - Balance-High
- ; @li @b 3 - Balance-Low
- ; @li @b 4 - Power Saving
- ;
-GNB_CONFIGURATION ENDS
-
-GNB_LATE_CONFIGURATION STRUCT ;
- DockedTdpHeadroom BOOLEAN ? ; This item enables docked Tdp headroom.
-GNB_LATE_CONFIGURATION ENDS ;
-
-; ---------------------------------------------------------------------------
-
-; MEMORY-SPECIFIC DATA STRUCTURES
-
-; ---------------------------------------------------------------------------
-
-
- ; AGESA MAXIMIUM VALUES
-
- ; These Max values are used to define array sizes and associated loop
- ; counts in the code. They reflect the maximum values that AGESA
- ; currently supports and does not necessarily reflect the hardware
- ; capabilities of configuration.
-
-
- MAX_SOCKETS_SUPPORTED EQU 8 ; < Max number of sockets in system
- MAX_CHANNELS_PER_SOCKET EQU 4 ; < Max Channels per sockets
- MAX_DIMMS_PER_CHANNEL EQU 4 ; < Max DIMMs on a memory channel (independent of platform)
- NUMBER_OF_DELAY_TABLES EQU 9 ; < Number of tables defined in CH_DEF_STRUCT.
- ; < Eg: UINT16 *RcvEnDlys;
- ; < UINT8 *WrDqsDlys;
- ; < UINT8 *RdDqsDlys;
- ; < UINT8 *WrDatDlys;
- ; < UINT8 *RdDqsMinDlys;
- ; < UINT8 *RdDqsMaxDlys;
- ; < UINT8 *WrDatMinDlys;
- ; < UINT8 *WrDatMaxDlys;
- NUMBER_OF_FAILURE_MASK_TABLES EQU 1 ; < Number of failure mask tables
- MAX_PLATFORM_TYPES EQU 16 ; < Platform types per system
- DATAEYE_VREF_RANGE EQU 31 ; < Number of VREF steps in Data Eye Bitmap
- MCT_TRNG_KEEPOUT_START EQU 00004000h ; < base [39:8]
- MCT_TRNG_KEEPOUT_END EQU 00007FFFh ; < base [39:8]
-
- UMA_ATTRIBUTE_INTERLEAVE EQU 80000000h ; < Uma Region is interleaved
- UMA_ATTRIBUTE_ON_DCT0 EQU 40000000h ; < UMA resides on memory that belongs to DCT0
- UMA_ATTRIBUTE_ON_DCT1 EQU 20000000h ; < UMA resides on memory that belongs to DCT1
- UMA_ATTRIBUTE_ON_DCT2 EQU 10000000h ; < UMA resides on memory that belongs to DCT2
- UMA_ATTRIBUTE_ON_DCT3 EQU 08000000h ; < UMA resides on memory that belongs to DCT3
-
- PSO_TABLE TEXTEQU <UINT8>; < Platform Configuration Table
-
- ; AGESA DEFINITIONS
-
- ; Many of these are derived from the platform and hardware specific definitions
-
- ; EccSymbolSize override value
- ECCSYMBOLSIZE_USE_BKDG EQU 0 ; < Use BKDG Recommended Value
- ECCSYMBOLSIZE_FORCE_X4 EQU 4 ; < Force to x4
- ECCSYMBOLSIZE_FORCE_X8 EQU 8 ; < Force to x8
- ; CPU Package Type
- PT_L1 EQU 0 ; < L1 Package type
- PT_M2 EQU 1 ; < AM Package type
- PT_S1 EQU 2 ; < S1 Package type
-
- ; Structures use to pass system Logical CPU-ID
-CPU_LOGICAL_ID STRUCT
- Family UINT64 ? ; < Indicates logical ID Family
- Revision UINT64 ? ; < Indicates logical ID Family
-CPU_LOGICAL_ID ENDS
-
- ; Structures use to report AMP status
-AMP_STATUS STRUCT
- AmpVoltageValid BOOLEAN ? ; < Indicates if Amp voltage is valid
- AmpSupportDetectedButNotEnabled BOOLEAN ? ; < Indicates if Amp support is detected but not enabled
- AmpSelectedButNotEnabled BOOLEAN ? ; < Indicates if Amp is selected but not enabled
-AMP_STATUS ENDS
-
- ; Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
-
- AMD_PLATFORM_SERVER EQU 8000h ; < Server
- AMD_PLATFORM_DESKTOP EQU 10000h ; < Desktop
- AMD_PLATFORM_MOBILE EQU 20000h ; < Mobile
-AMD_PLATFORM_TYPE TEXTEQU <DWORD>
-
- ; Dram technology type
-
- DDR2_TECHNOLOGY EQU 0 ; < DDR2 technology
- DDR3_TECHNOLOGY EQU 1 ; < DDR3 technology
- GDDR5_TECHNOLOGY EQU 2 ; < GDDR5 technology
- UNSUPPORTED_TECHNOLOGY EQU 3 ; < Unsupported technology
-TECHNOLOGY_TYPE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
-
- DDR400_FREQUENCY EQU 200 ; < DDR 400
- DDR533_FREQUENCY EQU 266 ; < DDR 533
- DDR667_FREQUENCY EQU 333 ; < DDR 667
- DDR800_FREQUENCY EQU 400 ; < DDR 800
- DDR1066_FREQUENCY EQU 533 ; < DDR 1066
- DDR1333_FREQUENCY EQU 667 ; < DDR 1333
- DDR1600_FREQUENCY EQU 800 ; < DDR 1600
- DDR1866_FREQUENCY EQU 933 ; < DDR 1866
- DDR2100_FREQUENCY EQU 1050 ; < DDR 2100
- DDR2133_FREQUENCY EQU 1066 ; < DDR 2133
- DDR2400_FREQUENCY EQU 1200 ; < DDR 2400
- UNSUPPORTED_DDR_FREQUENCY EQU 1201 ; < Highest limit of DDR frequency
-
- ; Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
-
- QUADRANK_REGISTERED EQU 0
- QUADRANK_UNBUFFERED EQU 1
-
- ; Build Configuration values for BLDCFG_TIMING_MODE_SELECT
-
- TIMING_MODE_AUTO EQU 0 ; < Use best rate possible
- TIMING_MODE_LIMITED EQU 1 ; < Set user top limit
- TIMING_MODE_SPECIFIC EQU 2 ; < Set user specified speed
-
- ; Build Configuration values for BLDCFG_POWER_DOWN_MODE
-
- POWER_DOWN_BY_CHANNEL EQU 0
- POWER_DOWN_BY_CHIP_SELECT EQU 1
- POWER_DOWN_MODE_AUTO EQU 2
-
- ; Low voltage support
-
- VOLT_INITIAL EQU 0 ; < Initial value for VDDIO
- VOLT1_5 EQU 1 ; < 1.5 Volt
- VOLT1_35 EQU 2 ; < 1.35 Volt
- VOLT1_25 EQU 3 ; < 1.25 Volt
- VOLT_UNSUPPORTED EQU 0FFh ; < No common voltage found
-DIMM_VOLTAGE TEXTEQU <DWORD>
-
- ; AMP voltage support
-
- AMP_VOLT_RSVD EQU 0 ;< Reserved
- AMP_VOLT1_5 EQU 1 ;< 1.5 Volt
- AMP_VOLT1_55 EQU 2 ;< 1.55 Volt
- AMP_VOLT1_6 EQU 3 ;< 1.6 Volt
- AMP_VOLT1_65 EQU 4 ;< 1.65 Volt
- AMP_VOLT1_7 EQU 5 ;< 1.7 Volt
- AMP_VOLT1_75 EQU 6 ;< 1.75 Volt
- AMP_VOLT1_8 EQU 7 ;< 1.8 Volt
- AMP_VOLT1_85 EQU 8 ;< 1.85 Volt
- AMP_VOLT1_9 EQU 9 ;< 1.9 Volt
- AMP_VOLT1_45 EQU 10h ;< 1.45 Volt
- AMP_VOLT1_4 EQU 20h ;< 1.4 Volt
- AMP_VOLT1_35 EQU 30h ;< 1.35 Volt
- AMP_VOLT1_3 EQU 40h ;< 1.3 Volt
- AMP_VOLT1_25 EQU 50h ;< 1.25 Volt
- AMP_VOLT1_2 EQU 60h ;< 1.2 Volt
-AMP_DIMM_VOLTAGE TEXTEQU <DWORD>
-
- ; UMA Mode
-
- UMA_NONE EQU 0 ; < UMA None
- UMA_SPECIFIED EQU 1 ; < UMA Specified
- UMA_AUTO EQU 2 ; < UMA Auto
-UMA_MODE TEXTEQU <DWORD>
-
- ; Force Training Mode
-
- FORCE_TRAIN_1D EQU 0 ; < 1D Training only
- FORCE_TRAIN_2D EQU 1 ; < 2D Training only
- FORCE_TRAIN_AUTO EQU 2 ; < Auto - 1D or 2D depending on configuration
-FORCE_TRAIN_MODE TEXTEQU <DWORD>
-
-; The possible DRAM prefetch mode settings.
- DRAM_PREFETCHER_AUTO EQU 0 ; Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
- DISABLE_DRAM_PREFETCH_FOR_IO EQU 1 ; Disable DRAM prefetching for I/O requests only.
- DISABLE_DRAM_PREFETCH_FOR_CPU EQU 2 ; Disable DRAM prefetching for requests from processor cores only.
- DISABLE_DRAM_PREFETCHER EQU 3 ; Disable DRAM prefetching.
- MAX_DRAM_FREFETCH_MODE EQU 4 ; Not a DRAM prefetch mode, use for limit checking.
-DRAM_PREFETCH_MODE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_UMA_ALIGNMENT
-
- NO_UMA_ALIGNED EQU 00FFFFFFh
- UMA_4MB_ALIGNED EQU 00FFFFC0h
- UMA_128MB_ALIGNED EQU 00FFF800h
- UMA_256MB_ALIGNED EQU 00FFF000h
- UMA_512MB_ALIGNED EQU 00FFE000h
-UMA_ALIGNMENT TEXTEQU <DWORD>
- ; ===============================================================================
- ; Global MCT Configuration Status Word (GStatus)
- ; ===============================================================================
-
- GsbMTRRshort EQU 0 ; < Ran out of MTRRs while mapping memory
- GsbAllECCDimms EQU 1 ; < All banks of all Nodes are ECC capable
- GsbDramECCDis EQU 2 ; < Dram ECC requested but not enabled.
- GsbSoftHole EQU 3 ; < A Node Base gap was created
- GsbHWHole EQU 4 ; < A HW dram remap was created
- GsbNodeIntlv EQU 5 ; < Node Memory interleaving was enabled
- GsbSpIntRemapHole EQU 6 ; < Special condition for Node Interleave and HW remapping
- GsbEnDIMMSpareNW EQU 7 ; < Indicates that DIMM Spare can be used without a warm reset
-
- GsbEOL EQU 8 ; < End of list
-GLOBAL_STATUS_FIELD TEXTEQU <DWORD>
-
-; ===============================================================================
- ; Local Error Status (DIE_STRUCT.ErrStatus[31:0])
-; ===============================================================================
-
- EsbNoDimms EQU 0 ; < No DIMMs
- EsbSpdChkSum EQU 1 ; < SPD Checksum fail
- EsbDimmMismatchM EQU 2 ; < dimm module type(buffer) mismatch
- EsbDimmMismatchT EQU 3 ; < dimm CL/T mismatch
- EsbDimmMismatchO EQU 4 ; < dimm organization mismatch (128-bit)
- EsbNoTrcTrfc EQU 5 ; < SPD missing Trc or Trfc info
- EsbNoCycTime EQU 6 ; < SPD missing byte 23 or 25
- EsbBkIntDis EQU 7 ; < Bank interleave requested but not enabled
- EsbDramECCDis EQU 8 ; < Dram ECC requested but not enabled
- EsbSpareDis EQU 9 ; < Online spare requested but not enabled
- EsbMinimumMode EQU 10 ; < Running in Minimum Mode
- EsbNoRcvrEn EQU 11 ; < No DQS Receiver Enable pass window found
- EsbSmallRcvr EQU 12 ; < DQS Rcvr En pass window too small (far right of dynamic range)
- EsbNoDqsPos EQU 13 ; < No DQS-DQ passing positions
- EsbSmallDqs EQU 14 ; < DQS-DQ passing window too small
- EsbDCBKScrubDis EQU 15 ; < DCache scrub requested but not enabled
-
- EsbEMPNotSupported EQU 16 ; < Processor is not capable for EMP.
- EsbEMPConflict EQU 17 ; < EMP requested but cannot be enabled since
- ; < channel interleaving, bank interleaving, or bank swizzle is enabled.
- EsbEMPDis EQU 18 ; < EMP requested but cannot be enabled since
- ; < memory size of each DCT is not a power of two.
-
- EsbEOL EQU 19 ; < End of list
-ERROR_STATUS_FIELD TEXTEQU <DWORD>
-
-; ===============================================================================
- ; Local Configuration Status (DIE_STRUCT.Status[31:0])
-; ===============================================================================
-
- SbRegistered EQU 0 ; < All DIMMs are Registered
- SbEccDimms EQU 1 ; < All banks ECC capable
- SbParDimms EQU 2 ; < All banks Addr/CMD Parity capable
- SbDiagClks EQU 3 ; < Jedec ALL slots clock enable diag mode
- Sb128bitmode EQU 4 ; < DCT in 128-bit mode operation
- Sb64MuxedMode EQU 5 ; < DCT in 64-bit mux'ed mode.
- Sb2TMode EQU 6 ; < 2T CMD timing mode is enabled.
- SbSWNodeHole EQU 7 ; < Remapping of Node Base on this Node to create a gap.
- SbHWHole EQU 8 ; < Memory Hole created on this Node using HW remapping.
- SbOver400Mhz EQU 9 ; < DCT freq greater than or equal to 400MHz flag
- SbDQSPosPass2 EQU 10 ; < Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
- SbDQSRcvLimit EQU 11 ; < Used for DQSRcvEnTrain to know we have reached the upper bound.
- SbExtConfig EQU 12 ; < Indicate the default setting for extended PCI configuration support
- SbLrdimms EQU 13 ; < All DIMMs are LRDIMMs
- SbEOL EQU 14 ; < End of list
-LOCAL_STATUS_FIELD TEXTEQU <DWORD>
-
-
-; < CPU MSR Register definitions ------------------------------------------
- SYS_CFG EQU 0C0010010h
- TOP_MEM EQU 0C001001Ah
- TOP_MEM2 EQU 0C001001Dh
- HWCR EQU 0C0010015h
- NB_CFG EQU 0C001001Fh
-
- FS_BASE EQU 0C0000100h
- IORR0_BASE EQU 0C0010016h
- IORR0_MASK EQU 0C0010017h
- BU_CFG EQU 0C0011023h
- BU_CFG2 EQU 0C001102Ah
- COFVID_STAT EQU 0C0010071h
- TSC EQU 10h
-
-; ===============================================================================
- ; SPD Data for each DIMM
-; ===============================================================================
-SPD_DEF_STRUCT STRUCT
- DimmPresent BOOLEAN ? ; < Indicates that the DIMM is present and Data is valid
- Data UINT8 (256) DUP (?) ; < Buffer for 256 Bytes of SPD data from DIMM
-SPD_DEF_STRUCT ENDS
-
-; ===============================================================================
- ; Channel Definition Structure
- ; This data structure defines entries that are specific to the channel initialization
-; ===============================================================================
-CH_DEF_STRUCT STRUCT
- ChannelID UINT8 ? ; < Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
- TechType TECHNOLOGY_TYPE ? ; < Technology type of this channel
- ChDimmPresent UINT8 ? ; < For each bit n 0..7, 1 = DIMM n is present.
- ; < DIMM# Select Signal
- ; < 0 MA0_CS_L[0, 1]
- ; < 1 MB0_CS_L[0, 1]
- ; < 2 MA1_CS_L[0, 1]
- ; < 3 MB1_CS_L[0, 1]
- ; < 4 MA2_CS_L[0, 1]
- ; < 5 MB2_CS_L[0, 1]
- ; < 6 MA3_CS_L[0, 1]
- ; < 7 MB3_CS_L[0, 1]
-
- DCTPtr POINTER ? ; < Pointer to the DCT data of this channel.
- MCTPtr POINTER ? ; < Pointer to the node data of this channel.
- SpdPtr POINTER ? ; < Pointer to the SPD data for this channel. (Setup by NB Constructor)
- DimmSpdPtr POINTER (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Array of pointers to
- ; < SPD Data for each Dimm. (Setup by Tech Block Constructor)
- ChDimmValid UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved.
- RegDimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved.
- LrDimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
- SODimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is a SO-DIMM where 4..7 are reserved.
- Loads UINT8 ? ; < Number of devices loading bus
- Dimms UINT8 ? ; < Number of DIMMs loading Channel
- Ranks UINT8 ? ; < Number of ranks loading Channel DATA
- SlowMode BOOLEAN ? ; < 1T or 2T CMD mode (slow access mode)
- ; < FALSE = 1T
- ; < TRUE = 2T
- ; < The following pointers will be pointed to dynamically allocated buffers.
- ; < Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
- ; < Example: If DIMM and Byte based training, then
- ; < XX is a value in Hex
- ; < BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
- ; < Row1 - Logical DIMM0 XX XX XX XX XX XX XX XX XX
- ; < Row2 - Logical DIMM1 XX XX XX XX XX XX XX XX XX
- RcvEnDlys POINTER ? ; < DQS Receiver Enable Delays
- WrDqsDlys POINTER ? ; < Write DQS delays (only valid for DDR3)
- RdDqsDlys POINTER ? ; < Read Dqs delays
- WrDatDlys POINTER ? ; < Write Data delays
- RdDqs2dDlys POINTER ? ; < 2d Read DQS data
- RdDqsMinDlys POINTER ? ; < Minimum Window for Read DQS
- RdDqsMaxDlys POINTER ? ; < Maximum Window for Read DQS
- WrDatMinDlys POINTER ? ; < Minimum Window for Write data
- WrDatMaxDlys POINTER ? ; < Maximum Window for Write data
- RcvEnDlysMemPs1 POINTER ? ; < DQS Receiver Enable Delays for Memory Pstate 1
- WrDqsDlysMemPs1 POINTER ? ; < Write DQS delays for Memory Pstate 1 (only valid for DDR3)
- RdDqsDlysMemPs1 POINTER ? ; < Read Dqs delays for Memory Pstate 1
- WrDatDlysMemPs1 POINTER ? ; < Write Data delays for Memory Pstate 1
- RdDqs2dDlysMemPs1 POINTER ? ; < 2d Read DQS data for Memory Pstate 1
- RdDqsMinDlysMemPs1 POINTER ? ; < Minimum Window for Read DQS for Memory Pstate 1
- RdDqsMaxDlysMemPs1 POINTER ? ; < Maximum Window for Read DQS for Memory Pstate 1
- WrDatMinDlysMemPs1 POINTER ? ; < Minimum Window for Write data for Memory Pstate 1
- WrDatMaxDlysMemPs1 POINTER ? ; < Maximum Window for Write data for Memory Pstate 1
- RowCount UINT8 ? ; < Number of rows of the allocated buffer.
- ColumnCount UINT8 ? ; < Number of columns of the allocated buffer.
-
- FailingBitMask POINTER ? ; < Table of masks to Track Failing bits
- FailingBitMaskMemPs1 POINTER ? ; < Table of masks to Track Failing bits for Memory Pstate 1
- RdDataEyes POINTER ? ; < Pointer to Read Data Eye Bitmaps
- WrDataEyes POINTER ? ; < Pointer to Write Data Eye Bitmaps
- DctOdcCtl UINT32 ? ; < Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
- DctAddrTmg UINT32 ? ; < Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
- PhyRODTCSLow UINT32 ? ; < Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h)
- PhyRODTCSHigh UINT32 ? ; < Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h)
- PhyWODTCSLow UINT32 ? ; < Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h)
- PhyWODTCSHigh UINT32 ? ; < Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183)
- PhyWLODT UINT8 (4) DUP (?) ; < Write Levelization ODT Pattern for Dimm 0-3 or CS 0-7(see BKDG FN2:Offset 9Ch, index 0x8[11:8])
- DctEccDqsLike UINT16 ? ; < DCT DQS ECC UINT8 like...
- DctEccDqsScale UINT8 ? ; < DCT DQS ECC UINT8 scale
- PtrPatternBufA UINT16 ? ; < Ptr on stack to aligned DQS testing pattern
- PtrPatternBufB UINT16 ? ; < Ptr on stack to aligned DQS testing pattern
- ByteLane UINT8 ? ; < Current UINT8 Lane (0..7)
- Direction UINT8 ? ; < Current DQS-DQ training write direction (0=read, 1=write)
- Pattern UINT8 ? ; < Current pattern
- DqsDelay UINT8 ? ; < Current DQS delay value
- HostBiosSrvc1 UINT16 ? ; < UINT16 sized general purpose field for use by host BIOS. Scratch space.
- HostBiosSrvc2 UINT32 ? ; < UINT32 sized general purpose field for use by host BIOS. Scratch space.
- DctMaxRdLat UINT16 (4) DUP (?) ; < Max Read Latency (ns) for the DCT
- ; < DctMaxRdLat [i] is for NBPstate i DIMMValidCh UINT8 ? ; < DIMM# in CH
- DIMMValidCh UINT8 ? ; < DIMM# in CH
- MaxCh UINT8 ? ; < Max number of CH in system
- Dct UINT8 ? ; < Dct pointer
- WrDatGrossH UINT8 ? ; < Write Data Gross delay high value
- DqsRcvEnGrossL UINT8 ? ; < DQS Receive Enable Gross Delay low
-
- TrwtWB UINT8 ? ; < Non-SPD timing value for TrwtWB
- CurrRcvrDctADelay UINT8 ? ; < for keep current RcvrEnDly
- T1000 UINT16 ? ; < get the T1000 figure (cycle time (ns) * 1K)
- DqsRcvEnPass UINT8 ? ; < for TrainRcvrEn UINT8 lane pass flag
- DqsRcvEnSaved UINT8 ? ; < for TrainRcvrEn UINT8 lane saved flag
- SeedPass1Remainder UINT8 ? ; < for Phy assisted DQS receiver enable training
-
- ClToNbFlag UINT8 ? ; < is used to restore ClLinesToNbDis bit after memory
- NodeSysBase UINT32 ? ; < for channel interleave usage
- RefRawCard UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Array of rawcards detected
- CtrlWrd02 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 2 values per DIMM
- CtrlWrd03 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 3 values per DIMM
- CtrlWrd04 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 4 values per DIMM
- CtrlWrd05 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 5 values per DIMM
- CtrlWrd08 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 8 values per DIMM
-
- CsPresentDCT UINT16 ? ; < For each bit n 0..7, 1 = Chip-select n is present
- DimmMirrorPresent UINT8 ? ; < For each bit n 0..7, 1 = DIMM n is OnDimmMirror capable
- DimmSpdCse UINT8 ? ; < For each bit n 0..7, 1 = DIMM n SPD checksum error
- DimmExclude UINT8 ? ; < For each bit n 0..7, 1 = DIMM n gets excluded
- DimmYr06 UINT8 ? ; < Bitmap indicating which Dimms have a manufacturer's year code <= 2006
- DimmWk2406 UINT8 ? ; < Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
- DimmPlPresent UINT8 ? ; < Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
- DimmQrPresent UINT8 ? ; < QuadRank DIMM present?
- DimmDrPresent UINT8 ? ; < Bitmap indicating that Dual Rank Dimms are present
- DimmSRPresent UINT8 ? ; < Bitmap indicating that Single Rank Dimms are present
- Dimmx4Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved.
- Dimmx8Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved.
- Dimmx16Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved.
- LrdimmPhysicalRanks UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Number of Physical Ranks for LRDIMMs
- LrDimmLogicalRanks UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Number of LRDIMM Logical ranks in this configuration
- LrDimmRankMult UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Rank Multipication factor per dimm.
- DimmNibbleAccess UINT8 ? ; < For each bit n 0..3, 1 = DIMM n will use nibble signaling. Where 4..7 are reserved.
- MemClkDisMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
- ; < base on this array to disable unused MemClk to save power.
- ; <
- ; < The array must have 8 entries. Each entry, which associates with
- ; < one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
- ; < Example:
- ; < BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package
- ; < is like below:
- ; < Bit AM3/S1g3 pin name
- ; < 0 M[B,A]_CLK_H/L[0]
- ; < 1 M[B,A]_CLK_H/L[1]
- ; < 2 M[B,A]_CLK_H/L[2]
- ; < 3 M[B,A]_CLK_H/L[3]
- ; < 4 M[B,A]_CLK_H/L[4]
- ; < 5 M[B,A]_CLK_H/L[5]
- ; < 6 M[B,A]_CLK_H/L[6]
- ; < 7 M[B,A]_CLK_H/L[7]
- ; < And platform has the following routing:
- ; < CS0 M[B,A]_CLK_H/L[4]
- ; < CS1 M[B,A]_CLK_H/L[2]
- ; < CS2 M[B,A]_CLK_H/L[3]
- ; < CS3 M[B,A]_CLK_H/L[5]
- ; < Then MemClkDisMap should be pointed to the following array:
- ; < CLK_2 CLK_3 CLK_4 CLK_5
- ; < 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00
- ; < Each entry of the array is the bitmask of 8 chip selects.
-
- CKETriMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of CKE pins to the DIMMs' ranks.
- ; < The array must have 2 entries. Each entry, which associates with
- ; < one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
- ; < AGESA will base on this array to disable unused CKE pins to save power.
-
- ODTTriMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of ODT pins to the DIMMs' ranks.
- ; < The array must have 4 entries. Each entry, which associates with
- ; < one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
- ; < AGESA will base on this array to disable unused ODT pins to save power.
-
- ChipSelTriMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of chip select pins to the DIMMs' ranks.
- ; < The array must have 8 entries. Each entry is a bitmap of 8 CS.
- ; < AGESA will base on this array to disable unused Chip select pins to save power.
-
- ExtendTmp BOOLEAN ? ; < If extended temperature is supported on all dimms on a channel.
-
- MaxVref UINT8 ? ; < Maximum Vref Value for channel
-
- Reserved UINT8 (100) DUP (?) ; < Reserved
-CH_DEF_STRUCT ENDS
-
-; ===============================================================================
- ; DCT Channel Timing Parameters
- ; This data structure sets timings that are specific to the channel
-; ===============================================================================
-CH_TIMING_STRUCT STRUCT
- DctDimmValid UINT16 ? ; < For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved.
- DimmMirrorPresent UINT16 ? ; < For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved.
- DimmSpdCse UINT16 ? ; < For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved.
- DimmExclude UINT16 ? ; < For each bit n 0..3, 1 = DIMM n gets excluded because of no common voltage is found
- CsPresent UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is present
- CsEnabled UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is enabled
- CsTestFail UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is present but disabled
- CsTrainFail UINT16 ? ; < Bitmap showing which chipselects failed training
- DIMM1KPage UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved.
- DimmQrPresent UINT16 ? ; < QuadRank DIMM present?
- DimmDrPresent UINT16 ? ; < Bitmap indicating that Dual Rank Dimms are present
- DimmSRPresent UINT8 ? ; < Bitmap indicating that Single Rank Dimms are present
- Dimmx4Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved.
- Dimmx8Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved.
- Dimmx16Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved.
-
- DIMMTrcd UINT16 ? ; < Minimax Trcd*40 (ns) of DIMMs
- DIMMTrp UINT16 ? ; < Minimax Trp*40 (ns) of DIMMs
- DIMMTrtp UINT16 ? ; < Minimax Trtp*40 (ns) of DIMMs
- DIMMTras UINT16 ? ; < Minimax Tras*40 (ns) of DIMMs
- DIMMTrc UINT16 ? ; < Minimax Trc*40 (ns) of DIMMs
- DIMMTwr UINT16 ? ; < Minimax Twr*40 (ns) of DIMMs
- DIMMTrrd UINT16 ? ; < Minimax Trrd*40 (ns) of DIMMs
- DIMMTwtr UINT16 ? ; < Minimax Twtr*40 (ns) of DIMMs
- DIMMTfaw UINT16 ? ; < Minimax Tfaw*40 (ns) of DIMMs
- TargetSpeed UINT16 ? ; < Target DRAM bus speed in MHz
- Speed UINT16 ? ; < DRAM bus speed in MHz
- ; < 400 (MHz)
- ; < 533 (MHz)
- ; < 667 (MHz)
- ; < 800 (MHz)
- ; < and so on...
- CasL UINT8 ? ; < CAS latency DCT setting (busclocks)
- Trcd UINT8 ? ; < DCT Trcd (busclocks)
- Trp UINT8 ? ; < DCT Trp (busclocks)
- Trtp UINT8 ? ; < DCT Trtp (busclocks)
- Tras UINT8 ? ; < DCT Tras (busclocks)
- Trc UINT8 ? ; < DCT Trc (busclocks)
- Twr UINT8 ? ; < DCT Twr (busclocks)
- Trrd UINT8 ? ; < DCT Trrd (busclocks)
- Twtr UINT8 ? ; < DCT Twtr (busclocks)
- Tfaw UINT8 ? ; < DCT Tfaw (busclocks)
- Trfc0 UINT8 ? ; < DCT Logical DIMM0 Trfc
- ; < 0 = 75ns (for 256Mb devs)
- ; < 1 = 105ns (for 512Mb devs)
- ; < 2 = 127.5ns (for 1Gb devs)
- ; < 3 = 195ns (for 2Gb devs)
- ; < 4 = 327.5ns (for 4Gb devs)
- Trfc1 UINT8 ? ; < DCT Logical DIMM1 Trfc (see Trfc0 for format)
- Trfc2 UINT8 ? ; < DCT Logical DIMM2 Trfc (see Trfc0 for format)
- Trfc3 UINT8 ? ; < DCT Logical DIMM3 Trfc (see Trfc0 for format)
- DctMemSize UINT32 ? ; < Base[47:16], total DRAM size controlled by this DCT.
- SlowMode BOOLEAN ? ; < 1T or 2T CMD mode (slow access mode)
- ; < FALSE = 1T
- ; < TRUE = 2T
- TrwtTO UINT8 ? ; < DCT TrwtTO (busclocks)
- Twrrd UINT8 ? ; < DCT Twrrd (busclocks)
- Twrwr UINT8 ? ; < DCT Twrwr (busclocks)
- Trdrd UINT8 ? ; < DCT Trdrd (busclocks)
- TrwtWB UINT8 ? ; < DCT TrwtWB (busclocks)
- TrdrdSD UINT8 ? ; < DCT TrdrdSD (busclocks)
- TwrwrSD UINT8 ? ; < DCT TwrwrSD (busclocks)
- TwrrdSD UINT8 ? ; < DCT TwrrdSD (busclocks)
- MaxRdLat UINT16 ? ; < Max Read Latency
- WrDatGrossH UINT8 ? ; < Temporary variables must be removed
- DqsRcvEnGrossL UINT8 ? ; < Temporary variables must be removed
-CH_TIMING_STRUCT ENDS
-
-; ===============================================================================
- ; Data for each DCT
- ; This data structure defines data used to configure each DRAM controller
-; ===============================================================================
-DCT_STRUCT STRUCT
- Dct UINT8 ? ; < Current Dct
- Timings CH_TIMING_STRUCT {} ; < Channel Timing structure
- TimingsMemPs1 POINTER ? ; < Pointed to channel timing structure for Memory Pstate 1
- ChData POINTER ? ; < Pointed to a dynamically allocated array of Channel structures
- ChannelCount UINT8 ? ; < Number of channel per this DCT
- BkIntDis BOOLEAN ? ; < Bank interleave requested but not enabled on current DCT
- BankAddrMap UINT8 ? ; < Bank Address Mapping
- EnabledChipSels UINT8 ? ; < Number of enabled chip selects on current DCT
-DCT_STRUCT ENDS
-
-
-; ===============================================================================
- ; Data Structure defining each Die
- ; This data structure contains information that is used to configure each Die
-; ===============================================================================
-DIE_STRUCT STRUCT
-
- ; Advanced:
-
- NodeId UINT8 ? ; < Node ID of current controller
- SocketId UINT8 ? ; < Socket ID of this Die
- DieId UINT8 ? ; < ID of this die relative to the socket
- PciAddr PCI_ADDR {} ; < Pci bus and device number of this controller.
- ErrCode AGESA_STATUS ? ; < Current error condition of Node
- ; < 0x0 = AGESA_SUCCESS
- ; < 0x1 = AGESA_UNSUPPORTED
- ; < 0x2 = AGESA_BOUNDS_CHK
- ; < 0x3 = AGESA_ALERT
- ; < 0x4 = AGESA_WARNING
- ; < 0x5 = AGESA_ERROR
- ; < 0x6 = AGESA_CRITICAL
- ; < 0x7 = AGESA_FATAL
- ; <
- ErrStatus BOOLEAN (EsbEOL) DUP (?) ; < Error Status bit Field
- Status BOOLEAN (SbEOL) DUP (?) ; < Status bit Field
- NodeMemSize UINT32 ? ; < Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
- NodeSysBase UINT32 ? ; < Base[47:16] (system address) DRAM base address of this Node.
- NodeHoleBase UINT32 ? ; < If not zero, Base[47:16] (system address) of dram hole for HW remapping. Dram hole exists on this Node
- NodeSysLimit UINT32 ? ; < Base[47:16] (system address) DRAM limit address of this Node.
- DimmPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is present.
- ; < DIMM# Select Signal
- ; < 0 MA0_CS_L[0, 1]
- ; < 1 MB0_CS_L[0, 1]
- ; < 2 MA1_CS_L[0, 1]
- ; < 3 MB1_CS_L[0, 1]
- ; < 4 MA2_CS_L[0, 1]
- ; < 5 MB2_CS_L[0, 1]
- ; < 6 MA3_CS_L[0, 1]
- ; < 7 MB3_CS_L[0, 1]
- DimmValid UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
- RegDimmPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is registered DIMM
- LrDimmPresent UINT32 ? ; < For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
- DimmEccPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is ECC capable.
- DimmParPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
- DimmTrainFail UINT16 ? ; < Bitmap showing which dimms failed training
- ChannelTrainFail UINT16 ? ; < Bitmap showing the channel information about failed Chip Selects
- ; < 0 in any bit field indicates Channel 0
- ; < 1 in any bit field indicates Channel 1
- Dct UINT8 ? ; < Need to be removed
- ; < DCT pointer
- GangedMode BOOLEAN ? ; < Ganged mode
- ; < 0 = disabled
- ; < 1 = enabled
- LogicalCpuid CPU_LOGICAL_ID {} ; < The logical CPUID of the node
- HostBiosSrvc1 UINT16 ? ; < UINT16 sized general purpose field for use by host BIOS. Scratch space.
- HostBiosSrvc2 UINT32 ? ; < UINT32 sized general purpose field for use by host BIOS. Scratch space.
- MLoad UINT8 ? ; < Need to be removed
- ; < Number of devices loading MAA bus
- MaxAsyncLat UINT8 ? ; < Legacy wrapper
- ChbD3Rcvrdly UINT8 ? ; < Legacy wrapper
- ChaMaxRdLat UINT16 ? ; < Max Read Latency (ns) for DCT 0
- ChbD3BcRcvrdly UINT8 ? ; < CHB DIMM 3 Check UINT8 Receiver Enable Delay
-
- DctData POINTER ? ; < Pointed to a dynamically allocated array of DCT_STRUCTs
- DctCount UINT8 ? ; < Number of DCTs per this Die
- Reserved UINT8 (16) DUP (?) ; < Reserved
-DIE_STRUCT ENDS
-
-; *********************************************************************
-; * S3 Support structure
-; *********************************************************************
- ; AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure
-AMD_S3_PARAMS STRUCT
- Signature UINT32 ? ; < "ASTR" for AMD Suspend-To-RAM
- Version UINT16 ? ; < S3 Params version number
- Flags UINT32 ? ; < Indicates operation
- NvStorage POINTER ? ; < Pointer to memory critical save state data
- NvStorageSize UINT32 ? ; < Size in bytes of the NvStorage region
- VolatileStorage POINTER ? ; < Pointer to remaining AMD save state data
- VolatileStorageSize UINT32 ? ; < Size in bytes of the VolatileStorage region
-AMD_S3_PARAMS ENDS
-
-; ===============================================================================
- ; MEM_PARAMETER_STRUCT
- ; This data structure is used to pass wrapper parameters to the memory configuration code
-; ===============================================================================
-MEM_PARAMETER_STRUCT STRUCT
-
- ; Basic (Return parameters)
- ; (This section contains the outbound parameters from the memory init code)
-
- GStatus BOOLEAN (GsbEOL) DUP (?) ; < Global Status bitfield
- HoleBase UINT32 ? ; < If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping.
- Sub4GCacheTop UINT32 ? ; < If not zero, the 32-bit top of cacheable memory.
- Sub1THoleBase UINT32 ? ; < If not zero Base[47:16] (system address) of sub 1TB dram hole.
- SysLimit UINT32 ? ; < Limit[47:16] (system address)
- DDR3Voltage DIMM_VOLTAGE ? ; < Find support voltage and send back to platform BIOS.
- ExternalVrefValue UINT8 ? ; < Target reference voltage for external Vref for 2D training
- MemData POINTER ? ; < Pointer to MEM_DATA_STRUCT
- ; Advanced (Optional parameters)
- ; Optional (all defaults values will be initialized by the
- ; 'AmdMemInitDataStructDef' based on AMD defaults. It is up
- ; to the IBV/OEM to change the defaults after initialization
- ; but prior to the main entry to the memory code):
-
- ; Memory Map/Mgt.
-
- BottomIo UINT16 ? ; < Bottom of 32-bit IO space (8-bits)
- ; < NV_BOTTOM_IO[7:0]=Addr[31:24]
- MemHoleRemapping BOOLEAN ? ; < Memory Hole Remapping (1-bit)
- ; < FALSE = disable
- ; < TRUE = enable
- LimitMemoryToBelow1Tb BOOLEAN ? ; < Limit memory address space to below 1 TB
- ; < FALSE = disable
- ; < TRUE = enable
- ; Dram Timing
-
- UserTimingMode UINT32 ? ; < User Memclock Mode
-
- MemClockValue UINT32 ? ; < Memory Clock Value
-
- ; Dram Configuration
-
- EnableBankIntlv BOOLEAN ? ; < Dram Bank (chip-select) Interleaving (1-bit)
- ; < FALSE =disable (AMD default)
- ; < TRUE =enable
- EnableNodeIntlv BOOLEAN ? ; < Node Memory Interleaving (1-bit)
- ; < FALSE = disable (AMD default)
- ; < TRUE = enable
- EnableChannelIntlv BOOLEAN ? ; < Channel Interleaving (1-bit)
- ; < FALSE = disable (AMD default)
- ; < TRUE = enable
- ; ECC
-
- EnableEccFeature BOOLEAN ? ; < enable ECC error to go into MCE
- ; < FALSE = disable (AMD default)
- ; < TRUE = enable
- ; Dram Power
-
- EnablePowerDown BOOLEAN ? ; < CKE based power down mode (1-bit)
- ; < FALSE =disable (AMD default)
- ; < TRUE =enable
- ; Online Spare
-
- EnableOnLineSpareCtl BOOLEAN ? ; < Chip Select Spare Control bit 0:
- ; < FALSE = disable Spare (AMD default)
- ; < TRUE = enable Spare
- TableBasedAlterations POINTER ? ; < Point to an array of data bytes describing desired modifications to register settings.
-
- PlatformMemoryConfiguration POINTER ?
- ; < Points to a table that contains platform specific settings
- ; < (i.e. MemClk routing, the number of DIMM slots per channel,...)
- ; < AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that
- ; < contains default conservative settings. Platform BIOS can either tweak
- ; < DefaultPlatformMemoryConfiguration or reassign this pointer to its own table.
- ; <
- EnableParity BOOLEAN ? ; < Parity control
- ; < TRUE = enable
- ; < FALSE = disable (AMD default)
- EnableBankSwizzle BOOLEAN ? ; < BankSwizzle control
- ; < FALSE = disable
- ; < TRUE = enable (AMD default)
- EnableMemClr BOOLEAN ? ; < Memory Clear functionality control
- ; < FALSE = disable
- ; < TRUE = enable (AMD default)
- ; Uma Configuration
-
- UmaMode UMA_MODE ? ; < Uma Mode
- ; < 0 = None
- ; < 1 = Specified
- ; < 2 = Auto
- UmaSize UINT32 ? ; < The size of shared graphics dram (16-bits)
- ; < NV_UMA_Size[31:0]=Addr[47:16]
- ; <
- UmaBase UINT32 ? ; < The allocated Uma base address (32-bits)
- ; < NV_UMA_Base[31:0]=Addr[47:16]
- ; <
-
- ; Memory Restore Feature
-
- MemRestoreCtl BOOLEAN ? ; < Memory context restore control
- ; < FALSE = perform memory init as normal (AMD default)
- ; < TRUE = restore memory context and skip training. This requires
- ; < MemContext is valid before AmdInitPost
- SaveMemContextCtl BOOLEAN ? ; < Control switch to save memory context at the end of MemAuto
- ; < TRUE = AGESA will setup MemContext block before exit AmdInitPost
- ; < FALSE = AGESA will not setup MemContext block. Platform is
- ; < expected to call S3Save later in POST if it wants to
- ; < use memory context restore feature.
- MemContext AMD_S3_PARAMS {} ; < Memory context block describes the data that platform needs to
- ; < save and restore for memory context restore feature to work.
- ; < It uses the subset of S3Save block to save/restore. Hence platform
- ; < may save only S3 block and uses it for both S3 resume and
- ; < memory context restore.
- ; < - If MemRestoreCtl is TRUE, platform needs to pass in MemContext
- ; < before AmdInitPost.
- ; < - If SaveMemContextCtl is TRUE, platform needs to save MemContext
- ; < right after AmdInitPost.
- IsCapsuleMode BOOLEAN ? ;< Capsule reboot control
- ; < FALSE = This is not a capsule reboot.
- ; < TRUE = This is a capsule reboot.
- ; <
- ExternalVrefCtl BOOLEAN ? ; < Control the use of external Vref
- ; < TRUE = AGESA will use the function defined in "AGESA_EXTERNAL_2D_TRAIN_VREF_CHANGE" in function list
- ; < to change the vref
- ; < FALSE = AGESA will will use the internal vref control.
- ForceTrainMode FORCE_TRAIN_MODE ? ; < Training Mode
- ; < 0 = Force 1D Training for all configurations
- ; < 1 = Force 2D Training for all configurations
- ; < 2 = Auto - AGESA will control 1D or 2D
- DimmTypeUsedInMixedConfig TECHNOLOGY_TYPE ? ; < Select the preferred technology type that AGESA will enable
- ; < when it is mixed with other technology types.
- ; < DDR3_TECHNOLOGY = Use DDR3 DIMMs
- ; < GDDR5_TECHNOLOGY = Use GDDR5 DIMMs
- ; < UNSUPPORTED_TECHNOLOGY = Exit with fatal error when DDR3 and GDDR5 DIMMs
- ; < are installed on the same system
- AmpEnable BOOLEAN ? ; < AMP functionality control
- ; < TRUE = Enable, platform BIOS requests to enable memory overclocking function, and AGESA
- ; < detects if memory is capable of it
- ; < FALSE = Disable, there is no request to enable memory overclocking function
- ; <
- AmpWarningMsgEnable BOOLEAN ? ; < AMP warning messages control
- ; < TRUE = Enable to log the warning messages of AMP
- ; < FALSE = Disable
- ; <
- AmpStatus AMP_STATUS {} ; < AMP status allows platform BIOS to check which voltage or warning message it should
- ; < use/apply.
- ; <
- ; < AmpVoltageValid :
- ; < TRUE - AGESA does enable AMP function, so use AmpVoltage for voltage adjustment
- ; < FALSE - AGESA does not enable AMP function, so use DDR3Voltage for voltage adjustment
- ; <
- ; < AmpSupportDetectedButNotEnabled :
- ; < TRUE - Display warning message of "AMP support detected but not enabled"
- ; < FALSE - No corresponding message should be displayed
- ; <
- ; < AmpSelectedButNotEnabled :
- ; < TRUE - Display warning message of "AMP selected but not enabled"
- ; < FALSE - No corresponding message should be displayed
- ; <
- ; < Note that both of warning message status reports are controlled by AmpWarningMsgEnable
- ; <
- AmpVoltage AMP_DIMM_VOLTAGE ? ; < AMP voltage which will be sent back to platform BIOS, and
- ; < the value in AmpVoltage is valid only if AmpStatus is TRUE returned
- DataEyeEn BOOLEAN ? ; < Get 2D training data eye.
- ; < TRUE = Enable to get the 2D data eye.
- ; < FALSE = The 2D data eye is not enabled.
- ; <
- DramDoubleRefreshRate BOOLEAN ? ; < Specify the average time between refresh requests to all DRAM devices.
- ; < TRUE = 2x refresh rate (3.9us)
- ; < FALSE = 1x refresh rate (7.8us)
-MEM_PARAMETER_STRUCT ENDS
-
-
-; ===============================================================================
- ; Function definition
- ; This data structure passes function pointers to the memory configuration code.
- ; The wrapper can use this structure with customized versions
-; ================================================================================
-MEM_FUNCTION_STRUCT STRUCT
-
- ; PUBLIC required Internal functions
-
- amdMemGetPsCfgU POINTER ? ; < Proc for Unbuffered DIMMs, platform specific
- amdMemGetPsCfgR POINTER ? ; < Proc for Registered DIMMs, platform specific
-
- ; PUBLIC optional functions
-
- amdMemEccInit POINTER ? ; < NB proc for ECC feature
- amdMemChipSelectInterleaveInit POINTER ? ; < NB proc for CS interleave feature
- amdMemDctInterleavingInit POINTER ? ; < NB proc for Channel interleave feature
- amdMemMctInterleavingInit POINTER ? ; < NB proc for Node interleave feature
- amdMemParallelTraining POINTER ? ; < NB proc for parallel training feature
- amdMemEarlySampleSupport POINTER ? ; < NB code for early sample support feature
- amdMemMultiPartInitSupport POINTER ? ; < NB code for 'multi-part'
- amdMemOnlineSpareSupport POINTER ? ; < NB code for On-Line Spare feature
- amdMemUDimmInit POINTER ? ; < NB code for UDIMMs
- amdMemRDimmInit POINTER ? ; < NB code for RDIMMs
- amdMemLrDimmInit POINTER ? ; < NB code for LRDIMMs
- Reserved UINT32 (100) DUP (?) ; < Reserved for later function definition
-MEM_FUNCTION_STRUCT ENDS
-
-; ===============================================================================
- ; Socket Structure
-
-; ===============================================================================
-MEM_SOCKET_STRUCT STRUCT
- ChannelPtr POINTER (MAX_CHANNELS_PER_SOCKET) DUP (?) ; < Pointers to each channels training data
-
- TimingsPtr POINTER (MAX_CHANNELS_PER_SOCKET) DUP (?) ; < Pointers to each channels timing data
-
-MEM_SOCKET_STRUCT ENDS
-
-; ===============================================================================
- ; MEM_DATA_STRUCT
-; ===============================================================================
-MEM_DATA_STRUCT STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < AGESA Standard Header
-
- ParameterListPtr POINTER ? ; < List of input Parameters
-
- FunctionList MEM_FUNCTION_STRUCT {} ; < List of function Pointers
-
- GetPlatformCfg POINTER (MAX_PLATFORM_TYPES) DUP (?) ; < look-up platform info
-
- ErrorHandling POINTER ? ; < Error Handling
-
- ; SocketList is a shortcut for IBVs to retrieve training
- ; and timing data for each channel indexed by socket/channel,
- ; eliminating their need to parse die/dct/channel etc.
- ; It contains pointers to the populated data structures for
- ; each channel and skips the channel structures that are
- ; unpopulated. In the case of channels sharing the same DCT,
- ; the pTimings pointers will point to the same DCT Timing data.
-
- SocketList MEM_SOCKET_STRUCT (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Socket list for memory code
-
- DiesPerSystem POINTER ? ; < Pointed to an array of DIE_STRUCTs
- DieCount UINT8 ? ; < Number of MCTs in the system.
-
- SpdDataStructure POINTER ? ; < Pointer to SPD Data structure
-
- PlatFormConfig POINTER ? ; < Pointer to Platform profile/build option config structure
-
- IsFlowControlSupported BOOLEAN ? ; < Indicates if flow control is supported
-
- TscRate UINT32 ? ; < The rate at which the TSC increments in megahertz.
-
-MEM_DATA_STRUCT ENDS
-
-; ===============================================================================
-; UMA_INFO_STRUCT
-; ===============================================================================
-UMA_INFO STRUCT
- UmaBase UINT64 ? ; < UmaBase[63:0] = Addr[63:0]
- UmaSize UINT32 ? ; < UmaSize[31:0] = Addr[31:0]
- UmaAttributes UINT32 ? ; < Indicate the attribute of Uma
- UmaMode UINT8 ? ; < Indicate the mode of Uma
- MemClock UINT16 ? ; < Indicate memory running speed in MHz
- MemType UINT8 ? ; < Indicate the DRAM technology type that is being used
- Reserved UINT8 (2) DUP (?) ; < Reserved for future usage
-UMA_INFO ENDS
-
-; ===============================================================================
-; Bitfield for ID
-; ===============================================================================
-ID_FIELD STRUCT
- SocketId UINT16 ?
-; OUT UINT16 SocketId:8; ; < Socket ID
-; OUT UINT16 ModuleId:8; ; < Module ID
-ID_FIELD ENDS
-
-; ===============================================================================
-; Union for ID of socket and module that will be passed out in call out
-; ===============================================================================
-ID_INFO UNION
- IdField ID_FIELD {} ; < Bitfield for ID
- IdInformation UINT16 ? ; < ID information for call out
-ID_INFO ENDS
-
- ; AGESA MEMORY ERRORS
-
- ; AGESA_SUCCESS memory events
-MEM_EVENT_CAPSULE_IN_EFFECT EQU 04013600h ; < Capsule is in effect
-MEM_EVENT_CONTEXT_RESTORE_IN_EFFECT EQU 04023600h ; < Context restore is in effect
-
- ; AGESA_ALERT Memory Errors
-MEM_ALERT_USER_TMG_MODE_OVERRULED EQU 04010000h ; < TIMING_MODE_SPECIFIC is requested but
- ; < cannot be applied to current configurations.
-MEM_ALERT_ORG_MISMATCH_DIMM EQU 04010100h ; < DIMM organization miss-match
-MEM_ALERT_BK_INT_DIS EQU 04010200h ; < Bank interleaving disable for internal issue
-
- ; AGESA_ERROR Memory Errors
-MEM_ERROR_NO_DQS_POS_RD_WINDOW EQU 04010300h ; < No DQS Position window for RD DQS
-MEM_ERROR_SMALL_DQS_POS_RD_WINDOW EQU 04020300h ; < Small DQS Position window for RD DQS
-MEM_ERROR_NO_DQS_POS_WR_WINDOW EQU 04030300h ; < No DQS Position window for WR DQS
-MEM_ERROR_SMALL_DQS_POS_WR_WINDOW EQU 04040300h ; < Small DQS Position window for WR DQS
-MEM_ERROR_ECC_DIS EQU 04010400h ; < ECC has been disabled as a result of an internal issue
-MEM_ERROR_DIMM_SPARING_NOT_ENABLED EQU 04010500h ; < DIMM sparing has not been enabled for an internal issues
-MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE EQU 04050300h ; < Receive Enable value is too large
-MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW EQU 04060300h ; < There is no DQS receiver enable window
-MEM_ERROR_DRAM_ENABLED_TIME_OUT EQU 04010600h ; < Time out when polling DramEnabled bit
-MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT EQU 04010700h ; < Time out when polling DctAccessDone bit
-MEM_ERROR_SEND_CTRL_WORD_TIME_OUT EQU 04010800h ; < Time out when polling SendCtrlWord bit
-MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT EQU 04010900h ; < Time out when polling PrefDramTrainMode bit
-MEM_ERROR_ENTER_SELF_REF_TIME_OUT EQU 04010A00h ; < Time out when polling EnterSelfRef bit
-MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT EQU 04010B00h ; < Time out when polling FreqChgInProg bit
-MEM_ERROR_EXIT_SELF_REF_TIME_OUT EQU 04020A00h ; < Time out when polling ExitSelfRef bit
-MEM_ERROR_SEND_MRS_CMD_TIME_OUT EQU 04010C00h ; < Time out when polling SendMrsCmd bit
-MEM_ERROR_SEND_ZQ_CMD_TIME_OUT EQU 04010D00h ; < Time out when polling SendZQCmd bit
-MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT EQU 04010E00h ; < Time out when polling DctExtraAccessDone bit
-MEM_ERROR_MEM_CLR_BUSY_TIME_OUT EQU 04010F00h ; < Time out when polling MemClrBusy bit
-MEM_ERROR_MEM_CLEARED_TIME_OUT EQU 04020F00h ; < Time out when polling MemCleared bit
-MEM_ERROR_FLUSH_WR_TIME_OUT EQU 04011000h ; < Time out when polling FlushWr bit
-MEM_ERROR_NBPSTATE_TRANSITION_TIME_OUT EQU 04012600h ; < Time out when polling CurNBPstate bit
-MEM_ERROR_MAX_LAT_NO_WINDOW EQU 04070300h ; < Fail to find pass during Max Rd Latency training
-MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL EQU 04080300h ; < Fail to launch training code on an AP
-MEM_ERROR_PARALLEL_TRAINING_TIME_OUT EQU 04090300h ; < Fail to finish parallel training
-MEM_ERROR_NO_ADDRESS_MAPPING EQU 04011100h ; < No address mapping found for a dimm
-MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT EQU 040A0300h ; < There is no DQS receiver enable window and the value is equal to the largest value
-MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE EQU 040B0300h ; < Receive Enable value is too large and is 1 less than limit
-MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR EQU 04011200h ; < SPD Checksum error for NV_SPDCHK_RESTRT
-MEM_ERROR_NO_CHIPSELECT EQU 04011300h ; < No chipselects found
-MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM EQU 04011500h ; < Unbuffered dimm is not supported at 333MHz
-MEM_ERROR_WL_PRE_OUT_OF_RANGE EQU 040C0300h ; < Returned PRE value during write levelization was out of range
-MEM_ERROR_NO_2D_RDDQS_WINDOW EQU 040D0300h ; < No 2D RdDqs Window
-MEM_ERROR_NO_2D_RDDQS_HEIGHT EQU 040E0300h ; < No 2D RdDqs Height
-MEM_ERROR_2D_DQS_ERROR EQU 040F0300h ; < 2D RdDqs Error
-MEM_ERROR_INVALID_2D_RDDQS_VALUE EQU 04022400h ; < 2d RdDqs invalid value found
-MEM_ERROR_2D_DQS_VREF_MARGIN_ERROR EQU 04023400h ; < 2d RdDqs Vef Margin error found
-MEM_ERROR_LR_IBT_NOT_FOUND EQU 04013500h ; < No LR dimm IBT value is found
-MEM_ERROR_MR0_NOT_FOUND EQU 04023500h ; < No MR0 value is found
-MEM_ERROR_ODT_PATTERN_NOT_FOUND EQU 04033500h ; < No odt pattern value is found
-MEM_ERROR_RC2_IBT_NOT_FOUND EQU 04043500h ; < No RC2 IBT value is found
-MEM_ERROR_RC10_OP_SPEED_NOT_FOUND EQU 04053500h ; < No RC10 op speed is found
-MEM_ERROR_RTT_NOT_FOUND EQU 04063500h ; < No RTT value is found
-MEM_ERROR_P2D_NOT_FOUND EQU 04073500h ; < No 2D training config value is found
-MEM_ERROR_SAO_NOT_FOUND EQU 04083500h ; < No slow access mode, Address timing and Output driver compensation value is found
-MEM_ERROR_CLK_DIS_MAP_NOT_FOUND EQU 04093500h ; < No CLK disable map is found
-MEM_ERROR_CKE_TRI_MAP_NOT_FOUND EQU 040A3500h ; < No CKE tristate map is found
-MEM_ERROR_ODT_TRI_MAP_NOT_FOUND EQU 040B3500h ; < No ODT tristate map is found
-MEM_ERROR_CS_TRI_MAP_NOT_FOUND EQU 040C3500h ; < No CS tristate map is found
-MEM_ERROR_TRAINING_SEED_NOT_FOUND EQU 040D3500h ; < No training seed is found
-MEM_ERROR_NO_2D_WRDAT_WINDOW EQU 040D0400h ; < No 2D WrDat Window
-MEM_ERROR_NO_2D_WRDAT_HEIGHT EQU 040E0400h ; < No 2D WrDat Height
-MEM_ERROR_2D_WRDAT_ERROR EQU 040F0400h ; < 2d WrDat Error
-MEM_ERROR_INVALID_2D_WRDAT_VALUE EQU 04100400h ; < 2d WrDat invalid value found
-MEM_ERROR_2D_WRDAT_VREF_MARGIN_ERROR EQU 04110400h ; < 2d WrDat Vef Margin error found
-
- ; AGESA_WARNING Memory Errors
- MEM_WARNING_UNSUPPORTED_QRDIMM EQU 04011600h ; < QR DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_UDIMM EQU 04021600h ; < U DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_SODIMM EQU 04031600h ; < SO-DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_X4DIMM EQU 04041600h ; < x4 DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_RDIMM EQU 04051600h ; < R DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_LRDIMM EQU 04061600h ; < LR DIMMs detected but not supported
-
- MEM_WARNING_EMP_NOT_SUPPORTED EQU 04011700h ; < Processor is not capable for EMP
- MEM_WARNING_EMP_CONFLICT EQU 04021700h ; < EMP cannot be enabled if channel interleaving,
- ; < bank interleaving, or bank swizzle is enabled.
- MEM_WARNING_EMP_NOT_ENABLED EQU 04031700h ; < Memory size is not power of two.
- MEM_WARNING_ECC_DIS EQU 04041700h ; < ECC has been disabled as a result of an internal issue
- MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED EQU 04011800h ; < Performance has been enabled, but battery life is preferred.
- MEM_WARNING_NO_SPDTRC_FOUND EQU 04011900h ; < No Trc timing value found in SPD of a dimm.
- MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED EQU 04012000h ; < Node Interleaveing Requested, but could not be enabled
- MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED EQU 04012100h ; < Channel Interleaveing Requested, but could not be enabled
- MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED EQU 04012200h ; < Bank Interleaveing Requested, but could not be enabled
- MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED EQU 04012300h ; < Voltage 1.35 determined, but could not be supported
- MEM_WARNING_INITIAL_DDR3VOLT_NONZERO EQU 04012400h ; < DDR3 voltage initial value is not 0
- MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO EQU 04012500h ; < Cannot find a commonly supported VDDIO
- MEM_WARNING_AMP_SUPPORT_DETECTED_BUT_NOT_ENABLED EQU 04012900h ; < AMP support detected but not enabled
- MEM_WARNING_AMP_SELECTED_BUT_NOT_ENABLED EQU 04022900h ; < AMP selected but not enabled
-
-
- ; AGESA_FATAL Memory Errors
- MEM_ERROR_MINIMUM_MODE EQU 04011A00h ; < Running in minimum mode
- MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM EQU 04011B00h ; < DIMM modules are miss-matched
- MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM EQU 04011C00h ; < No DIMMs have been found on system
- MEM_ERROR_MISMATCH_DIMM_CLOCKS EQU 04011D00h ; < DIMM clocks miss-matched
- MEM_ERROR_NO_CYC_TIME EQU 04011E00h ; < No cycle time found
- MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS EQU 04011F00h ; < Heap allocation error with dynamic storing of trained timings
- MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs EQU 04021F00h ; < Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
- MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV EQU 04031F00h ; < Heap allocation error with REMOTE_TRAINING_ENV
- MEM_ERROR_HEAP_ALLOCATE_FOR_SPD EQU 04041F00h ; < Heap allocation error for SPD data
- MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA EQU 04051F00h ; < Heap allocation error for RECEIVED_DATA during parallel training
- MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS EQU 04061F00h ; < Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
- MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA EQU 04071F00h ; < Heap allocation error for Training Data
- MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK EQU 04081F00h ; < Heap allocation error for DIMM Identify "MEM_NB_BLOCK
- MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM EQU 04022300h ; < No Constructor for DIMM Identify
- MEM_ERROR_VDDIO_UNSUPPORTED EQU 04022500h ; < VDDIO of the dimms on the board is not supported
- MEM_ERROR_HEAP_ALLOCATE_FOR_2D EQU 040B1F00h ; < Heap allocation error for 2D training data
- MEM_ERROR_HEAP_DEALLOCATE_FOR_2D EQU 040C1F00h ; < Heap de-allocation error for 2D training data
- MEM_ERROR_HEAP_ALLOCATE_FOR_DATAEYE EQU 040F1F00h ; < Heap allocation error for DATAEYE Storage
- MEM_ERROR_HEAP_DEALLOCATE_FOR_DATAEYE EQU 040E1F00h ; < Heap de-allocation error for DATAEYE Storage
-
- ; AGESA_CRITICAL Memory Errors
- MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 EQU 04091F00h ; < Heap allocation error for DMI table for DDR3
- MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 EQU 040A1F00h ; < Heap allocation error for DMI table for DDR2
- MEM_ERROR_UNSUPPORTED_DIMM_CONFIG EQU 04011400h ; < Dimm population is not supported
- MEM_ERROR_HEAP_ALLOCATE_FOR_CRAT_MEM_AFFINITY EQU 040D1F00h ;< Heap allocation error for CRAT memory affinity info
-
-; ----------------------------------------------------------------------------
-; *
-; * END OF MEMORY-SPECIFIC DATA STRUCTURES
-; *
-; *----------------------------------------------------------------------------
-;
-
-
-; ----------------------------------------------------------------------------
-; *
-; * CPU RELATED DEFINITIONS
-; *
-; *----------------------------------------------------------------------------
-;
-
-; CPU Event definitions.
-
-; Defines used to filter CPU events based on functional blocks
-CPU_EVENT_PM_EVENT_MASK EQU 0FF00FF00h
-CPU_EVENT_PM_EVENT_CLASS EQU 008000400h
-
-;================================================================
-; CPU General events
-; Heap allocation (AppFunction = 01h)
-CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT EQU 008000100h
-CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED EQU 008010100h
-CPU_ERROR_HEAP_IS_FULL EQU 008020100h
-CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED EQU 008030100h
-CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT EQU 008040100h
-; BrandId (AppFunction = 02h)
-CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE EQU 008000200h
-; Micro code patch (AppFunction = 03h)
-CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED EQU 008000300h
-; Power management (AppFunction = 04h)
-CPU_EVENT_PM_PSTATE_OVERCURRENT EQU 008000400h
-CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT EQU 008010400h
-CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE EQU 008020400h
-CPU_ERROR_PM_NB_PSTATE_MISMATCH EQU 008030400h
-; TDP Limiting
-CPU_EVENT_TDP_LIMIT_FORCE_TO_50_PERCENTAGE EQU 008060100h
-CPU_ERROR_TDP_LIMIT_SAVE_PSTATE_FAIL EQU 008060200h
-CPU_ERROR_TDP_LIMIT_RESTORE_PSTATE_FAIL EQU 008060201h
-CPU_ERROR_TDP_LIMIT_TDP2WATT_IS_ZERO EQU 008060202h
-CPU_ERROR_TDP_LIMIT_INVALID_INPUT EQU 008060203h
-; Other CPU events (AppFunction = 05h)
-CPU_EVENT_BIST_ERROR EQU 008000500h
-CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY EQU 008010500h
-CPU_EVENT_STACK_REENTRY EQU 008020500h
-CPU_EVENT_CORE_NOT_IDENTIFIED EQU 008030500h
-;=================================================================
-; CPU Feature events
-; Execution cache (AppFunction = 21h)
-; AGESA_CACHE_SIZE_REDUCED 2101
-; AGESA_CACHE_REGIONS_ACROSS_1MB 2102
-; AGESA_CACHE_REGIONS_ACROSS_4GB 2103
-; AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 2104
-; AGESA_CACHE_START_ADDRESS_LESS_D0000 2105
-; AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 2106
-; AGESA_DEALLOCATE_CACHE_REGIONS 2107
-CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR EQU 008002100h
-; Core Leveling (AppFunction = 22h)
-CPU_WARNING_ADJUSTED_LEVELING_MODE EQU 008002200h
-; HT Assist (AppFunction = 23h)
-CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG EQU 008002300h
-; SCS initialization (AppFunction = 24h)
-; AGESA_SCS_HEAP_ENTRY_MISSING 2401
-; AGESA_SCS_BUFFER_EMPTY 2402
-; AGESA_SCS_WEIGHTS_MISMATCH 2403
-CPU_EVENT_SCS_INITIALIZATION_ERROR EQU 008002400h
-
-; CPU Build Configuration structures and definitions
-
-; Build Configuration values for BLDGCFG_AP_MTRR_SETTINGS
-AP_MTRR_SETTINGS STRUCT
- MsrAddr UINT32 ? ; < Fixed-Sized MTRR address
- MsrData UINT64 ? ; < MTRR Settings
-AP_MTRR_SETTINGS ENDS
-
-AMD_AP_MTRR_FIX64k_00000 EQU 000000250h
-AMD_AP_MTRR_FIX16k_80000 EQU 000000258h
-AMD_AP_MTRR_FIX16k_A0000 EQU 000000259h
-AMD_AP_MTRR_FIX4k_C0000 EQU 000000268h
-AMD_AP_MTRR_FIX4k_C8000 EQU 000000269h
-AMD_AP_MTRR_FIX4k_D0000 EQU 00000026Ah
-AMD_AP_MTRR_FIX4k_D8000 EQU 00000026Bh
-AMD_AP_MTRR_FIX4k_E0000 EQU 00000026Ch
-AMD_AP_MTRR_FIX4k_E8000 EQU 00000026Dh
-AMD_AP_MTRR_FIX4k_F0000 EQU 00000026Eh
-AMD_AP_MTRR_FIX4k_F8000 EQU 00000026Fh
-CPU_LIST_TERMINAL EQU 0FFFFFFFFh
-
-; ***********************************************************************
-; *
-; * AGESA interface Call-Out function parameter structures
-; *
-; **********************************************************************
-
- ; Parameters structure for interface call-out AgesaAllocateBuffer
-AGESA_BUFFER_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- BufferLength UINT32 ? ; < Size of buffer to allocate
- BufferHandle UINT32 ? ; < Identifier or name for the buffer
- BufferPointer POINTER ? ; < location of the created buffer
-AGESA_BUFFER_PARAMS ENDS
-
- ; Parameters structure for interface call-out AgesaRunCodeOnAp
-AP_EXE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- FunctionNumber UINT32 ? ; < Index of the procedure to execute
- RelatedDataBlock POINTER ? ; < Location of data structure the procedure will use
- RelatedBlockLength UINT32 ? ; < Size of the related data block
-AP_EXE_PARAMS ENDS
-
- ; Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery
-AGESA_READ_SPD_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < standard header
- SocketId UINT8 ? ; < Address of SPD - socket ID
- MemChannelId UINT8 ? ; < Address of SPD - memory channel ID
- DimmId UINT8 ? ; < Address of SPD - DIMM ID
- Buffer POINTER ? ; < Location where to place the SPD content
- MemData POINTER ? ; < Location of the MemData structure, for reference
-AGESA_READ_SPD_PARAMS ENDS
-
-; VoltageType values
- VTYPE_CPU_VREF EQU 0 ; < Cpu side Vref
- VTYPE_DIMM_VREF EQU 1 ; < Dimm Side Vref
- VTYPE_VDDIO EQU 2 ; < Vddio
-VTYPE TEXTEQU <DWORD>
-
-; Parameters structure for the interface call-out AgesaExternalVoltageAdjust
-VOLTAGE_ADJUST STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard configuration header
- MemData POINTER ? ; < Location of the MemData structure, for reference
- VoltageType VTYPE ? ; < Which Voltage Type to adjust
- AdjustValue INT8 ? ; < Positive/Negative Ajdust Value
-VOLTAGE_ADJUST ENDS
-
- ; Buffer Handles
- AMD_DMI_INFO_BUFFER_HANDLE EQU 000D000h ; < Assign 0x000D000 buffer handle to DMI function
- AMD_PSTATE_DATA_BUFFER_HANDLE EQU 000D001h ; < Assign 0x000D001 buffer handle to Pstate data
- AMD_PSTATE_ACPI_BUFFER_HANDLE EQU 000D002h ; < Assign 0x000D002 buffer handle to Pstate table
- AMD_BRAND_ID_BUFFER_HANDLE EQU 000D003h ; < Assign 0x000D003 buffer handle to Brand ID
- AMD_ACPI_SLIT_BUFFER_HANDLE EQU 000D004h ; < Assign 0x000D004 buffer handle to SLIT function
- AMD_SRAT_INFO_BUFFER_HANDLE EQU 000D005h ; < Assign 0x000D005 buffer handle to SRAT function
- AMD_WHEA_BUFFER_HANDLE EQU 000D006h ; < Assign 0x000D006 buffer handle to WHEA function
- AMD_S3_INFO_BUFFER_HANDLE EQU 000D007h ; < Assign 0x000D007 buffer handle to S3 function
- AMD_S3_NB_INFO_BUFFER_HANDLE EQU 000D008h ; < Assign 0x000D008 buffer handle to S3 NB device info
- AMD_ACPI_ALIB_BUFFER_HANDLE EQU 000D009h ; < Assign 0x000D009 buffer handle to ALIB SSDT table
- AMD_ACPI_IVRS_BUFFER_HANDLE EQU 000D00Ah ; < Assign 0x000D00A buffer handle to IOMMU IVRS table
- AMD_CRAT_INFO_BUFFER_HANDLE EQU 000D00Bh ; < Assign 0x000D00B buffer handle to CRAT function
- AMD_ACPI_CDIT_BUFFER_HANDLE EQU 000D00Ch ; < Assign 0x000D00C buffer handle to CDIT function
-AMD_BUFFER_HANDLE TEXTEQU <DWORD>
-; ***********************************************************************
-; *
-; * AGESA interface Call-Out function prototypes
-; *
-; **********************************************************************
-
-; ***********************************************************************
-; *
-; * AGESA interface structure definition and function prototypes
-; *
-; **********************************************************************
-
-; *********************************************************************
-; * Platform Configuration: The parameters in boot branch function
-; *********************************************************************
-
-; The possible platform control flow settings.
- Nfcm EQU 0 ; < Normal Flow Control Mode.
- UmaDr EQU 1 ; < UMA using Display Refresh flow control.
- UmaIfcm EQU 2 ; < UMA using Isochronous Flow Control.
- Ifcm EQU 3 ; < Isochronous Flow Control Mode (other than for UMA).
- Iommu EQU 4 ; < An IOMMU is in use in the system.
- MaxControlFlow EQU 5 ; < Not a control flow mode, use for limit checking.
-PLATFORM_CONTROL_FLOW TEXTEQU <DWORD>
-
-; Platform Deemphasis Levels.
- DeemphasisLevelNone EQU 0 ; < No Deemphasis.
- DeemphasisLevelMinus3 EQU 1 ; < Minus 3 db deemphasis.
- DeemphasisLevelMinus6 EQU 2 ; < Minus 6 db deemphasis.
- DeemphasisLevelMinus8 EQU 3 ; < Minus 8 db deemphasis.
- DeemphasisLevelMinus11 EQU 4 ; < Minus 11 db deemphasis.
- DeemphasisLevelMinus11pre8 EQU 5 ; < Minus 11, Minus 8 precursor db deemphasis.
- DcvLevelNone EQU 16 ; < No DCV Deemphasis.
- DcvLevelMinus2 EQU 17 ; < Minus 2 db DCV deemphasis.
- DcvLevelMinus3 EQU 18 ; < Minus 3 db DCV deemphasis.
- DcvLevelMinus5 EQU 19 ; < Minus 5 db DCV deemphasis.
- DcvLevelMinus6 EQU 20 ; < Minus 6 db DCV deemphasis.
- DcvLevelMinus7 EQU 21 ; < Minus 7 db DCV deemphasis.
- DcvLevelMinus8 EQU 22 ; < Minus 8 db DCV deemphasis.
- DcvLevelMinus9 EQU 23 ; < Minus 9 db DCV deemphasis.
- DcvLevelMinus11 EQU 24 ; < Minus 11 db DCV deemphasis.
- MaxPlatformDeemphasisLevel EQU 25 ; < Not a deemphasis level, use for limit checking.
-PLATFORM_DEEMPHASIS_LEVEL TEXTEQU <DWORD>
-
-; Provide Deemphasis Levels for HT Links.
-;
-; For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will
-; be checked for a match. The item matches for a Socket, Link if the link frequency is
-; is in the inclusive range HighFreq:LoFreq.
-; AGESA does not set deemphasis in IO devices, only in processors.
-
-CPU_HT_DEEMPHASIS_LEVEL STRUCT
- ; Match fields
- Socket UINT8 ? ; < One Socket on which this Link is located
- Link UINT8 ? ; < The Link on this Processor.
- LoFreq UINT8 ? ; < If the link is set to this frequency or greater, apply these levels, and
- HighFreq UINT8 ? ; < If the link is set to this frequency or less, apply these levels.
- ; Value fields
- ReceiverDeemphasis PLATFORM_DEEMPHASIS_LEVEL ? ; < The deemphasis level for this link
- DcvDeemphasis PLATFORM_DEEMPHASIS_LEVEL ? ; < The DCV, or far transmitter deemphasis level.
-CPU_HT_DEEMPHASIS_LEVEL ENDS
-
-; The possible hardware prefetch mode settings.
- HARDWARE_PREFETCHER_AUTO EQU 0 ; Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
- DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES EQU 1 ; Use the recommended setting for the hardware prefetcher, but disable training on software prefetches.
- DISABLE_L1_PREFETCHER EQU 2 ; Use the recommended settings for the hardware prefetcher, but disable L1 prefetching and above.
- DISABLE_L1_PREFETCHER_AND_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES EQU 3 ; (deprecated) - This setting is deprecated; it has the same effect as DISABLE_L1_PREFETCHER
- DISABLE_L2_STRIDE_PREFETCHER EQU 4 ; Use the recommended settings for the hardware prefetcher, but disable the L2 stride prefetcher and above
- DISABLE_HARDWARE_PREFETCH EQU 5 ; Disable hardware prefetching.
- MAX_HARDWARE_PREFETCH_MODE EQU 6 ; Not a hardware prefetch mode, use for limit checking.
-HARDWARE_PREFETCH_MODE TEXTEQU <DWORD>
-
-; The possible software prefetch mode settings.
- SOFTWARE_PREFETCHES_AUTO EQU 0 ; Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
- DISABLE_SOFTWARE_PREFETCHES EQU 1 ; Disable software prefetches (convert software prefetch instructions to NOP).
- MAX_SOFTWARE_PREFETCH_MODE EQU 2 ; Not a software prefetch mode, use for limit checking.
-SOFTWARE_PREFETCH_MODE TEXTEQU <DWORD>
-
-; Advanced performance tunings, prefetchers.
-; These settings provide for performance tuning to optimize for specific workloads.
-ADVANCED_PERFORMANCE_PROFILE STRUCT
- HardwarePrefetchMode HARDWARE_PREFETCH_MODE ? ; This value provides for advanced performance tuning by controlling the hardware prefetcher setting.
- SoftwarePrefetchMode SOFTWARE_PREFETCH_MODE ? ; This value provides for advanced performance tuning by controlling the software prefetch instructions.
- DramPrefetchMode DRAM_PREFETCH_MODE ? ; This value provides for advanced performance tuning by controlling the DRAM prefetcher setting.
-ADVANCED_PERFORMANCE_PROFILE ENDS
-
-; The possible platform power policy settings.
- Performance EQU 0 ; < Optimize for performance.
- BatteryLife EQU 1 ; < Optimize for battery life.
- MaxPowerPolicy EQU 2 ; < Not a power policy mode, use for limit checking.
-PLATFORM_POWER_POLICY TEXTEQU <DWORD>
-
-; Platform performance settings for optimized settings.
-; Several configuration settings for the processor depend upon other parts and
-; general designer choices for the system. The determination of these data points
-; is not standard for all platforms, so the host environment needs to provide these
-; to specify how the system is to be configured.
-PERFORMANCE_PROFILE STRUCT
- PlatformControlFlowMode PLATFORM_CONTROL_FLOW ? ; < The platform's control flow mode for optimum platform performance.
- UseHtAssist BOOLEAN ? ; < HyperTransport link traffic optimization.
- UseAtmMode BOOLEAN ? ; < HyperTransport link traffic optimization.
- UseNeighborCache BOOLEAN ? ; < Neighbor cache mode
- Use32ByteRefresh BOOLEAN ? ; < Display Refresh traffic generates 32 byte requests.
- UseVariableMctIsocPriority BOOLEAN ? ; < The Memory controller will be set to Variable Isoc Priority.
- AdvancedPerformanceProfile ADVANCED_PERFORMANCE_PROFILE {} ; < The advanced platform performance settings.
- PlatformPowerPolicy PLATFORM_POWER_POLICY ? ; < The platform's desired power policy
- NbPstatesSupported BOOLEAN ? ; < The Nb-Pstates is supported or not
-PERFORMANCE_PROFILE ENDS
-
-; Platform settings that describe the voltage regulator modules of the system.
-; Many power management settings are dependent upon the characteristics of the
-; on-board voltage regulator module (VRM). The host environment needs to provide
-; these to specify how the system is to be configured.
-PLATFORM_VRM_CONFIGURATION STRUCT
- CurrentLimit UINT32 ? ; < Vrm Current Limit.
- LowPowerThreshold UINT32 ? ; < Vrm Low Power Threshold.
- SlewRate UINT32 ? ; < Vrm Slew Rate.
- HiSpeedEnable BOOLEAN ? ; < Select high speed VRM.
- MaximumCurrentLimit UINT32 ? ; < Vrm Maximum Current Limit.
- SviOcpLevel UINT32 ? ; < Vrm SVI OCP Level.
-PLATFORM_VRM_CONFIGURATION ENDS
-
-; The VRM types to characterize.
- CoreVrm EQU 0 ; < VDD plane.
- NbVrm EQU 1 ; < VDDNB plane.
- MaxVrmType EQU 2 ; < Not a valid VRM type, use for limit checking.
-PLATFORM_VRM_TYPE TEXTEQU <DWORD>
-
-; FCH Platform Configuration Policy
-FCH_PLATFORM_POLICY STRUCT
- CfgSmbus0BaseAddress UINT16 ? ; SMBUS0 Controller Base Address
- CfgSmbus1BaseAddress UINT16 ? ; SMBUS1 Controller Base Address
- CfgSioPmeBaseAddress UINT16 ? ; I/O base address for LPC I/O target range
- CfgAcpiPm1EvtBlkAddr UINT16 ? ; I/O base address of ACPI power management Event Block
- CfgAcpiPm1CntBlkAddr UINT16 ? ; I/O base address of ACPI power management Control Block
- CfgAcpiPmTmrBlkAddr UINT16 ? ; I/O base address of ACPI power management Timer Block
- CfgCpuControlBlkAddr UINT16 ? ; I/O base address of ACPI power management CPU Control Block
- CfgAcpiGpe0BlkAddr UINT16 ? ; I/O base address of ACPI power management General Purpose Event Block
- CfgSmiCmdPortAddr UINT16 ? ; I/O base address of ACPI SMI Command Block
- CfgAcpiPmaCntBlkAddr UINT16 ? ; I/O base address of ACPI power management additional control block
- CfgGecShadowRomBase UINT32 ? ; 32-bit base address to the GEC shadow ROM
- CfgWatchDogTimerBase UINT32 ? ; Watchdog Timer base address
- CfgSpiRomBaseAddress UINT32 ? ; Base address for the SPI ROM controller
- CfgHpetBaseAddress UINT32 ? ; HPET MMIO base address
- CfgAzaliaSsid UINT32 ? ; Subsystem ID of HD Audio controller
- CfgSmbusSsid UINT32 ? ; Subsystem ID of SMBUS controller
- CfgIdeSsid UINT32 ? ; Subsystem ID of IDE controller
- CfgSataAhciSsid UINT32 ? ; Subsystem ID of SATA controller in AHCI mode
- CfgSataIdeSsid UINT32 ? ; Subsystem ID of SATA controller in IDE mode
- CfgSataRaid5Ssid UINT32 ? ; Subsystem ID of SATA controller in RAID5 mode
- CfgSataRaidSsid UINT32 ? ; Subsystem ID of SATA controller in RAID mode
- CfgEhciSsid UINT32 ? ; Subsystem ID of EHCI
- CfgOhciSsid UINT32 ? ; Subsystem ID of OHCI
- CfgLpcSsid UINT32 ? ; Subsystem ID of LPC ISA Bridge
- CfgSdSsid UINT32 ? ; Subsystem ID of SecureDigital controller
- CfgXhciSsid UINT32 ? ; Subsystem ID of XHCI
- CfgFchPort80BehindPcib BOOLEAN ? ; Is port80 cycle going to the PCI bridge
- CfgFchEnableAcpiSleepTrap BOOLEAN ? ; ACPI sleep SMI enable/disable
- CfgFchGppLinkConfig GPP_LINKMODE ? ; FCH GPP link configuration
- CfgFchGppPort0Present BOOLEAN ? ; Is FCH GPP port 0 present
- CfgFchGppPort1Present BOOLEAN ? ; Is FCH GPP port 1 present
- CfgFchGppPort2Present BOOLEAN ? ; Is FCH GPP port 2 present
- CfgFchGppPort3Present BOOLEAN ? ; Is FCH GPP port 3 present
- CfgFchGppPort0HotPlug BOOLEAN ? ; Is FCH GPP port 0 hotplug capable
- CfgFchGppPort1HotPlug BOOLEAN ? ; Is FCH GPP port 1 hotplug capable
- CfgFchGppPort2HotPlug BOOLEAN ? ; Is FCH GPP port 2 hotplug capable
- CfgFchGppPort3HotPlug BOOLEAN ? ; Is FCH GPP port 3 hotplug capable
-
- CfgFchEsataPortBitMap UINT8 ? ; ESATA Port definition, eg: [0]=1, means port 0 is ESATA capable
- CfgFchIrPinControl UINT8 ? ; Register bitfield describing Infrared Pin Control:
- CfgFchSdClockControl SD_CLOCK_CONTROL ? ; FCH SD Clock Control
- CfgFchSciMapControl POINTER ? ; FCH SCI Mapping Control
- CfgFchSataPhyControl POINTER ? ; FCH SATA PHY Control
- CfgFchGpioControl POINTER ? ; FCH GPIO Control
- CfgFchRtcWorkaround BOOLEAN ? ; FCH RTC Workaround
-FCH_PLATFORM_POLICY ENDS
-
-
-; Build Option/Configuration Boolean Structure
-BUILD_OPT_CFG STRUCT
- ; Build Option Area
- VersionString AMD_CODE_HEADER {} ; < AMD embedded code version string
- OptionUDimms BOOLEAN ? ; < UDIMMS
- OptionRDimms BOOLEAN ? ; < RDIMMS
- OptionLrDimms BOOLEAN ? ; < LRDIMMS
- OptionEcc BOOLEAN ? ; < ECC
- OptionBankInterleave BOOLEAN ? ; < BANK_INTERLEAVE
- OptionDctInterleave BOOLEAN ? ; < DCT_INTERLEAVE
- OptionNodeInterleave BOOLEAN ? ; < NODE_INTERLEAVE
- OptionParallelTraining BOOLEAN ? ; < PARALLEL_TRAINING
- OptionOnlineSpare BOOLEAN ? ; < ONLINE_SPARE
- OptionMemRestore BOOLEAN ? ; < MEM CONTEXT RESTORE
- OptionMultisocket BOOLEAN ? ; < MULTISOCKET
- OptionAcpiPstates BOOLEAN ? ; < ACPI_PSTATES
- OptionPStatesInHpcMode BOOLEAN ? ; < PSTATES_HPC_MODE
- OptionCrat BOOLEAN ? ; < CRAT
- OptionCdit BOOLEAN ? ; < CDIT
- OptionSrat BOOLEAN ? ; < SRAT
- OptionSlit BOOLEAN ? ; < SLIT
- OptionWhea BOOLEAN ? ; < WHEA
- OptionDmi BOOLEAN ? ; < DMI
- OptionEarlySamples BOOLEAN ? ; < EARLY_SAMPLES
- OptionAddrToCsTranslator BOOLEAN ? ; < ADDR_TO_CS_TRANSLATOR
-
- ; Build Configuration Area
- CfgPciMmioAddress UINT64 ? ; < PciMmioBase
- CfgPciMmioSize UINT32 ? ; < PciMmioSize
- CfgPlatVrmCfg PLATFORM_VRM_CONFIGURATION (MaxVrmType) DUP ({}) ; < Several configuration settings for the voltage regulator modules.
- CfgPlatNumIoApics UINT32 ? ; < PlatformApicIoNumber
- CfgMemInitPstate UINT32 ? ; < MemoryInitPstate
- CfgPlatformC1eMode PLATFORM_C1E_MODES ? ; < PlatformC1eMode
- CfgPlatformC1eOpData UINT32 ? ; < PlatformC1eOpData
- CfgPlatformC1eOpData1 UINT32 ? ; < PlatformC1eOpData1
- CfgPlatformC1eOpData2 UINT32 ? ; < PlatformC1eOpData2
- CfgPlatformC1eOpData3 UINT32 ? ; < PlatformC1eOpData3
- CfgPlatformCStateMode PLATFORM_CSTATE_MODES ? ; < PlatformCStateMode
- CfgPlatformCStateOpData UINT32 ? ; < PlatformCStateOpData
- CfgPlatformCStateIoBaseAddress UINT16 ? ; < PlatformCStateIoBaseAddress
- CfgPlatformCpbMode PLATFORM_CPB_MODES ? ; < PlatformCpbMode
- CfgLowPowerPstateForProcHot PLATFORM_LOW_POWER_PSTATE_MODES ? ; < Low power Pstate for PROCHOT mode
- CfgCoreLevelingMode UINT32 ? ; < CoreLevelingCofig
- CfgPerformanceProfile PERFORMANCE_PROFILE {} ; < The platform's control flow mode and platform performance settings.
- CfgPlatformDeemphasisList POINTER ? ; < HT Deemphasis
- CfgAmdPlatformType UINT32 ? ; < AmdPlatformType
- CfgAmdPowerCeiling UINT32 ? ; < PowerCeiling, specifies a maximum power usage limit for the platform
- CfgHtcTemperatureLimit UINT16 ? ; < Hardware Thermal Control temperature limit in tenths of degrees Celsius.
- CfgLhtcTemperatureLimit UINT16 ? ; < Local Hardware Thermal Control temperature limit in tenths of degrees Celsius.
-
- CfgMemoryBusFrequencyLimit UINT32 ? ; < Memory Bus Frequency Limit
- CfgMemoryModeUnganged BOOLEAN ? ; < Memory Mode Unganged
- CfgMemoryQuadRankCapable BOOLEAN ? ; < Memory Quad Rank Capable
- CfgMemoryQuadrankType UINT32 ? ; < Memory Quadrank Type
- CfgMemoryRDimmCapable BOOLEAN ? ; < Memory RDIMM Capable
- CfgMemoryLRDimmCapable BOOLEAN ? ; < Memory LRDIMM Capable
- CfgMemoryUDimmCapable BOOLEAN ? ; < Memory UDIMM Capable
- CfgMemorySODimmCapable BOOLEAN ? ; < Memory SODimm Capable
- CfgLimitMemoryToBelow1Tb BOOLEAN ? ; < Limit memory address space to below 1TB
- CfgMemoryEnableBankInterleaving BOOLEAN ? ; < Memory Enable Bank Interleaving
- CfgMemoryEnableNodeInterleaving BOOLEAN ? ; < Memory Enable Node Interleaving
- CfgMemoryChannelInterleaving BOOLEAN ? ; < Memory Channel Interleaving
- CfgMemoryPowerDown BOOLEAN ? ; < Memory Power Down
- CfgPowerDownMode UINT32 ? ; < Power Down Mode
- CfgOnlineSpare BOOLEAN ? ; < Online Spare
- CfgMemoryParityEnable BOOLEAN ? ; < Memory Parity Enable
- CfgBankSwizzle BOOLEAN ? ; < Bank Swizzle
- CfgTimingModeSelect UINT32 ? ; < Timing Mode Select
- CfgMemoryClockSelect UINT32 ? ; < Memory Clock Select
- CfgDqsTrainingControl BOOLEAN ? ; < Dqs Training Control
- CfgIgnoreSpdChecksum BOOLEAN ? ; < Ignore Spd Checksum
- CfgUseBurstMode BOOLEAN ? ; < Use Burst Mode
- CfgMemoryAllClocksOn BOOLEAN ? ; < Memory All Clocks On
- CfgEnableEccFeature BOOLEAN ? ; < Enable ECC Feature
- CfgEccRedirection BOOLEAN ? ; < ECC Redirection
- CfgScrubDramRate UINT16 ? ; < Scrub Dram Rate
- CfgScrubL2Rate UINT16 ? ; < Scrub L2Rate
- CfgScrubL3Rate UINT16 ? ; < Scrub L3Rate
- CfgScrubIcRate UINT16 ? ; < Scrub Ic Rate
- CfgScrubDcRate UINT16 ? ; < Scrub Dc Rate
- CfgEccSyncFlood BOOLEAN ? ; < ECC Sync Flood
- CfgEccSymbolSize UINT16 ? ; < ECC Symbol Size
- CfgHeapDramAddress UINT64 ? ; < Heap contents will be temporarily stored in this address during the transition
- CfgNodeMem1GBAlign BOOLEAN ? ; < Node Mem 1GB boundary Alignment
- CfgS3LateRestore BOOLEAN ? ; < S3 Late Restore
- CfgAcpiPstateIndependent BOOLEAN ? ; < PSD method dependent/Independent
- CfgAcpiPstatesPsdPolicy UINT32 ? ; < PSD policy
- CfgApMtrrSettingsList POINTER ? ; < The AP's MTRR settings before final halt
- CfgUmaMode UMA_MODE ? ; < Uma Mode
- CfgUmaSize UINT32 ? ; < Uma Size [31:0]=Addr[47:16]
- CfgUmaAbove4G BOOLEAN ? ; < Uma Above 4G Support
- CfgUmaAlignment UMA_ALIGNMENT ? ; < Uma alignment
- CfgProcessorScopeInSb BOOLEAN ? ; < ACPI Processor Object in \_SB scope
- CfgProcessorScopeName0 CHAR8 ? ; < OEM specific 1st character of processor scope name.
- CfgProcessorScopeName1 CHAR8 ? ; < OEM specific 2nd character of processor scope name.
- CfgGnbHdAudio UINT8 ? ; < Gnb HD Audio Enable
- CfgAbmSupport UINT8 ? ; < ABM support
- CfgDynamicRefreshRate UINT8 ? ; < Dynamic refresh rate
- CfgLcdBackLightControl UINT16 ? ; < Lcd back light control
- CfgGnb3dStereoPinIndex UINT8 ? ; < 3D Stereo Pin ID
- CfgTempPcieMmioBaseAddress UINT32 ? ; < Temp pcie MMIO base address
- CfgGnbIGPUSSID UINT32 ? ; < Gnb internal GPU SSID
- CfgGnbHDAudioSSID UINT32 ? ; < Gnb HD Audio SSID
- CfgGnbPcieSSID UINT32 ? ; < Gnb PCIe SSID
- CfgLvdsSpreadSpectrum UINT16 ? ; < Lvds Spread Spectrum. Build-time customizable only
- CfgLvdsSpreadSpectrumRate UINT16 ? ; < Lvds Spread Spectrum Rate. Build-time customizable only
- FchBldCfg POINTER ? ; < FCH platform build configuration policy
- CfgIommuSupport BOOLEAN ? ; IOMMU support
- CfgLvdsPowerOnSeqDigonToDe UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqDeToVaryBl UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqDeToDigon UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqVaryBlToDe UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqOnToOffDelay UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqVaryBlToBlon UINT8 ? ; Panel initialization timing
- CfgLvdsPowerOnSeqBlonToVaryBl UINT8 ? ; Panel initialization timing
- CfgLvdsMaxPixelClockFreq UINT16 ? ; The maximum pixel clock frequency supported
- CfgLcdBitDepthControlValue UINT32 ? ; The LCD bit depth control settings
- CfgLvds24bbpPanelMode UINT8 ? ; The LVDS 24 BBP mode
- CfgLvdsMiscControl LVDS_MISC_CONTROL {}; THe LVDS Misc control
- CfgPcieRefClkSpreadSpectrum UINT16 ? ; PCIe Reference Clock Spread Spectrum
- CfgExternalVrefCtlFeature BOOLEAN ? ; External Vref control
- CfgForceTrainMode FORCE_TRAIN_MODE ? ; < Force Train Mode
- CfgGnbRemoteDisplaySupport BOOLEAN ? ; Wireless Display Support
- CfgIvrsExclusionRangeList POINTER ? ; IOMMU Exclusion Range List
- CfgGnbSyncFloodPinAsNmi BOOLEAN ? ; Define function of NMI_SYNCFLOOD as NMI
- CfgIgpuEnableDisablePolicy UINT8 ? ; This item defines the iGPU Enable/Disable policy
- CfgGnbSwTjOffset UINT8 ? ; Software-writeable TjOffset
- CfgLvdsMiscVoltAdjustment UINT8 ? ; Register LVDS_CTRL_4 to adjust LVDS output voltage
- CfgDisplayMiscControl DISPLAY_MISC_CONTROL {}; The Display Misc control
- CfgDpFixedVoltSwingType DP_FIXED_VOLT_SWING_TYPE ? ;To indicate fixed voltage swing value
- CfgDimmTypeUsedInMixedConfig TECHNOLOGY_TYPE ? ; Select the preferred technology type that AGESA will enable
- ; when it is mixed with other technology types.
- CfgHybridBoostEnable BOOLEAN ? ; HyBrid Boost support
- CfgGnbIoapicAddress UINT64 ? ; GNB IOAPIC Base Address(NULL if platform configured)
- CfgDataEyeEn BOOLEAN ? ; Enable get 2D data eye
- CfgDockedTdpHeadroom BOOLEAN ? ; Configure Docked Tdp Headroom.
- CfgDramDoubleRefreshRateEn BOOLEAN ? ; Double DRAM refresh rate
- Reserved BOOLEAN ? ; < reserved...
-BUILD_OPT_CFG ENDS
-
- ; A structure containing platform specific operational characteristics. This
- ; structure is initially populated by the initializer with a copy of the same
- ; structure that was created at build time using the build configuration controls.
-PLATFORM_CONFIGURATION STRUCT
- PlatformProfile PERFORMANCE_PROFILE {} ; < Several configuration settings for the processor.
- PlatformDeemphasisList POINTER ? ; < Deemphasis levels for the platform's HT links.
- CoreLevelingMode UINT8 ? ; < Indicates how to balance the number of cores per processor.
- C1eMode PLATFORM_C1E_MODES ? ; < Specifies the method of C1e enablement - Disabled, HW, or message based.
- C1ePlatformData UINT32 ? ; < If C1eMode is HW, specifies the P_LVL3 I/O port of the platform.
- C1ePlatformData1 UINT32 ? ; < If C1eMode is SW, specifies the address of chipset's SMI command port.
- C1ePlatformData2 UINT32 ? ; < If C1eMode is SW, specifies the unique number used by the SMI handler to identify SMI source.
- C1ePlatformData3 UINT32 ? ; < If C1eMode is Auto, specifies the P_LVL3 I/O port of the platform for HW C1e
- CStateMode PLATFORM_CSTATE_MODES ? ; < Specifies the method of C-State enablement - Disabled, or C6.
- CStatePlatformData UINT32 ? ; < This element specifies some pertinent data needed for the operation of the Cstate feature
- ; < If CStateMode is CStateModeC6, this item is reserved
- CStateIoBaseAddress UINT16 ? ; < This item specifies a free block of 8 consecutive bytes of I/O ports that
- ; < can be used to allow the CPU to enter Cstates.
- CpbMode PLATFORM_CPB_MODES ? ; < Specifies the method of core performance boost enablement - Disabled, or Auto.
- UserOptionDmi BOOLEAN ? ; < When set to TRUE, the DMI data table is generated.
- UserOptionPState BOOLEAN ? ; < When set to TRUE, the PState data tables are generated.
- UserOptionCrat BOOLEAN ? ; < When set to TRUE, the CRAT data table is generated.
- UserOptionCdit BOOLEAN ? ; < When set to TRUE, the CDIT data table is generated.
- UserOptionSrat BOOLEAN ? ; < When set to TRUE, the SRAT data table is generated.
- UserOptionSlit BOOLEAN ? ; < When set to TRUE, the SLIT data table is generated.
- UserOptionWhea BOOLEAN ? ; < When set to TRUE, the WHEA data table is generated.
- LowPowerPstateForProcHot PLATFORM_LOW_POWER_PSTATE_MODES ? ; < Specifies the method of low power Pstate for PROCHOT enablement - Disabled, or Auto.
- PowerCeiling UINT32 ? ; < P-State Ceiling Enabling Deck - Max power milli-watts.
- ForcePstateIndependent BOOLEAN ? ; < Deprecated in favor of PstatesPsdPolicy.
- ; < P-State _PSD is forced independent.
- PstatesPsdPolicy UINT32 ? ; < P-State _PSD policy
- PStatesInHpcMode BOOLEAN ? ; < High performance computing (HPC) mode
- NumberOfIoApics UINT32 ? ; < Number of I/O APICs in the system
- VrmProperties PLATFORM_VRM_CONFIGURATION (MaxVrmType) DUP ({}) ; < Several configuration settings for the voltage regulator modules.
- ProcessorScopeInSb BOOLEAN ? ; < ACPI Processor Object in \_SB scope
- ProcessorScopeName0 CHAR8 ? ; < OEM specific 1st character of processor scope name.
- ProcessorScopeName1 CHAR8 ? ; < OEM specific 2nd character of processor scope name.
- GnbHdAudio UINT8 ? ; < Control GFX HD Audio controller(Used for HDMI and DP display output),
- ; < essentially it enables function 1 of graphics device.
- ; < @li 0 = HD Audio disable
- ; < @li 1 = HD Audio enable
- AbmSupport UINT8 ? ; < Automatic adjust LVDS/eDP Back light level support.It is
- ; < characteristic specific to display panel which used by platform design.
- ; < @li 0 = ABM support disabled
- ; < @li 1 = ABM support enabled
- DynamicRefreshRate UINT8 ? ; < Adjust refresh rate on LVDS/eDP.
- LcdBackLightControl UINT16 ? ; < The PWM frequency to LCD backlight control.
- ; < If equal to 0 backlight not controlled by iGPU.
- HtcTemperatureLimit UINT16 ? ; < The Hardware Thermal Control temperature limit in tenths of degrees Celsius.
- ; < If equal to 0, use hardware defaults.
- LhtcTemperatureLimit UINT16 ? ; < The Local Hardware Thermal Control temperature limit in tenths of degrees Celsius.
- ; < If equal to 0, use hardware defaults.
-PLATFORM_CONFIGURATION ENDS
-
-
-; *********************************************************************
-; * Structures for: AmdInitLate
-; *********************************************************************
- PROC_VERSION_LENGTH EQU 48
- MAX_DIMMS_PER_SOCKET EQU 16
- PROC_MANU_LENGTH EQU 29
-
- ; Interface Parameter Structures
- ; DMI Type4 - Processor ID
-TYPE4_PROC_ID STRUCT
- ProcIdLsd UINT32 ? ; < Lower half of 64b ID
- ProcIdMsd UINT32 ? ; < Upper half of 64b ID
-TYPE4_PROC_ID ENDS
-
- ; DMI Type 4 - Processor information
-TYPE4_DMI_INFO STRUCT
- T4ProcType UINT8 ? ; < CPU Type
- T4ProcFamily UINT8 ? ; < Family 1
- T4ProcId TYPE4_PROC_ID {} ; < Id
- T4Voltage UINT8 ? ; < Voltage
- T4ExternalClock UINT16 ? ; < External clock
- T4MaxSpeed UINT16 ? ; < Max speed
- T4CurrentSpeed UINT16 ? ; < Current speed
- T4Status UINT8 ? ; < Status
- T4ProcUpgrade UINT8 ? ; < Up grade
- T4CoreCount UINT8 ? ; < Core count
- T4CoreEnabled UINT8 ? ; < Core Enable
- T4ThreadCount UINT8 ? ; < Thread count
- T4ProcCharacteristics UINT16 ? ; < Characteristics
- T4ProcFamily2 UINT16 ? ; < Family 2
- T4ProcVersion CHAR8 (PROC_VERSION_LENGTH) DUP (?) ; < Cpu version
- T4ProcManufacturer CHAR8 (PROC_MANU_LENGTH) DUP (?) ; < Manufacturer
-TYPE4_DMI_INFO ENDS
-
- ; DMI Type 7 - Cache information
-TYPE7_DMI_INFO STRUCT
- T7CacheCfg UINT16 ? ; < Cache cfg
- T7MaxCacheSize UINT16 ? ; < Max size
- T7InstallSize UINT16 ? ; < Install size
- T7SupportedSramType UINT16 ? ; < Supported Sram Type
- T7CurrentSramType UINT16 ? ; < Current type
- T7CacheSpeed UINT8 ? ; < Speed
- T7ErrorCorrectionType UINT8 ? ; < ECC type
- T7SystemCacheType UINT8 ? ; < Cache type
- T7Associativity UINT8 ? ; < Associativity
-TYPE7_DMI_INFO ENDS
-
- ; DMI Type 16 offset 04h - Location
-
- OtherLocation EQU 01h ; < Assign 01 to Other
- UnknownLocation EQU 2 ; < Assign 02 to Unknown
- SystemboardOrMotherboard EQU 3 ; < Assign 03 to systemboard or motherboard
- IsaAddonCard EQU 4 ; < Assign 04 to ISA add-on card
- EisaAddonCard EQU 5 ; < Assign 05 to EISA add-on card
- PciAddonCard EQU 6 ; < Assign 06 to PCI add-on card
- McaAddonCard EQU 7 ; < Assign 07 to MCA add-on card
- PcmciaAddonCard EQU 8 ; < Assign 08 to PCMCIA add-on card
- ProprietaryAddonCard EQU 9 ; < Assign 09 to proprietary add-on card
- NuBus EQU 10 ; < Assign 0A to NuBus
- Pc98C20AddonCard EQU 11 ; < Assign 0A0 to PC-98/C20 add-on card
- Pc98C24AddonCard EQU 12 ; < Assign 0A1 to PC-98/C24 add-on card
- Pc98EAddoncard EQU 13 ; < Assign 0A2 to PC-98/E add-on card
- Pc98LocalBusAddonCard EQU 14 ; < Assign 0A3 to PC-98/Local bus add-on card
-DMI_T16_LOCATION TEXTEQU <DWORD> ;} DMI_T16_LOCATION;
-
- ; DMI Type 16 offset 05h - Memory Error Correction
-
- OtherUse EQU 01h ; < Assign 01 to Other
- UnknownUse EQU 2 ; < Assign 02 to Unknown
- SystemMemory EQU 3 ; < Assign 03 to system memory
- VideoMemory EQU 4 ; < Assign 04 to video memory
- FlashMemory EQU 5 ; < Assign 05 to flash memory
- NonvolatileRam EQU 6 ; < Assign 06 to non-volatile RAM
- CacheMemory EQU 7 ; < Assign 07 to cache memory
-DMI_T16_USE TEXTEQU <DWORD> ;} DMI_T16_USE;
-
- ; DMI Type 16 offset 07h - Maximum Capacity
-
- Dmi16OtherErrCorrection EQU 01h ; < Assign 01 to Other
- Dmi16UnknownErrCorrection EQU 2 ; < Assign 02 to Unknown
- Dmi16NoneErrCorrection EQU 3 ; < Assign 03 to None
- Dmi16Parity EQU 4 ; < Assign 04 to parity
- Dmi16SingleBitEcc EQU 5 ; < Assign 05 to Single-bit ECC
- Dmi16MultiBitEcc EQU 6 ; < Assign 06 to Multi-bit ECC
- Dmi16Crc EQU 7 ; < Assign 07 to CRC
-DMI_T16_ERROR_CORRECTION TEXTEQU <DWORD> ;} DMI_T16_ERROR_CORRECTION;
-
- ; DMI Type 16 - Physical Memory Array
-TYPE16_DMI_INFO STRUCT
- Location DMI_T16_LOCATION ? ; < The physical location of the Memory Array,
- ; < whether on the system board or an add-in board.
- Use DMI_T16_USE ? ; < Identifies the function for which the array
- ; < is used.
- MemoryErrorCorrection DMI_T16_ERROR_CORRECTION ? ; < The primary hardware error correction or
- ; < detection method supported by this memory array.
- MaximumCapacity UINT32 ? ; < The maximum memory capacity, in kilobytes,
- ; < for the array.
- NumberOfMemoryDevices UINT16 ? ; < The number of slots or sockets available
- ; < for memory devices in this array.
- ExtMaxCapacity UINT64 ? ; < The maximum memory capacity, in bytes,
- ; < for this array.
-TYPE16_DMI_INFO ENDS
-
- ; DMI Type 17 offset 0Eh - Form Factor
- OtherFormFactor EQU 01h ; < Assign 01 to Other
- UnknowFormFactor EQU 2 ; < Assign 02 to Unknown
- SimmFormFactor EQU 3 ; < Assign 03 to SIMM
- SipFormFactor EQU 4 ; < Assign 04 to SIP
- ChipFormFactor EQU 5 ; < Assign 05 to Chip
- DipFormFactor EQU 6 ; < Assign 06 to DIP
- ZipFormFactor EQU 7 ; < Assign 07 to ZIP
- ProprietaryCardFormFactor EQU 8 ; < Assign 08 to Proprietary Card
- DimmFormFactorFormFactor EQU 9 ; < Assign 09 to DIMM
- TsopFormFactor EQU 10 ; < Assign 10 to TSOP
- RowOfChipsFormFactor EQU 11 ; < Assign 11 to Row of chips
- RimmFormFactor EQU 12 ; < Assign 12 to RIMM
- SodimmFormFactor EQU 13 ; < Assign 13 to SODIMM
- SrimmFormFactor EQU 14 ; < Assign 14 to SRIMM
- FbDimmFormFactor EQU 15 ; < Assign 15 to FB-DIMM
-DMI_T17_FORM_FACTOR TEXTEQU <DWORD>
-
- ; DMI Type 17 offset 12h - Memory Type
- OtherMemType EQU 01h ; < Assign 01 to Other
- UnknownMemType EQU 2 ; < Assign 02 to Unknown
- DramMemType EQU 3 ; < Assign 03 to DRAM
- EdramMemType EQU 4 ; < Assign 04 to EDRAM
- VramMemType EQU 5 ; < Assign 05 to VRAM
- SramMemType EQU 6 ; < Assign 06 to SRAM
- RamMemType EQU 7 ; < Assign 07 to RAM
- RomMemType EQU 8 ; < Assign 08 to ROM
- FlashMemType EQU 9 ; < Assign 09 to Flash
- EepromMemType EQU 10 ; < Assign 10 to EEPROM
- FepromMemType EQU 11 ; < Assign 11 to FEPROM
- EpromMemType EQU 12 ; < Assign 12 to EPROM
- CdramMemType EQU 13 ; < Assign 13 to CDRAM
- ThreeDramMemType EQU 14 ; < Assign 14 to 3DRAM
- SdramMemType EQU 15 ; < Assign 15 to SDRAM
- SgramMemType EQU 16 ; < Assign 16 to SGRAM
- RdramMemType EQU 17 ; < Assign 17 to RDRAM
- DdrMemType EQU 18 ; < Assign 18 to DDR
- Ddr2MemType EQU 19 ; < Assign 19 to DDR2
- Ddr2FbdimmMemType EQU 20 ; < Assign 20 to DDR2 FB-DIMM
- Ddr3MemType EQU 24 ; < Assign 24 to DDR3
- Fbd2MemType EQU 25 ; < Assign 25 to FBD2
-DMI_T17_MEMORY_TYPE TEXTEQU <DWORD>
-
- ; DMI Type 17 offset 13h - Type Detail
-DMI_T17_TYPE_DETAIL STRUCT
- Reserved1 UINT16 ?
-; OUT UINT16 Reserved1:1; ; < Reserved
-; OUT UINT16 Other:1; ; < Other
-; OUT UINT16 Unknown:1; ; < Unknown
-; OUT UINT16 FastPaged:1; ; < Fast-Paged
-; OUT UINT16 StaticColumn:1; ; < Static column
-; OUT UINT16 PseudoStatic:1; ; < Pseudo-static
-; OUT UINT16 Rambus:1; ; < RAMBUS
-; OUT UINT16 Synchronous:1; ; < Synchronous
-; OUT UINT16 Cmos:1; ; < CMOS
-; OUT UINT16 Edo:1; ; < EDO
-; OUT UINT16 WindowDram:1; ; < Window DRAM
-; OUT UINT16 CacheDram:1; ; < Cache Dram
-; OUT UINT16 NonVolatile:1; ; < Non-volatile
-; OUT UINT16 Registered:1; ; < Registered (Buffered)
-; OUT UINT16 Unbuffered:1; ; < Unbuffered (Unregistered)
-; OUT UINT16 Reserved2:1; ; < Reserved
-DMI_T17_TYPE_DETAIL ENDS
-
- ; DMI Type 17 - Memory Device
-TYPE17_DMI_INFO STRUCT
- Handle UINT16 ? ; < The temporary handle, or instance number, associated with the structure
- TotalWidth UINT16 ? ; < Total Width, in bits, of this memory device, including any check or error-correction bits.
- DataWidth UINT16 ? ; < Data Width, in bits, of this memory device.
- MemorySize UINT16 ? ; < The size of the memory device.
- FormFactor DMI_T17_FORM_FACTOR ? ; < The implementation form factor for this memory device.
- DeviceSet UINT8 ? ; < Identifies when the Memory Device is one of a set of
- ; < Memory Devices that must be populated with all devices of
- ; < the same type and size, and the set to which this device belongs.
- DeviceLocator CHAR8 (8) DUP (?) ; < The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
- BankLocator CHAR8 (10) DUP (?) ; < The string number of the string that identifies the physically labeled bank where the memory device is located.
- MemoryType DMI_T17_MEMORY_TYPE ? ; < The type of memory used in this device.
- TypeDetail DMI_T17_TYPE_DETAIL {} ; < Additional detail on the memory device type
- Speed UINT16 ? ; < Identifies the speed of the device, in megahertz (MHz).
- ManufacturerIdCode UINT64 ? ; < Manufacturer ID code.
- SerialNumber CHAR8 (9) DUP (?) ; < Serial Number.
- PartNumber CHAR8 (19) DUP (?) ; < Part Number.
- Attributes UINT8 ? ; < Bits 7-4: Reserved, Bits 3-0: rank.
- ExtSize UINT32 ? ; < Extended Size.
- ConfigSpeed UINT16 ? ; < Configured memory clock speed
-TYPE17_DMI_INFO ENDS
-
- ; Memory DMI Type 17 - for memory use
-MEM_DMI_PHYSICAL_DIMM_INFO STRUCT
- Socket UINT8 ?
-; OUT UINT8 Socket:3 ; < Socket ID
-; OUT UINT8 Channel:2 ; < Channel ID
-; OUT UINT8 Dimm:2 ; < DIMM ID
-; OUT UINT8 DimmPresent:1 ; < Dimm Present
- Handle UINT16 ? ; < The temporary handle, or instance number, associated with the structure
- TotalWidth UINT16 ? ; < Total Width, in bits, of this memory device, including any check or error-correction bits.
- DataWidth UINT16 ? ; < Data Width, in bits, of this memory device.
- MemorySize UINT16 ? ; < The size of the memory device.
- FormFactor DMI_T17_FORM_FACTOR ? ; < The implementation form factor for this memory device.
- DeviceLocator UINT8 ? ; < The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
- BankLocator UINT8 ? ; < The string number of the string that identifies the physically labeled bank where the memory device is located.
- Speed UINT16 ? ; < Identifies the speed of the device, in megahertz (MHz).
- ManufacturerIdCode UINT64 ? ; < Manufacturer ID code.
- SerialNumber UINT8 (4) DUP (?) ; < Serial Number.
- PartNumber UINT8 (18) DUP (?) ; < Part Number.
- Attributes UINT8 ? ; < Bits 7-4: Reserved, Bits 3-0: rank.
- ExtSize UINT32 ? ; < Extended Size.
- ConfigSpeed UINT16 ? ; < Configured memory clock speed
-MEM_DMI_PHYSICAL_DIMM_INFO ENDS
-
- ; Memory DMI Type 20 - for memory use
-MEM_DMI_LOGICAL_DIMM_INFO STRUCT
- Socket UINT8 ?
-; OUT UINT8 Socket:3 ; < Socket ID
-; OUT UINT8 Channel:2 ; < Channel ID
-; OUT UINT8 Dimm:2 ; < DIMM ID
-; OUT UINT8 DimmPresent:1 ; < Dimm Present
- StartingAddr UINT32 ? ; < The physical address, in kilobytes, of a range
- ; < of memory mapped to the referenced Memory Device.
- EndingAddr UINT32 ? ; < The handle, or instance number, associated with
- ; < the Memory Device structure to which this address
- ; < range is mapped.
- MemoryDeviceHandle UINT16 ? ; < The handle, or instance number, associated with
- ; < the Memory Device structure to which this address
- ; < range is mapped.
- ExtStartingAddr UINT64 ? ; < The physical address, in bytes, of a range of
- ; < memory mapped to the referenced Memory Device.
- ExtEndingAddr UINT64 ? ; < The physical ending address, in bytes, of the last of
- ; < a range of addresses mapped to the referenced Memory Device.
-MEM_DMI_LOGICAL_DIMM_INFO ENDS
-
- ; DMI Type 19 - Memory Array Mapped Address
-TYPE19_DMI_INFO STRUCT
- StartingAddr UINT32 ? ; < The physical address, in kilobytes,
- ; < of a range of memory mapped to the
- ; < specified physical memory array.
- EndingAddr UINT32 ? ; < The physical ending address of the
- ; < last kilobyte of a range of addresses
- ; < mapped to the specified physical memory array.
- MemoryArrayHandle UINT16 ? ; < The handle, or instance number, associated
- ; < with the physical memory array to which this
- ; < address range is mapped.
- PartitionWidth UINT8 ? ; < Identifies the number of memory devices that
- ; < form a single row of memory for the address
- ; < partition defined by this structure.
- ExtStartingAddr UINT64 ? ; < The physical address, in bytes, of a range of
- ; < memory mapped to the specified Physical Memory Array.
- ExtEndingAddr UINT64 ? ; < The physical address, in bytes, of a range of
- ; < memory mapped to the specified Physical Memory Array.
-TYPE19_DMI_INFO ENDS
-
-; DMI Type 20 - Memory Device Mapped Address
-TYPE20_DMI_INFO STRUCT
- StartingAddr UINT32 ? ; < The physical address, in kilobytes, of a range
- ; < of memory mapped to the referenced Memory Device.
- EndingAddr UINT32 ? ; < The handle, or instance number, associated with
- ; < the Memory Device structure to which this address
- ; < range is mapped.
- MemoryDeviceHandle UINT16 ? ; < The handle, or instance number, associated with
- ; < the Memory Device structure to which this address
- ; < range is mapped.
- MemoryArrayMappedAddressHandle UINT16 ? ; < The handle, or instance number, associated
- ; < with the Memory Array Mapped Address structure to
- ; < which this device address range is mapped.
- PartitionRowPosition UINT8 ? ; < Identifies the position of the referenced Memory
- ; < Device in a row of the address partition.
- InterleavePosition UINT8 ? ; < The position of the referenced Memory Device in
- ; < an interleave.
- InterleavedDataDepth UINT8 ? ; < The maximum number of consecutive rows from the
- ; < referenced Memory Device that are accessed in a
- ; < single interleaved transfer.
- ExtStartingAddr UINT64 ? ; < The physical address, in bytes, of a range of
- ; < memory mapped to the referenced Memory Device.
- ExtEndingAddr UINT64 ? ; < The physical ending address, in bytes, of the last of
- ; < a range of addresses mapped to the referenced Memory Device.
-TYPE20_DMI_INFO ENDS
-
- ; Collection of pointers to the DMI records
-DMI_INFO STRUCT
- T4 TYPE4_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 4 struc
- T7L1 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 1
- T7L2 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 2
- T7L3 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 3
- T16 TYPE16_DMI_INFO {} ; < Type 16 struc
- T17 TYPE17_DMI_INFO (MAX_SOCKETS_SUPPORTED * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL) DUP ({}) ; < Type 17 struc
- T19 TYPE19_DMI_INFO {} ; < Type 19 struc
- T20 TYPE20_DMI_INFO (MAX_SOCKETS_SUPPORTED * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL) DUP ({}) ; < Type 20 struc
-DMI_INFO ENDS
-
-
-
-; *********************************************************************
-; * Interface call: AllocateExecutionCache
-; *********************************************************************
- MAX_CACHE_REGIONS EQU 3
-
- ; AllocateExecutionCache sub param structure for cached memory region
-EXECUTION_CACHE_REGION STRUCT
- ExeCacheStartAddr UINT32 ? ; < Start address
- ExeCacheSize UINT32 ? ; < Size
-EXECUTION_CACHE_REGION ENDS
-
-; *********************************************************************
-; * Interface call: AmdGetAvailableExeCacheSize
-; *********************************************************************
- ; Get available Cache remain
-AMD_GET_EXE_SIZE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- AvailableExeCacheSize UINT32 ? ; < Remain size
-AMD_GET_EXE_SIZE_PARAMS ENDS
-
-
-
-
-
-
- ; Selection type for core leveling
- CORE_LEVEL_LOWEST EQU 0 ; < Level to lowest common denominator
- CORE_LEVEL_TWO EQU 1 ; < Level to 2 cores
- CORE_LEVEL_POWER_OF_TWO EQU 2 ; < Level to 1,2,4 or 8
- CORE_LEVEL_NONE EQU 3 ; < Do no leveling
- CORE_LEVEL_COMPUTE_UNIT EQU 4 ; < Level cores to one core per compute unit
- CORE_LEVEL_COMPUTE_UNIT_TWO EQU 5 ; < Level cores to two cores per compute unit
- CORE_LEVEL_COMPUTE_UNIT_THREE EQU 6 ; < Level cores to three cores per compute unit
- CORE_LEVEL_ONE EQU 7 ; < Level to 1 core
- CORE_LEVEL_THREE EQU 8 ; < Level to 3 cores
- CORE_LEVEL_FOUR EQU 9 ; < Level to 4 cores
- CORE_LEVEL_FIVE EQU 10 ; < Level to 5 cores
- CORE_LEVEL_SIX EQU 11 ; < Level to 6 cores
- CORE_LEVEL_SEVEN EQU 12 ; < Level to 7 cores
- CORE_LEVEL_EIGHT EQU 13 ; < Level to 8 cores
- CORE_LEVEL_NINE EQU 14 ; < Level to 9 cores
- CORE_LEVEL_TEN EQU 15 ; < Level to 10 cores
- CORE_LEVEL_ELEVEN EQU 16 ; < Level to 11 cores
- CORE_LEVEL_TWELVE EQU 17 ; < Level to 12 cores
- CORE_LEVEL_THIRTEEN EQU 18 ; < Level to 13 cores
- CORE_LEVEL_FOURTEEN EQU 19 ; < Level to 14 cores
- CORE_LEVEL_FIFTEEN EQU 20 ; < Level to 15 cores
- CoreLevelModeMax EQU 21 ; < Used for bounds checking
-CORE_LEVELING_TYPE TEXTEQU <DWORD>
-
-
-; ***********************************************************************
-; *
-; * AGESA Basic Level interface structure definition and function prototypes
-; *
-; **********************************************************************
-
-; *********************************************************************
-; * Interface call: AmdCreateStruct
-; *********************************************************************
-
-; *********************************************************************
-; * Interface call: AmdReleaseStruct
-; *********************************************************************
-
-; *********************************************************************
-; * Interface call: AmdInitReset
-; *********************************************************************
- ; AmdInitReset param structure
-AMD_RESET_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < The cached memory region
- HtConfig AMD_HT_RESET_INTERFACE {} ; < The interface for Ht Recovery
- FchInterface FCH_RESET_INTERFACE {} ; Interface for FCH configuration
-AMD_RESET_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitEarly
-; *********************************************************************
- ; InitEarly param structure
-
- ; Provide defaults or customizations to each service performed in AmdInitEarly.
-
-AMD_EARLY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < The standard header
- CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < Execution Map Interface
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- HtConfig AMD_HT_INTERFACE {} ; < HyperTransport Interface
- GnbConfig GNB_CONFIGURATION {} ; < GNB configuration
-AMD_EARLY_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitPost
-; *********************************************************************
- ; AmdInitPost param structure
-AMD_POST_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- MemConfig MEM_PARAMETER_STRUCT {} ; < Memory post param
- GnbPostConfig GNB_POST_CONFIGURATION {}
-AMD_POST_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitEnv
-; *********************************************************************
- ; AmdInitEnv param structure
-AMD_ENV_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- GnbEnvConfiguration GNB_ENV_CONFIGURATION {} ; < GNB configuration
- FchInterface FCH_INTERFACE {} ; FCH configuration
-AMD_ENV_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitMid
-; *********************************************************************
- ; AmdInitMid param structure
-AMD_MID_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics
- GnbMidConfiguration GNB_MID_CONFIGURATION {} ; < GNB configuration
- FchInterface FCH_INTERFACE {} ; FCH configuration
-AMD_MID_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitLate
-; *********************************************************************
- ; AmdInitLate param structure
-AMD_LATE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- IvrsExclusionRangeList POINTER ? ; < IVMD exclusion range descriptor
- DmiTable POINTER ? ; < DMI Interface
- AcpiPState POINTER ? ; < Acpi Pstate SSDT Table
- AcpiSrat POINTER ? ; < SRAT Table
- AcpiSlit POINTER ? ; < SLIT Table
- AcpiWheaMce POINTER ? ; < WHEA MCE Table
- AcpiWheaCmc POINTER ? ; < WHEA CMC Table
- AcpiAlib POINTER ? ; < ALIB Table
- AcpiIvrs POINTER ? ; < IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table
- AcpiCrat POINTER ? ; < Component Resource Affinity Table table
- AcpiCdit POINTER ? ; < Component Locality Distance Information table
- GnbLateConfiguration GNB_LATE_CONFIGURATION {} ; < GNB configuration
-AMD_LATE_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitRecovery
-; *********************************************************************
- ; CPU Recovery Parameters
-AMD_CPU_RECOVERY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard Header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics
-AMD_CPU_RECOVERY_PARAMS ENDS
-
- ; AmdInitRecovery param structure
-AMD_RECOVERY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- MemConfig MEM_PARAMETER_STRUCT {} ; < Memory post param
- CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < The cached memory region. And the max cache region is 3
- CpuRecoveryParams AMD_CPU_RECOVERY_PARAMS {} ; < Params for CPU related recovery init.
-AMD_RECOVERY_PARAMS ENDS
-
-
-; *********************************************************************
-; * Interface call: AmdInitResume
-; *********************************************************************
- ; AmdInitResume param structure
-AMD_RESUME_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < Platform operational characteristics
- S3DataBlock AMD_S3_PARAMS {} ; < Save state data
-AMD_RESUME_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdS3LateRestore
-; *********************************************************************
- ; AmdS3LateRestore param structure
-AMD_S3LATE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- S3DataBlock AMD_S3_PARAMS {} ; < Save state data
-AMD_S3LATE_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdS3Save
-; *********************************************************************
- ; AmdS3Save param structure
-AMD_S3SAVE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- S3DataBlock AMD_S3_PARAMS {} ; < Standard header
- FchInterface FCH_INTERFACE {} ; FCH configuration
-AMD_S3SAVE_PARAMS ENDS
-
- ; General Services API
-
-
-; *********************************************************************
-; * Interface service call: AmdGetApicId
-; *********************************************************************
- ; Request the APIC ID of a particular core.
-
-AMD_APIC_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- Socket UINT8 ? ; < The Core's Socket.
- Core UINT8 ? ; < The Core id.
- IsPresent BOOLEAN ? ; < The Core is present, and ApicAddress is valid.
- ApicAddress UINT8 ? ; < The Core's APIC ID.
-AMD_APIC_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdGetPciAddress
-; *********************************************************************
- ; Request the PCI Address of a Processor Module (that is, its Northbridge)
-
-AMD_GET_PCI_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- Socket UINT8 ? ; < The Processor's socket
- Module UINT8 ? ; < The Module in that Processor
- IsPresent BOOLEAN ? ; < The Core is present, and PciAddress is valid.
- PciAddress PCI_ADDR {} ; < The Processor's PCI Config Space address (Function 0, Register 0)
-AMD_GET_PCI_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdIdentifyCore
-; *********************************************************************
- ; Request the identity (Socket, Module, Core) of the current Processor Core
-
-AMD_IDENTIFY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- Socket UINT8 ? ; < The current Core's Socket
- Module UINT8 ? ; < The current Core's Processor Module
- Core UINT8 ? ; < The current Core's core id.
-AMD_IDENTIFY_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdReadEventLog
-; *********************************************************************
- ; An Event Log Entry.
-EVENT_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- EventClass UINT32 ? ; < The severity of this event, matches AGESA_STATUS.
- EventInfo UINT32 ? ; < The unique event identifier, zero means "no event".
- DataParam1 UINT32 ? ; < Data specific to the Event.
- DataParam2 UINT32 ? ; < Data specific to the Event.
- DataParam3 UINT32 ? ; < Data specific to the Event.
- DataParam4 UINT32 ? ; < Data specific to the Event.
-EVENT_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdIdentifyDimm
-; *********************************************************************
- ; Request the identity of dimm from system address
-
-AMD_IDENTIFY_DIMM STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- MemoryAddress UINT64 ? ; < System Address that needs to be translated to dimm identification.
- SocketId UINT8 ? ; < The socket on which the targeted address locates.
- MemChannelId UINT8 ? ; < The channel on which the targeted address locates.
- DimmId UINT8 ? ; < The dimm on which the targeted address locates.
-AMD_IDENTIFY_DIMM ENDS
-
-; *********************************************************************
-; * Interface service call: AmdGet2DDataEye
-; *********************************************************************
- ; Get 2D training data eye.
- RD_DATAEYE EQU 0 ; < Request read 2D data eye training
- WR_DATAEYE EQU 1 ; < Request write 2D data eye training
-
-AMD_GET_DATAEYE STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- PostParamsPtr POINTER ? ; < Post parameters structure.
- SocketId UINT8 ? ; < The socket on which the targeted address locates.
- MemChannelId UINT8 ? ; < The channel on which the targeted address locates.
- DimmId UINT8 ? ; < The dimm on which the targeted address locates.
- DataEyeType UINT8 ? ; < The data eye type of training read/write.
- DataEyeBuffer POINTER ? ; < Buffer to store data eye.
-AMD_GET_DATAEYE ENDS
-
- ; Data structure for the Mapping Item between Unified ID for IDS Setup Option
- ; and the option value.
-
-IDS_NV_ITEM STRUCT
- IdsNvId UINT16 ? ; < Unified ID for IDS Setup Option.
- IdsNvValue UINT16 ? ; < The value of IDS Setup Option.
-IDS_NV_ITEM ENDS
-
- ; Data Structure for IDS CallOut Function
-IDS_CALLOUT_STRUCT STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < The Standard Header for AGESA Service
- IdsNvPtr POINTER ? ; < Memory Pointer of IDS NV Table
- Reserved UINT32 ? ; < reserved
-IDS_CALLOUT_STRUCT ENDS
-
- AGESA_IDS_DFT_VAL EQU 0FFFFh; < Default value of every uninitlized NV item, the action for it will be ignored
- AGESA_IDS_NV_END EQU 0FFFFh; < Flag specify end of option structure
-; WARNING: Don't change the comment below, it used as signature for script
-; AGESA IDS NV ID Definitions
- AGESA_IDS_EXT_ID_START EQU 0000h; < specify the start of external NV id
-
- AGESA_IDS_NV_UCODE EQU 0001h; < Enable or disable microcode patching
-
- AGESA_IDS_NV_TARGET_PSTATE EQU 0002h; < Set the P-state required to be activated
- AGESA_IDS_NV_POSTPSTATE EQU 0003h; < Set the P-state required to be activated through POST
-
- AGESA_IDS_NV_BANK_INTERLEAVE EQU 0004h; < Enable or disable Bank Interleave
- AGESA_IDS_NV_CHANNEL_INTERLEAVE EQU 0005h; < Enable or disable Channel Interleave
- AGESA_IDS_NV_NODE_INTERLEAVE EQU 0006h; < Enable or disable Node Interleave
- AGESA_IDS_NV_MEMHOLE EQU 0007h; < Enables or disable memory hole
-
- AGESA_IDS_NV_SCRUB_REDIRECTION EQU 0008h; < Enable or disable a write to dram with corrected data
- AGESA_IDS_NV_DRAM_SCRUB EQU 0009h; < Set the rate of background scrubbing for DRAM
- AGESA_IDS_NV_DCACHE_SCRUB EQU 000Ah; < Set the rate of background scrubbing for the DCache.
- AGESA_IDS_NV_L2_SCRUB EQU 000Bh; < Set the rate of background scrubbing for the L2 cache
- AGESA_IDS_NV_L3_SCRUB EQU 000Ch; < Set the rate of background scrubbing for the L3 cache
- AGESA_IDS_NV_ICACHE_SCRUB EQU 000Dh; < Set the rate of background scrubbing for the Icache
- AGESA_IDS_NV_SYNC_ON_ECC_ERROR EQU 000Eh; < Enable or disable the sync flood on un-correctable ECC error
- AGESA_IDS_NV_ECC_SYMBOL_SIZE EQU 000Fh; < Set ECC symbol size
-
- AGESA_IDS_NV_ALL_MEMCLKS EQU 0010h; < Enable or disable all memory clocks enable
- AGESA_IDS_NV_DCT_GANGING_MODE EQU 0011h; < Set the Ganged mode
- AGESA_IDS_NV_DRAM_BURST_LENGTH32 EQU 0012h; < Set the DRAM Burst Length 32
- AGESA_IDS_NV_MEMORY_POWER_DOWN EQU 0013h; < Enable or disable Memory power down mode
- AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE EQU 0014h; < Set the Memory power down mode
- AGESA_IDS_NV_DLL_SHUT_DOWN EQU 0015h; < Enable or disable DLLShutdown
- AGESA_IDS_NV_ONLINE_SPARE EQU 0016h; < Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap
-
- AGESA_IDS_NV_HT_ASSIST EQU 0017h; < Enable or Disable HT Assist
- AGESA_IDS_NV_ATMMODE EQU 0018h; < Enable or Disable ATM mode
-
- AGESA_IDS_NV_HDTOUT EQU 0019h; < Enable or disable HDTOUT feature
-
- AGESA_IDS_NV_HTLINKSOCKET EQU 001Ah; < HT Link Socket
- AGESA_IDS_NV_HTLINKPORT EQU 001Bh; < HT Link Port
- AGESA_IDS_NV_HTLINKFREQ EQU 001Ch; < HT Link Frequency
- AGESA_IDS_NV_HTLINKWIDTHIN EQU 001Dh; < HT Link In Width
- AGESA_IDS_NV_HTLINKWIDTHOUT EQU 001Eh; < HT Link Out Width
-
- AGESA_IDS_NV_GNBHDAUDIOEN EQU 001Fh; < Enable or disable GNB HD Audio
-
- AGESA_IDS_NV_CPB_EN EQU 0020h; < Core Performance Boost
-
- AGESA_IDS_NV_HTC_EN EQU 0021h; < HTC Enable
- AGESA_IDS_NV_HTC_OVERRIDE EQU 0022h; < HTC Override
- AGESA_IDS_NV_HTC_PSTATE_LIMIT EQU 0023h; < HTC P-state limit select
- AGESA_IDS_NV_HTC_TEMP_HYS EQU 0024h; < HTC Temperature Hysteresis
- AGESA_IDS_NV_HTC_ACT_TEMP EQU 0025h; < HTC Activation Temp
-
- AGESA_IDS_NV_POWER_POLICY EQU 0026h; < Select Platform Power Policy
- AGESA_IDS_NV_DRAMCON EQU 0027h; < Specify the mode for controller initialization
- AGESA_IDS_EXT_ID_END EQU 0028h; < specify the end of external NV ID
-
- IDS_EX_NV_ID TEXTEQU <DWORD>
diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/amd.inc b/src/vendorcode/amd/agesa/f16kb/Legacy/amd.inc
deleted file mode 100644
index 9d2870b5a0..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Legacy/amd.inc
+++ /dev/null
@@ -1,462 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * Agesa structures and definitions
-; *
-; * Contains AMD AGESA core interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
-;
-; ****************************************************************************
-; *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; *
-; **************************************************************************
-
-
-UINT64 TEXTEQU <QWORD>
-UINT32 TEXTEQU <DWORD>
-UINT16 TEXTEQU <WORD>
-UINT8 TEXTEQU <BYTE>
-CHAR8 TEXTEQU <BYTE>
-BOOLEAN TEXTEQU <BYTE>
-POINTER TEXTEQU <DWORD>
-
- ; AGESA Types and Definitions
-
- AGESA_REVISION EQU "Arch2008"
- AGESA_ID EQU "AGESA"
-
- LAST_ENTRY EQU 0FFFFFFFFh
- IMAGE_SIGNATURE EQU 'DMA$'
- IOCF8 EQU 0CF8h
- IOCFC EQU 0CFCh
-
- ; The return status for all AGESA public services.
-
- ; Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
- ; will have log entries with more detail.
-
- AGESA_SUCCESS EQU 0 ; < The service completed normally. Info may be logged.
- AGESA_UNSUPPORTED EQU 1 ; < The dispatcher or create struct had an unimplemented function requested.
- ; < Not logged.
- AGESA_BOUNDS_CHK EQU 2 ; < A dynamic parameter was out of range and the service was not provided.
- ; < Example, memory address not installed, heap buffer handle not found.
- ; < Not Logged.
- ; AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
- AGESA_ALERT EQU 3 ; < An observed condition, but no loss of function.
- ; < See log. Example, HT CRC.
- AGESA_WARNING EQU 4 ; < Possible or minor loss of function. See Log.
- AGESA_ERROR EQU 5 ; < Significant loss of function, boot may be possible. See Log.
- AGESA_CRITICAL EQU 6 ; < Continue boot only to notify user. See Log.
- AGESA_FATAL EQU 7 ; < Halt booting. See Log.
- AgesaStatusMax EQU 8 ; < Not a status, use for limit checking.
-AGESA_STATUS TEXTEQU <DWORD>
-
-; For checking whether a status is at or above the mandatory log level.
-AGESA_STATUS_LOG_LEVEL EQU AGESA_ALERT
-
- CALLOUT_ENTRY TEXTEQU <POINTER>
- IMAGE_ENTRY TEXTEQU <POINTER>
- MODULE_ENTRY TEXTEQU <POINTER>
-
-; This allocation type is used by the AmdCreateStruct entry point
- PreMemHeap EQU 0 ; < Create heap in cache.
- PostMemDram EQU 1 ; < Create heap in memory.
- ByHost EQU 2 ; < Create heap by Host.
-ALLOCATION_METHOD TEXTEQU <DWORD>
-
- ; These width descriptors are used by the library function, and others, to specify the data size
- AccessWidth8 EQU 1 ; < Access width is 8 bits.
- AccessWidth16 EQU 2 ; < Access width is 16 bits.
- AccessWidth32 EQU 3 ; < Access width is 32 bits.
- AccessWidth64 EQU 4 ; < Access width is 64 bits.
-
- AccessS3SaveWidth8 EQU 81h ; < Save 8 bits data.
- AccessS3SaveWidth16 EQU 130 ; < Save 16 bits data.
- AccessS3SaveWidth32 EQU 131 ; < Save 32 bits data.
- AccessS3SaveWidth64 EQU 132 ; < Save 64 bits data.
-ACCESS_WIDTH TEXTEQU <DWORD>
-
- ; AGESA struct name
-
- ; AGESA BASIC FUNCTIONS
- AMD_INIT_RECOVERY EQU 00020000h
- AMD_CREATE_STRUCT EQU 00020001h
- AMD_INIT_EARLY EQU 00020002h
- AMD_INIT_ENV EQU 00020003h
- AMD_INIT_LATE EQU 00020004h
- AMD_INIT_MID EQU 00020005h
- AMD_INIT_POST EQU 00020006h
- AMD_INIT_RESET EQU 00020007h
- AMD_INIT_RESUME EQU 00020008h
- AMD_RELEASE_STRUCT EQU 00020009h
- AMD_S3LATE_RESTORE EQU 0002000Ah
- AMD_S3_SAVE EQU 0002000Bh
- AMD_GET_APIC_ID EQU 0002000Ch
- AMD_GET_PCI_ADDRESS EQU 0002000Dh
- AMD_IDENTIFY_CORE EQU 0002000Eh
- AMD_READ_EVENT_LOG EQU 0002000Fh
- AMD_GET_EXECACHE_SIZE EQU 00020010h
- AMD_LATE_RUN_AP_TASK EQU 00020011h
- AMD_IDENTIFY_DIMMS EQU 00020012h
- AMD_GET_2D_DATA_EYE EQU 00020013h
-AGESA_STRUCT_NAME TEXTEQU <DWORD>
-
-
- ; ResetType constant values
- WARM_RESET_WHENEVER EQU 1
- COLD_RESET_WHENEVER EQU 2
- WARM_RESET_IMMEDIATELY EQU 3
- COLD_RESET_IMMEDIATELY EQU 4
-
-
- ; AGESA Structures
-
- ; The standard header for all AGESA services.
-AMD_CONFIG_PARAMS STRUCT
- ImageBasePtr UINT32 ? ; < The AGESA Image base address.
- Func UINT32 ? ; < The service desired, @sa dispatch.h.
- AltImageBasePtr UINT32 ? ; < Alternate Image location
- CalloutPtr CALLOUT_ENTRY ? ; < For Callout from AGESA
- HeapStatus UINT8 ? ; < For heap status from boot time slide.
- HeapBasePtr UINT64 ? ; < Location of the heap
- Reserved UINT8 (7) DUP (?) ; < This space is reserved for future use.
-AMD_CONFIG_PARAMS ENDS
-
-
- ; Create Struct Interface.
-AMD_INTERFACE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Config header
- AgesaFunctionName AGESA_STRUCT_NAME ? ; < The service to init, @sa dispatch.h
- AllocationMethod ALLOCATION_METHOD ? ; < How to handle buffer allocation
- NewStructSize UINT32 ? ; < The size of the allocated data, in for ByHost, else out only.
- NewStructPtr POINTER ? ; < The struct for the service.
- ; < The struct to init for ByHost allocation,
- ; < the initialized struct on return.
-AMD_INTERFACE_PARAMS ENDS
-
- FUNC_0 EQU 0 ; bit-placed for PCI address creation
- FUNC_1 EQU 1
- FUNC_2 EQU 2
- FUNC_3 EQU 3
- FUNC_4 EQU 4
- FUNC_5 EQU 5
- FUNC_6 EQU 6
- FUNC_7 EQU 7
-
- ; AGESA Binary module header structure
-AMD_IMAGE_HEADER STRUCT
- Signature UINT32 ? ; < Binary Signature
- CreatorID CHAR8 (8) DUP (?) ; < 8 characters ID
- Version CHAR8 (12) DUP (?) ; < 12 characters version
- ModuleInfoOffset UINT32 ? ; < Offset of module
- EntryPointAddress UINT32 ? ; < Entry address
- ImageBase UINT32 ? ; < Image base
- RelocTableOffset UINT32 ? ; < Relocate Table offset
- ImageSize UINT32 ? ; < Size
- Checksum UINT16 ? ; < Checksum
- ImageType UINT8 ? ; < Type
- V_Reserved UINT8 ? ; < Reserved
-AMD_IMAGE_HEADER ENDS
- ; AGESA Binary module header structure
-AMD_MODULE_HEADER STRUCT
- ModuleHeaderSignature UINT32 ? ; < Module signature
- ModuleIdentifier CHAR8 (8) DUP (?) ; < 8 characters ID
- ModuleVersion CHAR8 (12) DUP (?) ; < 12 characters version
- ModuleDispatcher POINTER ? ; < A pointer point to dispatcher
- NextBlock POINTER ? ; < Next module header link
-AMD_MODULE_HEADER ENDS
-
-; AMD_CODE_HEADER Signatures.
-AGESA_CODE_SIGNATURE TEXTEQU <'!', '!', '!', 'A', 'G', 'E', 'S', 'A'>
-CIMXNB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'>
-CIMXSB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'>
-
-; AGESA_CODE_SIGNATURE
-AMD_CODE_HEADER STRUCT
- Signature CHAR8 (8) DUP (?) ; < code header Signature
- ComponentName CHAR8 (16) DUP (?) ; < 16 character name of the code module
- Version CHAR8 (12) DUP (?) ; < 12 character version string
- TerminatorNull CHAR8 ? ; < null terminated string
- VerReserved CHAR8 (7) DUP (?) ; < reserved space
-AMD_CODE_HEADER ENDS
-
- ; Extended PCI address format
-EXT_PCI_ADDR STRUCT
- Register UINT32 ?
-; IN OUT UINT32 Register:12; ; < Register offset
-; IN OUT UINT32 Function:3; ; < Function number
-; IN OUT UINT32 Device:5; ; < Device number
-; IN OUT UINT32 Bus:8; ; < Bus number
-; IN OUT UINT32 Segment:4; ; < Segment
-EXT_PCI_ADDR ENDS
-
- ; Union type for PCI address
-PCI_ADDR UNION
- AddressValue UINT32 ? ; < Formal address
- Address EXT_PCI_ADDR {} ; < Extended address
-PCI_ADDR ENDS
-
- ; SBDFO - Segment Bus Device Function Offset
- ; 31:28 Segment (4-bits)
- ; 27:20 Bus (8-bits)
- ; 19:15 Device (5-bits)
- ; 14:12 Function(3-bits)
- ; 11:00 Offset (12-bits)
-
-
-
- ILLEGAL_SBDFO EQU 0FFFFFFFFh
-
- ; CPUID data received registers format
-CPUID_DATA STRUCT
- EAX_Reg UINT32 ? ; < CPUID instruction result in EAX
- EBX_Reg UINT32 ? ; < CPUID instruction result in EBX
- ECX_Reg UINT32 ? ; < CPUID instruction result in ECX
- EDX_Reg UINT32 ? ; < CPUID instruction result in EDX
-CPUID_DATA ENDS
-
- ; HT frequency for external callbacks
-;typedef enum {
- HT_FREQUENCY_200M EQU 0 ; < HT speed 200 for external callbacks
- HT_FREQUENCY_400M EQU 2 ; < HT speed 400 for external callbacks
- HT_FREQUENCY_600M EQU 4 ; < HT speed 600 for external callbacks
- HT_FREQUENCY_800M EQU 5 ; < HT speed 800 for external callbacks
- HT_FREQUENCY_1000M EQU 6 ; < HT speed 1000 for external callbacks
- HT_FREQUENCY_1200M EQU 7 ; < HT speed 1200 for external callbacks
- HT_FREQUENCY_1400M EQU 8 ; < HT speed 1400 for external callbacks
- HT_FREQUENCY_1600M EQU 9 ; < HT speed 1600 for external callbacks
- HT_FREQUENCY_1800M EQU 10 ; < HT speed 1800 for external callbacks
- HT_FREQUENCY_2000M EQU 11 ; < HT speed 2000 for external callbacks
- HT_FREQUENCY_2200M EQU 12 ; < HT speed 2200 for external callbacks
- HT_FREQUENCY_2400M EQU 13 ; < HT speed 2400 for external callbacks
- HT_FREQUENCY_2600M EQU 14 ; < HT speed 2600 for external callbacks
- HT_FREQUENCY_2800M EQU 17 ; < HT speed 2800 for external callbacks
- HT_FREQUENCY_3000M EQU 18 ; < HT speed 3000 for external callbacks
- HT_FREQUENCY_3200M EQU 19 ; < HT speed 3200 for external callbacks
- HT_FREQUENCY_MAX EQU 20 ; < Limit Check.
-HT_FREQUENCIES TEXTEQU <DWORD> ;} HT_FREQUENCIES;
-
-HT3_FREQUENCY_MIN EQU HT_FREQUENCY_1200M
-
-IFNDEF BIT0
- BIT0 EQU 0000000000000001h
-ENDIF
-IFNDEF BIT1
- BIT1 EQU 0000000000000002h
-ENDIF
-IFNDEF BIT2
- BIT2 EQU 0000000000000004h
-ENDIF
-IFNDEF BIT3
- BIT3 EQU 0000000000000008h
-ENDIF
-IFNDEF BIT4
- BIT4 EQU 0000000000000010h
-ENDIF
-IFNDEF BIT5
- BIT5 EQU 0000000000000020h
-ENDIF
-IFNDEF BIT6
- BIT6 EQU 0000000000000040h
-ENDIF
-IFNDEF BIT7
- BIT7 EQU 0000000000000080h
-ENDIF
-IFNDEF BIT8
- BIT8 EQU 0000000000000100h
-ENDIF
-IFNDEF BIT9
- BIT9 EQU 0000000000000200h
-ENDIF
-IFNDEF BIT10
- BIT10 EQU 0000000000000400h
-ENDIF
-IFNDEF BIT11
- BIT11 EQU 0000000000000800h
-ENDIF
-IFNDEF BIT12
- BIT12 EQU 0000000000001000h
-ENDIF
-IFNDEF BIT13
- BIT13 EQU 0000000000002000h
-ENDIF
-IFNDEF BIT14
- BIT14 EQU 0000000000004000h
-ENDIF
-IFNDEF BIT15
- BIT15 EQU 0000000000008000h
-ENDIF
-IFNDEF BIT16
- BIT16 EQU 0000000000010000h
-ENDIF
-IFNDEF BIT17
- BIT17 EQU 0000000000020000h
-ENDIF
-IFNDEF BIT18
- BIT18 EQU 0000000000040000h
-ENDIF
-IFNDEF BIT19
- BIT19 EQU 0000000000080000h
-ENDIF
-IFNDEF BIT20
- BIT20 EQU 0000000000100000h
-ENDIF
-IFNDEF BIT21
- BIT21 EQU 0000000000200000h
-ENDIF
-IFNDEF BIT22
- BIT22 EQU 0000000000400000h
-ENDIF
-IFNDEF BIT23
- BIT23 EQU 0000000000800000h
-ENDIF
-IFNDEF BIT24
- BIT24 EQU 0000000001000000h
-ENDIF
-IFNDEF BIT25
- BIT25 EQU 0000000002000000h
-ENDIF
-IFNDEF BIT26
- BIT26 EQU 0000000004000000h
-ENDIF
-IFNDEF BIT27
- BIT27 EQU 0000000008000000h
-ENDIF
-IFNDEF BIT28
- BIT28 EQU 0000000010000000h
-ENDIF
-IFNDEF BIT29
- BIT29 EQU 0000000020000000h
-ENDIF
-IFNDEF BIT30
- BIT30 EQU 0000000040000000h
-ENDIF
-IFNDEF BIT31
- BIT31 EQU 0000000080000000h
-ENDIF
-IFNDEF BIT32
- BIT32 EQU 0000000100000000h
-ENDIF
-IFNDEF BIT33
- BIT33 EQU 0000000200000000h
-ENDIF
-IFNDEF BIT34
- BIT34 EQU 0000000400000000h
-ENDIF
-IFNDEF BIT35
- BIT35 EQU 0000000800000000h
-ENDIF
-IFNDEF BIT36
- BIT36 EQU 0000001000000000h
-ENDIF
-IFNDEF BIT37
- BIT37 EQU 0000002000000000h
-ENDIF
-IFNDEF BIT38
- BIT38 EQU 0000004000000000h
-ENDIF
-IFNDEF BIT39
- BIT39 EQU 0000008000000000h
-ENDIF
-IFNDEF BIT40
- BIT40 EQU 0000010000000000h
-ENDIF
-IFNDEF BIT41
- BIT41 EQU 0000020000000000h
-ENDIF
-IFNDEF BIT42
- BIT42 EQU 0000040000000000h
-ENDIF
-IFNDEF BIT43
- BIT43 EQU 0000080000000000h
-ENDIF
-IFNDEF BIT44
- BIT44 EQU 0000100000000000h
-ENDIF
-IFNDEF BIT45
- BIT45 EQU 0000200000000000h
-ENDIF
-IFNDEF BIT46
- BIT46 EQU 0000400000000000h
-ENDIF
-IFNDEF BIT47
- BIT47 EQU 0000800000000000h
-ENDIF
-IFNDEF BIT48
- BIT48 EQU 0001000000000000h
-ENDIF
-IFNDEF BIT49
- BIT49 EQU 0002000000000000h
-ENDIF
-IFNDEF BIT50
- BIT50 EQU 0004000000000000h
-ENDIF
-IFNDEF BIT51
- BIT51 EQU 0008000000000000h
-ENDIF
-IFNDEF BIT52
- BIT52 EQU 0010000000000000h
-ENDIF
-IFNDEF BIT53
- BIT53 EQU 0020000000000000h
-ENDIF
-IFNDEF BIT54
- BIT54 EQU 0040000000000000h
-ENDIF
-IFNDEF BIT55
- BIT55 EQU 0080000000000000h
-ENDIF
-IFNDEF BIT56
- BIT56 EQU 0100000000000000h
-ENDIF
-IFNDEF BIT57
- BIT57 EQU 0200000000000000h
-ENDIF
-IFNDEF BIT58
- BIT58 EQU 0400000000000000h
-ENDIF
-IFNDEF BIT59
- BIT59 EQU 0800000000000000h
-ENDIF
-IFNDEF BIT60
- BIT60 EQU 1000000000000000h
-ENDIF
-IFNDEF BIT61
- BIT61 EQU 2000000000000000h
-ENDIF
-IFNDEF BIT62
- BIT62 EQU 4000000000000000h
-ENDIF
-IFNDEF BIT63
- BIT63 EQU 8000000000000000h
-ENDIF
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/bridge32.inc b/src/vendorcode/amd/agesa/f16kb/Legacy/bridge32.inc
deleted file mode 100644
index 4e55a57f5c..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Legacy/bridge32.inc
+++ /dev/null
@@ -1,576 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * Agesa structures and definitions
-; *
-; * Contains AMD AGESA core interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
-;
-; ****************************************************************************
-;
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*****************************************************************************
-
-PARAM1 textequ <[bp+8]>
-PARAM2 textequ <[bp+12]>
-PARAM3 textequ <[bp+16]>
-RETAddress textequ <[bp+4]>
-
-AMD_PRIVATE_PARAMS STRUCT
- Gate16_CS DW ? ; Segment of AMD_BRIDGE_32 and AMD_CALLOUT_16
- Gate16_SS DW ? ; RM stack segment
- Router_Seg DW ? ; Segment of oem router
- Router_Off DW ? ; Offset of oem router
-AMD_PRIVATE_PARAMS ENDS
-
-; OEM may pre-define the GDT and selector offsets. If they do not, use our defaults.
-IFNDEF AGESA_SELECTOR_GDT
- AGESA_SELECTOR_GDT EQU 00h
-ENDIF
-IFNDEF AGESA_SELECTOR_CODE16
- AGESA_SELECTOR_CODE16 EQU 08h
-ENDIF
-IFNDEF AGESA_SELECTOR_DATA16
- AGESA_SELECTOR_DATA16 EQU 10h
-ENDIF
-IFNDEF AGESA_SELECTOR_CODE32
- AGESA_SELECTOR_CODE32 EQU 18h
-ENDIF
-IFNDEF AGESA_SELECTOR_DATA32
- AGESA_SELECTOR_DATA32 EQU 20h
-ENDIF
-
-
-AMD_BRIDGE_32_GDT MACRO GDT_Name:REQ
-
- GDT_Name LABEL BYTE
- DD 000000000h, 000000000h ; NULL descriptor
- DD 00000ffffh, 000009b00h ; 16-bit code, fixed up
- DD 00000ffffh, 000009300h ; 16-bit data, fixed up
- DD 00000ffffh, 000CF9B00h ; 32-bit protected mode code
- DD 00000ffffh, 000CF9300h ; 32-bit protected mode data
- GDT_Length EQU ($-GDT_Name)
-
-ENDM
-
-;+-------------------------------------------------------------------------
-;
-; AMD_BRIDGE_32 - Execute Agesa through Pushhigh interface
-;
-; Processing:
-; The following steps are taken:
-; 1) Enter 32bit Protected Mode (PM32)
-; 2) Run AGESA code
-; 3) Restore Real Mode (RM)
-;
-; Entry:
-; [big real mode] : ds, es set to base 0 limit 4G segment
-; EDX - if not 0, provides a FAR PTR to oem router (Seg | Offset)
-; ESI - configuration block pointer
-;
-; Exit:
-; EAX - return value
-; ESI - configuration block pointer
-; ds, es, fs, gs - Set to 4GB segment limit for Big Real Mode
-;
-; Modified:
-; None
-;
-
-AMD_BRIDGE_32 MACRO GDT_Name
-
- local copyGDT
- local flushTo16PM
- local agesaReturnAddress
- local leave32bitPM
- local flush2RM
-
- push gs
- push fs
- push ebx
- push ecx
- push edi
- mov eax, esp
- push eax
- movzx esp, sp
-;
-; Do not use any locals here, BP will be changed frequently during RM->PM32->RM
-;
- pushf
- cli ; Disable interrupts during AGESA
- cld ; Need known direction flag during AGESA
-
-;
-; Save the FAR PTR input parameter
-;
- mov gs, dx ; Offset
- shr edx, 16
- mov fs, dx ; Segment
-;
-; Determine where our binary file is and get entry point
-;
- mov edx, (AMD_CONFIG_PARAMS PTR [esi]).ImageBasePtr
- add edx, (AMD_IMAGE_HEADER PTR [edx]).EntryPointAddress
-;
-; Figure out the return address we will use after calling AGESA
-; and store it in ebx until we have our stack set up properly
-;
- mov ebx, cs
- shl ebx, 4
- add ebx, OFFSET agesaReturnAddress
-;
-; Save our current RM stack AND entry EBP
-;
- push ebp
-; push esp
- push ss
-
-;
-; BEGIN --- STACK MUST BE BALANCED AT THIS POINT --- BEGIN
-;
-; Copy the GDT onto the stack for modification
-;
- mov cx, GDT_Length
- sub sp, cx
- mov bp, sp
- lea di, GDT_Name
-copyGDT:
- mov al, cs:[di]
- mov [bp], al
- inc di
- inc bp
- loop copyGDT
-;
-; Patch 16-bit code and data descriptors on stack. We will
-; fix up CS and SS for PM16 during the callout if applicable.
-;
- mov bp, sp
-
- mov eax, cs
- shl eax, 4
- mov [bp+AGESA_SELECTOR_CODE16+2], ax
- shr eax, 16
- mov [bp+AGESA_SELECTOR_CODE16+4], al
-
- mov eax, ss
- shl eax, 4
- mov [bp+AGESA_SELECTOR_DATA16+2], ax
- shr eax, 16
- mov [bp+AGESA_SELECTOR_DATA16+4], al
-;
-; Need to place Length and Address on GDT
-;
- mov eax, ss
- shl eax, 4
- add eax, esp
- push eax
- push WORD PTR (GDT_Length-1)
-;
-; Load the GDT
-;
- mov bp, sp
- lgdt FWORD PTR [bp]
-;
-; TABLE 1
-;
-; Place PRIVATE DATA on stack DIRECTLY following GDT
-; During this routine, stack data is critical. If
-; order is changed or additional added, bad things
-; will happen!
-;
-; HIGHEST PHYSICAL ADDRESS
-;
-; | ... |
-; ------------------------
-; | old RM SP |
-; | old RM SS |
-; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS + (SIZEOF GDT_LENGTH + 6 {size, address})
-; | GDT_DATA32 |
-; | ... |
-; | GDT_NULL |
-; | GDT Addr, Length |
-; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS
-; | Priv.Gate16_SS |
-; | Priv.Gate16_CS |
-; ------------------------ sp
-; ------ THEN PUSH -------
-; | Return to 16-bit CS |
-; | Return to 16-bit Off |
-; | ... |
-;
-; LOWEST PHYSICAL ADDRESS
-;
- mov edi, esp
- sub edi, SIZEOF AMD_PRIVATE_PARAMS
- mov ax, cs
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS, ax
- mov ax, ss
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS, ax
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off, gs
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg, fs
-
- mov esp, edi
-;
-; Save an address for returning to 16 bit real mode on stack,
-; we'll use it in a far ret after turning off CR0.PE so that
-; we can take our address off and force a far jump. Be sure
-; no unexpected data is on the stack after this!
-;
- mov ax, cs
- push cs
- lea ax, flush2RM
- push ax
-;
-; Convert ss:esp to "flat"
-;
-
- mov ax, sp
- push ax
- mov eax, ss
- shl eax, 4
- add eax, esp
- mov esp, eax ; Load the zero based ESP
-
-;
-; Set CR0.PE
-;
- mov eax, CR0 ; Get CPU control word 0
- or al, 01 ; Enable CPU protected mode
- mov CR0, eax ; Write back to CPU control word 0
- jmp flushTo16PM
-
-flushTo16PM:
-;
-; 16-bit protected mode
-;
- mov ax, AGESA_SELECTOR_DATA32
- mov ds, ax
- mov es, ax
- mov fs, ax
- mov gs, ax
- mov ss, ax
-;
-; Push our parameters RIGHT TO LEFT, and then return address
-;
- push esi ; AGESA configuration block pointer (data)
- push ebx ; after AGESA return offset (32PM flat) - consumed by dispatcher ret
- pushd AGESA_SELECTOR_CODE32 ; AGESA entry selector (32PM flat)
- push edx ; AGESA entry point (32PM flat)
-
- DB 066h
- retf ; <><><> Enter AGESA 32-bit code!!! <><><>
-
-agesaReturnAddress:
-;
-; Returns from the Agesa 32-bit code still PM32
-;
- DB 0EAh
- DD OFFSET leave32bitPM
- DW AGESA_SELECTOR_CODE16
-
-leave32bitPM:
-;
-; Now in 16-bit PM
-;
- add esp, 4 ; +4 to remove our config block pointer
-;
-; Eax reserve AGESA_STATUS return code, save it
-;
- mov ebx, eax
-;
-; Turn off CR0.PE, restore 64K stack limit
-;
- pop ax
- mov sp, ax
- mov ax, AGESA_SELECTOR_DATA16
- mov ss, ax
-
- mov eax, CR0
- and al, NOT 1 ; Disable protected mode
- mov CR0, eax ; Write back CR0.PE
-;
-; Jump far to enter RM, we saved this address on the stack
-; already. Hopefully stack is balanced through AGESA
-; nor were any params added by pushing them on the stack and
-; not removing them between BEGIN-END comments.
-;
- retf
-
-flush2RM:
-;
-; Set segments registers for big real mode before returning
-;
- xor ax, ax
- mov ds, ax
- mov es, ax
- mov fs, ax
- mov gs, ax
-;
-; Discard GDT, +6 for GDT pointer/size, privates
-;
- add esp, GDT_Length + 6 + SIZEOF AMD_PRIVATE_PARAMS
-;
-; Restore real mode stack and entry EBP
-;
- pop cx
-; mov esp, [esp]
- mov ss, cx
- pop ebp
-;
-; Restore AGESA_STATUS return code to eax
-;
- mov eax, ebx
-;
-; END --- STACK MUST BE BALANCED TO THIS POINT --- END
-;
-
- popf
- pop ebx
- mov esp, ebx
- pop edi
- pop ecx
- pop ebx
- pop fs
- pop gs
- ; EXIT AMD_BRIDGE_32
-ENDM
-;+-------------------------------------------------------------------------
-;
-; AMD_CALLOUT_16 - Execute Callback from Pushhigh interface
-;
-; Processing:
-; The following steps are taken:
-; 1) Enter PM16
-; 2) Setup stack, get private params
-; 3) Enter RM
-; 4) Get 3 params
-; 5) Call oemCallout OR oem router
-; 6) Enter PM32
-; 7) Return to Agesa PH
-;
-; Entry:
-; [32-bit protected mode]
-; [esp+8] Func
-; [esp+12] Data
-; [esp+16] Configuration Block
-; [esp+4] return address to Agesa
-;
-; Exit:
-; [32-bit protected mode]
-;
-; Modified:
-; None
-;
-AMD_CALLOUT_16 MACRO LocalOemCalloutRouter
-;
-; Note that we are still PM32, so MASM may work strangely
-;
-
- push bp ; Save our original SP to access params
- mov bp, sp
- push bx
- push si
- push di
- push cx
- push dx
- push di
-
- DB 066h, 0EAh
- DW OFFSET PM16Entry
- DW AGESA_SELECTOR_CODE16
-
-PM16Entry:
-;
-; PM16 CS, but still PM32 SS, as we need to access our private params
-; before we enter RM.
-;
-; Note: we are working below the stack temporarily, and and it will
-; not affect our ability to get entry params
-;
- xor ecx, ecx
- xor edx, edx
-;
-; SGDT will give us the original location of the GDT on our CAS stack.
-; We need this value because our private parameters are located just
-; below the GDT.
-;
- mov edi, esp
- sub edi, GDT_Length + 6
- sgdt FWORD PTR [edi] ; [edi] = word size, dword address
- mov edi, DWORD PTR [edi+2] ; Get the PM32 address only
- sub edi, SIZEOF AMD_PRIVATE_PARAMS + 6
-;
-; cx = code segment of this code in RM
-; dx = stack segment of CAS in RM
-; fs = code segment of oem router (save for later)
-; gs = offset of oem router (save for later)
-; fs and gs are loaded after switch to real mode because we can't
-; use them as scratch pad registers in protected mode
-;
- mov cx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS
- mov dx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS
-
- mov eax, edi ; Save edi in eax for after RM switch
- mov edi, esp ; Save our current ESP for RM
-
- movzx ebx, dx
- shl ebx, 4
- sub esp, ebx
-
-;
-; We had been accessing the stack in PM32, we will now change to PM16 so we
-; will make the stack segment 64KB limit so SP needs to be fixed made PM16
-; compatible.
-;
- mov bx, AGESA_SELECTOR_DATA16
- mov ss, bx
-
-;
-; Save the RM segment and RM offset of the jump we will need to make in
-; order to enter RM so that code in this segment is relocatable.
-;
-; BEGIN --- Don't unbalance the stack --- BEGIN
-;
- push cx
- pushw OFFSET RMEntry
-
- mov ebx, CR0
- and bl, NOT 1
- mov CR0, ebx ; CR0.PE cleared
-;
-; Far jump to clear segment descriptor cache and enter RM
-;
- retf
-
-RMEntry:
-;
-; We are in RM, setup RM stack
-;
- movzx ebx, dx ; Get RM SS in ebx
- shl ebx, 4 ; Get our stack top on entry in EBP to
- sub ebp, ebx ; access our entry parameters
- sub eax, ebx ; save copy of parameters address
- mov ss, dx ; Set stack segment
-;
-; We are going to figure out the address to use when we return
-; and have to go back into PM32 while we have access to it
-;
- movzx ebx, cx ; Get original CS in ebx
- shl ebx, 4
- add ebx, OFFSET PM32Entry
-;
-; Now we put our data, func, block params into calling convention
-; for our hook
-;
-; ECX = Func
-; EDX = Data
-; ESI = config pointer
-;
- mov ecx, PARAM1 ; Func
- mov edx, PARAM2 ; Data
- mov esi, PARAM3 ; pointer
-
- push ebx ; Save PM32 mode switch address
- push edi ; Save PM32 stack pointer
- pushf
-;
-; Get Router Function Address
-;
- mov edi, eax
- mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg
- mov fs, ax
- mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off
- mov gs, ax
-
- mov eax, AGESA_UNSUPPORTED ; Default return value
-;
-; If AMD_BRIDGE_32 EDX == 0 call oemCallout
-; otherwise call FAR PTR EDX
-;
-; Critical:
-; sp+2 - EDI aka PM32 stack address
-; sp+4 - address of PM32Entry in PM32
-;
- mov bx, fs
- shl ebx, 16
- mov bx, gs
-
- .if (ebx == 0)
- call LocalOemCalloutRouter
- .else
-;
-; Make far call to Router function
-;
- push cs
- push offset CalloutReturn
- push ebx
- retf
-CalloutReturn:
- .endif
-;
-; Restore PM32 esp from RM stack
-;
- popf
- pop edi ; Our PM32 stack pointer
- pop edx ; Our PM32 mode switch address
-
- mov ebx, CR0
- or bl, 1 ; CR0.PE set
- mov CR0, ebx
-
- mov ebx, AGESA_SELECTOR_DATA32
- pushd AGESA_SELECTOR_CODE32 ; PM32 selector
- push edx ; PM32 entry point
-
- DB 066h
- retf ; Far jump to enter PM32
-
-PM32Entry:
-;
-; END --- Don't unbalance the stack --- END
-; We are now PM32, so remember MASM is assembling in 16-bit again
-;
- mov ss, bx
- mov ds, bx
- mov es, bx
- mov fs, bx
- mov gs, bx
-
- mov sp, di
- pop di
- pop dx
- pop cx
- pop di
- pop si
- pop bx
- pop bp
- ; EXIT AMD_CALLOUT_16
-ENDM
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Control/IdsLib32.asm b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Control/IdsLib32.asm
deleted file mode 100644
index 6d2c0b1362..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Control/IdsLib32.asm
+++ /dev/null
@@ -1,335 +0,0 @@
-;/**
-; * @file
-; *
-; * Ids Assembly library 32bit
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: IDS
-; * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
-; */
-;*****************************************************************************
-;
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*****************************************************************************
-
-.586p
-.model flat
-ASSUME FS:NOTHING
-.code
-public IdsDelay
-IdsDelay PROC NEAR C USES EAX EDX
-Local targetedx:dword, targeteax:dword
- rdtsc
-;set target time
- add eax,1500000000
- adc edx,0
- mov targetedx,edx
- mov targeteax,eax
-
- rdtsc
-;set "Si!=0" skip below loop
- .while(1)
- .if(si != 0)
- jmp delay_exit
- .endif
- .if(edx > targetedx)
- jmp delay_exit
- .elseif (edx == targetedx)
- .if(eax > targeteax)
- jmp delay_exit
- .endif
- .endif
- rdtsc
- .endw
-delay_exit:
- ret
-IdsDelay ENDP
-;/*++
-;
-;Routine Description:
-;
-; IdsErrorStop -- Function for Assert
-;
-;Arguments:
-; Filecode
-;
-;Returns:
-;
-; None
-;
-;--*/
-public IdsErrorStop
-IdsErrorStop PROC NEAR C filecode:dword
-local tmpebx:dword,tmpedx:dword
- pushad
-
- mov si,0 ; Si is used as control flag, "Si!=0" skip postcode loop
-; send debug port 1st, then fire SimNow breakpoint
- mov ax, 0deadh
- out 0e0h, ax
- mov eax, filecode
- out 84h, eax
- mov eax, 0BACCD00Bh ; Backdoor in SimNow
- mov ebx, 2 ; Select breakpoint feature
- cpuid
-
- mov ebx,0dead0000h
- mov edx,filecode
- ror edx,16
- mov bx,dx
- mov dx,0
-;ebx:edx = deadxxxxyyyy0000 xxxx is the filecode yyyy is the line num
- mov tmpebx,ebx
- mov tmpedx,edx
-
- xor eax,eax
- mov cl,6
-
- .while((cl != 0) && (si == 0))
- .if(cl <= 2)
- shld eax,edx,8
- shl edx,8
- .else
- shld eax,ebx,8
- shl ebx,8
- .endif
-
- out 80h,eax
- call IdsDelay
- dec cl
- .if(cl == 0)
- mov cl,6
- mov ebx,tmpebx
- mov edx,tmpedx
- .endif
- .endw
-
- popad
- xor eax,eax
- ret
-IdsErrorStop endp
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Stop CPU
-; *
-; *
-; *
-; */
-IDS_STOP_HERE MACRO
-@@:
- jmp short @b
-ENDM
-
-;======================================================================
-; IdsExceptionHandler: Simply performs a jmp $ and IRET.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-PUBLIC _IdsExceptionHandler
-PUBLIC _SizeIdtDescriptor
-PUBLIC _SizeTotalIdtDescriptors
-
-; Size of each exception MUST be the same
-Exception00:
- push eax
- mov al, 00h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception01:
- push eax
- mov al, 01h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception02:
- push eax
- mov al, 02h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception03:
- push eax
- mov al, 03h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception04:
- push eax
- mov al, 04h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception05:
- push eax
- mov al, 05h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception06:
- push eax
- mov al, 06h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception07:
- push eax
- mov al, 07h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception08:
- push eax
- mov al, 08h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception09:
- push eax
- mov al, 09h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception10:
- push eax
- mov al, 10h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception11:
- push eax
- mov al, 11h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception12:
- push eax
- mov al, 12h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception13:
- push eax
- mov al, 13h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception14:
- push eax
- mov al, 14h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception15:
- push eax
- mov al, 15h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception16:
- push eax
- mov al, 16h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception17:
- push eax
- mov al, 17h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception18:
- push eax
- mov al, 18h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception19:
- push eax
- mov al, 19h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception20:
- push eax
- mov al, 20h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception21:
- push eax
- mov al, 21h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception22:
- push eax
- mov al, 22h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception23:
- push eax
- mov al, 23h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception24:
- push eax
- mov al, 24h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception25:
- push eax
- mov al, 25h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception26:
- push eax
- mov al, 26
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception27:
- push eax
- mov al, 27h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception28:
- push eax
- mov al, 28h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception29:
- push eax
- mov al, 29h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception30:
- push eax
- mov al, 30h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception31:
- push eax
- mov al, 31h
- jmp near ptr CommonHandler
-CommonHandler:
- out 80h, al
- pop eax
- IDS_STOP_HERE
- iretd
-
-_IdsExceptionHandler dq offset Exception00
-_SizeIdtDescriptor dd (offset Exception01 - offset Exception00)
-_SizeTotalIdtDescriptors dd (offset CommonHandler - offset Exception00)
-
-END
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Control/IdsLib64.asm b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Control/IdsLib64.asm
deleted file mode 100644
index a6a97a2680..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Control/IdsLib64.asm
+++ /dev/null
@@ -1,342 +0,0 @@
-;/**
-; * @file
-; *
-; * Ids Assembly library 64bit
-; *
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: IDS
-; * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
-; */
-;*****************************************************************************
-;
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*****************************************************************************
-
-.code
-IdsDelay PROC
- push rax
- push rdx
- push rbx
- xor rax,rax
- xor rdx,rdx
- rdtsc
-;set target time
- add eax,1500000000
- adc edx,0
- shl rdx,32
- add rdx,rax
- mov rbx,rdx
-;rbx store the target
-;set "Si!=0" skip below loop
-__loop:
- cmp si,0
- jnz __loopexit
- rdtsc
- shl rdx,32
- add rdx,rax
- cmp rdx,rbx
- jae __loopexit
- jmp __loop
-__loopexit:
- pop rbx
- pop rdx
- pop rax
- ret
-IdsDelay ENDP
-;/*++
-;
-;Routine Description:
-;
-; IdsErrorStop -- Function for Assert
-;
-;Arguments:
-; Filecode
-;
-;Returns:
-;
-; None
-;
-;--*/
-public IdsErrorStop
-IdsErrorStop PROC
-;As x64 calling convention RCX is used as input parameters
- push rcx
- push rbx
- push si
- push dx
- push rbx
-
- mov si,0 ; Si is used as control flag, "Si!=0" skip postcode loop
-; send debug port 1st, then fire SimNow breakpoint
- mov ax, 0deadh
- out 0e0h, ax
- mov eax, ecx
- out 84h, eax
- mov eax, 0BACCD00Bh ; Backdoor in SimNow
- mov ebx, 2 ; Select breakpoint feature
- cpuid
-
- mov rax,0dead00000000h
- or rcx,rax
-;rcx= 0dead__FILECODE
- shl rcx,16
-;rcx= 0dead__FILECODE__0000
- mov rbx,rcx
-
- xor rax,rax
- mov dl,6
-
-IdsErrorStopLoop:
- cmp dl,0
- jz IdsErrorStopExit
- cmp si,0
- jnz IdsErrorStopExit
-
- shld rax,rcx,8
- shl rcx,8
- out 80h,eax
- call IdsDelay
-
- dec dl
- cmp dl,0
- jnz _nextloop
- mov dl,6
- mov rcx,rbx
-_nextloop:
- jmp IdsErrorStopLoop
-IdsErrorStopExit:
- pop rbx
- pop dx
- pop si
- pop rbx
- pop rcx
- xor rax,rax
- ret
-IdsErrorStop endp
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Stop CPU
-; *
-; *
-; *
-; */
-IDS_STOP_HERE MACRO
-@@:
- jmp short @b
-ENDM
-
-;======================================================================
-; IdsExceptionHandler: Simply performs a jmp $ and IRET.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-PUBLIC IdsExceptionHandler
-PUBLIC SizeIdtDescriptor
-PUBLIC SizeTotalIdtDescriptors
-
-; Size of each exception MUST be the same
-Exception00:
- push rax
- mov al, 00h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception01:
- push rax
- mov al, 01h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception02:
- push rax
- mov al, 02h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception03:
- push rax
- mov al, 03h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception04:
- push rax
- mov al, 04h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception05:
- push rax
- mov al, 05h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception06:
- push rax
- mov al, 06h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception07:
- push rax
- mov al, 07h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception08:
- push rax
- mov al, 08h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception09:
- push rax
- mov al, 09h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception10:
- push rax
- mov al, 10h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception11:
- push rax
- mov al, 11h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception12:
- push rax
- mov al, 12h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception13:
- push rax
- mov al, 13h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception14:
- push rax
- mov al, 14h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception15:
- push rax
- mov al, 15h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception16:
- push rax
- mov al, 16h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception17:
- push rax
- mov al, 17h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception18:
- push rax
- mov al, 18h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception19:
- push rax
- mov al, 19h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception20:
- push rax
- mov al, 20h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception21:
- push rax
- mov al, 21h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception22:
- push rax
- mov al, 22h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception23:
- push rax
- mov al, 23h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception24:
- push rax
- mov al, 24h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception25:
- push rax
- mov al, 25h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception26:
- push rax
- mov al, 26
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception27:
- push rax
- mov al, 27h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception28:
- push rax
- mov al, 28h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception29:
- push rax
- mov al, 29h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception30:
- push rax
- mov al, 30h
- jmp near ptr CommonHandler
-; Size of each exception MUST be the same
-Exception31:
- push rax
- mov al, 31h
- jmp near ptr CommonHandler
-CommonHandler:
- out 80h, al
- pop rax
- IDS_STOP_HERE
- iretq
-
-IdsExceptionHandler dq offset Exception00
-SizeIdtDescriptor dd (offset Exception01 - offset Exception00)
-SizeTotalIdtDescriptors dd (offset CommonHandler - offset Exception00)
-
-END
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mu.asm b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mu.asm
deleted file mode 100644
index 8f14379b42..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mu.asm
+++ /dev/null
@@ -1,496 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; $Workfile:: mu.asm $ $Revision:: 841#$ $Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
-; Description: Main memory controller system configuration for AGESA
-;
-;
-;*****************************************************************************
-;
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*****************************************************************************
-;============================================================================
-
-
- .XLIST
- .LIST
-
- .686p
- .MODEL FLAT
- .CODE
- ASSUME FS: NOTHING
-
-; Define the calling convention used for the C library modules
-;@attention - This should be in a central include file
-CALLCONV EQU NEAR C
-
-
-;===============================================================================
-;memUOutPort:
-;
-; Do a 32 Bit IO Out operation using edx.
-; NOTE: This function will be obsolete in the future.
-;
-; In: Port - port number
-; Value - value to be written
-;
-; Out:
-;
-; All registers preserved.
-;===============================================================================
-MemUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD
- pushad
- mov edx,Port
- mov eax,Value
- out dx,al
- popad
- ret
-MemUOutPort ENDP
-
-
-;----------------------------------------------------------------------------
-; _SFENCE();
-;
-_SFENCE macro
- db 0Fh,0AEh,0F8h
- endm
-
-;----------------------------------------------------------------------------
-; _MFENCE();
-;
-_MFENCE macro
- db 0Fh,0AEh,0F0h
- endm
-
-;----------------------------------------------------------------------------
-; _EXECFENCE();
-;
-_EXECFENCE macro
- out 0EDh,al ;prevent speculative execution of following instructions
- endm
-
-;===============================================================================
-;MemUWriteCachelines:
-; Write a test pattern to DRAM
-;
-; In: Pattern - pointer to the write pattern
-; Address - Physical address to be read
-; ClCount - number of cachelines to be read
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUWriteCachelines PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD, ClCount:WORD
- pushad
- push ds
-
- mov eax,Address
- push ss
- pop ds
- xor edx,edx
- mov edx, DWORD PTR Pattern
- mov esi,edx
- mov edx,16
- _EXECFENCE
- xor ecx, ecx
- mov cx,ClCount
- shl ecx,2
- @@:
- db 66h, 0Fh,6Fh,06 ;MOVDQA xmm0,[esi]
- db 64h, 66h, 0Fh,0E7h,00 ;MOVNTDQ fs:[eax],xmm0 (xmm0 is 128 bits)
- add eax,edx
- add esi,edx
- loop @B
-
- pop ds
- popad
- ret
-MemUWriteCachelines ENDP
-
-;===============================================================================
-;MemUReadCachelines:
-;
-; Read a pattern of 72 bit times (per DQ), to test dram functionality. The
-;pattern is a stress pattern which exercises both ISI and crosstalk. The number
-;of cache lines to fill is dependent on DCT width mode and burstlength.
-;
-; In: Buffer - pointer to a buffer where read data will be stored
-; Address - Physical address to be read
-; ClCount - number of cachelines to be read
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUReadCachelines PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
-LOCAL Count:BYTE
- pushad
- ; First, issue continuous dummy reads to fill up the cache
- mov eax,Address
- .if (ClCount > 18)
- mov cx,ClCount
- shr cx,4
- mov Count,cl
- .while (Count != 0)
- push eax
- mov edi,eax
- add edi,128 ;bias value (to account for signed displacement)
- ;clflush opcode=0F AE /7
- mov esi,edi
- mov ebx,esi
- mov ecx,esi
- mov edx,esi
- add edi,4*64 ;TestAddr+4 cache lines
- add ebx,8*64 ;TestAddr+8 cache lines
- add ecx,12*64 ;TestAddr+12 cache lines
- add edx,16*64 ;TestAddr+16 cache lines
- sub edx,128
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- mov eax,fs:[edi] ;TestAddr+6 cache lines
- _MFENCE
- mov eax,fs:[edi+64] ;TestAddr+7 cache lines
- _MFENCE
- mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
- _MFENCE
- mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
- _MFENCE
- mov eax,fs:[ebx] ;TestAddr+10 cache lines
- _MFENCE
- mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
- _MFENCE
- mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
- _MFENCE
- mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
- _MFENCE
- mov eax,fs:[ecx] ;TestAddr+14 cache lines
- _MFENCE
- mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
- _MFENCE
- pop eax
- add eax,(16*64) ;Next 16CL
- dec Count
- .endw
- .else
- mov edi,eax
- add edi,128 ;bias value (to account for signed displacement)
- ;clflush opcode=0F AE /7
- mov esi,edi
- mov ebx,esi
- mov ecx,esi
- mov edx,esi
- add edi,4*64 ;TestAddr+4 cache lines
- add ebx,8*64 ;TestAddr+8 cache lines
- add ecx,12*64 ;TestAddr+12 cache lines
- add edx,16*64 ;TestAddr+16 cache lines
- sub edx,128
- .if(ClCount == 1)
- _MFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- .elseif(ClCount == 3)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- .elseif(ClCount == 6)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- .elseif(ClCount == 9)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- mov eax,fs:[edi] ;TestAddr+6 cache lines
- _MFENCE
- mov eax,fs:[edi+64] ;TestAddr+7 cache lines
- _MFENCE
- mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
- _MFENCE
- .elseif(ClCount == 18)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- mov eax,fs:[edi] ;TestAddr+6 cache lines
- _MFENCE
- mov eax,fs:[edi+64] ;TestAddr+7 cache lines
- _MFENCE
- mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
- _MFENCE
- mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
- _MFENCE
- mov eax,fs:[ebx] ;TestAddr+10 cache lines
- _MFENCE
- mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
- _MFENCE
- mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
- _MFENCE
- mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
- _MFENCE
- mov eax,fs:[ecx] ;TestAddr+14 cache lines
- _MFENCE
- mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
- _MFENCE
- mov eax,fs:[edx] ;TestAddr+16 cache lines
- _MFENCE
- mov eax,fs:[edx+64] ;TestAddr+17 cache lines
- _MFENCE
- .endif
- .endif
- _MFENCE
-
- ; Then, copy data to buffer
- mov esi,Address
- xor edx,edx
- mov edx,DWORD PTR Buffer
- mov edi,edx
- xor ecx, ecx
- mov cx,ClCount
- shl ecx,6
- @@:
- mov al,fs:[esi]
- mov ss:[edi],al
- inc esi
- inc edi
- loop @B
-
- popad
- ret
-MemUReadCachelines ENDP
-
-;===============================================================================
-;MemUDummyCLRead:
-;
-; Perform a single cache line read from a given physical address.
-;
-; In: Address - Physical address to be read
-; ClCount - number of cachelines to be read
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUDummyCLRead PROC CALLCONV PUBLIC Address:DWORD
- _SFENCE
- pushad
- mov eax,Address
- mov dl,fs:[eax]
- popad
- ret
-MemUDummyCLRead ENDP
-
-;===============================================================================
-;MemUFlushPattern:
-;
-; Flush a pattern of 72 bit times (per DQ) from cache. This procedure is used
-;to ensure cache miss on the next read training.
-;
-; In: Address - Physical address to be flushed
-; ClCount - number of cachelines to be flushed
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUFlushPattern PROC CALLCONV PUBLIC Address:DWORD, ClCount:WORD
- pushad
- mov edi,Address
- movzx ecx,ClCount
- @@:
- _MFENCE ; Force strong ordering of clflush
- db 64h,0Fh,0AEh,3Fh ; MemUClFlush fs:[edi]
- _MFENCE
- add edi,64
- loop @B
- popad
- ret
-MemUFlushPattern ENDP
-
-
-;===============================================================================
-;MemUGetWrLvNblErr:
-; Read ClCount number of cachelines then return the bitmap that indicates
-; the write leveling result of each byte lane.
-;
-; IN: ErrBitmap - pointer to a DWORD that will be assigned with WL result
-; Address - Physical address to be sampled
-; ClCount - number of cachelines to be read
-;
-; OUT: ErrBitmap - WL result
-;
-;All registers preserved
-;===============================================================================
-MemUGetWrLvNblErr PROC CALLCONV PUBLIC ErrBitmap:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
-LOCAL ZeroCount[32]:WORD
-
- pushad
- mov esi,Address
- _EXECFENCE
- ;Cache fill
- movzx ecx,ClCount
- @@:
- mov eax,fs:[esi]
- add esi,64
- loop @B
- _MFENCE
-
- ; Then, count the number of 0's
- ;push es
- ;push ss
- ;pop es
- lea edi,ZeroCount
- mov cx,SIZEOF ZeroCount
- mov al,0
- rep stosb
- ;pop es
-
- mov esi,Address
- lea edi,ZeroCount
- mov cx,ClCount
- shl cx,6
- .while(cx > 0)
- mov al,fs:[esi]
- test al,00Fh ;check lower nibble
- .if(ZERO?)
- inc WORD PTR [edi]
- .endif
- add edi,2
- test al,0F0h ;check upper nibble
- .if(ZERO?)
- inc WORD PTR [edi]
- .endif
- add edi,2
- inc esi
- dec cx
- test cx,07h
- .if(ZERO?)
- sub edi,(16*2)
- sub cx,8
- add esi,8
- .endif
- .endw
-
- ; Then, average and compress data to error bits
- lea esi,ZeroCount
- mov dx,ClCount
- shl dx,1
- xor eax,eax
- xor ecx,ecx
- mov cl,0
- .while(cl<16)
- .if(WORD PTR [esi] < dx)
- bts eax,ecx
- .endif
- add esi,2
- inc cl
- .endw
- xor edx,edx
- mov dx,WORD PTR ErrBitmap
- mov [edx], ax
-
- popad
- ret
-MemUGetWrLvNblErr ENDP
-
-;===============================================================================
-;AlignPointerTo16Byte:
-; Modifies BufferPtr to be 16 byte aligned
-;
-; In: BufferPtrPtr - Pointer to buffer pointer
-; Out: BufferPtrPtr - Pointer to buffer pointer that has been 16 byte aligned
-;
-;All registers preserved.
-;===============================================================================
-AlignPointerTo16Byte PROC CALLCONV PUBLIC BufferPtrPtr:NEAR PTR DWORD
- push edx
- push eax
- mov edx, BufferPtrPtr
- mov eax, [edx]
- add eax, 16
- and ax, 0FFF0h
- mov [edx], eax
- pop eax
- pop edx
- ret
-AlignPointerTo16Byte ENDP
-
-;===============================================================================
-;MemUMFenceInstr:
-; Serialize instruction
-;
-; In:
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUMFenceInstr PROC CALLCONV PUBLIC
- _MFENCE
- ret
-MemUMFenceInstr ENDP
-
- END
-