diff options
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 6 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/Makefile.inc | 6 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/bootblock/bootblock.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/pmutil.c | 12 |
4 files changed, 30 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4643887d05..d6c5ffcea9 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -123,6 +123,12 @@ config ROMSTAGE_ADDR help The base address (in CAR) where romstage should be linked +config VERSTAGE_ADDR + hex + default 0xfef60000 + help + The base address (in CAR) where verstage should be linked + config CACHE_MRC_SETTINGS bool default y diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 80617a7720..b8f0c1810d 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -56,6 +56,12 @@ postcar-y += mmap_boot.c postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-y += tsc_freq.c +verstage-y += memmap.c +verstage-y += mmap_boot.c +verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +verstage-y += tsc_freq.c +verstage-y += pmutil.c + CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include # Since FSP-M runs in CAR we need to relocate it to a specific address diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 82794327c9..b8d6f22e7a 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -67,6 +67,12 @@ void asmlinkage bootblock_c_entry(uint32_t tsc_hi, uint32_t tsc_lo) pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + /* Decode the ACPI I/O port range for early firmware verification.*/ + dev = PMC_DEV; + pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MASTER); + /* Call lib/bootblock.c main */ bootblock_main_with_timestamp(((uint64_t)tsc_hi << 32) | tsc_lo); } diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 16c8a0459a..9340ba53d2 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -26,6 +26,7 @@ #include <soc/pm.h> #include <device/device.h> #include <device/pci.h> +#include <vendorcode/google/chromeos/vboot_common.h> static uintptr_t read_pmc_mmio_bar(void) { @@ -336,3 +337,14 @@ int fill_power_state(struct chipset_power_state *ps) printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); return ps->prev_sleep_state; } + +int vboot_platform_is_resuming(void) +{ + int typ; + + if (!(inw(ACPI_PMIO_BASE + PM1_STS) & WAK_STS)) + return 0; + + typ = (inl(ACPI_PMIO_BASE + PM1_CNT) & SLP_TYP) >> SLP_TYP_SHIFT; + return typ == SLP_TYP_S3; +} |