diff options
170 files changed, 348 insertions, 347 deletions
diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c index 4009ba19de..abf02a3690 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c @@ -142,7 +142,8 @@ static void model_10xxx_init(struct device *dev) uint32_t f5x80; uint8_t enabled; uint8_t compute_unit_count = 0; - f5x80 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 5)), 0x80); + f5x80 = pci_read_config32(pcidev_on_root(0x18 + id.nodeid, 5), + 0x80); enabled = f5x80 & 0xf; if (enabled == 0x1) compute_unit_count = 1; @@ -161,11 +162,13 @@ static void model_10xxx_init(struct device *dev) uint32_t f0x160; uint8_t core_count = 0; uint8_t node_count = 0; - f0x60 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 0)), 0x60); + f0x60 = pci_read_config32(pcidev_on_root(0x18 + id.nodeid, 0), + 0x60); core_count = (f0x60 >> 16) & 0x1f; node_count = ((f0x60 >> 4) & 0x7) + 1; if (is_gt_rev_d()) { - f0x160 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 0)), 0x160); + f0x160 = pci_read_config32( + pcidev_on_root(0x18 + id.nodeid, 0), 0x160); core_count |= ((f0x160 >> 16) & 0x7) << 5; } core_count++; diff --git a/src/cpu/amd/family_10h-family_15h/monotonic_timer.c b/src/cpu/amd/family_10h-family_15h/monotonic_timer.c index aff1cee9d2..ad83684ed3 100644 --- a/src/cpu/amd/family_10h-family_15h/monotonic_timer.c +++ b/src/cpu/amd/family_10h-family_15h/monotonic_timer.c @@ -51,7 +51,8 @@ static void init_timer(void) /* Get boost capability */ if ((model == 0x8) || (model == 0x9)) { /* revision D */ - boost_capable = (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 4)), 0x15c) & 0x4) >> 2; + boost_capable = (pci_read_config32(pcidev_on_root(0x18, 4), + 0x15c) & 0x4) >> 2; } /* Set up TSC (BKDG v3.62 section 2.9.4)*/ diff --git a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c index 535b772e64..cf1646ebb4 100644 --- a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c +++ b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c @@ -233,16 +233,17 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) fam15h = !!(mctGetLogicalCPUID(0) & AMD_FAM15_ALL); /* Get number of cores */ if (fam15h) { - cmp_cap = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 5)), 0x84) & 0xff; + cmp_cap = pci_read_config32(pcidev_on_root(0x18, 5), 0x84) & + 0xff; } else { - dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xe8); + dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xe8); cmp_cap = (dtemp & 0x3000) >> 12; if (mctGetLogicalCPUID(0) & (AMD_FAM10_REV_D | AMD_FAM15_ALL)) /* revision D or higher */ cmp_cap |= (dtemp & 0x8000) >> 13; } /* Get number of nodes */ - dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 0)), 0x60); + dtemp = pci_read_config32(pcidev_on_root(0x18, 0), 0x60); node_count = ((dtemp & 0x70) >> 4) + 1; cores_per_node = cmp_cap + 1; @@ -251,7 +252,7 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) /* Get number of boost states */ uint8_t boost_count = 0; - dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 4)), 0x15c); + dtemp = pci_read_config32(pcidev_on_root(0x18, 4), 0x15c); if (fam10h_rev_e) boost_count = (dtemp >> 2) & 0x1; else if (mctGetLogicalCPUID(0) & AMD_FAM15_ALL) @@ -289,7 +290,7 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) uint8_t single_link; /* Determine if this is a PVI or SVI system */ - dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xA0); + dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xA0); if (dtemp & PVI_MODE) pviModeFlag = 1; @@ -361,10 +362,10 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) core_power = (core_voltage * cpuidd) / (expanded_cpuidv * 10); /* Calculate transition latency */ - dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xD4); + dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xD4); power_step_up = (dtemp & 0xf000000) >> 24; power_step_down = (dtemp & 0xf00000) >> 20; - dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xA0); + dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xA0); pll_lock_time = (dtemp & 0x3800) >> 11; if (all_enabled_cores_have_same_cpufid) core_latency = ((12 * power_step_down) + power_step_up) / 1000; @@ -396,7 +397,7 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) for (index = 0; index < total_core_count; index++) { /* Determine if this is a single-link processor */ node_index = 0x18 + (index / cores_per_node); - dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(node_index, 0)), 0x80); + dtemp = pci_read_config32(pcidev_on_root(node_index, 0), 0x80); single_link = !!(((dtemp & 0xff00) >> 8) == 0); /* Enter processor core scope */ diff --git a/src/cpu/amd/family_10h-family_15h/processor_name.c b/src/cpu/amd/family_10h-family_15h/processor_name.c index 478f0a510f..5672efdc13 100644 --- a/src/cpu/amd/family_10h-family_15h/processor_name.c +++ b/src/cpu/amd/family_10h-family_15h/processor_name.c @@ -235,7 +235,7 @@ int init_processor_name(void) if (fam15h) { /* Family 15h or later */ uint32_t dword; - struct device *cpu_fn5_dev = dev_find_slot(0, PCI_DEVFN(0x18, 5)); + struct device *cpu_fn5_dev = pcidev_on_root(0x18, 5); pci_write_config32(cpu_fn5_dev, 0x194, 0); dword = pci_read_config32(cpu_fn5_dev, 0x198); if (dword == 0) { diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c index ab2cafdcda..57bd2fc999 100644 --- a/src/cpu/amd/family_10h-family_15h/ram_calc.c +++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c @@ -72,7 +72,7 @@ uint64_t get_cc6_memory_size() if (pci_read_config32(PCI_DEV(0, 0x18, 2), 0x118) & (0x1 << 18)) enable_cc6 = 1; #else - struct device *dct_dev = dev_find_slot(0, PCI_DEVFN(0x18, 2)); + struct device *dct_dev = pcidev_on_root(0x18, 2); if (pci_read_config32(dct_dev, 0x118) & (0x1 << 18)) enable_cc6 = 1; #endif diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 36ea92a7fc..3948cfe519 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -308,7 +308,7 @@ static void setup_ied_area(struct smm_relocation_params *params) void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *dev = pcidev_on_root(0, 0); printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); @@ -362,6 +362,6 @@ void smm_lock(void) * make the SMM registers writable again. */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + pci_write_config8(pcidev_on_root(0, 0), SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 57d03adf37..0c51c7000a 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -77,7 +77,7 @@ void intel_gma_opregion_register(uintptr_t opregion) u16 reg16; u16 sci_reg; - igd = dev_find_slot(0, PCI_DEVFN(0x2, 0)); + igd = pcidev_on_root(0x2, 0); if (!igd || !igd->enabled) return; @@ -228,7 +228,7 @@ static enum cb_err locate_vbt_cbfs(struct region_device *rdev) static enum cb_err locate_vbt_vbios_cbfs(struct region_device *rdev) { const u8 *oprom = - (const u8 *)pci_rom_probe(dev_find_slot(0, PCI_DEVFN(0x2, 0))); + (const u8 *)pci_rom_probe(pcidev_on_root(0x2, 0)); if (oprom == NULL) return CB_ERR; diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index 1ddcb1c123..c805015088 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -120,7 +120,7 @@ static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr) int spdAddress; AGESA_READ_SPD_PARAMS *info = ConfigPtr; - DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2)); + DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2); DEVTREE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info; UINT8 spdAddrLookup_rev_F [2][2][4]= { { {0xA0, 0xA2}, {0xA4, 0xAC}, }, /* socket 0 - Channel 0 & 1 - 8-bit SPD addresses */ diff --git a/src/mainboard/amd/bettong/mptable.c b/src/mainboard/amd/bettong/mptable.c index e541c0ad3a..7c35f97c9b 100644 --- a/src/mainboard/amd/bettong/mptable.c +++ b/src/mainboard/amd/bettong/mptable.c @@ -108,7 +108,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c index 0cda7f7676..428e5751f8 100644 --- a/src/mainboard/amd/gardenia/mptable.c +++ b/src/mainboard/amd/gardenia/mptable.c @@ -113,7 +113,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index 6071868521..8d1ec59d9c 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -101,7 +101,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c index 9c357f9750..e2bc54eded 100644 --- a/src/mainboard/amd/mahogany_fam10/mainboard.c +++ b/src/mainboard/amd/mahogany_fam10/mainboard.c @@ -31,7 +31,7 @@ void set_pcie_dereset(void) u16 word; struct device *sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0xA8); word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */ @@ -44,7 +44,7 @@ void set_pcie_reset(void) u16 word; struct device *sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0xA8); word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */ @@ -64,13 +64,13 @@ static void get_ide_dma66(void) /*u32 sm_dev, ide_dev; */ struct device *sm_dev, ide_dev; - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); byte = pci_read_config8(sm_dev, 0xA9); byte |= (1 << 5); /* Set Gpio9 as input */ pci_write_config8(sm_dev, 0xA9, byte); - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); + ide_dev = pcidev_on_root(0x14, 1); byte = pci_read_config8(ide_dev, 0x56); byte &= ~(7 << 0); if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c index c94c9c8617..c87749e2d4 100644 --- a/src/mainboard/amd/olivehill/mptable.c +++ b/src/mainboard/amd/olivehill/mptable.c @@ -175,7 +175,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c index 6c3b05abde..cc5fa304a2 100644 --- a/src/mainboard/amd/olivehillplus/mptable.c +++ b/src/mainboard/amd/olivehillplus/mptable.c @@ -136,7 +136,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index e75181184c..a7d47c2cdd 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -136,7 +136,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index 31e8264344..2b2d05abe1 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -106,7 +106,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0 */ diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index 259e1f40a9..8052dc0d67 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -97,7 +97,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c index 0c487c5b17..403a282d55 100644 --- a/src/mainboard/amd/thatcher/mptable.c +++ b/src/mainboard/amd/thatcher/mptable.c @@ -136,7 +136,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index 5c052ec829..ec0144aac4 100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c @@ -50,7 +50,7 @@ void set_pcie_dereset(void) pm_iowrite(0x94, byte); /* set the GPIO65 output enable and the value is 1 */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0x7e); word |= (1 << 0); word &= ~(1 << 4); @@ -76,7 +76,7 @@ void set_pcie_reset(void) pm_iowrite(0x94, byte); /* set the GPIO65 output enable and the value is 0 */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0x7e); word &= ~(1 << 0); word &= ~(1 << 4); @@ -92,7 +92,7 @@ int is_dev3_present(void) struct device *sm_dev; /* access the smbus extended register */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); /* put the GPIO68 output to tristate */ word = pci_read_config16(sm_dev, 0x7e); @@ -130,7 +130,7 @@ static void set_gpio40_gfx(void) pm2_iowrite(0xf1, byte); /* access the smbus extended register */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); /*if the dev3 is present, set the gfx to 2x8 lanes*/ /*otherwise set the gfx to 1x16 lanes*/ @@ -190,7 +190,7 @@ static void set_thermal_config(void) pm2_iowrite(0x42, byte); /* set GPIO 64 to input */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0x56); word |= 1 << 7; pci_write_config16(sm_dev, 0x56, word); diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c index 4e0b8f1e71..2219d01d75 100644 --- a/src/mainboard/amd/torpedo/mptable.c +++ b/src/mainboard/amd/torpedo/mptable.c @@ -179,7 +179,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c index 259e1f40a9..8052dc0d67 100644 --- a/src/mainboard/amd/union_station/mptable.c +++ b/src/mainboard/amd/union_station/mptable.c @@ -97,7 +97,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/aopen/dxplplusu/fadt.c b/src/mainboard/aopen/dxplplusu/fadt.c index b78a3ed9e3..1d3598215c 100644 --- a/src/mainboard/aopen/dxplplusu/fadt.c +++ b/src/mainboard/aopen/dxplplusu/fadt.c @@ -32,7 +32,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index 54762d41ad..9c62712aa2 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c index 8e1b1c1b66..b64198092e 100644 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ b/src/mainboard/asrock/imb-a180/mptable.c @@ -176,7 +176,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c index d97663d89e..0811fd2e1c 100644 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -142,7 +142,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/asus/kcma-d8/acpi_tables.c b/src/mainboard/asus/kcma-d8/acpi_tables.c index c1006e5e7c..ef074608af 100644 --- a/src/mainboard/asus/kcma-d8/acpi_tables.c +++ b/src/mainboard/asus/kcma-d8/acpi_tables.c @@ -41,7 +41,7 @@ unsigned long acpi_fill_madt(unsigned long current) IO_APIC_ADDR, gsi_base); /* IOAPIC on rs5690 */ gsi_base += 24; /* SB700 has 24 IOAPIC entries. */ - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + dev = pcidev_on_root(0, 0); if (dev) { pci_write_config32(dev, 0xF8, 0x1); dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; diff --git a/src/mainboard/asus/kcma-d8/mainboard.c b/src/mainboard/asus/kcma-d8/mainboard.c index 8da41b085b..729ad35b13 100644 --- a/src/mainboard/asus/kcma-d8/mainboard.c +++ b/src/mainboard/asus/kcma-d8/mainboard.c @@ -28,7 +28,7 @@ void set_pcie_reset(void) { struct device *pcie_core_dev; - pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + pcie_core_dev = pcidev_on_root(0, 0); set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828); set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x00000028); } @@ -37,7 +37,7 @@ void set_pcie_dereset(void) { struct device *pcie_core_dev; - pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + pcie_core_dev = pcidev_on_root(0, 0); set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F); set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F); } diff --git a/src/mainboard/asus/kcma-d8/mptable.c b/src/mainboard/asus/kcma-d8/mptable.c index 44ba1567ae..54cf5edb69 100644 --- a/src/mainboard/asus/kcma-d8/mptable.c +++ b/src/mainboard/asus/kcma-d8/mptable.c @@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v) * 00:14.6: INTB MCI */ } - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + dev = pcidev_on_root(0, 0); if (dev) { pci_write_config32(dev, 0xF8, 0x1); dword_ptr = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0); @@ -125,32 +125,32 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((11)<<2)|(0)), apicid_sr5650, 30); /* Device 11 (LNKG, APIC pin 30) */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30); /* Device 12 (LNKG, APIC pin 30) */ - dev = dev_find_slot(0, PCI_DEVFN(0x2, 0)); + dev = pcidev_on_root(0x2, 0); if (dev && dev->enabled) { uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x2)|(0)), apicid_sr5650, 0); /* card behind dev2 */ } - dev = dev_find_slot(0, PCI_DEVFN(0x4, 0)); + dev = pcidev_on_root(0x4, 0); if (dev && dev->enabled) { uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x4)|(0)), apicid_sr5650, 0); /* PIKE */ } - dev = dev_find_slot(0, PCI_DEVFN(0x9, 0)); + dev = pcidev_on_root(0x9, 0); if (dev && dev->enabled) { uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x9)|(0)), apicid_sr5650, 23); /* NIC A */ } - dev = dev_find_slot(0, PCI_DEVFN(0xa, 0)); + dev = pcidev_on_root(0xa, 0); if (dev && dev->enabled) { uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xa)|(0)), apicid_sr5650, 24); /* NIC B */ } - dev = dev_find_slot(0, PCI_DEVFN(0xb, 0)); + dev = pcidev_on_root(0xb, 0); if (dev && dev->enabled) { uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xb)|(0)), apicid_sr5650, 0); /* card behind dev11 */ } - dev = dev_find_slot(0, PCI_DEVFN(0xc, 0)); + dev = pcidev_on_root(0xc, 0); if (dev && dev->enabled) { uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xc)|(0)), apicid_sr5650, 0); /* card behind dev12 */ @@ -177,7 +177,7 @@ static void *smp_write_config_table(void *v) PCI_INT(sp5100_bus_number, 0x11, 0x0, 0x16); /* 6, INTG */ /* PCI slots */ - dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; diff --git a/src/mainboard/asus/kfsn4-dre/acpi_tables.c b/src/mainboard/asus/kfsn4-dre/acpi_tables.c index 36f55afd47..e5e2613f28 100644 --- a/src/mainboard/asus/kfsn4-dre/acpi_tables.c +++ b/src/mainboard/asus/kfsn4-dre/acpi_tables.c @@ -38,7 +38,7 @@ unsigned long acpi_fill_madt(unsigned long current) current = acpi_create_madt_lapics(current); /* Write NVIDIA CK804 IOAPIC. */ - dev = dev_find_slot(0x0, PCI_DEVFN(sysconf.sbdn + 0x1, 0)); + dev = pcidev_on_root(sysconf.sbdn + 0x1, 0); ASSERT(dev != NULL); res = find_resource(dev, PCI_BASE_ADDRESS_1); diff --git a/src/mainboard/asus/kgpe-d16/acpi_tables.c b/src/mainboard/asus/kgpe-d16/acpi_tables.c index c1006e5e7c..ef074608af 100644 --- a/src/mainboard/asus/kgpe-d16/acpi_tables.c +++ b/src/mainboard/asus/kgpe-d16/acpi_tables.c @@ -41,7 +41,7 @@ unsigned long acpi_fill_madt(unsigned long current) IO_APIC_ADDR, gsi_base); /* IOAPIC on rs5690 */ gsi_base += 24; /* SB700 has 24 IOAPIC entries. */ - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + dev = pcidev_on_root(0, 0); if (dev) { pci_write_config32(dev, 0xF8, 0x1); dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; diff --git a/src/mainboard/asus/kgpe-d16/mainboard.c b/src/mainboard/asus/kgpe-d16/mainboard.c index 14a4a69762..02859369af 100644 --- a/src/mainboard/asus/kgpe-d16/mainboard.c +++ b/src/mainboard/asus/kgpe-d16/mainboard.c @@ -28,7 +28,7 @@ void set_pcie_reset(void) { struct device *pcie_core_dev; - pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + pcie_core_dev = pcidev_on_root(0, 0); set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828); set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x00000028); } @@ -37,7 +37,7 @@ void set_pcie_dereset(void) { struct device *pcie_core_dev; - pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + pcie_core_dev = pcidev_on_root(0, 0); set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F); set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F); } diff --git a/src/mainboard/asus/kgpe-d16/mptable.c b/src/mainboard/asus/kgpe-d16/mptable.c index c1b2a5de5d..3b7ff52ab7 100644 --- a/src/mainboard/asus/kgpe-d16/mptable.c +++ b/src/mainboard/asus/kgpe-d16/mptable.c @@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v) * 00:14.6: INTB MCI */ } - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + dev = pcidev_on_root(0, 0); if (dev) { pci_write_config32(dev, 0xF8, 0x1); dword_ptr = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0); @@ -126,37 +126,37 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30); /* Device 12 (LNKG, APIC pin 30) */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 30); /* Device 13 (LNKG, APIC pin 30)) */ - dev = dev_find_slot(0, PCI_DEVFN(0x2, 0)); + dev = pcidev_on_root(0x2, 0); if (dev && dev->enabled) { uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x2)|(0)), apicid_sr5650, 0); /* card behind dev2 */ } - dev = dev_find_slot(0, PCI_DEVFN(0x4, 0)); + dev = pcidev_on_root(0x4, 0); if (dev && dev->enabled) { uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x4)|(0)), apicid_sr5650, 0); /* PIKE */ } - dev = dev_find_slot(0, PCI_DEVFN(0x9, 0)); + dev = pcidev_on_root(0x9, 0); if (dev && dev->enabled) { uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x9)|(0)), apicid_sr5650, 23); /* NIC A */ } - dev = dev_find_slot(0, PCI_DEVFN(0xa, 0)); + dev = pcidev_on_root(0xa, 0); if (dev && dev->enabled) { uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xa)|(0)), apicid_sr5650, 24); /* NIC B */ } - dev = dev_find_slot(0, PCI_DEVFN(0xb, 0)); + dev = pcidev_on_root(0xb, 0); if (dev && dev->enabled) { uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xb)|(0)), apicid_sr5650, 0); /* card behind dev11 */ } - dev = dev_find_slot(0, PCI_DEVFN(0xc, 0)); + dev = pcidev_on_root(0xc, 0); if (dev && dev->enabled) { uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xc)|(0)), apicid_sr5650, 0); /* card behind dev12 */ } - dev = dev_find_slot(0, PCI_DEVFN(0xd, 0)); + dev = pcidev_on_root(0xd, 0); if (dev && dev->enabled) { uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xd)|(0)), apicid_sr5650, 0); /* card behind dev13 */ @@ -183,7 +183,7 @@ static void *smp_write_config_table(void *v) PCI_INT(sp5100_bus_number, 0x11, 0x0, 0x16); /* 6, INTG */ /* PCI slots */ - dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c index b075c6938e..fb01236beb 100644 --- a/src/mainboard/asus/m4a78-em/mainboard.c +++ b/src/mainboard/asus/m4a78-em/mainboard.c @@ -40,7 +40,7 @@ void set_pcie_dereset(void) pm_iowrite(0x94, byte); /* set the GPIO65 output enable and the value is 1 */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0x7e); word |= (1 << 0); word &= ~(1 << 4); @@ -66,7 +66,7 @@ void set_pcie_reset(void) pm_iowrite(0x94, byte); /* set the GPIO65 output enable and the value is 0 */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0x7e); word &= ~(1 << 0); word &= ~(1 << 4); @@ -84,7 +84,7 @@ int is_dev3_present(void) struct device *sm_dev; /* access the smbus extended register */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); /* put the GPIO68 output to tristate */ word = pci_read_config16(sm_dev, 0x7e); diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c index 53c97b8d43..6d0f5497d9 100644 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ b/src/mainboard/asus/m4a785-m/mainboard.c @@ -50,7 +50,7 @@ void set_pcie_dereset(void) pm_iowrite(0x94, byte); /* set the GPIO65 output enable and the value is 1 */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0x7e); word |= (1 << 0); word &= ~(1 << 4); @@ -76,7 +76,7 @@ void set_pcie_reset(void) pm_iowrite(0x94, byte); /* set the GPIO65 output enable and the value is 0 */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0x7e); word &= ~(1 << 0); word &= ~(1 << 4); @@ -94,7 +94,7 @@ int is_dev3_present(void) struct device *sm_dev; /* access the smbus extended register */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); /* put the GPIO68 output to tristate */ word = pci_read_config16(sm_dev, 0x7e); @@ -136,7 +136,7 @@ static void set_thermal_config(void) pm2_iowrite(0x42, byte); /* set GPIO 64 to input */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0x56); word |= 1 << 7; pci_write_config16(sm_dev, 0x56, word); diff --git a/src/mainboard/bap/ode_e20XX/mptable.c b/src/mainboard/bap/ode_e20XX/mptable.c index fc14165c2d..1808181cd8 100644 --- a/src/mainboard/bap/ode_e20XX/mptable.c +++ b/src/mainboard/bap/ode_e20XX/mptable.c @@ -104,7 +104,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0 */ diff --git a/src/mainboard/bap/ode_e21XX/mptable.c b/src/mainboard/bap/ode_e21XX/mptable.c index 6c3b05abde..cc5fa304a2 100644 --- a/src/mainboard/bap/ode_e21XX/mptable.c +++ b/src/mainboard/bap/ode_e21XX/mptable.c @@ -136,7 +136,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/biostar/a68n_5200/mptable.c b/src/mainboard/biostar/a68n_5200/mptable.c index c94c9c8617..c87749e2d4 100644 --- a/src/mainboard/biostar/a68n_5200/mptable.c +++ b/src/mainboard/biostar/a68n_5200/mptable.c @@ -175,7 +175,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/biostar/am1ml/mptable.c b/src/mainboard/biostar/am1ml/mptable.c index 637ae9a1ec..6cb655ec09 100644 --- a/src/mainboard/biostar/am1ml/mptable.c +++ b/src/mainboard/biostar/am1ml/mptable.c @@ -104,7 +104,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0 */ diff --git a/src/mainboard/elmex/pcm205400/mptable.c b/src/mainboard/elmex/pcm205400/mptable.c index 31e8264344..2b2d05abe1 100644 --- a/src/mainboard/elmex/pcm205400/mptable.c +++ b/src/mainboard/elmex/pcm205400/mptable.c @@ -106,7 +106,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0 */ diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index b8df5091a5..99184ca203 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -44,7 +44,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs) void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c index 3e37ff8526..5d271fd65b 100644 --- a/src/mainboard/getac/p470/mainboard.c +++ b/src/mainboard/getac/p470/mainboard.c @@ -59,16 +59,16 @@ static void pcie_limit_power(void) struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(28,0)); + dev = pcidev_on_root(28, 0); if (dev) pci_write_config32(dev, 0x54, 0x0010a0e0); - dev = dev_find_slot(0, PCI_DEVFN(28,1)); + dev = pcidev_on_root(28, 1); if (dev) pci_write_config32(dev, 0x54, 0x0018a0e0); - dev = dev_find_slot(0, PCI_DEVFN(28,2)); + dev = pcidev_on_root(28, 2); if (dev) pci_write_config32(dev, 0x54, 0x0020a0e0); - dev = dev_find_slot(0, PCI_DEVFN(28,3)); + dev = pcidev_on_root(28, 3); if (dev) pci_write_config32(dev, 0x54, 0x0028a0e0); #endif } diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c index 4c9799a510..d11deb082b 100644 --- a/src/mainboard/gigabyte/ma785gm/mainboard.c +++ b/src/mainboard/gigabyte/ma785gm/mainboard.c @@ -40,7 +40,7 @@ void set_pcie_dereset(void) pm_iowrite(0x94, byte); /* set the GPIO65 output enable and the value is 1 */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0x7e); word |= (1 << 0); word &= ~(1 << 4); @@ -66,7 +66,7 @@ void set_pcie_reset(void) pm_iowrite(0x94, byte); /* set the GPIO65 output enable and the value is 0 */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0x7e); word &= ~(1 << 0); word &= ~(1 << 4); @@ -106,7 +106,7 @@ static void set_gpio40_gfx(void) pm2_iowrite(0xf1, byte); /* access the smbus extended register */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); /* set the gfx to 1x16 lanes */ printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n"); diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c index 5949741b45..3b4edeece0 100644 --- a/src/mainboard/gigabyte/ma785gmt/mainboard.c +++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c @@ -50,7 +50,7 @@ void set_pcie_dereset(void) pm_iowrite(0x94, byte); /* set the GPIO65 output enable and the value is 1 */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0x7e); word |= (1 << 0); word &= ~(1 << 4); @@ -76,7 +76,7 @@ void set_pcie_reset(void) pm_iowrite(0x94, byte); /* set the GPIO65 output enable and the value is 0 */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0x7e); word &= ~(1 << 0); word &= ~(1 << 4); @@ -92,7 +92,7 @@ int is_dev3_present(void) struct device *sm_dev; /* access the smbus extended register */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); /* put the GPIO68 output to tristate */ word = pci_read_config16(sm_dev, 0x7e); @@ -130,7 +130,7 @@ static void set_gpio40_gfx(void) pm2_iowrite(0xf1, byte); /* access the smbus extended register */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); /*if the dev3 is present, set the gfx to 2x8 lanes*/ /*otherwise set the gfx to 1x16 lanes*/ @@ -190,7 +190,7 @@ static void set_thermal_config(void) pm2_iowrite(0x42, byte); /* set GPIO 64 to input */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0x56); word |= 1 << 7; pci_write_config16(sm_dev, 0x56, word); diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c index 6b0e229492..ff52b7b525 100644 --- a/src/mainboard/gigabyte/ma78gm/mainboard.c +++ b/src/mainboard/gigabyte/ma78gm/mainboard.c @@ -32,7 +32,7 @@ void set_pcie_dereset(void) u16 word; struct device *sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0xA8); word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */ @@ -45,7 +45,7 @@ void set_pcie_reset(void) u16 word; struct device *sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0xA8); word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */ diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index ecd770bbb9..04d3ac1dcb 100644 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -52,7 +52,7 @@ static void mainboard_final(void *chip_info) uintptr_t ABAR; u8 *memptr; - ahci_dev = dev_find_slot(0, PCI_DEVFN(0x11, 0)); + ahci_dev = pcidev_on_root(0x11, 0); ABAR = pci_read_config32(ahci_dev, 0x24); ABAR &= 0xFFFFFC00; memptr = (u8 *)(ABAR + 0x100 + 0x80 + 0x2C); /* we're on the 2nd port */ diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c index 6208aae99f..d44e27613e 100644 --- a/src/mainboard/gizmosphere/gizmo/mptable.c +++ b/src/mainboard/gizmosphere/gizmo/mptable.c @@ -98,7 +98,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/gizmosphere/gizmo2/mptable.c b/src/mainboard/gizmosphere/gizmo2/mptable.c index fc14165c2d..1808181cd8 100644 --- a/src/mainboard/gizmosphere/gizmo2/mptable.c +++ b/src/mainboard/gizmosphere/gizmo2/mptable.c @@ -104,7 +104,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0 */ diff --git a/src/mainboard/google/kahlee/mptable.c b/src/mainboard/google/kahlee/mptable.c index 0cda7f7676..428e5751f8 100644 --- a/src/mainboard/google/kahlee/mptable.c +++ b/src/mainboard/google/kahlee/mptable.c @@ -113,7 +113,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 4919e6baed..6c896fcc55 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -151,7 +151,7 @@ static void mainboard_init(struct device *dev) /* If running on proto1 - enable reversion of gpio11. */ u32 gpio_inv; u16 gpio_base = pci_read_config16 - (dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE) & + (pcidev_on_root(0x1f, 0), GPIO_BASE) & 0xfffc; u16 gpio_inv_addr = gpio_base + GPI_INV; gpio_inv = inl(gpio_inv_addr); diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index b8c13a1a19..73d33a3a12 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -39,7 +39,7 @@ void pch_enable_lpc(void) const struct device *lpc; const struct southbridge_intel_bd82x6x_config *config = NULL; - lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + lpc = pcidev_on_root(0x1f, 0); if (!lpc) return; if (lpc->chip_info) diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c index c94c9c8617..c87749e2d4 100644 --- a/src/mainboard/hp/abm/mptable.c +++ b/src/mainboard/hp/abm/mptable.c @@ -175,7 +175,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c index 66f8f463f1..08de04e4ca 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c @@ -142,7 +142,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c index 6deafaa05f..25229542e0 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c @@ -110,7 +110,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0 */ diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c index 066bd2edff..444cd33494 100644 --- a/src/mainboard/jetway/pa78vm5/mainboard.c +++ b/src/mainboard/jetway/pa78vm5/mainboard.c @@ -32,7 +32,7 @@ void set_pcie_dereset(void) u16 word; struct device *sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0xA8); word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */ @@ -45,7 +45,7 @@ void set_pcie_reset(void) u16 word; struct device *sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0xA8); word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */ @@ -65,13 +65,13 @@ static void get_ide_dma66(void) /*u32 sm_dev, ide_dev; */ struct device *sm_dev, ide_dev; - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); byte = pci_read_config8(sm_dev, 0xA9); byte |= (1 << 5); /* Set Gpio9 as input */ pci_write_config8(sm_dev, 0xA9, byte); - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); + ide_dev = pcidev_on_root(0x14, 1); byte = pci_read_config8(ide_dev, 0x56); byte &= ~(7 << 0); if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 37f0240662..3447646d24 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -172,7 +172,7 @@ static void mainboard_enable(struct device *dev) unsigned disable = 0; if ((get_option(&disable, "ethernet1") == CB_SUCCESS) && disable) { - struct device *nic = dev_find_slot(0, PCI_DEVFN(0x1c, 2)); + struct device *nic = pcidev_on_root(0x1c, 2); if (nic) { printk(BIOS_DEBUG, "DISABLE FIRST NIC!\n"); nic->enabled = 0; @@ -180,7 +180,7 @@ static void mainboard_enable(struct device *dev) } disable = 0; if ((get_option(&disable, "ethernet2") == CB_SUCCESS) && disable) { - struct device *nic = dev_find_slot(0, PCI_DEVFN(0x1c, 3)); + struct device *nic = pcidev_on_root(0x1c, 3); if (nic) { printk(BIOS_DEBUG, "DISABLE SECOND NIC!\n"); nic->enabled = 0; diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c index 66f8f463f1..08de04e4ca 100644 --- a/src/mainboard/lenovo/g505s/mptable.c +++ b/src/mainboard/lenovo/g505s/mptable.c @@ -142,7 +142,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/lenovo/t400/fadt.c b/src/mainboard/lenovo/t400/fadt.c index 5596115f42..ab257f8c3e 100644 --- a/src/mainboard/lenovo/t400/fadt.c +++ b/src/mainboard/lenovo/t400/fadt.c @@ -22,7 +22,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index bb52c87986..90bdc39662 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -51,7 +51,7 @@ static void mainboard_init(struct device *dev) if (acpi_is_wakeup_s3()) ec_write(0x0c, 0xc7); - idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); + idedev = pcidev_on_root(0x1f, 1); if (!(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40)) { /* legacy I/O connected */ diff --git a/src/mainboard/lenovo/x200/fadt.c b/src/mainboard/lenovo/x200/fadt.c index 5596115f42..ab257f8c3e 100644 --- a/src/mainboard/lenovo/x200/fadt.c +++ b/src/mainboard/lenovo/x200/fadt.c @@ -22,7 +22,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 419f8177a2..182d041f73 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -82,7 +82,7 @@ static void mainboard_enable(struct device *dev) dev->ops->init = mainboard_init; dev->ops->acpi_fill_ssdt_generator = fill_ssdt; - pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), + pmbase = pci_read_config32(pcidev_on_root(0x1f, 0), PMBASE) & 0xff80; printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); @@ -90,9 +90,9 @@ static void mainboard_enable(struct device *dev) outl(0, pmbase + SMI_EN); enable_lapic(); - pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE, + pci_write_config32(pcidev_on_root(0x1f, 0), GPIO_BASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_CNTL, + pci_write_config8(pcidev_on_root(0x1f, 0), GPIO_CNTL, 0x10); /* If we're resuming from suspend, blink suspend LED */ diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 96d8062fbf..5cf0d26bbf 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -87,7 +87,7 @@ static void mainboard_init(struct device *dev) if (acpi_is_wakeup_s3()) ec_write(0x0c, 0xc7); - idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); + idedev = pcidev_on_root(0x1f, 1); if (idedev && idedev->chip_info && dock_ultrabay_device_present()) { struct southbridge_intel_i82801gx_config *config = idedev->chip_info; config->ide_enable_primary = 1; diff --git a/src/mainboard/lenovo/z61t/mainboard.c b/src/mainboard/lenovo/z61t/mainboard.c index 5a565e06c2..c7e7868a30 100644 --- a/src/mainboard/lenovo/z61t/mainboard.c +++ b/src/mainboard/lenovo/z61t/mainboard.c @@ -51,7 +51,7 @@ static void mainboard_init(struct device *dev) if (acpi_is_wakeup_s3()) ec_write(0x0c, 0xc7); - idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); + idedev = pcidev_on_root(0x1f, 1); if (!(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40)) { /* legacy I/O connected */ diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index cc25957dd1..9660a73ed5 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -97,7 +97,8 @@ static void init(struct device *dev) } /* Lower SPI speed from default 66 to 22 MHz for SST 25VF032B */ - spi_base = (u8*)((uintptr_t)pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x14, 3)), 0xA0) & 0xFFFFFFE0); + spi_base = (u8 *)((uintptr_t)pci_read_config32(pcidev_on_root(0x14, 3), + 0xA0) & 0xFFFFFFE0); spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20; // NormSpeed in SPI_Cntrl1 register /* Notify the SMC we're alive and kicking, or after a while it will diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c index 26d22cd2e5..5e3a9508cb 100644 --- a/src/mainboard/lippert/frontrunner-af/mptable.c +++ b/src/mainboard/lippert/frontrunner-af/mptable.c @@ -97,7 +97,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index cea5350542..5cb0916244 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -63,7 +63,8 @@ static void init(struct device *dev) fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56)); /* Lower SPI speed from default 66 to 22 MHz for SST 25VF032B */ - spi_base = (u8*)((uintptr_t)pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x14, 3)), 0xA0) & 0xFFFFFFE0); + spi_base = (u8 *)((uintptr_t)pci_read_config32(pcidev_on_root(0x14, 3), + 0xA0) & 0xFFFFFFE0); spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20; // NormSpeed in SPI_Cntrl1 register /* Notify the SMC we're alive and kicking, or after a while it will diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c index 26d22cd2e5..5e3a9508cb 100644 --- a/src/mainboard/lippert/toucan-af/mptable.c +++ b/src/mainboard/lippert/toucan-af/mptable.c @@ -97,7 +97,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/msi/ms7721/mptable.c b/src/mainboard/msi/ms7721/mptable.c index d97663d89e..0811fd2e1c 100644 --- a/src/mainboard/msi/ms7721/mptable.c +++ b/src/mainboard/msi/ms7721/mptable.c @@ -142,7 +142,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index de9f13d0e3..1fe57d647d 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -99,7 +99,7 @@ static void mainboard_enable(struct device *dev) for (i = 0; i < 256; i++) ec_write (i, dmp[i]); - pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), + pmbase = pci_read_config32(pcidev_on_root(0x1f, 0), PMBASE) & 0xff80; printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); @@ -107,9 +107,9 @@ static void mainboard_enable(struct device *dev) outl(0, pmbase + SMI_EN); enable_lapic(); - pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE, + pci_write_config32(pcidev_on_root(0x1f, 0), GPIO_BASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_CNTL, + pci_write_config8(pcidev_on_root(0x1f, 0), GPIO_CNTL, 0x10); install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2); diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 1105d5f591..a9ce66b90f 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -255,7 +255,7 @@ const char *smbios_mainboard_serial_number(void) */ static void usb_oc_setup(void) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x12, 0)); + struct device *dev = pcidev_on_root(0x12, 0); pci_write_config32(dev, 0x58, 0x011f0); } diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 6a01a8b015..b875437493 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -207,7 +207,7 @@ const char *smbios_mainboard_serial_number(void) * Read secondary bus number from the PCIe bridge where the first NIC is * connected. */ - dev = dev_find_slot(0, PCI_DEVFN(2, 2)); + dev = pcidev_on_root(2, 2); if ((serial[0] != 0) || !dev) return serial; diff --git a/src/mainboard/roda/rk9/fadt.c b/src/mainboard/roda/rk9/fadt.c index 5596115f42..ab257f8c3e 100644 --- a/src/mainboard/roda/rk9/fadt.c +++ b/src/mainboard/roda/rk9/fadt.c @@ -22,7 +22,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); diff --git a/src/mainboard/siemens/mc_bdx1/mainboard.c b/src/mainboard/siemens/mc_bdx1/mainboard.c index 1e6acc7745..d13758636e 100644 --- a/src/mainboard/siemens/mc_bdx1/mainboard.c +++ b/src/mainboard/siemens/mc_bdx1/mainboard.c @@ -103,7 +103,7 @@ static void mainboard_enable(struct device *dev) static void mainboard_init(void *chip_info) { uint8_t actl = 0; - struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); /* Route SCI to IRQ 10 to free IRQ 9 slot. */ actl = pci_read_config8(dev, ACPI_CNTL_OFFSET); @@ -120,7 +120,7 @@ static void mainboard_final(void *chip_info) { void *spi_base = NULL; uint32_t rcba = 0; - struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); /* Get address of SPI controller. */ rcba = (pci_read_config32(dev, 0xf0) & 0xffffc000); diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c index 9ff43396ca..7ae3d70fad 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c +++ b/src/mainboard/supermicro/h8scm_fam10/mainboard.c @@ -36,7 +36,7 @@ void set_pcie_reset(void) { struct device *pcie_core_dev; - pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + pcie_core_dev = pcidev_on_root(0, 0); set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828); set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x00000028); } @@ -45,7 +45,7 @@ void set_pcie_dereset(void) { struct device *pcie_core_dev; - pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + pcie_core_dev = pcidev_on_root(0, 0); set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F); set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F); } diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index d652746765..c0c6eeb2cd 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1459,7 +1459,7 @@ static void cpu_bus_scan(struct device *dev) nb_cfg_54 = read_nb_cfg_54(); #if CONFIG_CBB - dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00 + dev_mc = pcidev_on_root(CONFIG_CDB, 0); //0x00 if (dev_mc && dev_mc->bus) { printk(BIOS_DEBUG, "%s found", dev_path(dev_mc)); pci_domain = dev_mc->bus->dev; @@ -1475,7 +1475,7 @@ static void cpu_bus_scan(struct device *dev) } dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); if (!dev_mc) { - dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + dev_mc = pcidev_on_root(0x18, 0); if (dev_mc && dev_mc->bus) { printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc)); pci_domain = dev_mc->bus->dev; @@ -1719,8 +1719,8 @@ static void detect_and_enable_probe_filter(struct device *dev) /* Disable L3 and DRAM scrubbers and configure system for probe filter support */ for (i = 0; i < sysconf.nodes; i++) { - struct device *f2x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 2)); - struct device *f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); + struct device *f2x_dev = pcidev_on_root(0x18 + i, 2); + struct device *f3x_dev = pcidev_on_root(0x18 + i, 3); f3x58[i] = pci_read_config32(f3x_dev, 0x58); f3x5c[i] = pci_read_config32(f3x_dev, 0x5c); @@ -1789,7 +1789,7 @@ static void detect_and_enable_probe_filter(struct device *dev) /* Enable probe filter */ for (i = 0; i < sysconf.nodes; i++) { - struct device *f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); + struct device *f3x_dev = pcidev_on_root(0x18 + i, 3); dword = pci_read_config32(f3x_dev, 0x1c4); dword |= (0x1 << 31); /* L3TagInit = 1 */ @@ -1810,8 +1810,10 @@ static void detect_and_enable_probe_filter(struct device *dev) /* Enable ATM mode */ for (i = 0; i < sysconf.nodes; i++) { - struct device *f0x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0)); - struct device *f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); + struct device *f0x_dev = + pcidev_on_root(0x18 + i, 0); + struct device *f3x_dev = + pcidev_on_root(0x18 + i, 3); dword = pci_read_config32(f0x_dev, 0x68); dword |= (0x1 << 12); /* ATMModeEn = 1 */ @@ -1827,7 +1829,7 @@ static void detect_and_enable_probe_filter(struct device *dev) /* Reenable L3 and DRAM scrubbers */ for (i = 0; i < sysconf.nodes; i++) { - struct device *f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); + struct device *f3x_dev = pcidev_on_root(0x18 + i, 3); pci_write_config32(f3x_dev, 0x58, f3x58[i]); pci_write_config32(f3x_dev, 0x5c, f3x5c[i]); @@ -1863,9 +1865,9 @@ static void detect_and_enable_cache_partitioning(struct device *dev) uint8_t dual_node = 0; for (i = 0; i < sysconf.nodes; i++) { - struct device *f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); - struct device *f4x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 4)); - struct device *f5x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 5)); + struct device *f3x_dev = pcidev_on_root(0x18 + i, 3); + struct device *f4x_dev = pcidev_on_root(0x18 + i, 4); + struct device *f5x_dev = pcidev_on_root(0x18 + i, 5); f3xe8 = pci_read_config32(f3x_dev, 0xe8); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index c4db5c5f6b..7267f12000 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -80,7 +80,7 @@ static uint32_t read_config32_dct(struct device *dev, uint8_t node, uint8_t dct, #ifdef __PRE_RAM__ pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); #else - struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1)); + struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); #endif /* Select DCT */ @@ -109,7 +109,7 @@ static void write_config32_dct(struct device *dev, uint8_t node, uint8_t dct, #ifdef __PRE_RAM__ pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); #else - struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1)); + struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); #endif /* Select DCT */ @@ -159,7 +159,7 @@ static uint32_t read_amd_dct_index_register_dct(struct device *dev, #ifdef __PRE_RAM__ pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); #else - struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1)); + struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); #endif /* Select DCT */ @@ -280,7 +280,7 @@ static uint32_t read_config32_dct_nbpstate(struct device *dev, uint8_t node, uint32_t reg) { uint32_t dword; - struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1)); + struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); /* Select DCT */ dword = pci_read_config32(dev_fn1, 0x10c); @@ -343,9 +343,9 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data *persistent_da /* Load data from DCTs into data structure */ for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1)); - struct device *dev_fn2 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 2)); - struct device *dev_fn3 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 3)); + struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); + struct device *dev_fn2 = pcidev_on_root(0x18 + node, 2); + struct device *dev_fn3 = pcidev_on_root(0x18 + node, 3); /* Test for node presence */ if ((!dev_fn1) || (pci_read_config32(dev_fn1, PCI_VENDOR_ID) == 0xffffffff)) { persistent_data->node[node].node_present = 0; diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index b4752c4c52..317f0874f8 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -38,7 +38,7 @@ static void mch_domain_read_resources(struct device *dev) pci_domain_read_resources(dev); - mc_dev = dev_find_slot(0, PCI_DEVFN(0x0, 0)); + mc_dev = pcidev_on_root(0, 0); if (!mc_dev) die("Could not find MCH device\n"); diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 93d9c63421..25560dd0e3 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -39,7 +39,7 @@ int bridge_silicon_revision(void) if (bridge_revision_id < 0) { uint8_t stepping = cpuid_eax(1) & 0xf; uint8_t bridge_id = pci_read_config16( - dev_find_slot(0, PCI_DEVFN(0, 0)), + pcidev_on_root(0, 0), PCI_DEVICE_ID) & 0xf0; bridge_revision_id = bridge_id | stepping; } @@ -62,7 +62,7 @@ static int get_pcie_bar(u32 *base) *base = 0; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + dev = pcidev_on_root(0, 0); if (!dev) return 0; diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index 467c6c195e..dc5937230f 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -68,9 +68,11 @@ unsigned long acpi_fill_mcfg(unsigned long current) static unsigned long acpi_fill_dmar(unsigned long current) { - int me_active = (dev_find_slot(0, PCI_DEVFN(3, 0)) != NULL) && - (pci_read_config8(dev_find_slot(0, PCI_DEVFN(3, 0)), PCI_CLASS_REVISION) != 0xff); - int stepping = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), PCI_CLASS_REVISION); + int me_active = (pcidev_on_root(3, 0) != NULL) && + (pci_read_config8(pcidev_on_root(3, 0), PCI_CLASS_REVISION) != + 0xff); + int stepping = pci_read_config8(pcidev_on_root(0, 0), + PCI_CLASS_REVISION); unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE1); diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 8acec29370..0ec0516ceb 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -815,7 +815,7 @@ static void gma_set_subsystem(struct device *dev, unsigned int vendor, const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + struct device *dev = pcidev_on_root(0x2, 0); if (!dev) { return NULL; } diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 014de26bbb..7ff046e9f3 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -41,7 +41,7 @@ static int decode_pcie_bar(u32 *const base, u32 *const len) *base = 0; *len = 0; - struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *dev = pcidev_on_root(0, 0); if (!dev) return 0; @@ -95,7 +95,7 @@ static void mch_domain_read_resources(struct device *dev) pci_domain_read_resources(dev); - struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *mch = pcidev_on_root(0, 0); /* Top of Upper Usable DRAM, including remap */ touud = pci_read_config16(mch, D0F0_TOUUD); @@ -196,7 +196,7 @@ static void mch_domain_init(struct device *dev) { u32 reg32; - struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *mch = pcidev_on_root(0, 0); /* Enable SERR */ reg32 = pci_read_config32(mch, PCI_COMMAND); @@ -222,7 +222,7 @@ static const char *northbridge_acpi_name(const struct device *dev) void northbridge_write_smram(u8 smram) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *dev = pcidev_on_root(0, 0); if (dev == NULL) die("could not find pci 00:00.0!\n"); @@ -309,7 +309,7 @@ static void gm45_init(void *const chip_info) } for (; fn >= 0; --fn) { const struct device *const d = - dev_find_slot(0, PCI_DEVFN(dev, fn)); + pcidev_on_root(dev, fn); if (!d || d->enabled) continue; const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); pci_write_config32(d0f0, D0F0_DEVEN, diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index a73432acfd..f655c3b6fb 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -31,7 +31,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) int max_buses; u32 mask; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + dev = pcidev_on_root(0, 0); if (!dev) return current; @@ -72,7 +72,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) static unsigned long acpi_fill_dmar(unsigned long current) { - struct device *const igfx_dev = dev_find_slot(0, PCI_DEVFN(2, 0)); + struct device *const igfx_dev = pcidev_on_root(2, 0); const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff; const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1; diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 6e3f452638..be83894f33 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -512,7 +512,7 @@ static void gma_set_subsystem(struct device *dev, unsigned int vendor, const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + struct device *dev = pcidev_on_root(0x2, 0); if (!dev) { return NULL; } diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index fcdb683320..8ae5a4ac0e 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -449,7 +449,7 @@ static void disable_devices(void) { PCI_DEVFN(7, 0), DEVEN_D7EN, "\"device 7\"" }, }; - struct device *host_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *host_dev = pcidev_on_root(0x0, 0); u32 deven; size_t i; diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index c36044f0f7..053815bbfd 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -29,7 +29,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) u32 pciexbar_reg; int max_buses; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + dev = pcidev_on_root(0, 0); if (!dev) return current; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 749d07b724..7a2a489c6b 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -73,7 +73,7 @@ static int gtt_setup(u8 *mmiobase) /* * The Video BIOS places the GTT right below top of memory. */ - tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24; + tom = pci_read_config8(pcidev_on_root(0, 0), TOLUD) << 24; PGETBL_save = tom - 256 * KiB; PGETBL_save |= PGETBL_ENABLED; PGETBL_save |= 2; /* set GTT to 256kb */ @@ -357,7 +357,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, /* Setup GTT. */ - reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); + reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC); uma_size = 0; if (!(reg16 & 2)) { uma_size = decode_igd_memory_size((reg16 >> 4) & 7); @@ -536,7 +536,7 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, /* Set up GTT. */ - reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); + reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC); uma_size = 0; if (!(reg16 & 2)) { uma_size = decode_igd_memory_size((reg16 >> 4) & 7); @@ -725,7 +725,7 @@ static void gma_func0_init(struct device *dev) be re-enabled later. */ static void gma_func0_disable(struct device *dev) { - struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0)); + struct device *dev_host = pcidev_on_root(0x0, 0); pci_write_config16(dev, GCFC, 0xa00); pci_write_config16(dev_host, GGC, (1 << 1)); @@ -768,7 +768,7 @@ static void gma_set_subsystem(struct device *dev, unsigned int vendor, const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2, 0)); + struct device *dev = pcidev_on_root(0x2, 0); if (!dev) return NULL; struct northbridge_intel_i945_config *chip = dev->chip_info; diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index ef3c59cb72..2b51b5ebd9 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -34,7 +34,7 @@ static int get_pcie_bar(u32 *base) *base = 0; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + dev = pcidev_on_root(0, 0); if (!dev) return 0; @@ -76,16 +76,16 @@ static void mch_domain_read_resources(struct device *dev) printk(BIOS_DEBUG, "pci_tolm: 0x%x\n", pci_tolm); printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n", - pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), BSM)); + pci_read_config32(pcidev_on_root(2, 0), BSM)); - tolud = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD); + tolud = pci_read_config8(pcidev_on_root(0, 0), TOLUD); printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08x\n", tolud << 24); tomk = tolud << 14; tomk_stolen = tomk; /* Note: subtract IGD device and TSEG */ - reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); + reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC); if (!(reg16 & 2)) { printk(BIOS_DEBUG, "IGD decoded, subtracting "); int uma_size = decode_igd_memory_size((reg16 >> 4) & 7); @@ -98,8 +98,8 @@ static void mch_domain_read_resources(struct device *dev) uma_memory_size = uma_size * 1024ULL; } - tseg_sizek = decode_tseg_size(pci_read_config8(dev_find_slot(0, - PCI_DEVFN(0, 0)), ESMRAMC)) >> 10; + tseg_sizek = decode_tseg_size(pci_read_config8(pcidev_on_root(0, 0), + ESMRAMC)) >> 10; printk(BIOS_DEBUG, "TSEG decoded, subtracting %dM\n", tseg_sizek >> 10); tomk_stolen -= tseg_sizek; tseg_memory_base = tomk_stolen * 1024ULL; @@ -157,7 +157,7 @@ static const char *northbridge_acpi_name(const struct device *dev) void northbridge_write_smram(u8 smram) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *dev = pcidev_on_root(0, 0); if (dev == NULL) die("could not find pci 00:00.0!\n"); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 5f06b7df66..64c87dafc5 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1219,7 +1219,7 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) tom = tolud >> 3; /* Limit the value of TOLUD to leave some space for PCI memory. */ - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + dev = pcidev_on_root(0, 0); if (dev) cfg = dev->chip_info; diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index b89215d634..039923ccb2 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -658,7 +658,7 @@ static void gma_read_resources(struct device *dev) const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + struct device *dev = pcidev_on_root(0x2, 0); if (!dev) { return NULL; } diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 00f6913a07..fbe6c11546 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -39,7 +39,7 @@ int bridge_silicon_revision(void) if (bridge_revision_id < 0) { uint8_t stepping = cpuid_eax(1) & 0xf; uint8_t bridge_id = - pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), + pci_read_config16(pcidev_on_root(0, 0), PCI_DEVICE_ID) & 0xf0; bridge_revision_id = bridge_id | stepping; } @@ -129,8 +129,8 @@ static void mc_read_resources(struct device *dev) mmconf_resource(dev, 0x50); - tseg_base = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG); - TOUUD = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), + tseg_base = pci_read_config32(pcidev_on_root(0, 0), TSEG); + TOUUD = pci_read_config16(pcidev_on_root(0, 0), D0F0_TOUUD); printk(BIOS_DEBUG, "ram_before_4g_top: 0x%x\n", tseg_base); @@ -142,7 +142,7 @@ static void mc_read_resources(struct device *dev) mmio_resource(dev, 5, tseg_base >> 10, CONFIG_SMM_TSEG_SIZE >> 10); - reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GGC); + reg16 = pci_read_config16(pcidev_on_root(0, 0), D0F0_GGC); const int uma_sizes_gtt[16] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 }; /* Igd memory */ @@ -156,9 +156,9 @@ static void mc_read_resources(struct device *dev) uma_size_gtt = uma_sizes_gtt[(reg16 >> 8) & 0xF]; igd_base = - pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_IGD_BASE); + pci_read_config32(pcidev_on_root(0, 0), D0F0_IGD_BASE); gtt_base = - pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GTT_BASE); + pci_read_config32(pcidev_on_root(0, 0), D0F0_GTT_BASE); mmio_resource(dev, 6, gtt_base >> 10, uma_size_gtt << 10); mmio_resource(dev, 7, igd_base >> 10, uma_size_igd << 10); @@ -174,7 +174,7 @@ static void mc_read_resources(struct device *dev) u32 northbridge_get_tseg_base(void) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *dev = pcidev_on_root(0, 0); return pci_read_config32(dev, TSEG) & ~1; } diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 7f90529ef2..89744289a2 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -41,7 +41,7 @@ static void early_graphics_setup(void) u16 reg16; u32 reg32; - const struct device *d0f0 = dev_find_slot(0, PCI_DEVFN(0,0)); + const struct device *d0f0 = pcidev_on_root(0, 0); const struct northbridge_intel_pineview_config *config = d0f0->chip_info; pci_write_config8(D0F0, DEVEN, BOARD_DEVEN); diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index e075ac136c..56242ceafe 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -72,7 +72,7 @@ void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) static int gtt_setup(u8 *mmiobase) { u32 gttbase; - struct device *dev = dev_find_slot(0, PCI_DEVFN(0,0)); + struct device *dev = pcidev_on_root(0, 0); gttbase = pci_read_config32(dev, BGSM); printk(BIOS_DEBUG, "gttbase = %08x\n", gttbase); @@ -319,7 +319,7 @@ static void gma_set_subsystem(struct device *dev, unsigned int vendor, const struct i915_gpu_controller_info *intel_gma_get_controller_info(void) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + struct device *dev = pcidev_on_root(0x2, 0); if (!dev) { printk(BIOS_WARNING, "WARNING: Can't find IGD (0,2,0)\n"); return NULL; diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 33e8089f49..ee1efd3b1e 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -60,7 +60,7 @@ static void mch_domain_read_resources(struct device *dev) u16 index; const u32 top32memk = 4 * (GiB / KiB); - struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *mch = pcidev_on_root(0, 0); index = 3; @@ -143,7 +143,7 @@ static void mch_domain_read_resources(struct device *dev) void northbridge_write_smram(u8 smram) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *dev = pcidev_on_root(0, 0); if (dev == NULL) die("could not find pci 00:00.0!\n"); diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 0a31c8570d..c7914a0a45 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -29,7 +29,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) u32 pciexbar_reg; int max_buses; - struct device *const dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *const dev = pcidev_on_root(0, 0); if (!dev) return current; @@ -68,7 +68,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) static unsigned long acpi_fill_dmar(unsigned long current) { - const struct device *const igfx = dev_find_slot(0, PCI_DEVFN(2, 0)); + const struct device *const igfx = pcidev_on_root(2, 0); if (igfx && igfx->enabled) { const unsigned long tmp = current; diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index cd8f7b9e22..150f78aa4f 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -684,7 +684,7 @@ static void gma_set_subsystem(struct device *dev, unsigned int vendor, const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + struct device *dev = pcidev_on_root(0x2, 0); if (!dev) { return NULL; } @@ -737,7 +737,7 @@ static const char *gma_acpi_name(const struct device *dev) static void gma_func0_disable(struct device *dev) { u16 reg16; - struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0,0)); + struct device *dev_host = pcidev_on_root(0, 0); reg16 = pci_read_config16(dev_host, GGC); reg16 |= (1 << 1); /* disable VGA decode */ diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index 23ecd44835..6371c16188 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -504,7 +504,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info, write32(mmio + 0x0004f05c, 0x00000008); /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)), + generate_fake_intel_oprom(info, pcidev_on_root(2, 0), "$VBT SNB/IVB-MOBILE"); return 1; diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c index 5e8c18855f..977cca8c61 100644 --- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c @@ -469,7 +469,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, } /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)), + generate_fake_intel_oprom(info, pcidev_on_root(2, 0), "$VBT SNB/IVB-MOBILE"); return 1; diff --git a/src/northbridge/intel/sandybridge/iommu.c b/src/northbridge/intel/sandybridge/iommu.c index 08fbe05102..017c73233c 100644 --- a/src/northbridge/intel/sandybridge/iommu.c +++ b/src/northbridge/intel/sandybridge/iommu.c @@ -37,8 +37,7 @@ void sandybridge_init_iommu(void) /* lock policies */ write32((void *)(IOMMU_BASE1 + 0xff0), 0x80000000); - const struct device *const azalia = - dev_find_slot(0x00, PCI_DEVFN(0x1b, 0)); + const struct device *const azalia = pcidev_on_root(0x1b, 0); if (azalia && azalia->enabled) { write32((void *)(IOMMU_BASE2 + 0xff0), 0x20000000); write32((void *)(IOMMU_BASE2 + 0xff0), 0xa0000000); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 5ec8292f62..4a8419a32c 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -42,7 +42,7 @@ int bridge_silicon_revision(void) if (bridge_revision_id < 0) { uint8_t stepping = cpuid_eax(1) & 0xf; uint8_t bridge_id = pci_read_config16( - dev_find_slot(0, PCI_DEVFN(0, 0)), + pcidev_on_root(0, 0), PCI_DEVICE_ID) & 0xf0; bridge_revision_id = bridge_id | stepping; } @@ -65,7 +65,7 @@ static int get_pcie_bar(u32 *base) *base = 0; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + dev = pcidev_on_root(0, 0); if (!dev) return 0; @@ -151,7 +151,7 @@ static void pci_domain_set_resources(struct device *dev) * 14fe00000 5368MB TOUUD */ - struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *mch = pcidev_on_root(0, 0); /* Top of Upper Usable DRAM, including remap */ touud = pci_read_config32(mch, TOUUD+4); @@ -351,46 +351,46 @@ static void disable_peg(void) struct device *dev; u32 reg; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + dev = pcidev_on_root(0, 0); reg = pci_read_config32(dev, DEVEN); - dev = dev_find_slot(0, PCI_DEVFN(1, 2)); + dev = pcidev_on_root(1, 2); if (!dev || !dev->enabled) { printk(BIOS_DEBUG, "Disabling PEG12.\n"); reg &= ~DEVEN_PEG12; } - dev = dev_find_slot(0, PCI_DEVFN(1, 1)); + dev = pcidev_on_root(1, 1); if (!dev || !dev->enabled) { printk(BIOS_DEBUG, "Disabling PEG11.\n"); reg &= ~DEVEN_PEG11; } - dev = dev_find_slot(0, PCI_DEVFN(1, 0)); + dev = pcidev_on_root(1, 0); if (!dev || !dev->enabled) { printk(BIOS_DEBUG, "Disabling PEG10.\n"); reg &= ~DEVEN_PEG10; } - dev = dev_find_slot(0, PCI_DEVFN(2, 0)); + dev = pcidev_on_root(2, 0); if (!dev || !dev->enabled) { printk(BIOS_DEBUG, "Disabling IGD.\n"); reg &= ~DEVEN_IGD; } - dev = dev_find_slot(0, PCI_DEVFN(4, 0)); + dev = pcidev_on_root(4, 0); if (!dev || !dev->enabled) { printk(BIOS_DEBUG, "Disabling Device 4.\n"); reg &= ~DEVEN_D4EN; } - dev = dev_find_slot(0, PCI_DEVFN(6, 0)); + dev = pcidev_on_root(6, 0); if (!dev || !dev->enabled) { printk(BIOS_DEBUG, "Disabling PEG60.\n"); reg &= ~DEVEN_PEG60; } - dev = dev_find_slot(0, PCI_DEVFN(7, 0)); + dev = pcidev_on_root(7, 0); if (!dev || !dev->enabled) { printk(BIOS_DEBUG, "Disabling Device 7.\n"); reg &= ~DEVEN_D7EN; } - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + dev = pcidev_on_root(0, 0); pci_write_config32(dev, DEVEN, reg); if (!(reg & (DEVEN_PEG60 | DEVEN_PEG10 | DEVEN_PEG11 | DEVEN_PEG12))) { /* Set the PEG clock gating bit. @@ -469,7 +469,7 @@ static u32 northbridge_get_base_reg(struct device *dev, int reg) u32 northbridge_get_tseg_base(void) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *dev = pcidev_on_root(0, 0); return northbridge_get_base_reg(dev, TSEG); } @@ -481,7 +481,7 @@ u32 northbridge_get_tseg_size(void) void northbridge_write_smram(u8 smram) { - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, smram); + pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram); } static struct pci_operations intel_pci_ops = { diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c index 1b016bc2f3..da9ed40687 100644 --- a/src/northbridge/intel/x4x/acpi.c +++ b/src/northbridge/intel/x4x/acpi.c @@ -30,7 +30,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) u32 pciexbar = 0; u32 length = 0; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + dev = pcidev_on_root(0, 0); if (!decode_pciebar(&pciexbar, &length)) return current; diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 1fcc682c86..680b83698b 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -69,10 +69,10 @@ static void gma_func0_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32); /* configure GMBUSFREQ */ - reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x2, 0)), 0xcc); + reg16 = pci_read_config16(pcidev_on_root(0x2, 0), 0xcc); reg16 &= ~0x1ff; reg16 |= 0xbc; - pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x2, 0)), 0xcc, reg16); + pci_write_config16(pcidev_on_root(0x2, 0), 0xcc, reg16); int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; @@ -93,7 +93,7 @@ static void gma_func0_init(struct device *dev) static void gma_func0_disable(struct device *dev) { - struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *dev_host = pcidev_on_root(0, 0); u16 ggc; ggc = pci_read_config16(dev_host, D0F0_GGC); @@ -117,7 +117,7 @@ static void gma_set_subsystem(struct device *dev, unsigned int vendor, const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2, 0)); + struct device *dev = pcidev_on_root(0x2, 0); if (!dev) return NULL; struct northbridge_intel_x4x_config *chip = dev->chip_info; diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index ab58c94b44..7de39d1672 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -45,7 +45,7 @@ static void mch_domain_read_resources(struct device *dev) pci_domain_read_resources(dev); - struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *mch = pcidev_on_root(0, 0); /* Top of Upper Usable DRAM, including remap */ touud = pci_read_config16(mch, D0F0_TOUUD); @@ -174,7 +174,7 @@ static const char *northbridge_acpi_name(const struct device *dev) void northbridge_write_smram(u8 smram) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *dev = pcidev_on_root(0, 0); if (dev == NULL) die("could not find pci 00:00.0!\n"); @@ -266,7 +266,7 @@ static void x4x_init(void *const chip_info) } for (; fn >= 0; --fn) { const struct device *const d = - dev_find_slot(0, PCI_DEVFN(dev, fn)); + pcidev_on_root(dev, fn); if (!d || d->enabled) continue; const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c index 494d78a364..8d2cf9c89f 100644 --- a/src/northbridge/via/vx900/chrome9hd.c +++ b/src/northbridge/via/vx900/chrome9hd.c @@ -117,7 +117,7 @@ u8 vx900_int15_get_5f18_bl(void) * Bit[3:0] * N: Frame Buffer Size 2^N MB */ - dev = dev_find_slot(0, PCI_DEVFN(0, 3)); + dev = pcidev_on_root(0, 3); reg8 = pci_read_config8(dev, 0xa1); ret = (u32) ((reg8 & 0x70) >> 4) + 2; reg8 = pci_read_config8(dev, 0x90); diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 5fddc52dc5..038c071a78 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -21,7 +21,7 @@ #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> -#define _SOC_DEV(slot, func) dev_find_slot(0, PCI_DEVFN(slot, func)) +#define _SOC_DEV(slot, func) pcidev_on_root(slot, func) #else #include <arch/io.h> #define _SOC_DEV(slot, func) PCI_DEV(0, slot, func) diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index 06751f1a80..be870fc8b9 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -43,7 +43,7 @@ static struct device *pcu_dev; static struct device *get_pcu_dev(void) { if (pcu_dev == NULL) - pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0)); + pcu_dev = pcidev_on_root(PCU_DEV, 0); return pcu_dev; } #endif diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index e9925a24f5..1715198c51 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -80,7 +80,7 @@ static void fill_in_pattrs(void) struct pattrs *attrs = (struct pattrs *)pattrs_get(); attrs->cpuid = cpuid_eax(1); - dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + dev = pcidev_on_root(LPC_DEV, LPC_FUNC); attrs->revid = pci_read_config8(dev, REVID); /* The revision to stepping IDs have two values per metal stepping. */ if (attrs->revid >= RID_D_STEPPING_START) { diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index b47f7dfe6c..e77d00d36c 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -44,7 +44,7 @@ void punit_init(void) const struct soc_intel_baytrail_config *cfg = NULL; rid = pci_read_config8(IOSF_PCI_DEV, REVID); - dev = dev_find_slot(0, PCI_DEVFN(SOC_DEV, SOC_FUNC)); + dev = pcidev_on_root(SOC_DEV, SOC_FUNC); if (dev) cfg = dev->chip_info; diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index d893816145..81e118c4e6 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -267,7 +267,7 @@ static ich9_spi_regs *spi_regs(void) #ifdef __SMM__ pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); #else - struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); #endif pci_read_config_dword(dev, SBASE, &sbase); sbase &= ~0x1ff; diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index ccd6c9fe41..7a63b5b715 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -86,7 +86,7 @@ __weak void board_silicon_USB2_override(SILICON_INIT_UPD *params) void soc_silicon_init_params(SILICON_INIT_UPD *params) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); struct soc_intel_braswell_config *config; if (!dev) { @@ -406,7 +406,7 @@ struct pci_operations soc_pci_ops = { **/ int SocStepping(void) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); u8 revid = pci_read_config8(dev, 0x8); switch (revid & B_PCH_LPC_RID_STEPPING_MASK) { diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index 85384a6120..8dbb499202 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -44,7 +44,7 @@ static struct device *pcu_dev; static struct device *get_pcu_dev(void) { if (pcu_dev == NULL) - pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0)); + pcu_dev = pcidev_on_root(PCU_DEV, 0); return pcu_dev; } #endif /* ENV_SMM */ diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index a12db8034d..b8362cdc58 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -84,7 +84,7 @@ static void fill_in_pattrs(void) struct pattrs *attrs = (struct pattrs *)pattrs_get(); attrs->cpuid = cpuid_eax(1); - dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + dev = pcidev_on_root(LPC_DEV, LPC_FUNC); attrs->revid = pci_read_config8(dev, REVID); /* The revision to stepping IDs have two values per metal stepping. */ if (attrs->revid >= RID_D_STEPPING_START) { diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 14eaa6b3a8..9b9a0eba5d 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -216,7 +216,7 @@ void soc_memory_init_params(struct romstage_params *params, const struct soc_intel_braswell_config *config; /* Set the parameters for MemoryInit */ - dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + dev = pcidev_on_root(LPC_DEV, LPC_FUNC); if (!dev) { printk(BIOS_ERR, diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index a5f835d55a..988832d09d 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -236,7 +236,7 @@ static ich9_spi_regs *spi_regs(void) #if ENV_SMM pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); #else - struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); #endif if (!dev) { printk(BIOS_ERR, "%s: PCI device not found", __func__); diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 2fe5b39c0a..fb50b7401e 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -265,7 +265,7 @@ static void pch_lpc_interrupt_init(void) { const struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); + dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0); if (!dev || !dev->chip_info) return; @@ -278,7 +278,7 @@ void pch_enable_lpc(void) const struct device *dev; uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]; - dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); + dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0); if (!dev || !dev->chip_info) return; diff --git a/src/soc/intel/fsp_baytrail/i2c.c b/src/soc/intel/fsp_baytrail/i2c.c index 95761f3d19..22e565fd46 100644 --- a/src/soc/intel/fsp_baytrail/i2c.c +++ b/src/soc/intel/fsp_baytrail/i2c.c @@ -114,7 +114,7 @@ int i2c_init(unsigned bus) base_ptr = (char*)base_adr[bus]; /* Set the I2C-device the user wants to use */ - dev = dev_find_slot(0, PCI_DEVFN(I2C1_DEV, bus + 1)); + dev = pcidev_on_root(I2C1_DEV, bus + 1); /* Ensure we have the right PCI device */ if ((pci_read_config16(dev, 0x0) != I2C_PCI_VENDOR_ID) || @@ -171,7 +171,7 @@ int i2c_read(unsigned bus, unsigned chip, unsigned addr, int stat; /* Get base address of desired I2C-controller */ - dev = dev_find_slot(0, PCI_DEVFN(I2C1_DEV, bus + 1)); + dev = pcidev_on_root(I2C1_DEV, bus + 1); base_ptr = (char *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); if (base_ptr == NULL) { printk(BIOS_INFO, "I2C: Invalid Base address\n"); @@ -230,7 +230,7 @@ int i2c_write(unsigned bus, unsigned chip, unsigned addr, int stat; /* Get base address of desired I2C-controller */ - dev = dev_find_slot(0, PCI_DEVFN(I2C1_DEV, bus + 1)); + dev = pcidev_on_root(I2C1_DEV, bus + 1); base_ptr = (char *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); if (base_ptr == NULL) { return I2C_ERR_INVALID_ADR; diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index 93cd2f251d..416746d79e 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -92,7 +92,7 @@ static int get_pcie_bar(u32 *base) *base = 0; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + dev = pcidev_on_root(0, 0); if (!dev) return 0; diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c index 402842eb74..6e4a7c8ef5 100644 --- a/src/soc/intel/fsp_baytrail/pmutil.c +++ b/src/soc/intel/fsp_baytrail/pmutil.c @@ -41,7 +41,7 @@ static struct device *pcu_dev; static struct device *get_pcu_dev(void) { if (pcu_dev == NULL) - pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0)); + pcu_dev = pcidev_on_root(PCU_DEV, 0); return pcu_dev; } #endif diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index f4cdaa8300..754c5f5c45 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -78,7 +78,7 @@ static void fill_in_pattrs(void) struct pattrs *attrs = (struct pattrs *)pattrs_get(); attrs->cpuid = cpuid_eax(1); - dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + dev = pcidev_on_root(LPC_DEV, LPC_FUNC); attrs->revid = pci_read_config8(dev, REVID); /* The revision to stepping IDs have two values per metal stepping. */ if (attrs->revid >= RID_D_STEPPING_START) { diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 4537bcc339..41d5150f4d 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -254,11 +254,9 @@ static ich9_spi_regs *spi_regs(void) uint32_t sbase; #ifdef __SMM__ - pci_devfn_t dev; - dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); #else - struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); #endif pci_read_config_dword(dev, SBASE, &sbase); sbase &= ~0x1ff; diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index ad88313ade..0b07ea8c4c 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -81,7 +81,7 @@ static int acpi_sci_irq(void) { uint8_t actl = 0; static uint8_t sci_irq = 0; - struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); /* If this function was already called, just return the stored value. */ if (sci_irq) diff --git a/src/soc/intel/fsp_broadwell_de/ramstage.c b/src/soc/intel/fsp_broadwell_de/ramstage.c index 7b94268a02..492378ec4b 100644 --- a/src/soc/intel/fsp_broadwell_de/ramstage.c +++ b/src/soc/intel/fsp_broadwell_de/ramstage.c @@ -62,7 +62,7 @@ static void fill_in_pattrs(void) attrs->cpuid = cpuid_eax(1); attrs->stepping = (attrs->cpuid & 0x0F) - 1; - dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + dev = pcidev_on_root(LPC_DEV, LPC_FUNC); attrs->revid = pci_read_config8(dev, REVID); attrs->microcode_patch = intel_microcode_find(); attrs->address_bits = cpuid_eax(0x80000008) & 0xff; diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index 960b53f675..83bed34347 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -31,9 +31,8 @@ unsigned long acpi_fill_mcfg(unsigned long current) void acpi_fill_in_fadt(acpi_fadt_t *fadt) { - struct device *dev = dev_find_slot(0, - PCI_DEVFN(PCI_DEVICE_NUMBER_QNC_LPC, - PCI_FUNCTION_NUMBER_QNC_LPC)); + struct device *dev = pcidev_on_root(PCI_DEVICE_NUMBER_QNC_LPC, + PCI_FUNCTION_NUMBER_QNC_LPC); uint32_t gpe0_base = pci_read_config32(dev, R_QNC_LPC_GPE0BLK) & B_QNC_LPC_GPE0BLK_MASK; uint32_t pmbase = pci_read_config32(dev, R_QNC_LPC_PM1BLK) diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index 574c0621db..8cfa24bbc5 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -50,7 +50,7 @@ void spi_init() { struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + dev = pcidev_on_root(0x14, 3); spibar = pci_read_config32(dev, 0xA0) & ~0x1F; } diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index 16270d6d89..2ef9cd6bf2 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -192,8 +192,8 @@ void set_pcie_enable_bits(struct device *dev, u32 reg_pos, u32 mask, u32 val) void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) { /* K8 Function1 is address map */ - struct device *k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + struct device *k8_f1 = pcidev_on_root(0x18, 1); + struct device *k8_f0 = pcidev_on_root(0x18, 0); if (in_out) { u32 dword, sblk; diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index 575a340894..8431223690 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -175,7 +175,7 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO) CIM_STATUS Status = CIM_UNSUPPORTED; u8 Bus, Dev, Reg, BusStart, BusEnd; u32 Value; - struct device *dev0x14 = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev0x14 = pcidev_on_root(0x14, 4); struct device *tempdev; Value = pci_read_config32(dev0x14, 0x18); BusStart = (Value >> 8) & 0xFF; @@ -235,7 +235,7 @@ static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute) int i, j, n = 7; struct device *k8_f1; - k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + k8_f1 = pcidev_on_root(0x18, 1); for (i = 0; i < 8; i++) { int k = 0, MmioReg; @@ -787,7 +787,7 @@ static void rs780_internal_gfx_enable(struct device *dev) /* LPC DMA Deadlock workaround? */ /* GFX_InitCommon*/ - struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + struct device *k8_f0 = pcidev_on_root(0x18, 0); l_dword = pci_read_config32(k8_f0, 0x68); l_dword &= ~(3 << 21); l_dword |= (1 << 21); @@ -802,9 +802,9 @@ static void rs780_internal_gfx_enable(struct device *dev) #if IS_ENABLED(CONFIG_GFXUMA) /* GFX_InitUMA. */ /* Copy CPU DDR Controller to NB MC. */ - struct device *k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - struct device *k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2)); - struct device *k8_f4 = dev_find_slot(0, PCI_DEVFN(0x18, 4)); + struct device *k8_f1 = pcidev_on_root(0x18, 1); + struct device *k8_f2 = pcidev_on_root(0x18, 2); + struct device *k8_f4 = pcidev_on_root(0x18, 4); for (i = 0; i < 12; i++) { l_dword = pci_read_config32(k8_f2, 0x40 + i * 4); nbmc_write_index(nb_dev, 0x30 + i, l_dword); @@ -1145,7 +1145,7 @@ static void dynamic_link_width_control(struct device *nb_dev, struct device *dev while (reg32 & 0x100); /* step 5.9.1.6 */ - sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0)); + sb_dev = pcidev_on_root(8, 0); do { reg32 = pci_ext_read_config32(nb_dev, sb_dev, PCIE_VC0_RESOURCE_STATUS); diff --git a/src/southbridge/amd/rs780/ht.c b/src/southbridge/amd/rs780/ht.c index 43fb899803..94df2337c1 100644 --- a/src/southbridge/amd/rs780/ht.c +++ b/src/southbridge/amd/rs780/ht.c @@ -26,7 +26,7 @@ void avoid_lpc_dma_deadlock(struct device *nb_dev, struct device *sb_dev) struct device *cpu_f0; u8 reg; - cpu_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + cpu_f0 = pcidev_on_root(0x18, 0); set_nbcfg_enable_bits(cpu_f0, 0x68, 3 << 21, 1 << 21); reg = nbpcie_p_read_index(sb_dev, 0x10); diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index a753da77be..c5e38c130c 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -271,14 +271,14 @@ void rs780_enable(struct device *dev) printk(BIOS_INFO, "rs780_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); - nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + nb_dev = pcidev_on_root(0, 0); if (!nb_dev) { die("rs780_enable: CAN NOT FIND RS780 DEVICE, HALT!\n"); /* NOT REACHED */ } /* sb_dev (dev 8) is a bridge that links to southbridge. */ - sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0)); + sb_dev = pcidev_on_root(8, 0); if (!sb_dev) { die("rs780_enable: CAN NOT FIND SB bridge, HALT!\n"); /* NOT REACHED */ diff --git a/src/southbridge/amd/sb700/ide.c b/src/southbridge/amd/sb700/ide.c index d08f2f1cb2..673464318c 100644 --- a/src/southbridge/amd/sb700/ide.c +++ b/src/southbridge/amd/sb700/ide.c @@ -56,7 +56,7 @@ static void ide_init(struct device *dev) /* set ide as primary, if you want to boot from IDE, you'd better set it * in $vendor/$mainboard/devicetree.cb */ if (conf->boot_switch_sata_ide == 1) { - struct device *sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + struct device *sm_dev = pcidev_on_root(0x14, 0); byte = pci_read_config8(sm_dev, 0xad); byte |= 1 << 4; pci_write_config8(sm_dev, 0xad, byte); diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 857503a7ed..eb0af0de1c 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -40,7 +40,7 @@ static void lpc_init(struct device *dev) printk(BIOS_SPEW, "%s\n", __func__); /* Enable the LPC Controller */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); dword = pci_read_config32(sm_dev, 0x64); dword |= 1 << 20; pci_write_config32(sm_dev, 0x64, dword); diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index 975e5ac132..f1c05f62f6 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -134,7 +134,7 @@ static void sata_init(struct device *dev) struct device *sm_dev; /* SATA SMBus Disable */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); /* WARNING * Enabling the SATA link latency enhancement (SMBUS 0xAD bit 5) @@ -171,7 +171,7 @@ static void sata_init(struct device *dev) struct device *ide_dev; /* IDE Device */ - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); + ide_dev = pcidev_on_root(0x14, 1); /* Disable legacy IDE mode (enable PATA_BAR0/2) */ byte = pci_read_config8(ide_dev, 0x09); diff --git a/src/southbridge/amd/sb700/spi.c b/src/southbridge/amd/sb700/spi.c index 1fa29aa817..8dc142db45 100644 --- a/src/southbridge/amd/sb700/spi.c +++ b/src/southbridge/amd/sb700/spi.c @@ -31,7 +31,7 @@ static uint32_t get_spi_bar(void) { struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + dev = pcidev_on_root(0x14, 3); return pci_read_config32(dev, 0xa0) & ~0x1f; } diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c index bf790565ee..3ca12f6866 100644 --- a/src/southbridge/amd/sb700/usb.c +++ b/src/southbridge/amd/sb700/usb.c @@ -35,7 +35,7 @@ static void usb_init(struct device *dev) /* 6.1 Enable OHCI0-4 and EHCI Controllers */ struct device *sm_dev; - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); byte = pci_read_config8(sm_dev, 0x68); byte |= 0xFF; pci_write_config8(sm_dev, 0x68, byte); @@ -88,7 +88,7 @@ static void usb_init2(struct device *dev) if (get_option(&nvram, "ehci_async_data_cache") == CB_SUCCESS) ehci_async_data_cache = !!nvram; - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); rev = get_sb700_revision(sm_dev); /* dword = pci_read_config32(dev, 0xf8); */ diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 3bbf823ddb..e67dcd7464 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -35,7 +35,7 @@ static void lpc_init(struct device *dev) struct device *sm_dev; /* Enable the LPC Controller */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); dword = pci_read_config32(sm_dev, 0x64); dword |= 1 << 20; pci_write_config32(sm_dev, 0x64, dword); diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c index 2186d37a41..acb899f6c2 100644 --- a/src/southbridge/amd/sb800/sata.c +++ b/src/southbridge/amd/sb800/sata.c @@ -88,7 +88,7 @@ static void sata_init(struct device *dev) struct device *sm_dev; /* SATA SMBus Disable */ /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); /* get rev_id */ rev_id = pci_read_config8(sm_dev, 0x08) - 0x2F; diff --git a/src/southbridge/amd/sb800/usb.c b/src/southbridge/amd/sb800/usb.c index 715095f443..9850014de1 100644 --- a/src/southbridge/amd/sb800/usb.c +++ b/src/southbridge/amd/sb800/usb.c @@ -57,7 +57,7 @@ static void usb_init2(struct device *dev) void *usb2_bar0; struct device *sm_dev; - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); //rev = get_sb800_revision(sm_dev); /* dword = pci_read_config32(dev, 0xf8); */ diff --git a/src/southbridge/amd/sr5650/ht.c b/src/southbridge/amd/sr5650/ht.c index 1b4c99bc6f..f8db2b8c6d 100644 --- a/src/southbridge/amd/sr5650/ht.c +++ b/src/southbridge/amd/sr5650/ht.c @@ -187,8 +187,8 @@ static void sr5690_set_resources(struct device *dev) printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__); /* Find requisite AMD CPU devices */ - amd_ht_cfg_dev = dev_find_slot(0, PCI_DEVFN(0x18, 0)); - amd_addr_map_dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + amd_ht_cfg_dev = pcidev_on_root(0x18, 0); + amd_addr_map_dev = pcidev_on_root(0x18, 1); if (!amd_ht_cfg_dev || !amd_addr_map_dev) { printk(BIOS_WARNING, "%s: %s Unable to locate CPU control devices\n", __func__, dev_path(dev)); diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index 5084a122ce..9d4c689759 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -843,7 +843,7 @@ static void lock_hwinitreg(struct device *nb_dev) */ void sr56x0_lock_hwinitreg(void) { - struct device *nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *nb_dev = pcidev_on_root(0, 0); /* Lock HWInit Register */ lock_hwinitreg(nb_dev); diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 0f8b265781..119e4f3141 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -129,8 +129,8 @@ void l1cfg_ind_write_index(struct device *nb_dev, uint32_t index, uint32_t data) void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) { /* K8 Function1 is address map */ - struct device *k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + struct device *k8_f1 = pcidev_on_root(0x18, 1); + struct device *k8_f0 = pcidev_on_root(0x18, 0); if (in_out) { u32 dword, sblk; @@ -331,7 +331,7 @@ void detect_and_enable_iommu(struct device *iommu_dev) { if (iommu) { printk(BIOS_DEBUG, "Initializing IOMMU\n"); - struct device *nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *nb_dev = pcidev_on_root(0, 0); if (!nb_dev) { printk(BIOS_WARNING, "Unable to find SR5690 device! IOMMU NOT initialized\n"); @@ -616,7 +616,7 @@ void sr5650_enable(struct device *dev) struct southbridge_amd_sr5650_config *cfg; printk(BIOS_INFO, "sr5650_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); - nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + nb_dev = pcidev_on_root(0, 0); if (!nb_dev) { die("sr5650_enable: CAN NOT FIND SR5650 DEVICE, HALT!\n"); /* NOT REACHED */ @@ -624,7 +624,7 @@ void sr5650_enable(struct device *dev) cfg = (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; /* sb_dev (dev 8) is a bridge that links to southbridge. */ - sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0)); + sb_dev = pcidev_on_root(8, 0); if (!sb_dev) { die("sr5650_enable: CAN NOT FIND SB bridge, HALT!\n"); /* NOT REACHED */ @@ -823,14 +823,14 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) { uint8_t *p; - struct device *nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *nb_dev = pcidev_on_root(0, 0); if (!nb_dev) { printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 " "device! IVRS table not generated...\n"); return (unsigned long)ivrs; } - struct device *iommu_dev = dev_find_slot(0, PCI_DEVFN(0, 2)); + struct device *iommu_dev = pcidev_on_root(0, 2); if (!iommu_dev) { printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 " "IOMMU device! IVRS table not generated...\n"); diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c index 2ccdf83c4d..ef345efb75 100644 --- a/src/southbridge/intel/bd82x6x/elog.c +++ b/src/southbridge/intel/bd82x6x/elog.c @@ -30,7 +30,7 @@ void pch_log_state(void) u32 gpe0_sts, gpe0_en; u8 gen_pmcon_2; int i; - struct device *lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *lpc = pcidev_on_root(0x1f, 0); if (!lpc) return; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 7ae538ebd2..d3da239321 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -738,7 +738,7 @@ static void southbridge_inject_dsdt(struct device *dev) void acpi_fill_fadt(acpi_fadt_t *fadt) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; @@ -875,7 +875,7 @@ static const char *lpc_acpi_name(const struct device *dev) static void southbridge_fill_ssdt(struct device *device) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 00265d0219..1a646b17b9 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -32,11 +32,9 @@ int pch_silicon_revision(void) static int pch_revision_id = -1; #ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 0); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); #else - struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); #endif if (pch_revision_id < 0) @@ -49,11 +47,9 @@ int pch_silicon_type(void) static int pch_type = -1; #ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 0); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); #else - struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); #endif if (pch_type < 0) diff --git a/src/southbridge/intel/bd82x6x/watchdog.c b/src/southbridge/intel/bd82x6x/watchdog.c index eb4d38cd2c..c186f353ba 100644 --- a/src/southbridge/intel/bd82x6x/watchdog.c +++ b/src/southbridge/intel/bd82x6x/watchdog.c @@ -34,7 +34,7 @@ void watchdog_off(void) struct device *dev; /* Get LPC device. */ - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + dev = pcidev_on_root(0x1f, 0); /* Disable interrupt. */ value = pci_read_config16(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/common/acpi_pirq_gen.c b/src/southbridge/intel/common/acpi_pirq_gen.c index 1f1a2ab258..6f28bc693f 100644 --- a/src/southbridge/intel/common/acpi_pirq_gen.c +++ b/src/southbridge/intel/common/acpi_pirq_gen.c @@ -32,7 +32,7 @@ static int create_pirq_matrix(char matrix[32][4]) struct device *dev; int num_devs = 0; - for (dev = dev_find_slot(0, PCI_DEVFN(0, 0)); dev; dev = dev->sibling) { + for (dev = pcidev_on_root(0, 0); dev; dev = dev->sibling) { u8 pci_dev; u8 int_pin; diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c index 7c8cfe8144..30c50283f6 100644 --- a/src/southbridge/intel/common/gpio.c +++ b/src/southbridge/intel/common/gpio.c @@ -31,7 +31,7 @@ #if defined(__SIMPLE_DEVICE__) #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) #else -#define PCH_LPC_DEV dev_find_slot(0, PCI_DEVFN(0x1f, 0)) +#define PCH_LPC_DEV pcidev_on_root(0x1f, 0) #endif static u16 get_gpio_base(void) diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index 2de57d6da4..8b3274f524 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -33,7 +33,7 @@ #if defined(__SIMPLE_DEVICE__) #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) #else -#define PCH_LPC_DEV dev_find_slot(0, PCI_DEVFN(0x1f, 0)) +#define PCH_LPC_DEV pcidev_on_root(0x1f, 0) #endif u16 lpc_get_pmbase(void) diff --git a/src/southbridge/intel/common/rtc.c b/src/southbridge/intel/common/rtc.c index e9ac2c2deb..1f0abeb450 100644 --- a/src/southbridge/intel/common/rtc.c +++ b/src/southbridge/intel/common/rtc.c @@ -27,7 +27,7 @@ #if defined(__SIMPLE_DEVICE__) #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) #else -#define PCH_LPC_DEV dev_find_slot(0, PCI_DEVFN(0x1f, 0)) +#define PCH_LPC_DEV pcidev_on_root(0x1f, 0) #endif int rtc_failure(void) diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 3ca0d6c8d6..9bc34140a9 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -306,7 +306,7 @@ void spi_init(void) #ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 31, 0); #else - struct device *dev = dev_find_slot(0, PCI_DEVFN(31, 0)); + struct device *dev = pcidev_on_root(31, 0); #endif pci_read_config_dword(dev, 0xf0, &rcba); diff --git a/src/southbridge/intel/fsp_rangeley/soc.c b/src/southbridge/intel/fsp_rangeley/soc.c index 13b64c4e7f..fd83342ac7 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.c +++ b/src/southbridge/intel/fsp_rangeley/soc.c @@ -29,7 +29,7 @@ int soc_silicon_revision(void) { if (soc_revision_id < 0) soc_revision_id = pci_read_config8( - dev_find_slot(0, PCI_DEVFN(0x1f, 0)), + pcidev_on_root(0x1f, 0), PCI_REVISION_ID); return soc_revision_id; } @@ -38,7 +38,7 @@ int soc_silicon_type(void) { if (soc_type < 0) soc_type = pci_read_config8( - dev_find_slot(0, PCI_DEVFN(0x1f, 0)), + pcidev_on_root(0x1f, 0), PCI_DEVICE_ID + 1); return soc_type; } diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 97548069ad..1571925027 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -341,14 +341,13 @@ void spi_init(void) { int ich_version = 0; uint8_t bios_cntl; - struct device *dev; uint32_t ids; uint16_t vendor_id, device_id; #ifdef __SMM__ - dev = PCI_DEV(0, 31, 0); + pci_devfn_t dev = PCI_DEV(0, 31, 0); #else - dev = dev_find_slot(0, PCI_DEVFN(31, 0)); + struct device *dev = pcidev_on_root(31, 0); #endif pci_read_config_dword(dev, 0, &ids); vendor_id = ids; diff --git a/src/southbridge/intel/fsp_rangeley/watchdog.c b/src/southbridge/intel/fsp_rangeley/watchdog.c index ff1c571505..d7d3141e59 100644 --- a/src/southbridge/intel/fsp_rangeley/watchdog.c +++ b/src/southbridge/intel/fsp_rangeley/watchdog.c @@ -29,7 +29,7 @@ void watchdog_off(void) u32 value, abase; /* Turn off the watchdog. */ - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + dev = pcidev_on_root(0x1f, 0); /* Enable I/O space. */ value = pci_read_config16(dev, 0x04); diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index 0ff813e1ae..bdea66f9b3 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -238,7 +238,7 @@ static void smm_relocate(void) printk(BIOS_DEBUG, "Initializing SMM handler..."); - pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), 0x40) & 0xfffc; + pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffc; printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); smi_en = inl(pmbase + SMI_EN); @@ -317,7 +317,7 @@ static void smm_relocate(void) static void smm_install(void) { /* enable the SMM memory window */ - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + pci_write_config8(pcidev_on_root(0, 0), SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG); /* copy the real SMM handler */ @@ -326,7 +326,7 @@ static void smm_install(void) wbinvd(); /* close the SMM memory window and enable normal SMM */ - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + pci_write_config8(pcidev_on_root(0, 0), SMRAM, G_SMRAME | C_BASE_SEG); } @@ -354,7 +354,7 @@ void smm_lock(void) * make the SMM registers writable again. */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + pci_write_config8(pcidev_on_root(0, 0), SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 7dcec507a8..c16b8a6649 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -487,7 +487,7 @@ unsigned long acpi_fill_madt(unsigned long current) void acpi_fill_fadt(acpi_fadt_t *fadt) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 588d68701c..567c1e5047 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -28,7 +28,7 @@ static u8 get_ich7_sata_ports(void) { struct device *lpc; - lpc = dev_find_slot(0, PCI_DEVFN(31, 0)); + lpc = pcidev_on_root(31, 0); switch (pci_read_config16(lpc, PCI_DEVICE_ID)) { case 0x27b0: diff --git a/src/southbridge/intel/i82801gx/watchdog.c b/src/southbridge/intel/i82801gx/watchdog.c index ac2de3a66c..ff4da6412c 100644 --- a/src/southbridge/intel/i82801gx/watchdog.c +++ b/src/southbridge/intel/i82801gx/watchdog.c @@ -26,7 +26,7 @@ void watchdog_off(void) unsigned long value, base; /* Turn off the ICH7 watchdog. */ - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + dev = pcidev_on_root(0x1f, 0); /* Enable I/O space. */ value = pci_read_config16(dev, 0x04); diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 797856ea78..46838fcbf4 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -58,7 +58,7 @@ static void i82801ix_pcie_init(const config_t *const info) /* PCIe - BIOS must program... */ for (i = 0; i < 6; ++i) { - pciePort[i] = dev_find_slot(0, PCI_DEVFN(0x1c, i)); + pciePort[i] = pcidev_on_root(0x1c, i); if (!pciePort[i]) { printk(BIOS_EMERG, "PCIe port 00:1c.%x", i); die(" is not listed in devicetree.\n"); @@ -68,7 +68,7 @@ static void i82801ix_pcie_init(const config_t *const info) pci_write_config8(pciePort[i], 0x324, 0x40); } - if (LPC_IS_MOBILE(dev_find_slot(0, PCI_DEVFN(0x1f, 0)))) { + if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0))) { for (i = 0; i < 6; ++i) { if (pciePort[i]->enabled) { reg32 = pci_read_config32(pciePort[i], 0xe8); @@ -116,10 +116,10 @@ static void i82801ix_pcie_init(const config_t *const info) static void i82801ix_ehci_init(void) { - struct device *const pciEHCI1 = dev_find_slot(0, PCI_DEVFN(0x1d, 7)); + struct device *const pciEHCI1 = pcidev_on_root(0x1d, 7); if (!pciEHCI1) die("EHCI controller (00:1d.7) not listed in devicetree.\n"); - struct device *const pciEHCI2 = dev_find_slot(0, PCI_DEVFN(0x1a, 7)); + struct device *const pciEHCI2 = pcidev_on_root(0x1a, 7); if (!pciEHCI2) die("EHCI controller (00:1a.7) not listed in devicetree.\n"); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 474c484ad6..b809a4e3b7 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -566,7 +566,7 @@ static const char *lpc_acpi_name(const struct device *dev) static void southbridge_fill_ssdt(struct device *device) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index e35babce28..e3b7e14b8c 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -213,8 +213,7 @@ static void sata_init(struct device *const dev) pci_write_config32(dev, 0x94, sclkcg); if (is_mobile && config->sata_traffic_monitor) { - struct device *const lpc_dev = dev_find_slot(0, - PCI_DEVFN(0x1f, 0)); + struct device *const lpc_dev = pcidev_on_root(0x1f, 0); if (((pci_read_config8(lpc_dev, D31F0_CxSTATE_CNF) >> 3) & 3) == 3) { u8 reg8 = pci_read_config8(dev, 0x9c); diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index 9dc9a3b989..74fa495695 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -50,7 +50,8 @@ static void smm_relocate(void) printk(BIOS_DEBUG, "Initializing SMM handler..."); - pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), D31F0_PMBASE) & 0xfffc; + pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), D31F0_PMBASE) & + 0xfffc; printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); smi_en = inl(pmbase + SMI_EN); @@ -138,7 +139,7 @@ static void smm_install(void) if (!acpi_is_wakeup_s3()) { /* enable the SMM memory window */ - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + pci_write_config8(pcidev_on_root(0, 0), SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG); /* copy the real SMM handler */ @@ -148,7 +149,7 @@ static void smm_install(void) } /* close the SMM memory window and enable normal SMM */ - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + pci_write_config8(pcidev_on_root(0, 0), SMRAM, G_SMRAME | C_BASE_SEG); } @@ -176,6 +177,6 @@ void smm_lock(void) * make the SMM registers writable again. */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + pci_write_config8(pcidev_on_root(0, 0), SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } diff --git a/src/southbridge/intel/i82801ix/thermal.c b/src/southbridge/intel/i82801ix/thermal.c index 5f40d2ec7c..931198254d 100644 --- a/src/southbridge/intel/i82801ix/thermal.c +++ b/src/southbridge/intel/i82801ix/thermal.c @@ -24,7 +24,7 @@ static void thermal_init(struct device *dev) { - if (LPC_IS_MOBILE(dev_find_slot(0, PCI_DEVFN(0x1f, 0)))) + if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0))) return; u8 reg8; diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c index 31df5c4d14..2f3ed4b195 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.c +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -57,7 +57,7 @@ static void i82801jx_pcie_init(const config_t *const info) /* PCIe - BIOS must program... */ for (i = 0; i < 6; ++i) { - pciePort[i] = dev_find_slot(0, PCI_DEVFN(0x1c, i)); + pciePort[i] = pcidev_on_root(0x1c, i); if (!pciePort[i]) { printk(BIOS_EMERG, "PCIe port 00:1c.%x", i); die(" is not listed in devicetree.\n"); @@ -67,7 +67,7 @@ static void i82801jx_pcie_init(const config_t *const info) pci_write_config8(pciePort[i], 0x324, 0x40); } - if (LPC_IS_MOBILE(dev_find_slot(0, PCI_DEVFN(0x1f, 0)))) { + if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0))) { for (i = 0; i < 6; ++i) { if (pciePort[i]->enabled) { reg32 = pci_read_config32(pciePort[i], 0xe8); @@ -115,10 +115,10 @@ static void i82801jx_pcie_init(const config_t *const info) static void i82801jx_ehci_init(void) { - struct device *const pciEHCI1 = dev_find_slot(0, PCI_DEVFN(0x1d, 7)); + struct device *const pciEHCI1 = pcidev_on_root(0x1d, 7); if (!pciEHCI1) die("EHCI controller (00:1d.7) not listed in devicetree.\n"); - struct device *const pciEHCI2 = dev_find_slot(0, PCI_DEVFN(0x1a, 7)); + struct device *const pciEHCI2 = pcidev_on_root(0x1a, 7); if (!pciEHCI2) die("EHCI controller (00:1a.7) not listed in devicetree.\n"); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index b9f2e4bffc..2ff2acd095 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -501,7 +501,7 @@ unsigned long acpi_fill_madt(unsigned long current) void acpi_fill_fadt(acpi_fadt_t *fadt) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; @@ -727,7 +727,7 @@ static const char *lpc_acpi_name(const struct device *dev) static void southbridge_fill_ssdt(struct device *device) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index b511c54d57..5978294616 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -208,8 +208,7 @@ static void sata_init(struct device *const dev) pci_write_config32(dev, 0x94, sclkcg); if (is_mobile && config->sata_traffic_monitor) { - struct device *const lpc_dev = dev_find_slot(0, - PCI_DEVFN(0x1f, 0)); + struct device *const lpc_dev = pcidev_on_root(0x1f, 0); if (((pci_read_config8(lpc_dev, D31F0_CxSTATE_CNF) >> 3) & 3) == 3) { u8 reg8 = pci_read_config8(dev, 0x9c); diff --git a/src/southbridge/intel/i82801jx/thermal.c b/src/southbridge/intel/i82801jx/thermal.c index ae111a6e07..4a8ba290f3 100644 --- a/src/southbridge/intel/i82801jx/thermal.c +++ b/src/southbridge/intel/i82801jx/thermal.c @@ -24,7 +24,7 @@ static void thermal_init(struct device *dev) { - if (LPC_IS_MOBILE(dev_find_slot(0, PCI_DEVFN(0x1f, 0)))) + if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0))) return; u8 reg8; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index e5cbc594ae..24a217d284 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -647,7 +647,7 @@ static void southbridge_inject_dsdt(struct device *dev) void acpi_fill_fadt(acpi_fadt_t *fadt) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; @@ -783,7 +783,7 @@ static const char *lpc_acpi_name(const struct device *dev) static void southbridge_fill_ssdt(struct device *device) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 27a3b2954c..46e803d82f 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -99,7 +99,7 @@ static int sleep_type_s3(void) void pch_enable_lpc(void) { - const struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + const struct device *dev = pcidev_on_root(0x1f, 0); const struct southbridge_intel_lynxpoint_config *config = NULL; /* Set COM1/COM2 decode range */ diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c index c575db0693..e16e1be18a 100644 --- a/src/southbridge/intel/lynxpoint/elog.c +++ b/src/southbridge/intel/lynxpoint/elog.c @@ -112,7 +112,7 @@ void pch_log_state(void) { u16 pm1_sts, gen_pmcon_3, tco2_sts; u8 gen_pmcon_2; - struct device *lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *lpc = pcidev_on_root(0x1f, 0); if (!lpc) return; diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index 2b07de2735..b6edc8da1f 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -27,7 +27,7 @@ static u16 get_gpio_base(void) #if defined(__PRE_RAM__) || defined(__SMM__) return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; #else - return pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), + return pci_read_config16(pcidev_on_root(0x1f, 0), GPIO_BASE) & 0xfffc; #endif } diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index f0fc22deaf..5b48da0848 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -456,7 +456,7 @@ static void enable_lp_clock_gating(struct device *dev) RCBA32_AND_OR(0x2614, 0x8bffffff, 0x0a206500); /* Check for LPT-LP B2 stepping and 0:31.0@0xFA > 4 */ - if (pci_read_config8(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x8) >= 0x0b) + if (pci_read_config8(pcidev_on_root(2, 0), 0x8) >= 0x0b) RCBA32_OR(0x2614, (1 << 26)); RCBA32_OR(0x900, 0x0000031f); @@ -775,7 +775,7 @@ static void southbridge_inject_dsdt(struct device *dev) void acpi_fill_fadt(acpi_fadt_t *fadt) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); struct southbridge_intel_lynxpoint_config *cfg = dev->chip_info; u16 pmbase = get_pmbase(); diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 1fb6d7ad54..b197bbcfc4 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -31,7 +31,7 @@ static pci_devfn_t pch_get_lpc_device(void) #else static struct device *pch_get_lpc_device(void) { - return dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + return pcidev_on_root(0x1f, 0); } #endif diff --git a/src/southbridge/intel/lynxpoint/watchdog.c b/src/southbridge/intel/lynxpoint/watchdog.c index 9a867e413a..ec7cb5d0b5 100644 --- a/src/southbridge/intel/lynxpoint/watchdog.c +++ b/src/southbridge/intel/lynxpoint/watchdog.c @@ -32,7 +32,7 @@ void watchdog_off(void) unsigned long value, base; /* Turn off the ICH7 watchdog. */ - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + dev = pcidev_on_root(0x1f, 0); /* Enable I/O space. */ value = pci_read_config16(dev, 0x04); diff --git a/src/southbridge/nvidia/ck804/ht.c b/src/southbridge/nvidia/ck804/ht.c index 48b18cb636..6028cd663f 100644 --- a/src/southbridge/nvidia/ck804/ht.c +++ b/src/southbridge/nvidia/ck804/ht.c @@ -29,7 +29,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) struct device *dev; unsigned long mcfg_base; - dev = dev_find_slot(0x0, PCI_DEVFN(0x0,0)); + dev = pcidev_on_root(0x0, 0); if (!dev) return current; |