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-rw-r--r--src/soc/nvidia/tegra124/Kconfig2
-rw-r--r--src/soc/nvidia/tegra124/Makefile.inc3
-rw-r--r--src/soc/nvidia/tegra124/bootblock.c52
-rw-r--r--src/soc/nvidia/tegra124/uart.c137
4 files changed, 192 insertions, 2 deletions
diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig
index 7f03ad71ce..4f33f566a7 100644
--- a/src/soc/nvidia/tegra124/Kconfig
+++ b/src/soc/nvidia/tegra124/Kconfig
@@ -2,6 +2,8 @@ config SOC_NVIDIA_TEGRA124
select ARCH_BOOTBLOCK_ARMV7
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
+ select HAVE_UART_SPECIAL
+ select BOOTBLOCK_CONSOLE
select ARM_BOOTBLOCK_CUSTOM
bool
default n
diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc
index c7d56ab114..34d24da6c1 100644
--- a/src/soc/nvidia/tegra124/Makefile.inc
+++ b/src/soc/nvidia/tegra124/Makefile.inc
@@ -14,14 +14,17 @@ bootblock-y += ../tegra/i2c.c
bootblock-y += ../tegra/pingroup.c
bootblock-y += ../tegra/pinmux.c
bootblock-y += timer.c
+bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c
romstage-y += cbfs.c
romstage-y += monotonic_timer.c
romstage-y += timer.c
+romstage-y += uart.c
ramstage-y += cbfs.c
ramstage-y += monotonic_timer.c
ramstage-y += timer.c
+ramstage-y += uart.c
CPPFLAGS_common += -Isrc/soc/nvidia/tegra124/include/
diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c
index 97180a0a33..cd7ea34147 100644
--- a/src/soc/nvidia/tegra124/bootblock.c
+++ b/src/soc/nvidia/tegra124/bootblock.c
@@ -18,19 +18,67 @@
*/
#include <arch/hlt.h>
-#include <arch/stages.h>
+#include <arch/io.h>
#include <cbfs.h>
#include <console/console.h>
+static void hacky_hardcoded_uart_setup_function(void)
+{
+ int i;
+
+ /*
+ * On poweron, AVP clock source (also called system clock) is set to
+ * PLLP_out0 with frequency set at 1MHz. Before initializing PLLP, we
+ * need to move the system clock's source to CLK_M temporarily. And
+ * then switch it to PLLP_out4 (204MHz) at a later time.
+ */
+ write32((0 << 12) | (0 << 8) | (0 << 4) | (0 << 0) | (2 << 28),
+ (void *)(0x60006000 + 0x28));
+
+ // wait a little bit (nominally 2-3 us)
+ for (i = 0; i < 0x10000; i++)
+ __asm__ __volatile__("");
+
+ // Set function.
+ setbits_le32((void *)(0x70000000 + 0x3000 + 0x2e0), 3 << 0);
+ setbits_le32((void *)(0x70000000 + 0x3000 + 0x2e4), 3 << 0);
+
+ // Output.
+ clrbits_le32((void *)(0x70000000 + 0x3000 + 0x2e0), 1 << 5);
+ // Input.
+ setbits_le32((void *)(0x70000000 + 0x3000 + 0x2e4), 1 << 5);
+
+ // Disable tristate.
+ clrbits_le32((void *)(0x70000000 + 0x3000 + 0x2e0), 1 << 4);
+ clrbits_le32((void *)(0x70000000 + 0x3000 + 0x2e4), 1 << 4);
+
+ // Assert UART reset and enable clock.
+ setbits_le32((void *)(0x60006000 + 4 + 0), 1 << 6);
+
+ // Enable the clock.
+ setbits_le32((void *)(0x60006000 + 4 * 4 + 0), 1 << 6);
+
+ // Set the clock source.
+ clrbits_le32((void *)(0x60006000 + 0x100 + 4 * 0x1e), 3 << 30);
+
+ // wait a little bit (nominally 2us?)
+ for (i = 0; i < 0x10000; i++)
+ __asm__ __volatile__("");
+
+ // De-assert reset to UART.
+ clrbits_le32((void *)(0x60006000 + 4 + 0), 1 << 6);
+}
+
void main(void)
{
void *entry;
+ hacky_hardcoded_uart_setup_function();
+
if (CONFIG_BOOTBLOCK_CONSOLE)
console_init();
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage");
- if (entry) stage_exit(entry);
hlt();
}
diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c
new file mode 100644
index 0000000000..d28cbb7016
--- /dev/null
+++ b/src/soc/nvidia/tegra124/uart.c
@@ -0,0 +1,137 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/uart.h>
+#include <arch/io.h>
+#include <boot/coreboot_tables.h>
+#include <console/console.h> /* for __console definition */
+#include <drivers/uart/uart8250reg.h>
+
+
+struct tegra124_uart {
+ union {
+ uint32_t thr; // Transmit holding register.
+ uint32_t rbr; // Receive buffer register.
+ uint32_t dll; // Divisor latch lsb.
+ };
+ union {
+ uint32_t ier; // Interrupt enable register.
+ uint32_t dlm; // Divisor latch msb.
+ };
+ union {
+ uint32_t iir; // Interrupt identification register.
+ uint32_t fcr; // FIFO control register.
+ };
+ uint32_t lcr; // Line control register.
+ uint32_t mcr; // Modem control register.
+ uint32_t lsr; // Line status register.
+ uint32_t msr; // Modem status register.
+} __attribute__ ((packed));
+
+static void tegra124_uart_tx_flush(struct tegra124_uart *uart_ptr);
+static int tegra124_uart_tst_byte(struct tegra124_uart *uart_ptr);
+
+static void tegra124_uart_init(struct tegra124_uart *uart_ptr)
+{
+ // Use a hardcoded divisor for now.
+ const unsigned divisor = 221;
+ const uint8_t line_config = UART8250_LCR_WLS_8; // 8n1
+
+ tegra124_uart_tx_flush(uart_ptr);
+
+ // Disable interrupts.
+ write8(0, &uart_ptr->ier);
+ // Set line configuration, access divisor latches.
+ write8(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr);
+ // Set the divisor.
+ write8(divisor & 0xff, &uart_ptr->dll);
+ write8((divisor >> 8) & 0xff, &uart_ptr->dlm);
+ // Hide the divisor latches.
+ write8(line_config, &uart_ptr->lcr);
+ // Enable FIFOs, and clear receive and transmit.
+ write8(UART8250_FCR_FIFO_EN |
+ UART8250_FCR_CLEAR_RCVR |
+ UART8250_FCR_CLEAR_XMIT, &uart_ptr->fcr);
+}
+
+static unsigned char tegra124_uart_rx_byte(struct tegra124_uart *uart_ptr)
+{
+ if (!tegra124_uart_tst_byte(uart_ptr))
+ return 0;
+ return read8(&uart_ptr->rbr);
+}
+
+static void tegra124_uart_tx_byte(struct tegra124_uart *uart_ptr, unsigned char data)
+{
+ while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE));
+ write8(data, &uart_ptr->thr);
+}
+
+static void tegra124_uart_tx_flush(struct tegra124_uart *uart_ptr)
+{
+ while (!(read8(&uart_ptr->lsr) & UART8250_LSR_TEMT));
+}
+
+static int tegra124_uart_tst_byte(struct tegra124_uart *uart_ptr)
+{
+ return (read8(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR;
+}
+
+unsigned int uart_platform_base(int idx)
+{
+ //TODO:return the correct address based on which UART has been selected
+ return CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
+}
+
+void uart_init(int idx)
+{
+ struct tegra124_uart *uart_ptr = uart_platform_baseptr(idx);
+ tegra124_uart_init(uart_ptr);
+}
+
+unsigned char uart_rx_byte(int idx)
+{
+ struct tegra124_uart *uart_ptr = uart_platform_baseptr(idx);
+ return tegra124_uart_rx_byte(uart_ptr);
+}
+
+void uart_tx_byte(int idx, unsigned char data)
+{
+ struct tegra124_uart *uart_ptr = uart_platform_baseptr(idx);
+ tegra124_uart_tx_byte(uart_ptr, data);
+}
+
+void uart_tx_flush(int idx)
+{
+ struct tegra124_uart *uart_ptr = uart_platform_baseptr(idx);
+ tegra124_uart_tx_flush(uart_ptr);
+}
+
+#ifndef __PRE_RAM__
+void uart_fill_lb(void *data)
+{
+ struct lb_serial serial;
+ serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+ serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
+ serial.baud = default_baudrate();
+ lb_add_serial(&serial, data);
+
+ lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
+}
+#endif