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-rw-r--r--src/mainboard/intel/saddlebrook/Kconfig1
-rw-r--r--src/mainboard/intel/saddlebrook/devicetree.cb5
-rw-r--r--src/soc/intel/apollolake/chip.c2
-rw-r--r--src/soc/intel/cannonlake/romstage/fsp_params.c3
-rw-r--r--src/soc/intel/common/block/chip/chip.c15
-rw-r--r--src/soc/intel/common/block/cpu/mp_init.c4
-rw-r--r--src/soc/intel/common/block/include/intelblocks/chip.h15
-rw-r--r--src/soc/intel/skylake/chip.c2
-rw-r--r--src/soc/intel/skylake/chip_fsp20.c3
9 files changed, 9 insertions, 41 deletions
diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig
index 524bcca011..f2b7344aaa 100644
--- a/src/mainboard/intel/saddlebrook/Kconfig
+++ b/src/mainboard/intel/saddlebrook/Kconfig
@@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS
select SADDLEBROOK_USES_FSP1_1
select HAVE_CMOS_DEFAULT
select MAINBOARD_USES_IFD_GBE_REGION
+ select USE_INTEL_FSP_MP_INIT
config SADDLEBROOK_USES_FSP1_1
bool "FSP driver 1.1"
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index 8f78249b3b..2f84a5dde5 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -140,11 +140,6 @@ chip soc/intel/skylake
.voltage_limit = 0x5F0 \
}"
- # Skip coreboot MP Init
- register "common_soc_config" = "{
- .use_fsp_mp_init = 1,
- }"
-
# Enable x1 slot
register "PcieRpEnable[7]" = "1"
register "PcieRpClkReqSupport[7]" = "1"
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 30a537b675..9d721671a8 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -733,7 +733,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
if (!CONFIG(SOC_INTEL_GLK))
silconfig->MonitorMwaitEnable = 0;
- silconfig->SkipMpInit = !chip_get_fsp_mp_init();
+ silconfig->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
/* Disable setting of EISS bit in FSP. */
silconfig->SpiEiss = 0;
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 791a6c83d3..3e3aa5e22a 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -64,8 +64,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
m_cfg->VmxEnable = 0;
else
m_cfg->VmxEnable = config->VmxEnable;
+
#if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE)
- m_cfg->SkipMpInit = !chip_get_fsp_mp_init();
+ m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
#endif
/* Disable CPU Flex Ratio and SaGv in recovery mode */
diff --git a/src/soc/intel/common/block/chip/chip.c b/src/soc/intel/common/block/chip/chip.c
index 3dae6214ff..eed1ada0e8 100644
--- a/src/soc/intel/common/block/chip/chip.c
+++ b/src/soc/intel/common/block/chip/chip.c
@@ -32,18 +32,3 @@ const struct soc_intel_common_config *chip_get_common_soc_structure(void)
return soc_config;
}
-
-/*
- * This function will get MP Init config
- *
- * Return values:
- * 0 = Make use of coreboot MP Init
- * 1 = Make use of FSP MP Init
- */
-int chip_get_fsp_mp_init(void)
-{
- const struct soc_intel_common_config *common_config;
- common_config = chip_get_common_soc_structure();
-
- return common_config->use_fsp_mp_init;
-}
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 48bc496dbc..342a1203e4 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -133,7 +133,7 @@ static void init_cpus(void *unused)
struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER);
assert(dev != NULL);
- if (chip_get_fsp_mp_init())
+ if (CONFIG(USE_INTEL_FSP_MP_INIT))
return;
microcode_patch = intel_microcode_find();
@@ -151,7 +151,7 @@ static void wrapper_x86_setup_mtrrs(void *unused)
/* Ensure to re-program all MTRRs based on DRAM resource settings */
static void post_cpus_init(void *unused)
{
- if (chip_get_fsp_mp_init())
+ if (CONFIG(USE_INTEL_FSP_MP_INIT))
return;
if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL, 1000) < 0)
diff --git a/src/soc/intel/common/block/include/intelblocks/chip.h b/src/soc/intel/common/block/include/intelblocks/chip.h
index d761f6be76..555bdaa893 100644
--- a/src/soc/intel/common/block/include/intelblocks/chip.h
+++ b/src/soc/intel/common/block/include/intelblocks/chip.h
@@ -33,24 +33,9 @@ struct soc_intel_common_config {
int chipset_lockdown;
struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
struct dw_i2c_bus_config i2c[CONFIG_SOC_INTEL_I2C_DEV_MAX];
- /*
- * Option for mainboard to skip coreboot MP initialization
- * 0 = Make use of coreboot MP Init
- * 1 = Make use of FSP MP Init
- */
- uint8_t use_fsp_mp_init;
};
/* This function to retrieve soc config structure required by common code */
const struct soc_intel_common_config *chip_get_common_soc_structure(void);
-/*
- * This function will get MP Init config
- *
- * Return values:
- * 0 = Make use of coreboot MP Init
- * 1 = Make use of FSP MP Init
- */
-int chip_get_fsp_mp_init(void);
-
#endif /* SOC_INTEL_COMMON_BLOCK_CHIP_H */
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 98e5baf483..9094348e78 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -197,7 +197,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->SerialIrqConfigStartFramePulse =
config->SerialIrqConfigStartFramePulse;
- params->SkipMpInit = !chip_get_fsp_mp_init();
+ params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++)
params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 15eb6b2651..c16a913218 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -27,6 +27,7 @@
#include <intelblocks/chip.h>
#include <intelblocks/itss.h>
#include <intelblocks/lpc_lib.h>
+#include <intelblocks/mp_init.h>
#include <intelblocks/xdci.h>
#include <intelpch/lockdown.h>
#include <romstage_handoff.h>
@@ -422,7 +423,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchSirqEnable = config->serirq_mode != SERIRQ_OFF;
params->PchSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS;
- params->CpuConfig.Bits.SkipMpInit = !chip_get_fsp_mp_init();
+ params->CpuConfig.Bits.SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++)
params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];