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-rw-r--r--src/soc/intel/cannonlake/chip.h2
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c7
2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index cb9ad3827f..1f26f1e146 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -216,6 +216,8 @@ struct soc_intel_cannonlake_config {
uint32_t tdp_psyspl3_dutycycle;
/* PL4 Value in Watts */
uint32_t tdp_pl4;
+ /* Estimated maximum platform power in Watts */
+ uint16_t psys_pmax;
/* Intel Speed Shift Technology */
uint8_t speed_shift_enable;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index c276c862e8..a198f1bfec 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -88,6 +88,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
mainboard_silicon_init_params(params);
+ /* Set PsysPmax if it is available from DT */
+ if (config->psys_pmax) {
+ printk(BIOS_DEBUG, "psys_pmax = %dW\n", config->psys_pmax);
+ /* PsysPmax is in unit of 1/8 Watt */
+ tconfig->PsysPmax = config->psys_pmax * 8;
+ }
+
/* Unlock upper 8 bytes of RTC RAM */
params->PchLockDownRtcMemoryLock = 0;