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-rw-r--r--src/mainboard/google/kahlee/mainboard.c12
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h12
2 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index bfd1f2f649..ebdcc935e9 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -146,15 +146,15 @@ static void mainboard_init(void *chip_info)
/* Set low-power mode for BayHub eMMC bridge's PCIe clock. */
clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL),
- GPP_CLK2_CLOCK_REQ_MAP_MASK,
- GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 <<
- GPP_CLK2_CLOCK_REQ_MAP_SHIFT);
+ GPP_CLK2_REQ_MAP_MASK,
+ GPP_CLK2_REQ_MAP_CLK_REQ2 <<
+ GPP_CLK2_REQ_MAP_SHIFT);
/* Same for the WiFi */
clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL),
- GPP_CLK0_CLOCK_REQ_MAP_MASK,
- GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 <<
- GPP_CLK0_CLOCK_REQ_MAP_SHIFT);
+ GPP_CLK0_REQ_MAP_MASK,
+ GPP_CLK0_REQ_MAP_CLK_REQ0 <<
+ GPP_CLK0_REQ_MAP_SHIFT);
}
/*************************************************
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index d25c90ba68..7f02811a3a 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -111,13 +111,13 @@
/* FCH MISC Registers 0xfed80e00 */
#define GPP_CLK_CNTRL 0
-#define GPP_CLK2_CLOCK_REQ_MAP_SHIFT 8
-#define GPP_CLK2_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK2_CLOCK_REQ_MAP_SHIFT)
-#define GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 3
+#define GPP_CLK2_REQ_MAP_SHIFT 8
+#define GPP_CLK2_REQ_MAP_MASK (0xf << GPP_CLK2_REQ_MAP_SHIFT)
+#define GPP_CLK2_REQ_MAP_CLK_REQ2 3
-#define GPP_CLK0_CLOCK_REQ_MAP_SHIFT 0
-#define GPP_CLK0_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK0_CLOCK_REQ_MAP_SHIFT)
-#define GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 1
+#define GPP_CLK0_REQ_MAP_SHIFT 0
+#define GPP_CLK0_REQ_MAP_MASK (0xf << GPP_CLK0_REQ_MAP_SHIFT)
+#define GPP_CLK0_REQ_MAP_CLK_REQ0 1
#define MISC_CGPLL_CONFIG1 0x08
#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0)