diff options
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 37 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/memmap.c | 31 |
2 files changed, 31 insertions, 37 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 47b9976786..544a93fd97 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -15,56 +15,19 @@ #include <stdint.h> #include <console/console.h> -#include <arch/cpu.h> #include <cf9_reset.h> #include <cpu/x86/bist.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> #include <timestamp.h> -#include <device/pci_def.h> #include <cpu/x86/lapic.h> #include <cbmem.h> #include <commonlib/helpers.h> -#include <program_loading.h> #include <romstage_handoff.h> -#include <vendorcode/google/chromeos/chromeos.h> -#if CONFIG(EC_GOOGLE_CHROMEEC) -#include <ec/google/chromeec/ec.h> -#endif #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/me.h> -#include <cpu/intel/romstage.h> #include "haswell.h" -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) -{ - struct postcar_frame pcf; - uintptr_t top_of_ram; - - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB - * above top of the ram. This satisfies MTRR alignment requirement - * with different TSEG size configurations. - */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, - MTRR_TYPE_WRBACK); - - run_postcar_phase(&pcf); -} - void romstage_common(const struct romstage_params *params) { int boot_mode; diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 3a63afcde6..14b66a0fc7 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -16,8 +16,12 @@ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ +#include <arch/cpu.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> #include <device/pci_ops.h> #include <cbmem.h> +#include <cpu/intel/romstage.h> #include <stage_cache.h> #include "haswell.h" @@ -48,3 +52,30 @@ void stage_cache_external_region(void **base, size_t *size) *size = CONFIG_SMM_RESERVED_SIZE; *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); } + +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +void platform_enter_postcar(void) +{ + struct postcar_frame pcf; + uintptr_t top_of_ram; + + if (postcar_frame_init(&pcf, 0)) + die("Unable to initialize postcar frame.\n"); + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache at least 8 MiB below the top of ram, and at most 8 MiB + * above top of the ram. This satisfies MTRR alignment requirement + * with different TSEG size configurations. + */ + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, + MTRR_TYPE_WRBACK); + + run_postcar_phase(&pcf); +} |