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-rw-r--r--src/cpu/amd/sc520/raminit.c19
-rw-r--r--src/cpu/amd/sc520/sc520.c13
2 files changed, 4 insertions, 28 deletions
diff --git a/src/cpu/amd/sc520/raminit.c b/src/cpu/amd/sc520/raminit.c
index 711614a5b8..c56117485a 100644
--- a/src/cpu/amd/sc520/raminit.c
+++ b/src/cpu/amd/sc520/raminit.c
@@ -234,18 +234,7 @@ dummy_write(void){
*ptr = 0;
}
-void sc520_udelay(int microseconds) {
- volatile int x;
- for(x = 0; x < 1000; x++)
- ;
-}
-
-/* looks like we define this now */
-void
-udelay(int microseconds) {
- sc520_udelay(microseconds);
-}
-
+#include "pc80/udelay_io.c"
static void dumpram(void){
print_err("ctl "); print_err_hex8(*drcctl); print_err("\n");
@@ -311,7 +300,7 @@ int sizemem(void)
print_err("NOP\n");
/* 100? 200? */
udelay(100);
- print_err("after sc520_udelay\n");
+ print_err("after udelay\n");
/* issue all banks precharge */
*drcctl=0x02;
@@ -385,8 +374,8 @@ int sizemem(void)
dummy_write();
print_err("NOP\n");
/* 100? 200? */
- //sc520_udelay(100);
- print_err("after sc520_udelay\n");
+ //udelay(100);
+ print_err("after udelay\n");
/* issue all banks precharge */
*drcctl=0x02;
diff --git a/src/cpu/amd/sc520/sc520.c b/src/cpu/amd/sc520/sc520.c
index 07991825cd..e867fae3d7 100644
--- a/src/cpu/amd/sc520/sc520.c
+++ b/src/cpu/amd/sc520/sc520.c
@@ -15,19 +15,6 @@
#include <delay.h>
#include "chip.h"
-
-/* hack for now */
-static void sc520_udelay(int microseconds) {
- volatile int x;
- for(x = 0; x < 1000; x++)
- ;
-}
-
-/* looks like we define this now */
-void
-udelay(unsigned microseconds) {
- sc520_udelay(microseconds);
-}
/*
* set up basic things ...
* PAR should NOT go here, as it might change with the mainboard.