summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/arch/x86/include/arch/memlayout.h7
-rw-r--r--src/include/memlayout.h18
-rw-r--r--src/include/rules.h25
-rw-r--r--src/lib/program.ld6
4 files changed, 20 insertions, 36 deletions
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index de80f42a0d..7dcdd981cb 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -16,13 +16,6 @@
#ifndef __ARCH_MEMLAYOUT_H
#define __ARCH_MEMLAYOUT_H
-
-#if ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE
-/* No .data or .bss sections. Cache as RAM is handled separately. */
-#define ARCH_STAGE_HAS_DATA_SECTION 0
-#define ARCH_STAGE_HAS_BSS_SECTION 0
-#endif
-
#if (CONFIG_RAMTOP == 0)
# error "CONFIG_RAMTOP not configured"
#endif
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 1ed87b61c9..505ccc1889 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -30,24 +30,6 @@
#define ARCH_CACHELINE_ALIGN_SIZE 64
#endif
-/* Default to data as well as bss. */
-#ifndef ARCH_STAGE_HAS_DATA_SECTION
-#define ARCH_STAGE_HAS_DATA_SECTION 1
-#endif
-
-#ifndef ARCH_STAGE_HAS_BSS_SECTION
-#define ARCH_STAGE_HAS_BSS_SECTION 1
-#endif
-
-/*
- * Default is that currently ENV_PAYLOAD_LOADER enable stage, smm,
- * and rmodules have a heap.
- */
-#ifndef ARCH_STAGE_HAS_HEAP_SECTION
-#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_PAYLOAD_LOADER || ENV_SMM || \
- ENV_RMODULE)
-#endif
-
#define STR(x) #x
#define ALIGN_COUNTER(align) \
diff --git a/src/include/rules.h b/src/include/rules.h
index 10cd715db1..ed147224b9 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -266,6 +266,23 @@
#define ENV_PAYLOAD_LOADER ENV_RAMSTAGE
#endif
+#if CONFIG(ARCH_X86)
+/* Indicates memory layout is determined by arch/x86/car.ld. */
+#define ENV_CACHE_AS_RAM (ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE)
+/* No .data sections with execute-in-place from ROM. */
+#define ENV_STAGE_HAS_DATA_SECTION !ENV_CACHE_AS_RAM
+/* No .bss sections with execute-in-place from ROM. */
+#define ENV_STAGE_HAS_BSS_SECTION !ENV_CACHE_AS_RAM
+#else
+/* Both .data and .bss, sometimes SRAM not DRAM. */
+#define ENV_STAGE_HAS_DATA_SECTION 1
+#define ENV_STAGE_HAS_BSS_SECTION 1
+#define ENV_CACHE_AS_RAM 0
+#endif
+
+/* Currently rmodules, ramstage and smm have heap. */
+#define ENV_STAGE_HAS_HEAP_SECTION (ENV_RMODULE || ENV_RAMSTAGE || ENV_SMM)
+
/**
* For pre-DRAM stages and post-CAR always build with simple device model, ie.
* PCI, PNP and CPU functions operate without use of devicetree. The reason
@@ -281,12 +298,4 @@
#define __SIMPLE_DEVICE__
#endif
-/* x86 specific. Indicates that the current stage is running with cache-as-ram
- * enabled from the beginning of the stage in C code. */
-#if defined(__PRE_RAM__)
-#define ENV_CACHE_AS_RAM CONFIG(ARCH_X86)
-#else
-#define ENV_CACHE_AS_RAM 0
-#endif
-
#endif /* _RULES_H */
diff --git a/src/lib/program.ld b/src/lib/program.ld
index 851aa75d67..1b30c0ebb6 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -85,7 +85,7 @@
#endif
/* Include data, bss, and heap in that order. Not defined for all stages. */
-#if ARCH_STAGE_HAS_DATA_SECTION
+#if ENV_STAGE_HAS_DATA_SECTION
.data . : {
. = ALIGN(ARCH_CACHELINE_ALIGN_SIZE);
_data = .;
@@ -125,7 +125,7 @@
}
#endif
-#if ARCH_STAGE_HAS_BSS_SECTION
+#if ENV_STAGE_HAS_BSS_SECTION
.bss . : {
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_bss = .;
@@ -138,7 +138,7 @@
}
#endif
-#if ARCH_STAGE_HAS_HEAP_SECTION
+#if ENV_STAGE_HAS_HEAP_SECTION
.heap . : {
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_heap = .;