diff options
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pcr.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/skylake/lpc.c | 13 |
3 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index e18b45a68a..ca902ae0ce 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -335,6 +335,8 @@ struct soc_intel_skylake_config { * 0 - Don't Send, 1 - Send */ u8 SendVrMbxCmd; + /* Statically clock gate 8254 PIT. */ + u8 clock_gate_8254; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/include/soc/pcr.h b/src/soc/intel/skylake/include/soc/pcr.h index 8a46cd1e5e..c3e8d83a90 100644 --- a/src/soc/intel/skylake/include/soc/pcr.h +++ b/src/soc/intel/skylake/include/soc/pcr.h @@ -60,6 +60,9 @@ #define R_PCH_PCR_ITSS_PIRQG_ROUT 0x3106 /* PIRQH Routing Control Register*/ #define R_PCH_PCR_ITSS_PIRQH_ROUT 0x3107 +/* ITSS Power reduction control */ +#define R_PCH_PCR_ITSS_ITSSPRC 0x3300 +# define CGE8254 (1 << 2) /* IO Trap PCRs */ /* Trap status Register */ diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index e47026c4f8..cebd836e9c 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -154,6 +154,18 @@ static const struct reg_script pch_misc_init_script[] = { REG_SCRIPT_END }; +static void clock_gate_8254(struct device *dev) +{ + config_t *config = dev->chip_info; + const uint32_t cge8254_mask = CGE8254; + + if (!config->clock_gate_8254) + return; + + pcr_andthenor32(PID_ITSS, R_PCH_PCR_ITSS_ITSSPRC, + ~cge8254_mask, cge8254_mask); +} + static void lpc_init(struct device *dev) { /* Legacy initialization */ @@ -165,6 +177,7 @@ static void lpc_init(struct device *dev) pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); + clock_gate_8254(dev); } static void pch_lpc_add_mmio_resources(device_t dev) |