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-rw-r--r--src/northbridge/intel/sandybridge/romstage.c3
-rw-r--r--src/southbridge/intel/bd82x6x/early_pch.c3
2 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 079e1b13ba..7d1c019207 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -82,9 +82,6 @@ void mainboard_romstage_entry(void)
mainboard_early_init(s3resume);
- /* Enable SPD ROMs and DDR-III DRAM */
- enable_smbus();
-
post_code(0x39);
perform_raminit(s3resume);
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index b19216b9ec..6f06a57129 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -327,4 +327,7 @@ void early_pch_init(void)
pch_enable_gbe();
setup_pch_gpios(&mainboard_gpio_map);
+
+ if (ENV_ROMSTAGE)
+ enable_smbus();
}