diff options
| -rw-r--r-- | src/drivers/generic/bayhub/bh720.c | 27 | ||||
| -rw-r--r-- | src/drivers/generic/bayhub/bh720.h | 47 | ||||
| -rw-r--r-- | src/mainboard/google/kahlee/variants/baseboard/mainboard.c | 26 |
3 files changed, 78 insertions, 22 deletions
diff --git a/src/drivers/generic/bayhub/bh720.c b/src/drivers/generic/bayhub/bh720.c index 3e78b4f049..b689b679d0 100644 --- a/src/drivers/generic/bayhub/bh720.c +++ b/src/drivers/generic/bayhub/bh720.c @@ -21,28 +21,11 @@ #include <device/pci.h> #include <device/pci_ids.h> #include "chip.h" +#include "bh720.h" -enum { - BH720_PROTECT = 0xd0, - BH720_PROTECT_LOCK_OFF = 0, - BH720_PROTECT_LOCK_ON = BIT(0), - BH720_PROTECT_OFF = 0, - BH720_PROTECT_ON = BIT(31), - - BH720_LINK_CTRL = 0x90, - BH720_LINK_CTRL_L0_ENABLE = BIT(0), - BH720_LINK_CTRL_L1_ENABLE = BIT(1), - BH720_LINK_CTRL_CLKREQ = BIT(8), - - BH720_MISC2 = 0xf0, - BH720_MISC2_ASPM_DISABLE = BIT(0), - BH720_MISC2_APSM_CLKREQ_L1 = BIT(7), - BH720_MISC2_APSM_PHY_L1 = BIT(10), - BH720_MISC2_APSM_MORE = BIT(12), - - BH720_RTD3_L1 = 0x3e0, - BH720_RTD3_L1_DISABLE_L1 = BIT(28), -}; +__attribute__((weak)) void bh720_driving_strength(struct device *dev) +{ +} static void bh720_init(struct device *dev) { @@ -71,6 +54,8 @@ static void bh720_init(struct device *dev) printk(BIOS_INFO, "BayHub BH720: Power-saving enabled (link_ctrl=%#x)\n", pci_read_config32(dev, BH720_LINK_CTRL)); } + + bh720_driving_strength(dev); } static struct pci_operations pci_ops = { diff --git a/src/drivers/generic/bayhub/bh720.h b/src/drivers/generic/bayhub/bh720.h new file mode 100644 index 0000000000..b6fd2738cd --- /dev/null +++ b/src/drivers/generic/bayhub/bh720.h @@ -0,0 +1,47 @@ +/* + * Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge + * + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +enum { + BH720_PROTECT = 0xd0, + BH720_PROTECT_LOCK_OFF = 0, + BH720_PROTECT_LOCK_ON = BIT(0), + BH720_PROTECT_OFF = 0, + BH720_PROTECT_ON = BIT(31), + + BH720_LINK_CTRL = 0x90, + BH720_LINK_CTRL_L0_ENABLE = BIT(0), + BH720_LINK_CTRL_L1_ENABLE = BIT(1), + BH720_LINK_CTRL_CLKREQ = BIT(8), + + BH720_MISC2 = 0xf0, + BH720_MISC2_ASPM_DISABLE = BIT(0), + BH720_MISC2_APSM_CLKREQ_L1 = BIT(7), + BH720_MISC2_APSM_PHY_L1 = BIT(10), + BH720_MISC2_APSM_MORE = BIT(12), + + BH720_MEM_RW_DATA = 0x200, + BH720_MEM_RW_ADR = 0x204, + BH720_MEM_ACCESS_EN = 0x208, + BH720_PCR = 0x304, + BH720_PCR_DATA_CMD_DRV_MAX = 7, + BH720_PCR_CLK_DRV_MAX = 7, + + BH720_RTD3_L1 = 0x3e0, + BH720_RTD3_L1_DISABLE_L1 = BIT(28), +}; + +void bh720_driving_strength(struct device *dev); diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c index 54743ef7c1..b1bd4928d2 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c +++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c @@ -17,7 +17,8 @@ #include <baseboard/variants.h> #include <gpio.h> #include <variant/gpio.h> - +#include <device/pci.h> +#include <drivers/generic/bayhub/bh720.h> uint8_t variant_board_sku(void) { @@ -36,3 +37,26 @@ void variant_mainboard_suspend_resume(void) gpio_set(GPIO_133, 0); } #endif + +void bh720_driving_strength(struct device *dev) +{ + u32 sdbar; + u32 bh720_pcr_data; + + sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); + + /* Enable Memory Access Function */ + write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000); + write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000); + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + + /* Read current EMMC 1.8V CLK/DATA,CMD driving strength */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x40000304); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + + /* set EMMC 1.8V CLK/DATA,CMD the max level */ + write32((void *)(sdbar + BH720_MEM_RW_DATA), + bh720_pcr_data | (BH720_PCR_CLK_DRV_MAX << 4) | + (BH720_PCR_DATA_CMD_DRV_MAX << 1)); + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x80000304); +} |