diff options
| -rw-r--r-- | src/soc/amd/picasso/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/acp.c | 72 | ||||
| -rw-r--r-- | src/soc/amd/picasso/chip.h | 8 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/northbridge.h | 3 |
4 files changed, 84 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 00dbffdfc4..76a4d70a8a 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -72,6 +72,7 @@ ramstage-y += southbridge.c ramstage-y += northbridge.c ramstage-y += pmutil.c ramstage-y += reset.c +ramstage-y += acp.c ramstage-y += sata.c ramstage-y += sm.c ramstage-y += smbus.c diff --git a/src/soc/amd/picasso/acp.c b/src/soc/amd/picasso/acp.c new file mode 100644 index 0000000000..ad5333a266 --- /dev/null +++ b/src/soc/amd/picasso/acp.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include "chip.h" +#include <soc/acpi.h> +#include <soc/pci_devs.h> +#include <soc/northbridge.h> +#include <soc/southbridge.h> +#include <amdblocks/acpimmio.h> +#include <commonlib/helpers.h> + +static void enable(struct device *dev) +{ + const struct soc_amd_picasso_config *cfg; + const struct device *nb_dev = pcidev_path_on_root(GNB_DEVFN); + struct resource *res; + uintptr_t bar; + + pci_dev_enable_resources(dev); + + /* Set the proper I2S_PIN_CONFIG state */ + if (!nb_dev || !nb_dev->chip_info) + return; + + cfg = nb_dev->chip_info; + + res = dev->resource_list; + if (!res || !res->base) { + printk(BIOS_ERR, "Error, unable to configure pin in %s\n", __func__); + return; + } + + bar = (uintptr_t)res->base; + write32((void *)(bar + ACP_I2S_PIN_CONFIG), cfg->acp_pin_cfg); + + if (cfg->acp_pin_cfg == I2S_PINS_I2S_TDM) + sb_clk_output_48Mhz(); /* Internal connection to I2S */ +} + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations acp_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = enable, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver acp_driver __pci_driver = { + .ops = &acp_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICD_ID_AMD_PCO_ACP, +}; diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 39c70269da..4e9e18b984 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -36,6 +36,14 @@ struct soc_amd_picasso_config { */ u8 i2c_scl_reset; struct dw_i2c_bus_config i2c[PICASSO_I2C_DEV_MAX]; + enum { + I2S_PINS_MAX_HDA = 0, /* HDA w/reset 3xSDI, SW w/Data0 */ + I2S_PINS_MAX_MHDA = 1, /* HDA no reset 3xSDI, SW w/Data0-1 */ + I2S_PINS_MIN_HDA = 2, /* HDA w/reset 1xSDI, SW w/Data0-2 */ + I2S_PINS_MIN_MHDA = 3, /* HDA no reset 1xSDI, SW w/Data0-3 */ + I2S_PINS_I2S_TDM = 4, + I2S_PINS_UNCONF = 7, /* All pads will be input mode */ + } acp_pin_cfg; }; typedef struct soc_amd_picasso_config config_t; diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h index e423ab1aa7..9c7419a997 100644 --- a/src/soc/amd/picasso/include/soc/northbridge.h +++ b/src/soc/amd/picasso/include/soc/northbridge.h @@ -73,6 +73,9 @@ #define D18F1_VGAEN 0xf4 # define VGA_ADDR_ENABLE (1 << 0) +/* Bus A D0F5 - Audio Processor */ +#define ACP_I2S_PIN_CONFIG 0x1400 /* HDA, Soundwire, I2S */ + void amd_initcpuio(void); void domain_enable_resources(struct device *dev); |