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-rw-r--r--src/mainboard/intel/apollolake_rvp/Makefile.inc3
-rw-r--r--src/mainboard/intel/apollolake_rvp/bootblock.c33
-rw-r--r--src/soc/intel/apollolake/bootblock/bootblock.c14
3 files changed, 15 insertions, 35 deletions
diff --git a/src/mainboard/intel/apollolake_rvp/Makefile.inc b/src/mainboard/intel/apollolake_rvp/Makefile.inc
index b2350b9490..37b198e60d 100644
--- a/src/mainboard/intel/apollolake_rvp/Makefile.inc
+++ b/src/mainboard/intel/apollolake_rvp/Makefile.inc
@@ -1,3 +1,2 @@
-bootblock-$(CONFIG_LPC_TPM) += bootblock.c
-
+#Nothing here yet
diff --git a/src/mainboard/intel/apollolake_rvp/bootblock.c b/src/mainboard/intel/apollolake_rvp/bootblock.c
deleted file mode 100644
index d075336235..0000000000
--- a/src/mainboard/intel/apollolake_rvp/bootblock.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <bootblock_common.h>
-#include <soc/gpio.h>
-
-static const struct pad_config tpm_spi_configs[] = {
- PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */
-};
-
-static void tpm_enable(void)
-{
- /* Configure gpios */
- gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs));
-}
-
-void bootblock_mainboard_init(void) {
- if (IS_ENABLED(CONFIG_LPC_TPM))
- tpm_enable();
-}
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index c65571490b..be07776f19 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -19,10 +19,21 @@
#include <device/pci.h>
#include <soc/bootblock.h>
#include <soc/cpu.h>
+#include <soc/gpio.h>
#include <soc/northbridge.h>
#include <soc/pci_devs.h>
#include <soc/uart.h>
+static const struct pad_config tpm_spi_configs[] = {
+ PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */
+};
+
+static void tpm_enable(void)
+{
+ /* Configure gpios */
+ gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs));
+}
+
void asmlinkage bootblock_c_entry(void)
{
device_t dev = NB_DEV_ROOT;
@@ -45,4 +56,7 @@ void bootblock_soc_early_init(void)
/* Prepare UART for serial console. */
if (IS_ENABLED(CONFIG_SOC_UART_DEBUG))
soc_console_uart_init();
+
+ if (IS_ENABLED(CONFIG_LPC_TPM))
+ tpm_enable();
}