diff options
| -rw-r--r-- | src/northbridge/amd/pi/00660F01/northbridge.c | 24 |
1 files changed, 17 insertions, 7 deletions
diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 139d4cb941..e4af5f02a6 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -304,6 +304,15 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) } +static void enable_mmconf_resource(device_t dev) +{ + struct resource *resource = new_resource(dev, 0xc0010058); + resource->base = CONFIG_MMCONF_BASE_ADDRESS; + resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +} + static void read_resources(device_t dev) { u32 nodeid; @@ -315,6 +324,14 @@ static void read_resources(device_t dev) amdfam15_link_read_bases(dev, nodeid, link->link_num); } } + + /* + * This MMCONF resource must be reserved in the PCI domain. + * It is not honored by the coreboot resource allocator if it is in + * the CPU_CLUSTER. + */ + if(IS_ENABLED(CONFIG_MMCONF_SUPPORT)) + enable_mmconf_resource(dev); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) @@ -1084,13 +1101,6 @@ static void cpu_bus_init(device_t dev) static void cpu_bus_read_resources(device_t dev) { -#if CONFIG_MMCONF_SUPPORT - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -#endif } static void cpu_bus_set_resources(device_t dev) |