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-rw-r--r--src/mainboard/google/drallion/dsdt.asl2
-rw-r--r--src/mainboard/google/hatch/dsdt.asl2
-rw-r--r--src/mainboard/google/sarien/dsdt.asl2
-rw-r--r--src/soc/intel/cannonlake/acpi/lpit.asl98
4 files changed, 3 insertions, 101 deletions
diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl
index ef2a94e1bd..c9f7391977 100644
--- a/src/mainboard/google/drallion/dsdt.asl
+++ b/src/mainboard/google/drallion/dsdt.asl
@@ -40,7 +40,7 @@ DefinitionBlock(
#include <southbridge/intel/common/acpi/sleepstates.asl>
/* Low power idle table */
- #include <soc/intel/cannonlake/acpi/lpit.asl>
+ #include <soc/intel/common/acpi/lpit.asl>
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl
index d43a499519..d60da37503 100644
--- a/src/mainboard/google/hatch/dsdt.asl
+++ b/src/mainboard/google/hatch/dsdt.asl
@@ -37,7 +37,7 @@ DefinitionBlock(
#include <southbridge/intel/common/acpi/sleepstates.asl>
/* Low power idle table */
- #include <soc/intel/cannonlake/acpi/lpit.asl>
+ #include <soc/intel/common/acpi/lpit.asl>
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl
index b666fbc4f6..0382fcb8dd 100644
--- a/src/mainboard/google/sarien/dsdt.asl
+++ b/src/mainboard/google/sarien/dsdt.asl
@@ -40,7 +40,7 @@ DefinitionBlock(
#include <southbridge/intel/common/acpi/sleepstates.asl>
/* Low power idle table */
- #include <soc/intel/cannonlake/acpi/lpit.asl>
+ #include <soc/intel/common/acpi/lpit.asl>
#if CONFIG(EC_GOOGLE_WILCO)
/* Chrome OS Embedded Controller */
diff --git a/src/soc/intel/cannonlake/acpi/lpit.asl b/src/soc/intel/cannonlake/acpi/lpit.asl
deleted file mode 100644
index 0653d3b7c0..0000000000
--- a/src/soc/intel/cannonlake/acpi/lpit.asl
+++ /dev/null
@@ -1,98 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-External(\_SB.MS0X, MethodObj)
-External(\_SB.PCI0.LPCB.EC0.S0IX, MethodObj)
-External(\_SB.PCI0.EGPM, MethodObj)
-External(\_SB.PCI0.RGPM, MethodObj)
-
-scope(\_SB)
-{
- Device(LPID) {
- Name(_ADR, 0x00000000)
- Name(_CID, EISAID("PNP0D80"))
- Name(UUID,
- ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66"))
- Method(_DSM, 4) {
- If(Arg0 == ^UUID) {
- /*
- * Enum functions
- */
- If(Arg2 == Zero) {
- Return(Buffer(One) {
- 0x60}
- )
- }
- /*
- * Function 1 - Get Device Constraints
- */
- If(Arg2 == 1) {
- Return(Package(5) {
- 0, Ones, Ones, Ones, Ones}
- )
- }
- /*
- * Function 2 - Get Crash Dump Device
- */
- If(Arg2 == 2) {
- Return(Buffer(One) {
- 0x0}
- )
- }
- /*
- * Function 3 - Display Off Notification
- */
- If(Arg2 == 3) {
- }
- /*
- * Function 4 - Display On Notification
- */
- If(Arg2 == 4) {
- }
- /*
- * Function 5 - Low Power S0 Entry Notification
- */
- If(Arg2 == 5) {
- /* Inform the EC */
- If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) {
- \_SB.PCI0.LPCB.EC0.S0IX(1)
- }
-
- /* provide board level s0ix hook */
- If (CondRefOf (\_SB.MS0X)) {
- \_SB.MS0X(1)
- }
-
- /*
- * Save the current PM bits then
- * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG
- */
- If (CondRefOf (\_SB.PCI0.EGPM))
- {
- \_SB.PCI0.EGPM ()
- }
- }
- /*
- * Function 6 - Low Power S0 Exit Notification
- */
- If(Arg2 == 6) {
- /* Inform the EC */
- If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) {
- \_SB.PCI0.LPCB.EC0.S0IX(0)
- }
-
- /* provide board level s0ix hook */
- If (CondRefOf (\_SB.MS0X)) {
- \_SB.MS0X(0)
- }
-
- /* Restore GPIO all Community PM */
- If (CondRefOf (\_SB.PCI0.RGPM))
- {
- \_SB.PCI0.RGPM ()
- }
- }
- }
- Return(Buffer(One) {0x00})
- } // Method(_DSM)
- } // device (LPID)
-} // End Scope(\_SB)