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-rw-r--r--src/soc/intel/tigerlake/acpi/pmc.asl26
-rw-r--r--src/soc/intel/tigerlake/acpi/southbridge.asl3
-rw-r--r--src/soc/intel/tigerlake/pmc.c30
3 files changed, 30 insertions, 29 deletions
diff --git a/src/soc/intel/tigerlake/acpi/pmc.asl b/src/soc/intel/tigerlake/acpi/pmc.asl
deleted file mode 100644
index 1dec1f876d..0000000000
--- a/src/soc/intel/tigerlake/acpi/pmc.asl
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <soc/iomap.h>
-
-Scope (\_SB.PCI0) {
-
- Device (PMC)
- {
- Name (_HID, "INTC1026")
- Name (_DDN, "Intel(R) Tiger Lake IPC Controller")
- /*
- * PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF.
- * 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR.
- */
- Name (_CRS, ResourceTemplate () {
- Memory32Fixed (ReadWrite, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE)
- })
-
- /* The OS mux driver will be bound to this device node. */
- Device (MUX)
- {
- Name (_HID, "INTC105C")
- Name (_DDN, "Intel(R) Tiger Lake North Mux-Agent")
- }
- }
-}
diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl
index 0d303e87b7..ff683cf4f6 100644
--- a/src/soc/intel/tigerlake/acpi/southbridge.asl
+++ b/src/soc/intel/tigerlake/acpi/southbridge.asl
@@ -26,9 +26,6 @@
/* PCIE Ports */
#include "pcie.asl"
-/* pmc 0:1f.2 */
-#include "pmc.asl"
-
/* Serial IO */
#include "serialio.asl"
diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c
index 62e37114f3..c24898faf3 100644
--- a/src/soc/intel/tigerlake/pmc.c
+++ b/src/soc/intel/tigerlake/pmc.c
@@ -6,6 +6,7 @@
* Chapter number: 4
*/
+#include <acpi/acpigen.h>
#include <bootstate.h>
#include <console/console.h>
#include <device/mmio.h>
@@ -17,6 +18,8 @@
#include <soc/pm.h>
#include <soc/soc_chip.h>
+#define PMC_HID "INTC1026"
+
enum pch_pmc_xtal pmc_get_xtal_freq(void)
{
uint8_t *const pmcbase = pmc_mmio_regs();
@@ -96,9 +99,36 @@ static void soc_pmc_read_resources(struct device *dev)
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
+static void soc_pmc_fill_ssdt(const struct device *dev)
+{
+ acpigen_write_scope(acpi_device_scope(dev));
+ acpigen_write_device(acpi_device_name(dev));
+
+ acpigen_write_name_string("_HID", PMC_HID);
+ acpigen_write_name_string("_DDN", "Intel(R) Tiger Lake IPC Controller");
+
+ /*
+ * Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF).
+ * The PMC gets 0xFE000000 - 0xFE00FFFF.
+ */
+ acpigen_write_name("_CRS");
+ acpigen_write_resourcetemplate_header();
+ acpigen_write_mem32fixed(1, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE);
+ acpigen_write_resourcetemplate_footer();
+
+ acpigen_pop_len(); /* PMC Device */
+ acpigen_pop_len(); /* Scope */
+
+ printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name,
+ dev_path(dev));
+}
+
struct device_operations pmc_ops = {
.read_resources = soc_pmc_read_resources,
.set_resources = noop_set_resources,
.enable = pmc_init,
+#if CONFIG(HAVE_ACPI_TABLES)
+ .acpi_fill_ssdt = soc_pmc_fill_ssdt,
+#endif
.scan_bus = scan_static_bus,
};