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-rw-r--r--src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
index 000d48db4c..15477d6fe2 100644
--- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
@@ -335,6 +335,8 @@ enum {
static uint32_t *pmc_set_sw_clamp_ptr = (void *)(PMC_CTLR_BASE + 0x47c);
/* Memory controller registers. */
+static uint32_t *mc_intstatus_ptr = (void *)(MC_CTLR_BASE);
+static uint32_t *mc_intmask_ptr = (void *)(MC_CTLR_BASE + 0x4);
static uint32_t *mc_video_protect_size_mb_ptr = (void *)(MC_CTLR_BASE + 0x64c);
static uint32_t *mc_video_protect_reg_ctrl_ptr =
@@ -979,6 +981,13 @@ void lp0_resume(void)
write32(pmc_dpd_sample_ptr, 0);
udelay(10);
+ /* Clear the MC_INTSTATUS if MC_INTMASK was 0. */
+ if (!read32(mc_intmask_ptr)) {
+ uint32_t mc_intst_val = read32(mc_intstatus_ptr);
+ if (mc_intst_val)
+ write32(mc_intstatus_ptr, mc_intst_val);
+ }
+
/*
* Set both _ACCESS bits so that kernel/secure code
* can reconfig VPR careveout as needed from the TrustZone.