diff options
| -rw-r--r-- | src/southbridge/amd/amd8151/amd8151_agp3.c | 58 |
1 files changed, 23 insertions, 35 deletions
diff --git a/src/southbridge/amd/amd8151/amd8151_agp3.c b/src/southbridge/amd/amd8151/amd8151_agp3.c index b58f7926d4..dfb8a5592b 100644 --- a/src/southbridge/amd/amd8151/amd8151_agp3.c +++ b/src/southbridge/amd/amd8151/amd8151_agp3.c @@ -13,56 +13,45 @@ static void agp3bridge_init(device_t dev) { uint8_t byte; - /* Enable BM and IO */ + /* Enable BM, MEM and IO */ byte = pci_read_config32(dev, 0x04); - byte |= 0x07; - pci_write_config8(dev, 0x04, byte); - - /* Eable VGA/ISA decoding */ - byte = pci_read_config32(dev, 0x3e); - byte |= 3<<2; - pci_write_config8(dev, 0x3e, byte); + byte |= 0x07; + pci_write_config8(dev, 0x04, byte); return; } static struct device_operations agp3bridge_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = agp3bridge_init, - .scan_bus = pci_scan_bridge, + .init = agp3bridge_init, + .scan_bus = pci_scan_bridge, }; static struct pci_driver agp3bridge_driver __pci_driver = { - .ops = &agp3bridge_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x7455, // AGP Bridge + .ops = &agp3bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x7455, // AGP Bridge }; static void agp3dev_enable(device_t dev) { uint32_t value; - // AGP enable - value = pci_read_config32(dev, 0xa8); - value |= (3<<8)|2; //AGP 8x - pci_write_config32(dev, 0xa8, value); -/* - // linkA 8bit-->16bit - value = pci_read_config32(dev, 0xc4); - value |= (0x11<<24); - pci_write_config32(dev, 0xc4, value); - - // linkA 200-->600 - value = pci_read_config32(dev, 0xcc); - value |= (4<<8); - pci_write_config32(dev, 0xcc, value); -*/ + /* AGP enable */ + value = pci_read_config32(dev, 0xa8); + value |= (3<<8)|2; //AGP 8x + pci_write_config32(dev, 0xa8, value); - value = pci_read_config32(dev, 0x4); - value |= 6; - pci_write_config32(dev, 0x4, value); + /* enable BM and MEM */ + value = pci_read_config32(dev, 0x4); + value |= 6; + pci_write_config32(dev, 0x4, value); +#if 0 + /* FIXME: should we add agp aperture base and size here ? + * or it is done by AGP drivers */ +#endif } static struct device_operations agp3dev_ops = { @@ -77,6 +66,5 @@ static struct device_operations agp3dev_ops = { static struct pci_driver agp3dev_driver __pci_driver = { .ops = &agp3dev_ops, .vendor = PCI_VENDOR_ID_AMD, - .device = 0x7454, //AGP Device - + .device = 0x7454, //AGP Device }; |