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-rw-r--r--src/mainboard/intel/kunimitsu/acpi/mainboard.asl13
-rw-r--r--src/mainboard/intel/kunimitsu/devicetree.cb2
-rwxr-xr-xsrc/mainboard/intel/kunimitsu/gpio.h7
3 files changed, 19 insertions, 3 deletions
diff --git a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl
index dce1371a4d..73193ddcde 100644
--- a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl
+++ b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl
@@ -58,6 +58,19 @@ Scope (\_SB.PCI0.LPCB)
#include <drivers/pc80/tpm/acpi/tpm.asl>
}
+/*
+ * WLAN connected to Root Port 1
+ */
+Scope (\_SB.PCI0.RP01)
+{
+ Device (WLAN)
+ {
+ Name (_ADR, 0x00000000)
+ Name (_DDR, "Wireless LAN")
+ Name (_PRW, Package () { GPE_WLAN_WAKE, 3 })
+ }
+}
+
Scope (\_SB.PCI0.I2C0)
{
/* Touchscreen */
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 4e99d68407..21af62a43d 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -9,7 +9,7 @@ chip soc/intel/skylake
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
- register "gpe0_dw0" = "GPP_C"
+ register "gpe0_dw0" = "GPP_B"
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h
index 87380d2fcd..1441738a83 100755
--- a/src/mainboard/intel/kunimitsu/gpio.h
+++ b/src/mainboard/intel/kunimitsu/gpio.h
@@ -39,12 +39,15 @@
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
#define GPE_EC_WAKE GPE0_LAN_WAK
+/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */
+#define GPE_WLAN_WAKE GPE0_DW0_16
+
/* Input device interrupt configuration */
#define TOUCHPAD_INT_L GPP_B3_IRQ
#define TOUCHSCREEN_INT_L GPP_E7_IRQ
#define MIC_INT_L GPP_F10_IRQ
-/* GPP_E16 is EC_SCI_L. GPP_E group is routed to dword 2 in the GPE0 block. */
+/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
#define EC_SCI_GPI GPE0_DW2_16
#define EC_SMI_GPI GPP_E15
@@ -91,7 +94,7 @@ static const struct pad_config gpio_table[] = {
/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
/* GPP_B_14_SPKR */ PAD_CFG_GPI(GPP_B14, NONE, DEEP),
/* GSPI0_CS# */ /* GPP_B15 */
-/* WLAN_PCIE_WAKE */ PAD_CFG_GPI(GPP_B16, NONE, DEEP),
+/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
/* SSD_PCIE_WAKE */ PAD_CFG_GPI(GPP_B17, NONE, DEEP),
/* GSPI0_MOSI */ /* GPP_B18 */
/* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),