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-rw-r--r--src/northbridge/amd/amdk8/incoherent_ht.c6
-rw-r--r--src/southbridge/amd/amd8111/amd8111_pci.c3
2 files changed, 5 insertions, 4 deletions
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index c04781f2c0..b07c62a5dc 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -275,12 +275,12 @@ static int ht_optimize_link(
static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus,
unsigned offset_unitid, struct sys_info *sysinfo);
-static int scan_pci_bus( unsigned bus , struct sys_info *sysinfo)
+static int scan_pci_bus(unsigned bus, struct sys_info *sysinfo)
#else
static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus,
unsigned offset_unitid);
-static int scan_pci_bus( unsigned bus)
+static int scan_pci_bus(unsigned bus)
#endif
{
/* Here we already can access PCI_DEV(bus, 0, 0) to
@@ -467,7 +467,7 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
* retrain, so lets knock it down and see
* if its transient
*/
- ctrl |= ((1 << 6) | (1 <<8)); // Link fail + Crc
+ ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
pci_write_config16(udev, upos + LINK_CTRL(uoffs), ctrl);
ctrl = pci_read_config16(udev, upos + LINK_CTRL(uoffs));
if (ctrl & ((1 << 4) | (1 << 8))) {
diff --git a/src/southbridge/amd/amd8111/amd8111_pci.c b/src/southbridge/amd/amd8111/amd8111_pci.c
index b9a9b3578d..6cedc1de94 100644
--- a/src/southbridge/amd/amd8111/amd8111_pci.c
+++ b/src/southbridge/amd/amd8111/amd8111_pci.c
@@ -23,7 +23,8 @@ static void pci_init(struct device *dev)
dword |= (1<<17); /* System */
dword |= (1<<21); /* Master abort */
// dword &= ~(1<<21); /* Master abort */
- dword |= (1<<27); /* Discard timer */
+// dword |= (1<<27); /* Discard timer */
+ dword &= ~(1<<27); /* Discard timer */
dword |= (1<<26); /* DTSTAT error clear */
pci_write_config32(dev, 0x3c, dword);