diff options
| -rw-r--r-- | src/southbridge/intel/bd82x6x/finalize.c | 10 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 3 |
2 files changed, 13 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index 90932e16bc..c9296fd949 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -16,11 +16,15 @@ #include <arch/io.h> #include <console/post_codes.h> +#include <cpu/x86/smm.h> #include "pch.h" #include <spi-generic.h> void intel_pch_finalize_smm(void) { + u16 tco1_cnt; + u16 pmbase; + if (CONFIG_LOCK_SPI_ON_RESUME_RO || CONFIG_LOCK_SPI_ON_RESUME_NO_ACCESS) { /* Copy flash regions from FREG0-4 to PR0-4 and enable write protection bit31 */ @@ -66,6 +70,12 @@ void intel_pch_finalize_smm(void) pci_write_config32(PCI_DEV(0, 27, 0), 0x74, pci_read_config32(PCI_DEV(0, 27, 0), 0x74)); + /* TCO_Lock */ + pmbase = smm_get_pmbase(); + tco1_cnt = inw(pmbase + TCO1_CNT); + tco1_cnt |= TCO_LOCK; + outw(tco1_cnt, pmbase + TCO1_CNT); + /* Indicate finalize step with post code */ outb(POST_OS_BOOT, 0x80); } diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 1977c8f9d2..8b22fca334 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -534,6 +534,9 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define TCO1_STS 0x64 #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 +#define TCO1_CNT 0x68 +#define TCO_LOCK (1 << 12) +#define TCO2_CNT 0x6a /* * SPI Opcode Menu setup for SPIBAR lockdown |