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-rw-r--r--src/cpu/amd/agesa/family14/Makefile.inc1
-rw-r--r--src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h10
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c141
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S203
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c2
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c10
-rw-r--r--src/vendorcode/amd/agesa/f14/gcccar.inc192
7 files changed, 325 insertions, 234 deletions
diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc
index 774d401b63..b08ceebf80 100644
--- a/src/cpu/amd/agesa/family14/Makefile.inc
+++ b/src/cpu/amd/agesa/family14/Makefile.inc
@@ -113,6 +113,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtMidPost.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/ON/mpuon3.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahaltasm.S
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnPciTables.c
diff --git a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h
index 58438b9815..5ce3ee3d23 100644
--- a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h
+++ b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h
@@ -305,7 +305,9 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void)
unsigned long value;
__asm__ __volatile__ (
"mov %%cr0, %[value]"
- : [value] "=a" (value));
+ : [value] "=a" (value)
+ :
+ : "memory");
return value;
}
@@ -379,6 +381,7 @@ static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long D
"mov %%eax, %%cr0"
:
: "a" (Data)
+ : "memory"
);
}
@@ -508,13 +511,16 @@ static __inline__ __attribute__((always_inline)) void __debugbreak(void)
__asm__ __volatile__ ("int3");
}
+static __inline__ __attribute__((always_inline)) void __invd(void)
+{
+ __asm__ __volatile__ ("invd");
+}
static __inline__ __attribute__((always_inline)) void __wbinvd(void)
{
__asm__ __volatile__ ("wbinvd");
}
-
static __inline__ __attribute__((always_inline)) void __lidt(void *Source)
{
__asm__ __volatile__("lidt %0" : : "m"(*(short*)Source));
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c
index ae9f3c7fd8..938300ae93 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c
@@ -106,149 +106,16 @@ ExecuteWbinvdInstruction (
*/
-//----------------------------------------------------------------------------
-
-STATIC
-VOID
-PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList)
- {
- UINT64 data;
- UINT32 msrno;
- // Configure the MTRRs on the AP so
- // when it runs remote code it will execute
- // out of RAM instead of ROM.
- // Disable MTRRs and turn on modification enable bit
-
- data = __readmsr (0xC0010010); // MTRR_SYS_CFG
- data &= ~(1 << 18); // MtrrFixDramEn
- data &= ~(1 << 20); // MtrrVarDramEn
- data |= (1 << 19); // MtrrFixDramModEn
- data |= (1 << 17); // SysUcLockEn
-
-
- __writemsr (0xC0010010, data);
-
- // Set 7FFFh-00000h and 9FFFFh-80000h as WB DRAM
- __writemsr (0x250, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX64k_00000
- __writemsr (0x258, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX16k_80000
-
- // Set BFFFFh-A0000h, DFFFFh-C0000h as Uncacheable Memory-mapped IO
- __writemsr (0x259, 0); // AMD_AP_MTRR_FIX16k_A0000
- __writemsr (0x268, 0); // AMD_MTRR_FIX4k_C0000
- __writemsr (0x269, 0); // AMD_MTRR_FIX4k_C8000
- __writemsr (0x26A, 0); // AMD_MTRR_FIX4k_D0000
- __writemsr (0x26B, 0); // AMD_MTRR_FIX4k_D8000
-
- // Set FFFFFh-E0000h as Uncacheable Memory
- for (msrno = 0x26C; msrno <= 0x26F; msrno++)
- __writemsr (msrno, 0x1818181818181818);
-
- // If IBV provided settings for Fixed-Sized MTRRs,
- // overwrite the default settings.
- if ((uintptr_t) ApMtrrSettingsList != 0 && (uintptr_t) ApMtrrSettingsList != 0xFFFFFFFF)
- {
- int index;
- for (index = 0; ApMtrrSettingsList [index].MsrAddr != CPU_LIST_TERMINAL; index++)
- __writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData);
- }
-
- // restore variable MTTR6 and MTTR7 to default states
- for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared
- __writemsr (msrno, 0);
-
- // Enable fixed-range and variable-range MTRRs
- // Set Fixed-Range Enable (FE) and MTRR Enable (E) bits
- __writemsr (0x2FF, __readmsr (0x2FF) | 0xC00);
-
- // Enable Top-of-Memory setting
- // Enable use of RdMem/WrMem bits attributes
- data = __readmsr (0xC0010010); // MTRR_SYS_CFG
- data |= (1 << 18); // MtrrFixDramEn
- data |= (1 << 20); // MtrrVarDramEn
- data &= ~(1 << 19); // MtrrFixDramModEn
- __writemsr (0xC0010010, data);
- }
-
-//----------------------------------------------------------------------------
-
+/* see cahaltasm.S
VOID
ExecuteFinalHltInstruction (
- IN UINT32 SharedCore,
+ IN UINT32 HaltFlags,
IN AP_MTRR_SETTINGS *ApMtrrSettingsList,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- int abcdRegs [4];
- UINT32 cr0val;
- UINT64 data;
-
- cr0val = __readcr0 ();
- if (SharedCore & 2)
- {
- // set CombineCr0Cd and enable cache in CR0
- __writemsr (MSR_CU_CFG3, __readmsr (MSR_CU_CFG3) | 1ULL << 49);
- __writecr0 (cr0val & ~0x60000000);
- }
- else
- __writecr0 (cr0val | 0x60000000);
-
- if (SharedCore & 1) PrimaryCoreFunctions (ApMtrrSettingsList);
-
- // Make sure not to touch any Shared MSR from this point on
-
- // Restore settings that were temporarily overridden for the cache as ram phase
- data = __readmsr (0xC0011022); // MSR_DC_CFG
- data &= ~(1 << 4); // DC_DIS_SPEC_TLB_RLD
- data &= ~(1 << 8); // DIS_CLR_WBTOL2_SMC_HIT
- data &= ~(1 << 13); // DIS_HW_PF
- __writemsr (0xC0011022, data);
-
- data = __readmsr (0xC0011021); // MSR_IC_CFG - C001_1021
- data &= ~(1 << 9); // IC_DIS_SPEC_TLB_RLD
- __writemsr (0xC0011021, data);
-
- // AMD_DISABLE_STACK_FAMILY_HOOK
- __cpuid (abcdRegs, 1);
- if ((abcdRegs [0] >> 20) == 1) //-----family 10h (Hydra) only-----
- {
- data = __readmsr (0xC0011022);
- data &= ~(1 << 4);
- data &= ~(1 << 8);
- data &= ~(1 << 13);
- __writemsr (0xC0011022, data);
-
- data = __readmsr (0xC0011021);
- data &= ~(1 << 14);
- data &= ~(1 << 9);
- __writemsr (0xC0011021, data);
-
- data = __readmsr (0xC001102A);
- data &= ~(1 << 15);
- data &= ~(1ull << 35);
- __writemsr (0xC001102A, data);
- }
- else if ((abcdRegs [0] >> 20) == 6) //-----family 15h (Orochi) only-----
- {
- data = __readmsr (0xC0011020);
- data &= ~(1 << 28);
- __writemsr (0xC0011020, data);
-
- data = __readmsr (0xC0011021);
- data &= ~(1 << 9);
- __writemsr (0xC0011021, data);
-
- data = __readmsr (0xC0011022);
- data &= ~(1 << 4);
- data &= ~(1l << 13);
- __writemsr (0xC0011022, data);
- }
-
- for (;;)
- {
- _disable ();
- __halt ();
- }
- }
+}
+*/
//----------------------------------------------------------------------------
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S
new file mode 100644
index 0000000000..48ee5d0238
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+.include "src/vendorcode/amd/agesa/f14/gcccar.inc"
+
+.code32
+.align 4
+.globl ExecuteFinalHltInstruction
+ .type ExecuteFinalHltInstruction, @function
+/* ExecuteFinalHltInstruction (
+ IN UINT32 HaltFlags,
+ IN AP_MTRR_SETTINGS *ApMtrrSettingsList,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+*/
+
+/* This function disables CAR. We don't care about the stack on this CPU */
+ExecuteFinalHltInstruction:
+ movl 4(%esp), %esi /* HaltFlags*/
+ movl 8(%esp), %edi /* ApMtrrSettingList */
+
+/* Do these special steps in case if the core is part of a compute unit
+ * Note: The following bits are family specific flags, that gets set during build time,
+ * and indicates things like "family cache control methodology", etc.
+ * esi bit0 = 0 -> not a Primary core
+ * esi bit0 = 1 -> Primary core
+ * esi bit1 = 0 -> Cache disable
+ * esi bit1 = 1 -> Cache enable
+ */
+
+ bt $1, %esi /* .if (esi & 2h) */
+ jz 0f
+ /* Set CombineCr0Cd bit */
+ movl $CU_CFG3, %ecx
+ rdmsr
+ bts $(COMBINE_CR0_CD - 32), %edx
+ wrmsr
+ /* Clear the CR0.CD bit */
+ movl %cr0, %eax /* Make sure cache is enabled for all APs */
+ btr $CR0_CD, %eax
+ btr $CR0_NW, %eax
+ mov %eax, %cr0 /* Write back to CR0 */
+ jmp 1f /* .else */
+0:
+ movl %cr0, %eax /* Make sure cache is disabled for all APs */
+ bts $CR0_CD, %eax /* Disable cache */
+ bts $CR0_NW, %eax
+ movl %eax, %cr0 /* Write back to CR0 */
+1: /* .endif */
+
+ bt $0, %esi /* .if (esi & 1h) */
+ jz 2f
+ /* This core is a primary core and needs to do all the MTRRs, including shared MTRRs. */
+ movl %edi, %esi /* Get ApMtrrSettingList */
+
+ /* Configure the MTRRs on the AP so
+ * when it runs remote code it will execute
+ * out of RAM instead of ROM.
+ */
+
+ /* Disable MTRRs and turn on modification enable bit */
+ movl $MTRR_SYS_CFG, %ecx
+ rdmsr
+ btr $MTRR_VAR_DRAM_EN, %eax /* Disable */
+ bts $MTRR_FIX_DRAM_MOD_EN, %eax /* Enable */
+ btr $MTRR_FIX_DRAM_EN, %eax /* Disable */
+ bts $SYS_UC_LOCK_EN, %eax
+ wrmsr
+
+ /* Setup default values for Fixed-Sized MTRRs */
+ /* Set 7FFFh-00000h as WB */
+ movl $AMD_AP_MTRR_FIX64k_00000, %ecx
+ movl $0x1E1E1E1E, %eax
+ movl %eax, %edx
+ wrmsr
+
+ /* Set 9FFFFh-80000h also as WB */
+ movl $AMD_AP_MTRR_FIX16k_80000, %ecx
+ wrmsr
+
+ /* Set BFFFFh-A0000h as Uncacheable Memory-mapped IO */
+ movl $AMD_AP_MTRR_FIX16k_A0000, %ecx
+ xorl %eax, %eax
+ xorl %edx, %edx
+ wrmsr
+
+ /* Set DFFFFh-C0000h as Uncacheable Memory-mapped IO */
+ xorl %eax, %eax
+ xorl %edx, %edx
+ movl $AMD_AP_MTRR_FIX4k_C0000, %ecx
+
+CDLoop:
+ wrmsr
+ inc %ecx
+ cmp $AMD_AP_MTRR_FIX4k_D8000, %ecx
+ jbe CDLoop
+
+ /* Set FFFFFh-E0000h as Uncacheable Memory */
+ movl $0x18181818, %eax
+ movl %eax, %edx
+
+ mov $AMD_AP_MTRR_FIX4k_E0000, %ecx
+
+EFLoop:
+ wrmsr
+ inc %ecx
+ cmp $AMD_AP_MTRR_FIX4k_F8000, %ecx
+ jbe EFLoop
+
+ /* If IBV provided settings for Fixed-Sized MTRRs,
+ * overwrite the default settings. */
+ cmp $0, %esi /*.if ((esi != 0) && (esi != 0FFFFFFFFh)) */
+ jz 4f
+ cmp $0xFFFFFFFF, %esi
+ jz 4f
+ 5:
+ mov (%esi), %ecx /* (AP_MTRR_SETTINGS ptr [esi]).MsrAddr */
+ /* While we are not at the end of the list */
+ cmp $CPU_LIST_TERMINAL, %ecx /* .while (ecx != CPU_LIST_TERMINAL)*/
+ je 4f
+ /* TODO - coreboot isn't checking for valid data.
+ * Ensure that the MSR address is valid for Fixed-Sized MTRRs */
+ /*.if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \
+ (ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || \
+ (ecx == AMD_AP_MTRR_FIX16k_A0000))
+ */
+ mov 4(%esi), %eax /* MsrData */
+ mov 8(%esi), %edx /* MsrData */
+ wrmsr
+ /* .endif */
+ add $12, %esi /* sizeof (AP_MTRR_SETTINGS) */
+ jmp 5b /* .endw */
+ 4: /* .endif */
+
+ /* restore variable MTTR6 and MTTR7 to default states */
+ movl $AMD_MTRR_VARIABLE_BASE6, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */
+ xor %eax, %eax /* and MTRRPhysBase7 MTRRPhysMask7 */
+ xor %edx, %edx
+ cmp $10, %ecx /* .while (cl < 010h) */
+ jge 6f
+ wrmsr
+ inc %ecx
+ 6: /* .endw */
+
+ /* Enable fixed-range and variable-range MTRRs */
+ mov $AMD_MTRR_DEFTYPE, %ecx
+ rdmsr
+ bts $MTRR_DEF_TYPE_EN, %eax /* MtrrDefTypeEn */
+ bts $MTRR_DEF_TYPE_FIX_EN, %eax /* MtrrDefTypeFixEn */
+ wrmsr
+
+ /* Enable Top-of-Memory setting */
+ /* Enable use of RdMem/WrMem bits attributes */
+ mov $MTRR_SYS_CFG, %ecx
+ rdmsr
+ bts $MTRR_VAR_DRAM_EN, %eax /* Enable */
+ btr $MTRR_FIX_DRAM_MOD_EN, %eax /* Disable */
+ bts $MTRR_FIX_DRAM_EN, %eax /* Enable */
+ wrmsr
+
+ bts $FLAG_IS_PRIMARY, %esi
+ jmp 3f /* .else ; end if primary core */
+ 2:
+ xor %esi, %esi
+ 3: /* .endif*/
+
+ /* Make sure not to touch any Shared MSR from this point on */
+
+ AMD_DISABLE_STACK_FAMILY_HOOK
+
+ xor %eax, %eax
+
+7:
+ cli
+ hlt
+ jmp 7b /* ExecuteHltInstruction */
+
+ .size ExecuteFinalHltInstruction, .-ExecuteFinalHltInstruction
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c
index f994c87f66..448d0f9313 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c
@@ -245,7 +245,7 @@ AmdS3Save (
HeapStatus = AmdS3SaveParams->StdHeader.HeapStatus;
AmdS3SaveParams->StdHeader.HeapStatus = HEAP_S3_RESUME;
- AmdS3SaveParams->StdHeader.HeapBasePtr = (UINT64) HeapPtr;
+ AmdS3SaveParams->StdHeader.HeapBasePtr = (VOID *) HeapPtr;
for (i = 0; i < S3LATE_TABLE_SIZE; i++) {
if (HeapPtrs[i] != NULL) {
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c
index df2071f5bc..eee980484d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c
@@ -259,30 +259,30 @@ MemFS3GetDeviceList (
(*DeviceBlockHdrPtr)->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize;
// Copy device list on the stack to the heap.
- BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) AllocHeapParams.BufferPtr;
+ BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) (UINT32) AllocHeapParams.BufferPtr;
for (Die = 0; Die < DieCount; Die ++) {
for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
// Copy PCI device descriptor to the heap if it exists.
if (DeviceDescript[Die].PCIDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader);
+ LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader);
(*DeviceBlockHdrPtr)->NumDevices ++;
BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR);
}
// Copy conditional PCI device descriptor to the heap if it exists.
if (DeviceDescript[Die].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader);
+ LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader);
(*DeviceBlockHdrPtr)->NumDevices ++;
BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
}
// Copy MSR device descriptor to the heap if it exists.
if (DeviceDescript[Die].MSRDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader);
+ LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader);
(*DeviceBlockHdrPtr)->NumDevices ++;
BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR);
}
// Copy conditional MSR device descriptor to the heap if it exists.
if (DeviceDescript[Die].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader);
+ LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader);
(*DeviceBlockHdrPtr)->NumDevices ++;
BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
}
diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc
index 874391982b..d81b6afe70 100644
--- a/src/vendorcode/amd/agesa/f14/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f14/gcccar.inc
@@ -37,99 +37,113 @@
.altmacro
-BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */
-BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */
-CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */
-CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */
-CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */
-CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */
-
-APIC_BASE_ADDRESS = 0x0000001B
- APIC_BSC = 8 /* Boot Strap Core */
-
-AMD_MTRR_VARIABLE_BASE0 = 0x0200
-AMD_MTRR_VARIABLE_BASE6 = 0x020C
-AMD_MTRR_FIX64k_00000 = 0x0250
-AMD_MTRR_FIX16k_80000 = 0x0258
-AMD_MTRR_FIX16k_A0000 = 0x0259
-AMD_MTRR_FIX4k_C0000 = 0x0268
-AMD_MTRR_FIX4k_C8000 = 0x0269
-AMD_MTRR_FIX4k_D0000 = 0x026A
-AMD_MTRR_FIX4k_D8000 = 0x026B
-AMD_MTRR_FIX4k_E0000 = 0x026C
-AMD_MTRR_FIX4k_E8000 = 0x026D
-AMD_MTRR_FIX4k_F0000 = 0x026E
-AMD_MTRR_FIX4k_F8000 = 0x026F
-
-AMD_MTRR_DEFTYPE = 0x02FF
- WB_DRAM_TYPE = 0x1E /* MemType - memory type */
- MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */
- MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */
-
-HWCR = 0x0C0010015 /* Hardware Configuration */
- INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */
-
-IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */
- /* uses 16h - 19h */
-TOP_MEM = 0x0C001001A /* Top of Memory */
-TOP_MEM2 = 0x0C001001D /* Top of Memory2 */
-
-LS_CFG = 0x0C0011020 /* Load-Store Configuration */
- DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */
- DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */
-
-IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */
- IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */
- DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */
- DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */
-
-DC_CFG = 0x0C0011022 /* Data Cache Configuration */
- DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */
- DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */
- DIS_HW_PF = 13 /* Hardware prefetches bit */
-
-DE_CFG = 0x0C0011029 /* Decode Configuration */
- CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */
-
-BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */
-CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */
- F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */
- IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */
-
-CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */
- COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */
-
-
+BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */
+BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */
+CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */
+CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */
+CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */
+CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */
+
+APIC_BASE_ADDRESS = 0x0000001B
+ APIC_BSC = 8 /* Boot Strap Core */
+
+AMD_MTRR_VARIABLE_BASE0 = 0x0200
+AMD_MTRR_VARIABLE_BASE6 = 0x020C
+AMD_MTRR_FIX64k_00000 = 0x0250
+AMD_MTRR_FIX16k_80000 = 0x0258
+AMD_MTRR_FIX16k_A0000 = 0x0259
+AMD_MTRR_FIX4k_C0000 = 0x0268
+AMD_MTRR_FIX4k_C8000 = 0x0269
+AMD_MTRR_FIX4k_D0000 = 0x026A
+AMD_MTRR_FIX4k_D8000 = 0x026B
+AMD_MTRR_FIX4k_E0000 = 0x026C
+AMD_MTRR_FIX4k_E8000 = 0x026D
+AMD_MTRR_FIX4k_F0000 = 0x026E
+AMD_MTRR_FIX4k_F8000 = 0x026F
+
+/* Reproduced from AGESA.h */
+AMD_AP_MTRR_FIX64k_00000 = 0x00000250
+AMD_AP_MTRR_FIX16k_80000 = 0x00000258
+AMD_AP_MTRR_FIX16k_A0000 = 0x00000259
+AMD_AP_MTRR_FIX4k_C0000 = 0x00000268
+AMD_AP_MTRR_FIX4k_C8000 = 0x00000269
+AMD_AP_MTRR_FIX4k_D0000 = 0x0000026A
+AMD_AP_MTRR_FIX4k_D8000 = 0x0000026B
+AMD_AP_MTRR_FIX4k_E0000 = 0x0000026C
+AMD_AP_MTRR_FIX4k_E8000 = 0x0000026D
+AMD_AP_MTRR_FIX4k_F0000 = 0x0000026E
+AMD_AP_MTRR_FIX4k_F8000 = 0x0000026F
+CPU_LIST_TERMINAL = 0xFFFFFFFF
+
+AMD_MTRR_DEFTYPE = 0x02FF
+ WB_DRAM_TYPE = 0x1E /* MemType - memory type */
+ MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */
+ MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */
+
+HWCR = 0x0C0010015 /* Hardware Configuration */
+ INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */
+
+IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */
+ /* uses 16h - 19h */
+TOP_MEM = 0x0C001001A /* Top of Memory */
+TOP_MEM2 = 0x0C001001D /* Top of Memory2 */
+
+LS_CFG = 0x0C0011020 /* Load-Store Configuration */
+ DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */
+ DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */
+
+IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */
+ IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */
+ DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */
+ DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */
+
+DC_CFG = 0x0C0011022 /* Data Cache Configuration */
+ DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */
+ DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */
+ DIS_HW_PF = 13 /* Hardware prefetches bit */
+
+DE_CFG = 0x0C0011029 /* Decode Configuration */
+ CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */
+
+BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */
+CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */
+ F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */
+ IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */
+
+CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */
+ COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */
+
+
CR0_PE = 1 # Protection Enable
CR0_NW = 29 # Not Write-through
CR0_CD = 30 # Cache Disable
CR0_PG = 31 # Paging Enable
-
-/* CPUID Functions */
-
-CPUID_MODEL = 1
-AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */
-AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */
-
-NB_CFG = 0x0C001001F /* Northbridge Configuration Register */
- INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */
-
-MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */
- CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */
- SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */
- MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */
- MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */
- MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */
- MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */
-
-PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */
- PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */
- PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */
- CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */
- CONFIG_EVENT_H = 4 /* Increment count by number of event */
- /* occured in clock cycle */
- EVENT_ENABLE = 22 /* Enable the event */
-PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */
+
+/* CPUID Functions */
+
+CPUID_MODEL = 1
+AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */
+AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */
+
+NB_CFG = 0x0C001001F /* Northbridge Configuration Register */
+ INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */
+
+MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */
+ CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */
+ SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */
+ MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */
+ MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */
+ MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */
+ MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */
+
+PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */
+ PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */
+ PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */
+ CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */
+ CONFIG_EVENT_H = 4 /* Increment count by number of event */
+ /* occured in clock cycle */
+ EVENT_ENABLE = 22 /* Enable the event */
+PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */
# Local use flags, in upper most byte if ESI
FLAG_UNKNOWN_FAMILY = 24 # Signals that the family# of the installed processor is not recognized
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 22:56:05 +0000